WO2020216225A1 - 阵列基板及其制造方法、显示面板和显示装置 - Google Patents

阵列基板及其制造方法、显示面板和显示装置 Download PDF

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Publication number
WO2020216225A1
WO2020216225A1 PCT/CN2020/086008 CN2020086008W WO2020216225A1 WO 2020216225 A1 WO2020216225 A1 WO 2020216225A1 CN 2020086008 W CN2020086008 W CN 2020086008W WO 2020216225 A1 WO2020216225 A1 WO 2020216225A1
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Prior art keywords
insulating layer
via hole
color
array substrate
base substrate
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PCT/CN2020/086008
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English (en)
French (fr)
Inventor
刘军
闫梁臣
周斌
李伟
苏同上
黄勇潮
罗标
桂学海
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/043,962 priority Critical patent/US11569307B2/en
Publication of WO2020216225A1 publication Critical patent/WO2020216225A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.
  • An organic light emitting diode (OLED) display device may include a plurality of OLEDs as light emitting devices and transistors (for example, thin film transistors) for driving the plurality of OLEDs for display.
  • the transistor may include a top gate type transistor and a bottom gate type transistor, and accordingly, the OLED display device includes a top gate type OLED display device and a bottom gate type OLED display device.
  • Ion on-state current
  • Ion on-state current
  • aperture ratio higher aperture ratio
  • better array substrate stability than large-size bottom-gate OLED display devices. Sex and attention.
  • an embodiment of the present disclosure provides an array substrate, including: a base substrate, a semiconductor active layer sequentially located on the base substrate, a gate, and a source and a drain, wherein the The array substrate further includes: a first insulating layer, a second insulating layer, a third insulating layer, at least one first via hole, and at least one second via hole;
  • the first insulating layer, the second insulating layer, and the third insulating layer are sequentially disposed on a base substrate provided with the source electrode and the drain electrode;
  • Each of the at least one first via hole penetrates the third insulating layer, and in each pixel unit provided with a plurality of color resists, each of the at least one first via hole is located in a pair of adjacent two Between the color resists, it is used to subsequently fill one of the pair of adjacent color resists;
  • Each of the at least one second via hole penetrates the second insulating layer, and the position of the at least one second via hole corresponds to the position of the at least one first via hole, and is parallel to the liner
  • the width of each of the at least one second via hole in the direction of the base substrate is greater than the width of the corresponding first via hole, and each of the at least one second via hole is used for subsequent filling and the corresponding position of the first via hole.
  • the color resists in the via holes are the same color resists.
  • the material of the first insulating layer and the third insulating layer is silicon oxide, and the material of the second insulating layer is silicon nitride.
  • the central axis of each of the at least one first via coincides with the central axis of the corresponding second via.
  • each of the at least one first via has a width of 6 ⁇ m to 10 ⁇ m.
  • the side of the corresponding second via is the same as that of the first via.
  • the distance between the sides of the via is 8 to 12 microns.
  • a cross section of each of the at least one first via is a long strip
  • a cross section of each of the at least one second via is a long strip shape
  • the array substrate further includes: a color filter layer; wherein,
  • the color film layer is located on the third insulating layer.
  • the color filter layer includes a red color resist, a green color resist, and a blue color resist in each pixel unit;
  • the at least one first via includes two first vias
  • the at least one second via includes two second vias
  • one of the first vias and the second vias at the corresponding positions of the first vias are filled with blue color resist, and the other of the first vias and the first vias are at the corresponding positions
  • the second via hole is filled with red color resist.
  • the array substrate further includes a planarization layer disposed on the color filter layer.
  • the cross section of each of the at least first via holes is rectangular, and the cross section of each of the at least one second via holes is rectangular.
  • each of the first insulating layer and the third insulating layer is 0.1 micrometers to 0.2 micrometers, and the thickness of the second insulating layer is 0.03 micrometers to 0.05 micrometers.
  • an embodiment of the present disclosure provides a display panel including the array substrate as described in any of the above-mentioned embodiments of the present disclosure.
  • an embodiment of the present disclosure provides a display device including the display panel as described in the above-mentioned embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a manufacturing method of an array substrate, including:
  • the semiconductor active layer, the gate, and the source and drain are sequentially fabricated on the base substrate through a patterning process
  • a patterning process is performed on the third insulating layer to form at least one first via hole penetrating the third insulating layer, and in each pixel unit provided with a plurality of color resists, each of the at least one The first via is located between a pair of adjacent two color resists, and is used to subsequently fill one of the pair of adjacent two color resists;
  • a patterning process is performed on the second insulating layer to form at least one second via hole penetrating the second insulating layer, and the position of the at least one second via hole is the same as the position of the at least one first via hole
  • the width of each of the at least one second via in a direction parallel to the base substrate is greater than the width of the corresponding first via, and each of the at least one second via is used for subsequent Fill the color resist with the same color as the color resist in the first via hole at the corresponding position.
  • performing a patterning process on the third insulating layer to form at least one first via hole penetrating the third insulating layer includes:
  • Carbon tetrafluoride and oxygen are used to etch the third insulating layer to form the at least one first via hole penetrating the third insulating layer.
  • the angle between the sidewall of each of the at least one preliminary via hole and the direction parallel to the base substrate is greater than 70°, and the thickness of the photoresist is greater than 1.8 microns.
  • performing a patterning process on the second insulating layer to form at least one second via hole penetrating the second insulating layer includes:
  • the photoresist is removed by a lift-off process.
  • silicon oxide is used to make each of the first insulating layer and the third insulating layer
  • silicon nitride is used to make the second insulating layer
  • each of the first insulating layer and the third insulating layer is formed to have a thickness of 0.1 ⁇ m to 0.2 ⁇ m, and the second insulating layer is formed to have a thickness of 0.03 ⁇ m to 0.05 ⁇ m. Micron thickness.
  • each of the at least first via holes is formed to have a rectangular cross section, and each of the at least one second via holes is formed to have Rectangular cross section.
  • FIG. 1 is a schematic diagram of an array substrate in the related art after a color resist is set, overlapping of adjacent color resists causes a planarization layer located above the color resist to easily fall off;
  • FIG. 2 is a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of the array substrate according to an embodiment of the present disclosure when the first via hole and the second via hole are not fabricated;
  • FIG. 6 is a schematic structural diagram of the array substrate according to an embodiment of the present disclosure when manufacturing the first via hole and the second via hole;
  • FIG. 7 is a schematic diagram of the positional relationship and size relationship of the first via hole and the second via hole of the array substrate according to an embodiment of the present disclosure.
  • OLED organic light-emitting diode
  • COA Color Filter On Array
  • the color film layer is disposed on the inorganic film included in the array substrate, and then the color film layer is flattened. Floor. Because the color film layer is formed on the inorganic film and has a thicker thickness, it protrudes above the inorganic film. In order to ensure the planarization effect, the subsequently formed organic film planarization layer has a larger thickness, which reduces the light transmittance of the opening area. Moreover, in order to prevent light leakage, the edges between two adjacent color resists of different colors of the color film layer are currently overlapped with each other, as shown in FIG. 1. FIG.
  • the thickness of the color film layer at the overlapping position is relatively thick, so that the formation is flat
  • the thickness of the flattening layer at the overlapping position is relatively thin, so that the flattening layer 16 has a small thickness at the overlapping position and is easy to crack, which easily causes the problem of the flattening layer 16 to fall off and reduces the array The reliability of the substrate.
  • an embodiment of the present disclosure provides an array substrate, as shown in FIG. 2.
  • the array substrate includes a base substrate 1, a semiconductor active layer 21, a gate insulating layer 3, a gate 4, an interlayer insulating layer 5, a source 6 and a drain 7 which are sequentially located on the base substrate 1.
  • the array substrate further includes: a first insulating layer 8, a second insulating layer 9, a third insulating layer 10, at least one first via hole 11 and at least one second via hole 12.
  • the first insulating layer 8, the second insulating layer 9 and the third insulating layer 10 are sequentially disposed on the base substrate 1 where the source electrode 6 and the drain electrode 7 are provided.
  • the at least one first via 11 and the at least one second via 12 may correspond one to one, and each of the at least one first via 11 and the corresponding second via 12 is perpendicular to the substrate.
  • the directions of the substrates 1 may overlap each other.
  • each of the at least one first via hole 11 and the corresponding second via hole 12 communicate with each other, so that they are filled with color resists of the same color.
  • each first via hole 11 penetrates the third insulating layer 10, and in each pixel unit provided with a plurality of color resists 13, 14 and 15 (see FIG. 3), each first The via hole 11 is located between a pair of two adjacent color resists (for example, between two adjacent color resists 13 and 14 or between two adjacent color resists 14 and 15, as shown in FIG. 3) for One of the pair of adjacent two color resists is subsequently filled.
  • Each second via hole 12 penetrates through the second insulating layer 9, and the position of each second via hole 12 corresponds to the position of one first via hole 11 (for example, each second via hole 12 corresponds to a first via hole 11 In a direction perpendicular to the base substrate 1 (for example, the vertical direction in FIGS.
  • each second via hole 12 is greater than the width of the corresponding first via hole 11, and each second via hole 12 is used for subsequent filling and color resistance in the first via hole 11 at the corresponding position Color resists of the same color.
  • the array substrate provided by the embodiment of the present disclosure is provided with a first insulating layer 8, a second insulating layer 9 and a third insulating layer 10 in sequence on a base substrate 1 provided with a source electrode 6 and a drain electrode 7, and is provided with a penetrating first insulating layer
  • the at least one first via hole 11 of the three insulating layer 10 penetrates the at least one second via hole 12 of the second insulating layer 9.
  • each first via 11 is located between a pair of adjacent two color resistors (in other words, each first via 11 is located between two adjacent pixels Between units)
  • the position of each second via hole 12 corresponds to the position of one first via hole 11
  • the width of each second via hole 12 in the direction parallel to the base substrate 1 is greater than that of the corresponding first via hole 12
  • the width of the via hole 11 so when multiple color resistors are subsequently provided, one of the two adjacent color resistors in the pair can fill each first via hole 11 and the corresponding second via hole 12 , Thereby forming an overlap area a1 with another color resist (see FIG. 3).
  • the array substrate of this embodiment does not need to form a color resist overlapping area for preventing light leakage at the edge position of the adjacent color resist in the color filter layer (as shown in FIG. 1), so in this embodiment
  • the thickness of the planarization layer is relatively uniform and does not easily fall off.
  • the array substrate may further include a light shielding layer 2 on the base substrate 1 and a buffer layer 20 on the light shielding layer 2.
  • the light-shielding layer 2 may be located between the base substrate 1 and the semiconductor active layer 21 for shielding light irradiated to the semiconductor active layer 21 to prevent the performance of the semiconductor active layer 21 from being reduced.
  • the orthographic projection of the light-shielding layer 2 on the base substrate 1 can at least completely cover the orthographic projection of the semiconductor active layer 21 on the base substrate 1, so that the light-shielding layer 2 can effectively shield the semiconductor active layer 21.
  • the buffer layer 20 may be located between the light shielding layer 2 and the semiconductor active layer 21.
  • the second insulating layer 9 and the third insulating layer 10 need to be etched during the manufacturing process, and the second insulating layer 9 cannot be etched.
  • the insulating layer 10 exerts an influence.
  • the third insulating layer 10 is etched, the second insulating layer 9 cannot be affected.
  • the material of the first insulating layer 8 and the third insulating layer 10 is silicon oxide, and the material of the second insulating layer 9 is silicon nitride.
  • each first via 11 coincides with the central axis AA' of the corresponding second via 12, as shown in FIG.
  • the width D1 of each first via hole 11 It is 6 microns to 10 microns.
  • each first via hole 11 in a direction parallel to the base substrate 1 (ie, the horizontal direction in the figure), and on the same central axis AA' of each first via hole 11 On the side (for example, on the left side of the central axis of the first via 11), the distance D2 between the side of the corresponding second via 12 and the side of the first via 11 is 8 to 12 microns.
  • the color resist material filled in each of the first via hole 11 and the corresponding second via hole 12 can effectively prevent the light leakage phenomenon between two adjacent color resists corresponding to it.
  • the size of each first via 11 and the corresponding second via 12 can also be adjusted according to different design needs based on the present disclosure.
  • each first via hole 11 in a direction perpendicular to the base substrate 1, the cross section of each first via hole 11 is elongated, and the cross section of the corresponding second via hole 12 is elongated.
  • the sidewalls of each first via hole 11 and the corresponding second via hole 12 may be perpendicular to Base substrate 1.
  • the cross section of each first via 11 in the direction perpendicular to the base substrate 1, may be rectangular, and the cross section of the corresponding second via 12 may be rectangular.
  • the array substrate further includes: a color filter layer on the third insulating layer 10.
  • the color film layer may include a red color resist 13, a green color resist 14 and a blue color resist 15 in each pixel unit.
  • the at least one first via 11 includes two first vias 11, and the at least one second via 12 includes two second vias 12.
  • a first via hole 11 and a second via hole 12 at a corresponding position of the first via hole 11 are filled with a blue color resist 15, another first via hole 11 and the first via hole 11
  • the second via hole 12 at the corresponding position of the hole 11 is filled with a red color resist 13.
  • the color film layer includes three color resists in each pixel unit: red color resist 13, green color resist 14 and blue color resist 15 as an example, but the present disclosure is not limited to this.
  • the number of color resists included in each pixel unit of the color film layer may be less than 3 or greater than 3, as long as a first via 11 and a corresponding second via 11 are formed between two adjacent color resists. Hole 12 is enough.
  • the array substrate further includes a planarization layer 16, which is disposed on the color filter layer. Since the edge positions of the red color resist 13, the green color resist 14 and the blue color resist 15 in the embodiment of the present disclosure do not overlap each other in the color film layer, when the planarization layer 16 is provided, the planarization layer 16 is only The red color resist 13, the green color resist 14, and the blue color resist 15 need to be flattened. Therefore, the planarization layer 16 has better flatness, is not easy to cause the problem of falling off, and improves the reliability of the array substrate.
  • the array substrate may further include a first contact hole V1, a second contact hole V2, and a third contact hole V3.
  • the first contact hole V1 penetrates the interlayer insulating layer 5 and is used to connect the source electrode 6 to the semiconductor active layer 21.
  • the second contact hole V2 penetrates the interlayer insulating layer 5 and is used to connect the drain 7 to the semiconductor active layer 21.
  • the third contact hole V3 penetrates the interlayer insulating layer 5 and the buffer layer 20, and is used to further connect the source electrode 6 to the light shielding layer 2 to prevent charges from accumulating on the light shielding layer 2 to become another gate.
  • a first process provided by the embodiment of the present disclosure is provided between the red color resistor 13 and the green color resistor 14, and between the green color resistor 14 and the blue color resistor 15. Hole 11 and a corresponding second via hole 12. Therefore, when the red color resistor 13 and the blue color resistor 15 are set, the red color resistor 13 and the blue color resistor 15 will flow into the corresponding first via hole 11 and the corresponding second In the two via holes 12, a color resist overlapping area a1 is further formed under the green color resist 14.
  • the color resists on both sides are indented so as not to differ from the green color resist 14 in the middle.
  • the middle color resist ie, the green resist 14
  • the middle color resist does not need to be indented.
  • two color resist overlapping areas a1 are formed. Since two color resist overlapping areas a1 are formed, light leakage can be prevented, and the red color resist 13, the green color resist 14 and the blue color resist 15 are not formed between the color resists of the related art shown in FIG. 1
  • the overlap makes the planarization layer 16 have a relatively uniform thickness, avoids the problem of the planarization layer 16 falling off, and improves the reliability of the array substrate.
  • an embodiment of the present disclosure provides a display panel including the array substrate of the first aspect. Since the display panel of the second aspect includes the array substrate of the first aspect, the display panel has the same beneficial effects as the array substrate. Therefore, the beneficial effects of the second aspect of the display panel will not be repeated here.
  • the display panel may further include a pixel driving circuit to drive each pixel unit of the array substrate to display information, and the pixel driving circuit may be a conventional pixel driving circuit.
  • embodiments of the present disclosure provide a display device including the display panel of the second aspect. Since the display device of the third aspect includes the display panel of the second aspect, the display device has the same beneficial effects as the display panel. Therefore, the beneficial effects of the display device of the third aspect will not be repeated here.
  • the display device may also include a touch panel and other known components arranged on the light emitting side of the display panel.
  • FIG. 4 is a flowchart of a manufacturing method of an array substrate according to an embodiment of the disclosure. As shown in FIG. 4, the manufacturing method of the array substrate may include the following steps S101 to S104.
  • Step S101 The semiconductor active layer 21, the gate insulating layer 3, the gate 4, the interlayer insulating layer 5, the source 6 and the drain 7 are sequentially fabricated on the base substrate 1 through a patterning process.
  • Step S102 the first insulating layer 8, the second insulating layer 9 and the third insulating layer 10 are sequentially formed on the base substrate 1 on which the source electrode 6 and the drain electrode 7 are formed.
  • Step S103 Perform a patterning process on the third insulating layer 10 to form at least one first via 11 penetrating the third insulating layer 10, and in each pixel unit provided with color resists 13, 14, 15 (see Figure 3), each of the first via holes is located between a pair of adjacent color resistors 13 and 14 or between a pair of adjacent color resistors 14 and 15 for subsequent filling of the pair of adjacent One of two color resists.
  • Step S104 Perform a patterning process on the second insulating layer 9 to form at least one second via 12 penetrating through the second insulating layer 9, and the position of the at least one second via 12 is the same as that of the at least one first via
  • the positions of 11 correspond to each other, and the width of each second via 12 in the direction parallel to the base substrate 1 is greater than the width of the corresponding first via 11, and each second via 12 is used for subsequent filling and
  • the color resists in the first via hole 11 at the corresponding position have the same color.
  • performing a patterning process on the third insulating layer 10 in S103 to form at least one first via 11 penetrating the third insulating layer 10 may include the following steps S103a and S103b.
  • Step S103a coating photoresist 17 on the third insulating layer 10, and removing the photoresist part above the position where the at least one first via hole 11 needs to be formed by exposure and development to form at least one preliminary pass.
  • Hole V4 as shown in Figure 6.
  • Step S103b using carbon tetrafluoride and oxygen to etch the third insulating layer 10 to form the at least one first via 11 penetrating the third insulating layer 10.
  • each first via 11 and the corresponding second via 12 needs to be formed into a strip shape (for example, a rectangle)
  • each first via At the corresponding position 11, the angle A11 between the sidewall of the preliminary via hole V4 in the photoresist 17 and the third insulating layer (for example, the horizontal direction in the figure) is greater than 70° (further optionally greater than 80°)
  • the thickness of the photoresist is greater than 1.8 microns (further optionally greater than 2.0 microns).
  • other angles and thicknesses can be set according to design requirements based on the present disclosure.
  • performing a patterning process on the second insulating layer 9 in step S104 to form at least one second via 12 penetrating the second insulating layer 10 may include the following steps S104a and S104b.
  • Step S104a using sulfur hexafluoride and oxygen to etch the second insulating layer 9 to form the at least second via hole 12 penetrating the second insulating layer 9.
  • Step S104b removing the remaining photoresist through a stripping process.
  • a metal layer is deposited on the base substrate 1 (for example, a glass substrate), where the material of the metal layer can be a metal such as molybdenum or molybdenum-niobium alloy, and the thickness of the metal layer It is 0.10 microns to 0.15 microns.
  • a thin film transistor (TFT) area located on the array substrate is formed by photolithography and wet etching (for example, the area of the array substrate of FIG. 2 including the semiconductor active layer 21, the gate 4, the source 6 and the drain 7) In the light-shielding layer 2.
  • TFT thin film transistor
  • a mixed acid for example, a mixed acid in which nitric acid and hydrochloric acid are mixed in a certain ratio
  • a buffer layer 20 is deposited, wherein the material of the buffer layer 20 may be silicon oxide with a thickness of 0.3 ⁇ m to 0.5 ⁇ m.
  • a thin film of indium gallium zinc oxide (IGZO) is deposited, and a semiconductor active layer 21 is formed by photolithography and wet etching.
  • the thickness of the semiconductor active layer 21 is 0.05 micrometers to 0.1 micrometers.
  • an insulating layer is deposited, the material of which can be silicon oxide, and the thickness is 0.1 ⁇ m to 0.2 ⁇ m.
  • a layer of metal is deposited.
  • the metal can be a metal such as copper with a thickness of 0.4 ⁇ m to 0.5 ⁇ m.
  • a patterning process is used to form the gate electrode 4 and the gate wiring pattern.
  • the gate mask is retained for dry etching of the insulating layer to form the gate insulating layer 3.
  • carbon tetrafluoride + oxygen dry etching mixed gas can be used for etching
  • the flow rate of carbon tetrafluoride can be 2000 standard ml/min ⁇ 2500 standard ml/min
  • the semiconductor active layer 21 at the contact position with the source 6 and the drain 7 and the capacitor region (for example, the semiconductor active layer 21 at the contact position with the source 6 and the semiconductor.
  • the portion between the left end of the source layer 21 and/or the portion between the position of the semiconductor active layer 21 that is in contact with the drain electrode 7 and the right end of the semiconductor active layer 21) of the IGZO film is subjected to conductive treatment to reduce the IGZO film The resistance.
  • the conductorization treatment can use ammonia or helium gas to perform plasma injection on the IGZO film, and after the conductorization treatment is completed, the remaining gate mask is stripped.
  • a layer of interlayer insulating layer 5 is deposited, where the interlayer insulating layer 5 may be silicon oxide with a thickness of 0.45 ⁇ m to 0.6 ⁇ m.
  • the interlayer insulating layer 5 (and the buffer layer 20) is dry-etched using a mask to form the first to third contact holes V1, V2, and V3, so that the source electrode 6 formed subsequently passes through the first
  • the contact hole V1 is connected to the semiconductor active layer 21, the subsequently formed drain 7 is connected to the semiconductor active layer 21 through the second contact hole V2, and the source 6 is connected to the light shielding layer 2 through the third contact hole V3.
  • a layer of metal is deposited.
  • the metal can be a metal such as copper or aluminum with a thickness of 0.5 ⁇ m to 0.7 ⁇ m.
  • the source electrode 6 and the drain electrode 7 are formed through a patterning process.
  • first insulating layer 8 and the third insulating layer 10 may be silicon oxide, and the second insulating layer 9 may be silicon nitride .
  • the thickness of each of the first insulating layer 8 and the third insulating layer 10 is 0.1 micrometers to 0.2 micrometers, and the thickness of the second insulating layer 9 is 0.03 micrometers to 0.05 micrometers. In this way, it is advantageous to form at least one first via 11 and at least one second via 12 as described above. So far, the structure formed by this method is shown in FIG. 5.
  • each pixel unit includes a red color resist 13, a green color resist 14 and The blue color resist 15 is taken as an example, so each pixel unit may include two overlapping strips a1.
  • each first via hole 11 and the corresponding second via hole 12 can be etched into a state perpendicular to the base substrate 1 (for example, each first via hole 11
  • the corresponding second via hole 12 is rectangular in cross section perpendicular to the base substrate 1).
  • the sidewall of the preliminary via V4 in the photoresist 17 is sandwiched between the third insulating layer 10 (for example, the horizontal direction in FIG. 6)
  • the angle A11 is 70° or more (optionally 80° or more), and the thickness T1 of the photoresist 17 is larger than 1.8 ⁇ m (further alternatively larger than 2.0 ⁇ m).
  • the third insulating layer 10 is etched using carbon tetrafluoride and oxygen, as well as high source power and high bias power. Due to the large angle between the sidewall of the preliminary via hole V4 in the photoresist 17 and the third insulating layer 10 and the thicker thickness of the photoresist 17, dry etching can only etch the third insulating layer 10 in the vertical direction , The at least one first via hole 11 is formed. Then, the second insulating layer 9 is etched using sulfur hexafluoride and oxygen, as well as high source power and low or no bias power.
  • this dry etching is similar to wet etching and has no etching effect on the first insulating layer 8 and the third insulating layer 10 , And has a strong etching effect on the second insulating layer 9. Therefore, the at least one elongated second via hole 12 can be etched in the second insulating layer 9, and in the horizontal direction, the width of each second via hole 12 etched can be larger than the corresponding The width of the first via hole 11.
  • the process of stroke color film layer can be executed later.
  • the blue color resist 15, the red color resist 13 and the green color resist 14 can be made in sequence, as shown in FIG. 3. Since the first via 11 and the second via 12 are formed, after the process of the blue color resist 15 and the red color resist 13 is completed, the blue color resist 15 will flow to the corresponding first via 11 and the corresponding second via 12 A color resist overlap area a1 is formed inside, and the red color resist 13 will flow into the corresponding first via 11 and the corresponding second via 12 to form another color resist overlap area a1. In this way, the green color resist 14 does not need to be formed to overlap with the adjacent blue color resist 15 and the red color resist 13 in the color film layer to prevent light leakage.
  • the array substrate and the manufacturing method thereof, the display panel and the display device provided by the embodiments of the present disclosure can at least obtain the following beneficial technical effects.
  • the array substrate provided by the embodiment of the present disclosure is provided with a first insulating layer, a second insulating layer, and a third insulating layer in sequence on a base substrate where the source electrode and the drain electrode are provided, and at least one insulating layer penetrating the third insulating layer is provided.
  • the first via hole, at least one second via hole penetrating the second insulating layer because in each pixel unit provided with multiple color resistors, each first via hole is located between a pair of adjacent two color resistors In between, the position of each second via corresponds to the position of a first via, and the width of each second via in the direction parallel to the base substrate is greater than the width of the corresponding first via.
  • one color resist When multiple color resists are subsequently set, in a pair of adjacent color resists, one color resist can fill a first via hole and a corresponding second via, and can form an intersection with another color resist. Stack area. Compared with the related art, in the present disclosure, there is no need to overlap the color resistance at the edge position of the color resistance in the color film layer to prevent light leakage. Therefore, after the flattening layer is provided on the color film layer, the thickness of the flattening layer is Relatively uniform and not easy to fall off.

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Abstract

本公开实施例提供了一种阵列基板，包括衬底基板、依次位于衬底基板上的半导体有源层、栅极、以及源极和漏极，其中，所述阵列基板还包括：第一绝缘层、第二绝缘层、第三绝缘层、至少一个第一过孔和至少一个第二过孔；所述第一绝缘层、所述第二绝缘层和所述第三绝缘层依次设置在设置有所述源极和所述漏极的衬底基板上；每一个所述至少一个第一过孔贯穿所述第三绝缘层，且在设置有多个彩色色阻的每一像素单元中，每一个所述至少一个第一过孔位于一对相邻两彩色色阻之间，用于后续填充所述一对相邻两彩色色阻中的一个；以及每一个所述至少一个第二过孔贯穿所述第二绝缘层，所述至少一个第二过孔的位置与所述至少一个第一过孔的位置一一对应，且在平行于所述衬底基板的方向上每一个所述至少一个第二过孔的宽度大于对应的第一过孔的宽度，每一个所述至少一个第二过孔用于后续填充与对应位置处的所述第一过孔内的彩色色阻的颜色相同的彩色色阻。

Description

阵列基板及其制造方法、显示面板和显示装置
相关申请的交叉引用
本申请要求于2019年4月23日提交的中国专利申请No.201910330130.4的优先权，该专利申请的全部内容通过引用方式合并于此。
技术领域
本公开涉及显示技术领域，具体为阵列基板及其制造方法、显示面板和显示装置。
背景技术
有机发光二极管(OLED)显示装置可以包括作为发光器件的多个OLED和用于驱动所述多个OLED进行显示的晶体管(例如，薄膜晶体管)。晶体管可以包括顶栅型晶体管和底栅型晶体管，相应地，OLED显示装置包括顶栅型OLED显示装置和底栅型OLED显示装置。近些年来，大尺寸顶栅型OLED显示装置由于比大尺寸底栅型OLED显示装置具有更高的开态(on-state)电流(Ion)、更高的开口率和更好的阵列基板稳定性而受到关注。
发明内容
在第一方面中，本公开的实施例提供了一种阵列基板，包括；衬底基板、依次位于衬底基板上的半导体有源层、栅极、以及源极和漏极，其中，所述阵列基板还包括：第一绝缘层、第二绝缘层、第三绝缘层、至少一个第一过孔和至少一个第二过孔；
所述第一绝缘层、所述第二绝缘层和所述第三绝缘层依次设置在设置有所述源极和所述漏极的衬底基板上；
每一个所述至少一个第一过孔贯穿所述第三绝缘层，且在设置 有多个彩色色阻的每一像素单元中，每一个所述至少一个第一过孔位于一对相邻两彩色色阻之间，用于后续填充所述一对相邻两彩色色阻中的一个；以及
每一个所述至少一个第二过孔贯穿所述第二绝缘层，所述至少一个第二过孔的位置与所述至少一个第一过孔的位置一一对应，且在平行于所述衬底基板的方向上每一个所述至少一个第二过孔的宽度大于对应的第一过孔的宽度，每一个所述至少一个第二过孔用于后续填充与对应位置处的所述第一过孔内的彩色色阻的颜色相同的彩色色阻。
在一个实施例中，所述第一绝缘层和第三绝缘层的材料为氧化硅，所述第二绝缘层的材料为氮化硅。
在一个实施例中，在垂直于所述衬底基板方向上，每一个所述至少一个第一过孔的中心轴与对应的第二过孔的中心轴重合。
在一个实施例中，在平行于所述衬底基板的方向上，每一个所述至少一个第一过孔的宽度为6微米到10微米。
在一个实施例中，在平行于所述衬底基板的方向上，且在每一个所述至少一个第一过孔的中心轴的同一侧，对应的第二过孔的侧边与该第一过孔的侧边之间的距离为8微米到12微米。
在一个实施例中，在垂直于所述衬底基板的方向上，每一个所述至少一个第一过孔的截面为长条状，每一个所述至少一个第二过孔的截面为长条状。
在一个实施例中，所述阵列基板还包括：彩膜层；其中，
所述彩膜层位于所述第三绝缘层上。
在一个实施例中，所述彩膜层在每一像素单元中包括红色色阻、绿色色阻和蓝色色阻；
在该像素单元中，所述至少一个第一过孔包括两个第一过孔，所述至少一个第二过孔包括两个第二过孔；以及
在该像素单元中，一个所述第一过孔和该第一过孔对应位置处的第二过孔内填充有蓝色色阻，另一个所述第一过孔和该第一过孔对应位置处的第二过孔内填充有红色色阻。
在一个实施例中，所述阵列基板还包括平坦化层，该平坦化层设置在所述彩膜层上。
在一个实施例中，在垂直于所述衬底基板的方向上，每一个所述至少第一过孔的截面为矩形，每一个所述至少一个第二过孔的截面为矩形。
在一个实施例中，所述第一绝缘层和所述第三绝缘层中的每一个的厚度为0.1微米至0.2微米，并且所述第二绝缘层的厚度为0.03微米至0.05微米。
在第二方面中，本公开的实施例提供了一种显示面板，包括如本公开的上述实施例中任一个所述的阵列基板。
在第三方面中，本公开的实施例提供了一种显示装置，包括如本公开的上述实施例所述的显示面板。
在第四方面中，本公开的实施例提供了一种阵列基板的制作方法，包括：
通过构图工艺在衬底基板上依次制作半导体有源层、栅极、以及源极和漏极；
在制作有所述源极和所述漏极的所述衬底基板上依次制作第一绝缘层、第二绝缘层和第三绝缘层；
对所述第三绝缘层进行构图工艺，以形成贯穿所述第三绝缘层的至少一个第一过孔，且在设置有多个彩色色阻的每一像素单元中，每一个所述至少一个第一过孔位于一对相邻两彩色色阻之间，用于后续填充所述一对相邻两彩色色阻中的一个；以及
对所述第二绝缘层进行构图工艺，以形成贯穿所述第二绝缘层的至少一个第二过孔，所述至少一个第二过孔的位置与所述至少一个第一过孔的位置一一对应，且在平行于所述衬底基板的方向上每一个所述至少一个第二过孔的宽度大于对应的第一过孔的宽度，每一个所述至少一个第二过孔用于后续填充与对应位置处的所述第一过孔内的彩色色阻的颜色相同的彩色色阻。
在一个实施例中，对所述第三绝缘层进行构图工艺，以形成贯穿所述第三绝缘层的至少一个第一过孔，包括：
在所述第三绝缘层上涂覆光刻胶，通过曝光、显影去除需要形成所述至少一个第一过孔位置上方的光刻胶的部分，以形成至少一个初步过孔；以及
采用四氟化碳和氧气，对所述第三绝缘层进行刻蚀，以形成贯穿所述第三绝缘层的所述至少一个第一过孔。
在一个实施例中，每一个所述至少一个初步过孔的侧壁与平行于所述衬底基板的方向之间的夹角大于70°，并且所述光刻胶的厚度大于1.8微米。
在一个实施例中，对所述第二绝缘层进行构图工艺，以形成贯穿所述第二绝缘层的至少一个第二过孔，包括：
采用六氟化硫和氧气，对所述第二绝缘层进行刻蚀，以形成贯穿所述第二绝缘层的所述至少一个第二过孔；以及
通过剥离工艺去除所述光刻胶。
在一个实施例中，采用氧化硅来制作所述第一绝缘层和第三绝缘层中的每一个，并且采用氮化硅来制作所述第二绝缘层。
在一个实施例中，将所述第一绝缘层和所述第三绝缘层中的每一个形成为具有0.1微米至0.2微米的厚度，并且将所述第二绝缘层形成为具有0.03微米至0.05微米的厚度。
在一个实施例中，在垂直于所述衬底基板的方向上，每一个所述至少第一过孔被形成为具有矩形的截面，并且每一个所述至少一个第二过孔被形成为具有矩形的截面。
附图说明
通过阅读下文可选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出可选实施方式的目的，而并不认为是对本公开实施例的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1为相关技术中的阵列基板在设置彩色色阻后，相邻彩色色阻的交叠导致位于彩色色阻的上方的平坦化层容易脱落的示意图；
图2为根据本公开实施例的阵列基板的结构示意图；
图3为根据本公开实施例的另一阵列基板的结构示意图；
图4为根据本公开实施例的阵列基板的制作方法的流程图；
图5为根据本公开实施例的阵列基板未制作第一过孔和第二过孔时的结构示意图；
图6为根据本公开实施例的阵列基板在制作第一过孔和第二过孔时的结构示意图；以及
图7为根据本公开实施例的阵列基板的第一过孔和第二过孔的位置关系和大小关系的示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
本技术领域技术人员可以理解，除非特意声明，否则这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、数值、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、数值、步骤、操作、元件、组件和/或它们的组。应该理解，当我们称元件被“连接”到另一元件时，它可以直接连接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”可以包括无线连接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
本技术领域技术人员可以理解，除非另外定义，否则这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与相关技术的上下文中的意义一致的意义，并且除非在本文中被特定定义，否则不应该用理想化或过于正式的含义来解释。
下面结合附图介绍本申请实施例的具体技术方案。
本公开的发明人发现，大尺寸有机发光二极管(OLED)显示装置目前采用COA(Color Filter On Array)技术，即将彩膜层设置在阵列基板包括的无机膜上，而后在彩膜层形成平坦化层。由于彩膜层形成于无机膜上，而且厚度较厚，突出于无机膜之上。为保证平坦化效果，随后形成的有机膜平坦化层具有较大的厚度，这样会降低开口区域的光透过率。而且，为防止漏光，目前会使彩膜层的不同颜色的两个相邻色阻之间的边缘互相交叠，如图1所示。图1中示出了位于衬底基板1上的蓝色色阻15与绿色色阻14交叠的情况。在保证满足彩膜层的色度和色规的要求的情况下，在蓝色色阻15与绿色色阻14交叠后，由于交叠位置的处彩膜层的厚度较厚，使得在形成平坦化层16时，交叠位置处的平坦化层的厚度较薄，使得平坦化层16在交叠位置处的厚度较小而容易破裂，从而容易导致平坦化层16脱落的问题，降低了阵列基板的可靠性。
在第一方面中，本公开实施例提供了一种阵列基板，如图2所示。该阵列基板包括：衬底基板1、依次位于衬底基板1上的半导体有源层21、栅极绝缘层3、栅极4、层间绝缘层5以及源极6和漏极7。此外，该阵列基板还包括：第一绝缘层8、第二绝缘层9、第三绝缘层10、至少一个第一过孔11和至少一个第二过孔12。第一绝缘层8、第二绝缘层9和第三绝缘层10依次设置在设置有源极6和漏极7的衬底基板1上。所述至少一个第一过孔11和所述至少一个第二过孔12可以一一对应，并且每一个所述至少一个第一过孔11和相对应的第二过孔12在垂直于衬底基板1的方向(例如，图2中的竖直方向)上可以互相重叠。此外，每一个所述至少一个第一过孔11和相对应的第二过孔12互相连通，以便它们被同一颜色的色阻填充。
如图2所示，每一个第一过孔11贯穿第三绝缘层10，且在设置有多个彩色色阻13、14和15(参见图3)的每一像素单元中，每一个第一过孔11位于一对相邻两彩色色阻之间(例如，位于相邻两彩色色阻13和14之间或相邻两彩色色阻14和15之间，如图3所示)，用于后续填充所述一对相邻两彩色色阻中的一个。每一个第二过孔 12贯穿第二绝缘层9，每一个第二过孔12的位置与一个第一过孔11的位置对应(例如，每一个第二过孔12与一个第一过孔11在垂直于衬底基板1的方向(例如，图2和图3中的竖直方向)上互相重叠)，且在平行于衬底基板1的方向(例如，图2和图3中的水平方向)上每一个第二过孔12的宽度大于对应的第一过孔11的宽度，每一个第二过孔12用于在后续填充与对应位置处的第一过孔11内的彩色色阻的颜色相同的彩色色阻。
本公开实施例提供的阵列基板在设置有源极6和漏极7的衬底基板1上依次设置有第一绝缘层8、第二绝缘层9和第三绝缘层10，且设置有贯穿第三绝缘层10的所述至少一个第一过孔11，贯穿第二绝缘层9的所述至少一个第二过孔12。由于在设置有多个彩色色阻的每一像素单元中，每一个第一过孔11位于一对相邻两彩色色阻之间(换言之，每一个第一过孔11位于相邻两个像素单元之间)，每一个第二过孔12的位置与一个第一过孔11的位置对应，且在平行于衬底基板1的方向上每一个第二过孔12的宽度大于对应的第一过孔11的宽度，因此在后续设置多个彩色色阻时，在所述一对相邻两彩色色阻中，其中一个可以填满每一个第一过孔11和对应的第二过孔12，从而可以与另一个彩色色阻形成交叠区a1(参见图3)。与相关技术相比，本实施例的阵列基板无需在彩膜层中的相邻色阻的边缘位置处形成用于防漏光的色阻交叠区(如图1所示)，因此在本实施例的阵列基板上设置平坦化层后，平坦化层的厚度相对均匀，不易脱落。
此外，如图2所示，该阵列基板还可以包括位于衬底基板1上的遮光层2，和位于遮光层2上的缓冲层20。遮光层2可以位于衬底基板1和半导体有源层21之间，用于遮挡照射到半导体有源层21的光线以防止半导体有源层21的性能降低。例如，遮光层2在衬底基板1上的正投影可以至少完全覆盖半导体有源层21在衬底基板1上的正投影，这样，遮光层2可以有效地遮挡照射到半导体有源层21的光线。缓冲层20可以位于遮光层2和半导体有源层21之间。
在一个实施例中，由于在制作过程时，需要对第二绝缘层9和第三绝缘层10均进行刻蚀工艺处理，且在对第二绝缘层9进行刻蚀 处理时，不能对第三绝缘层10产生影响。同样地，对第三绝缘层10进行刻蚀处理时，不能对第二绝缘层9产生影响。为此目的，在本实施例中，第一绝缘层8和第三绝缘层10的材料为氧化硅，第二绝缘层9的材料为氮化硅。
在一个实施例中，在后续设置多个彩色色阻(其在固化之前呈液态)时，为了能够使得彩色色阻更好地流入到每一个第一过孔11和对应的第二过孔中，在本实施例中，在垂直于衬底基板1方向上，每一个第一过孔11的中心轴AA’与对应的第二过孔12的中心轴AA’重合，如图7所示。
在一个实施例中，如图2和图7所示，在本实施例中，在平行于衬底基板1的方向(即图中的水平方向)上，每一个第一过孔11的宽度D1为6微米到10微米。
在一个实施例中，如图2和图7所示，在平行于衬底基板1的方向(即图中的水平方向)上，且在每一个第一过孔11的中心轴AA’的同一侧(如在该第一过孔11的中心轴的左侧)，对应的第二过孔12的侧边与该第一过孔11的侧边之间的距离D2为8微米到12微米。这样，填充在每一个第一过孔11和对应的第二过孔12中的色阻材料可以有效地防止其所对应的相邻两个彩色色阻之间的漏光现象。但是，对于本领域技术人员而言，也可以基于本公开根据不同设计需要调整每一个第一过孔11和对应的第二过孔12的尺寸。
在一个实施例中，在垂直于衬底基板1的方向上，每一个第一过孔11的截面为长条状，对应的第二过孔12的截面为长条状。。考虑到色阻的流动性以及色阻容易填充每一个第一过孔11和对应的第二过孔12，每一个第一过孔11和对应的第二过孔12的侧壁可以分别垂直于衬底基板1。换言之，在垂直于衬底基板1的方向上，每一个第一过孔11的截面可以为矩形，对应的第二过孔12的截面可以为矩形。
在一个实施例中，如图3所示，在本实施例中，该阵列基板还包括：位于第三绝缘层10上的彩膜层。例如，彩膜层在每一个像素单元中可以包括：红色色阻13、绿色色阻14和蓝色色阻15。在此情 况下，在该像素单元中，所述至少一个第一过孔11包括两个第一过孔11，所述至少一个第二过孔12包括两个第二过孔12。此外，在该像素单元中，一个第一过孔11和该第一过孔11对应位置处的第二过孔12内填充有蓝色色阻15，另一个第一过孔11和该第一过孔11对应位置处的第二过孔12内填充有红色色阻13。应当理解的是，本实施例以彩膜层在每一个像素单元中包括红色色阻13、绿色色阻14和蓝色色阻15总共三个色阻为例，然而本公开并不限于此。例如，彩膜层在每一个像素单元中包括的彩色色阻的数量可以小于3或者大于3，只要在相邻两个彩色色阻之间形成一个第一过孔11和一个对应的第二过孔12即可。
在一个实施例中，如图3所示，阵列基板还包括平坦化层16，其设置在彩膜层上。由于本公开实施例的红色色阻13、绿色色阻14和蓝色色阻15的边缘位置处并不会在彩膜层中彼此交叠，使得在设置平坦化层16时，平坦化层16仅需对红色色阻13、绿色色阻14和蓝色色阻15进行平坦化。因此，平坦化层16具有更好的平坦度，不容易产生脱落的问题，提高了阵列基板的可靠性。
此外，如图2所示，所述阵列基板还可以包括第一接触孔V1、第二接触孔V2和第三接触孔V3。第一接触孔V1贯穿层间绝缘层5，用于将源极6连接至半导体有源层21。第二接触孔V2贯穿层间绝缘层5，用于将漏极7连接至半导体有源层21。第三接触孔V3贯穿层间绝缘层5和缓冲层20，用于将源极6进一步连接至遮光层2，以防止遮光层2上聚集电荷而成为另外的栅极。
进一步参考图3，在每一个像素单元中，由于红色色阻13和绿色色阻14之间，以及绿色色阻14和蓝色色阻15之间分别设置了本公开实施例提供的一个第一过孔11和一个对应的第二过孔12，因此，在设置红色色阻13和蓝色色阻15时，红色色阻13和蓝色色阻15会流入到对应的第一过孔11和对应的第二过孔12内，进而在绿色色阻14下方形成色阻交叠区域a1。即，红色色阻13、绿色色阻14和蓝色色阻15中，两侧的彩色色阻(即，红色色阻13和蓝色色阻15)缩进以便不分别与位于中间的绿色色阻14交叠，转而分别填满对应 的第一过孔11和对应的第二过孔12，中间彩色色阻(即，绿色色阻14)无需进行缩进。这样，形成了两个色阻交叠区域a1。由于形成有两个色阻交叠区域a1，能够阻止漏光的产生，同时红色色阻13、绿色色阻14和蓝色色阻15之间并未形成图1所示的相关技术的彩色色阻间的交叠，使得平坦化层16具有相对均匀的厚度，避免产生平坦化层16脱落的问题，提高了阵列基板的可靠性。
在第二方面中，本公开实施例提供了一种显示面板，该显示面板包括第一方面的阵列基板。由于第二方面的显示面板包括了第一方面的阵列基板，使得显示面板具有与阵列基板相同的有益效果。因此，在此不再重复赘述第二方面的显示面板的有益效果。此外，该显示面板还可以包括像素驱动电路，以驱动阵列基板的各个像素单元进行显示信息，该像素驱动电路可以是常规的像素驱动电路。
在第三方面中，本公开实施例提供了一种显示装置，该显示装置包括第二方面的显示面板。由于第三方面的显示装置包括了第二方面的显示面板，使得该显示装置具有与显示面板相同的有益效果。因此，在此不再重复赘述第三方面的显示装置的有益效果。此外，该显示装置还可以包括设置在显示面板的出光侧的触控面板和其他已知的组件。
在第四方面中，图4为本公开实施例的阵列基板的制作方法的流程图。如图4所示，该阵列基板的制作方法可以包括以下步骤S101至S104。
步骤S101：通过构图工艺在衬底基板1上依次制作半导体有源层21、栅极绝缘层3、栅极4、层间绝缘层5以及源极6和漏极7。
步骤S102：在制作有源极6和漏极7的衬底基板1上依次制作第一绝缘层8、第二绝缘层9和第三绝缘层10。
步骤S103：对第三绝缘层10进行构图工艺，以形成贯穿第三绝缘层10的至少一个第一过孔11，且在设置有彩色色阻13、14、15的每一像素单元中(参见图3)，每一个所述第一过孔位于一对相邻两彩色色阻13和14之间或一对相邻两彩色色阻14和15之间，用于后续填充所述一对相邻两彩色色阻中的一个。
步骤S104：对第二绝缘层9进行构图工艺，以形成贯穿第二绝缘层9的至少一个第二过孔12，所述至少一个第二过孔12的位置与所述至少一个第一过孔11的位置一一对应，且在平行于衬底基板1的方向上每一个第二过孔12的宽度大于对应的第一过孔11的宽度，每一个第二过孔12用于后续填充与对应位置处的第一过孔11内的彩色色阻的颜色相同的彩色色阻。
在一个实施例中，S103中对第三绝缘层10进行构图工艺，以形成贯穿第三绝缘层10的至少一个第一过孔11可以包括以下步骤S103a和S103b。
步骤S103a、在第三绝缘层10上涂覆光刻胶17，通过曝光、显影去除需要形成所述至少一个第一过孔11的位置处的上方的光刻胶部分，以形成至少一个初步过孔V4，如图6所示。
步骤S103b、采用四氟化碳和氧气，对第三绝缘层10进行刻蚀，以形成贯穿第三绝缘层10的所述至少一个第一过孔11。
如上所述，在本实施例中，由于需要将每一个第一过孔11和对应的第二过孔12的截面都形成为长条状(例如，矩形)，因此在每一个第一过孔11对应位置处，光刻胶17中的初步过孔V4的侧壁与第三绝缘层(例如，图中的水平方向)之间的夹角A11大于70°(进一步可选地大于80°)，光刻胶的厚度大于1.8微米(进一步可选地大于2.0微米)。但是，对于本领域技术人员而言，可以基于本公开根据设计需要设置其他角度和厚度。
在一个实施例中，步骤S104中对第二绝缘层9进行构图工艺，以形成贯穿第二绝缘层10的至少一个第二过孔12可以包括以下步骤S104a和S104b。
步骤S104a、采用六氟化硫和氧气，对第二绝缘层9进行刻蚀，以形成贯穿第二绝缘层9的所述至少第二过孔12。
步骤S104b、通过剥离工艺去除剩余的光刻胶。
以下通过参考图5和图6来进一步说明本公开实施例的阵列基板的制作过程。
如图5所示，在一个实施例中，在衬底基板1(例如玻璃基板) 上沉积一金属层，其中，金属层的材料可以为钼或钼铌合金等金属，并且该金属层的厚度为0.10微米～0.15微米。接着，通过光刻、湿刻形成位于阵列基板的薄膜晶体管(TFT)的区域(例如，图2的阵列基板的包括半导体有源层21、栅极4、源极6和漏极7的区域)中的遮光层2。湿刻工艺可用混酸(例如，硝酸和盐酸按一定比例混合的混酸)进行刻蚀。随后沉积一层缓冲层20，其中，缓冲层20的材料可以为氧化硅，厚度0.3微米～0.5微米。
之后，沉积铟稼锌氧化物(IGZO)薄膜，并通过光刻、湿刻形成半导体有源层21，该半导体有源层21的厚度0.05微米～0.1微米。接着，沉积一层绝缘层，其材料可为氧化硅，厚度0.1微米～0.2微米。接着，沉积一层金属，金属可为铜等金属，厚度为0.4微米～0.5微米，随后通过构图工艺形成栅极4以及栅极走线图形。在对栅极4湿刻完成后，保留栅极掩膜进行绝缘层的干刻，形成栅极绝缘层3。在一个实施例中，可采用四氟化碳+氧气干刻混合气体进行刻蚀，四氟化碳流量可为2000标准毫升/分钟～2500标准毫升/分钟，氧气的流量1000标准毫升/分钟～1500标准毫升/分钟。
形成栅极绝缘层3后，继续对与源极6和漏极7接触位置处的半导体有源层21，以及电容区(例如，半导体有源层21的与源极6接触的位置与半导体有源层21的左端之间的部分和/或半导体有源层21的与漏极7接触的位置与半导体有源层21的右端之间的部分)的IGZO薄膜进行导体化处理，以降低IGZO薄膜的电阻。此处导体化处理可用氨气或者氦气对IGZO薄膜进行等离子体注入，在导体化处理完成后对剩余的栅极掩膜进行剥离。接着，沉积一层层间绝缘层5，其中，层间绝缘层5可以为氧化硅，厚度为0.45微米～0.6微米。随后利用掩膜对层间绝缘层5(和缓冲层20)进行接触孔干法刻蚀，形成所述第一至第三接触孔V1、V2和V3，以便后续形成的源极6通过第一接触孔V1与半导体有源层21连接，后续形成的漏极7通过第二接触孔V2与半导体有源层21连接，并且源极6通过第三接触孔V3与遮光层2连接。然后沉积一层金属，金属可为铜和铝等金属，厚度为0.5微米～0.7微米，通过构图工艺形成源极6和漏极7。
接着，依次沉积第一绝缘层8、第二绝缘层9和第三绝缘层10，其中，第一绝缘层8和第三绝缘层10可以为氧化硅，第二绝缘层9可以为氮化硅。第一绝缘层8和第三绝缘层10中的每一个的厚度为0.1微米～0.2微米，第二绝缘层9的厚度为0.03微米～0.05微米。这样，有利于形成如上所述的至少一个第一过孔11和至少一个第二过孔12。至此，该方法所形成的结构如图5所示。
如图6所示，接着，在第三绝缘层10上涂覆一层光刻胶17，通过曝光、显影去除需要形成第一过孔11位置上方的光刻胶的部分，以形成至少一个初步过孔V4。在本实施例中，由于需要相邻两彩色色阻交叠以防止该相邻两彩色色阻之间发生漏光，本公开实施例以每个像素单元包括红色色阻13、绿色色阻14和蓝色色阻15为例，因此每个像素单元可以包括两个交叠长条a1。考虑到色阻流动性，可以将每一个第一过孔11和对应的第二过孔12的侧壁都刻蚀成垂直于衬底基板1的状态(例如，使每一个第一过孔11和对应的第二过孔12在垂直于衬底基板1的截面都为矩形)。为此目的，在每一个第一过孔11对应位置的上方，光刻胶17中的初步过孔V4的侧壁与第三绝缘层10(例如，图6中的水平方向)之间的夹角A11为70°以上(进一步可以选地为80°以上)，光刻胶17的厚度T1大于1.8微米(进一步可以选地大于2.0微米)。
接着，进行干法刻蚀，首先对第三绝缘层10进行刻蚀，采用四氟化碳和氧气，以及高源极功率以及高偏置功率进行。由于光刻胶17中的初步过孔V4的侧壁与第三绝缘层10的角度大加之光刻胶17的厚度较厚，故而干刻只能对垂直方向的第三绝缘层10进行刻蚀，形成所述至少一个第一过孔11。接着，对第二绝缘层9进行刻蚀，可采用六氟化硫和氧气，以及高源极功率和低或无偏置功率进行。由于六氟化硫干刻时各向同性作用较强加之采用了无或低偏置功率，此次干刻类似湿法刻蚀，对第一绝缘层8和第三绝缘层10无刻蚀作用，而对第二绝缘层9有较强刻蚀作用。因此，在第二绝缘层9内能够刻蚀出长条形的所述至少一个第二过孔12，且在水平方向上，刻蚀出的每一个第二过孔12的宽度能够大于对应的第一过孔11的宽度。为 保证后续行程所述色阻交叠区域a1，在每一个第一过孔11的中心轴的同一侧，对应的第二过孔12的侧边与该第一过孔11的侧边之间的距离可控制在8微米到12微米之间。两步干刻完成后，去除剩下的光刻胶17，形成如图2所示的阵列基板。
后续可以执行行程彩膜层的工序。例如，可依次进行蓝色色阻15、红色色阻13和绿色色阻14的制作，如图3所示。由于形成有第一过孔11和第二过孔12，蓝色色阻15和红色色阻13工序完成后，蓝色色阻15会流到对应的第一过孔11和对应的第二过孔12内以形成一个色阻交叠区域a1，并且红色色阻13会流到对应的第一过孔11和对应的第二过孔12内以形成另一个色阻交叠区域a1。这样，绿色色阻14无需形成为在彩膜层中与相邻的蓝色色阻15和红色色阻13交叠以防止漏光，只需要正常进行绿色色阻14工艺后即可在绿色色阻14两侧形成对应的色阻交叠区域a1。以此方式，后续在形成平坦化层16时因交叠区域平坦度好，不会出现平坦化层16脱落的情况，提高了阵列基板的可靠性。
本公开实施例所提供的阵列基板及其制造方法、显示面板和显示装置至少能够获得的以下有益技术效果。
本公开实施例提供的阵列基板在设置有源极和漏极的衬底基板上依次设置有第一绝缘层、第二绝缘层和第三绝缘层，且设置有贯穿第三绝缘层的至少一个第一过孔，贯穿第二绝缘层的至少一个第二过孔，由于在设置有多个彩色色阻的每一像素单元中，每一个第一过孔位于一对相邻两彩色色阻之间，每一个第二过孔的位置与一个第一过孔的位置对应，且在平行于衬底基板的方向上每一个第二过孔的宽度大于对应的第一过孔的宽度，因此在后续设置多个彩色色阻时，在一对相邻两彩色色阻中，一个彩色色阻可以填满一个第一过孔和对应的第二过孔，而可以与另一个彩色色阻形成交叠区。与相关技术相比，在本公开中，无需在彩膜层中彩色色阻的边缘位置处进行色阻交叠以防漏光，因此在彩膜层上设置平坦化层后，平坦化层的厚度相对均匀，不易脱落。
以上所述仅是本公开的部分实施方式。应当指出，对于本技术 领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以做出若干改进和变形，这些改进和变形也属于由所附权利要求所限定的本公开的保护范围。

Claims (20)

  1. 一种阵列基板，包括；衬底基板、依次位于衬底基板上的半导体有源层、栅极、以及源极和漏极，其中，所述阵列基板还包括：第一绝缘层、第二绝缘层、第三绝缘层、至少一个第一过孔和至少一个第二过孔；
    所述第一绝缘层、所述第二绝缘层和所述第三绝缘层依次设置在设置有所述源极和所述漏极的衬底基板上；
    每一个所述至少一个第一过孔贯穿所述第三绝缘层，且在设置有多个彩色色阻的每一像素单元中，每一个所述至少一个第一过孔位于一对相邻两彩色色阻之间，用于后续填充所述一对相邻两彩色色阻中的一个；以及
    每一个所述至少一个第二过孔贯穿所述第二绝缘层，所述至少一个第二过孔的位置与所述至少一个第一过孔的位置一一对应，且在平行于所述衬底基板的方向上每一个所述至少一个第二过孔的宽度大于对应的第一过孔的宽度，每一个所述至少一个第二过孔用于后续填充与对应位置处的所述第一过孔内的彩色色阻的颜色相同的彩色色阻。
  2. 如权利要求1所述的阵列基板，其中，所述第一绝缘层和第三绝缘层的材料为氧化硅，所述第二绝缘层的材料为氮化硅。
  3. 如权利要求1或2所述的阵列基板，其中，在垂直于所述衬底基板方向上，每一个所述至少一个第一过孔的中心轴与对应的第二过孔的中心轴重合。
  4. 如权利要求1至3中任一项所述的阵列基板，其中，在平行于所述衬底基板的方向上，每一个所述至少一个第一过孔的宽度为6微米到10微米。
  5. 如权利要求4所述的阵列基板，其中，在平行于所述衬底基板的方向上，且在每一个所述至少一个第一过孔的中心轴的同一侧，对应的第二过孔的侧边与该第一过孔的侧边之间的距离为8微米到12微米。
  6. 如权利要求1至5中任一项所述的阵列基板，其中，在垂直于所述衬底基板的方向上，每一个所述至少一个第一过孔的截面为长条状，每一个所述至少一个第二过孔的截面为长条状。
  7. 如权利要求1至6中任一项所述的阵列基板，还包括：彩膜层；其中，
    所述彩膜层位于所述第三绝缘层上。
  8. 如权利要求7所述的阵列基板，其中，所述彩膜层在每一像素单元中包括红色色阻、绿色色阻和蓝色色阻；
    在该像素单元中，所述至少一个第一过孔包括两个第一过孔，所述至少一个第二过孔包括两个第二过孔；以及
    在该像素单元中，一个所述第一过孔和该第一过孔对应位置处的第二过孔内填充有蓝色色阻，另一个所述第一过孔和该第一过孔对应位置处的第二过孔内填充有红色色阻。
  9. 如权利要求7或8所述的阵列基板，还包括平坦化层，该平坦化层设置在所述彩膜层上。
  10. 如权利要求6所述的阵列基板，其中，在垂直于所述衬底基板的方向上，每一个所述至少第一过孔的截面为矩形，每一个所述至少一个第二过孔的截面为矩形。
  11. 如权利要求2所述的阵列基板，其中，所述第一绝缘层和所述第三绝缘层中的每一个的厚度为0.1微米至0.2微米，并且所述 第二绝缘层的厚度为0.03微米至0.05微米。
  12. 一种显示面板，包括如权利要求1至11中任一项所述的阵列基板。
  13. 一种显示装置，包括如权利要求12所述的显示面板。
  14. 一种阵列基板的制作方法，包括：
    通过构图工艺在衬底基板上依次制作半导体有源层、栅极、以及源极和漏极；
    在制作有所述源极和所述漏极的所述衬底基板上依次制作第一绝缘层、第二绝缘层和第三绝缘层；
    对所述第三绝缘层进行构图工艺，以形成贯穿所述第三绝缘层的至少一个第一过孔，且在设置有多个彩色色阻的每一像素单元中，每一个所述至少一个第一过孔位于一对相邻两彩色色阻之间，用于后续填充所述一对相邻两彩色色阻中的一个；以及
    对所述第二绝缘层进行构图工艺，以形成贯穿所述第二绝缘层的至少一个第二过孔，所述至少一个第二过孔的位置与所述至少一个第一过孔的位置一一对应，且在平行于所述衬底基板的方向上每一个所述至少一个第二过孔的宽度大于对应的第一过孔的宽度，每一个所述至少一个第二过孔用于后续填充与对应位置处的所述第一过孔内的彩色色阻的颜色相同的彩色色阻。
  15. 如权利要求14所述的制作方法，其中，对所述第三绝缘层进行构图工艺，以形成贯穿所述第三绝缘层的至少一个第一过孔，包括：
    在所述第三绝缘层上涂覆光刻胶，通过曝光、显影去除需要形成所述至少一个第一过孔位置上方的光刻胶的部分，以形成至少一个初步过孔；以及
    采用四氟化碳和氧气，对所述第三绝缘层进行刻蚀，以形成贯 穿所述第三绝缘层的所述至少一个第一过孔。
  16. 如权利要求14或15所述的制作方法，其中，每一个所述至少一个初步过孔的侧壁与平行于所述衬底基板的方向之间的夹角大于70°，并且所述光刻胶的厚度大于1.8微米。
  17. 如权利要求14至16中任一项所述的制作方法，其中，对所述第二绝缘层进行构图工艺，以形成贯穿所述第二绝缘层的至少一个第二过孔，包括：
    采用六氟化硫和氧气，对所述第二绝缘层进行刻蚀，以形成贯穿所述第二绝缘层的所述至少一个第二过孔；以及
    通过剥离工艺去除所述光刻胶。
  18. 如权利要求14至17中任一项所述的制作方法，其中，采用氧化硅来制作所述第一绝缘层和第三绝缘层中的每一个，并且采用氮化硅来制作所述第二绝缘层。
  19. 如权利要求18所述的制作方法，其中，将所述第一绝缘层和所述第三绝缘层中的每一个形成为具有0.1微米至0.2微米的厚度，并且将所述第二绝缘层形成为具有0.03微米至0.05微米的厚度。
  20. 如权利要求14至19中任一项所述的制作方法，其中，在垂直于所述衬底基板的方向上，每一个所述至少第一过孔被形成为具有矩形的截面，并且每一个所述至少一个第二过孔被形成为具有矩形的截面。
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Publication number Priority date Publication date Assignee Title
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CN111025734A (zh) * 2019-12-16 2020-04-17 友达光电（昆山）有限公司 显示装置
CN111090200B (zh) * 2020-03-22 2020-07-03 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105700258A (zh) * 2016-04-08 2016-06-22 深圳市华星光电技术有限公司 液晶显示面板及其制作方法
CN106920891A (zh) * 2015-12-28 2017-07-04 乐金显示有限公司 有机发光显示面板和包括其的有机发光显示装置
CN108873517A (zh) * 2018-06-25 2018-11-23 厦门天马微电子有限公司 一种阵列基板、显示面板以及显示装置
CN110021653A (zh) * 2019-04-23 2019-07-16 合肥鑫晟光电科技有限公司 阵列基板及其制造方法、显示面板和显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601370B1 (ko) * 2004-04-28 2006-07-13 삼성에스디아이 주식회사 박막 트랜지스터 및 그를 이용한 유기 전계 발광 표시 장치
CN104157612A (zh) * 2014-08-21 2014-11-19 深圳市华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板结构
US10180599B2 (en) * 2014-11-20 2019-01-15 Shenzhen China Star Optoelectronics Technology Co., Ltd. Display panel and display device
CN104409462B (zh) * 2014-12-18 2017-07-04 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN104656333A (zh) * 2015-03-18 2015-05-27 深圳市华星光电技术有限公司 Coa型液晶面板的制作方法及coa型液晶面板
CN104950541B (zh) * 2015-07-20 2018-05-01 深圳市华星光电技术有限公司 Boa型液晶显示面板及其制作方法
CN109634014A (zh) * 2019-02-22 2019-04-16 鄂尔多斯市源盛光电有限责任公司 一种显示基板及其制作方法、显示面板、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106920891A (zh) * 2015-12-28 2017-07-04 乐金显示有限公司 有机发光显示面板和包括其的有机发光显示装置
CN105700258A (zh) * 2016-04-08 2016-06-22 深圳市华星光电技术有限公司 液晶显示面板及其制作方法
CN108873517A (zh) * 2018-06-25 2018-11-23 厦门天马微电子有限公司 一种阵列基板、显示面板以及显示装置
CN110021653A (zh) * 2019-04-23 2019-07-16 合肥鑫晟光电科技有限公司 阵列基板及其制造方法、显示面板和显示装置

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