WO2021190049A1 - 显示基板及其制作方法、和显示面板 - Google Patents

显示基板及其制作方法、和显示面板 Download PDF

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Publication number
WO2021190049A1
WO2021190049A1 PCT/CN2020/141353 CN2020141353W WO2021190049A1 WO 2021190049 A1 WO2021190049 A1 WO 2021190049A1 CN 2020141353 W CN2020141353 W CN 2020141353W WO 2021190049 A1 WO2021190049 A1 WO 2021190049A1
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WIPO (PCT)
Prior art keywords
common electrode
conductive pattern
line
display
base substrate
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PCT/CN2020/141353
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English (en)
French (fr)
Inventor
田春光
夏天宇
李小龙
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/312,306 priority Critical patent/US11874565B2/en
Publication of WO2021190049A1 publication Critical patent/WO2021190049A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display panel.
  • a common electrode trace loaded with a common voltage Vcom is provided on the display substrate to transmit a common voltage signal to the common electrode.
  • the size of the display device is getting larger and larger. Therefore, it is necessary to design a common electrode bus on the periphery of the display area to connect the common electrode wires, so as to unify the common voltage Vcom of the common electrode wires and enhance the display performance of the display device. Uniformity.
  • the embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, and a display panel.
  • an embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area provided at the periphery of the display area, including:
  • a common electrode line extending in a first direction on the base substrate, the common electrode line being located in the display area and the peripheral area;
  • the first conductive pattern is located in the peripheral area and is electrically connected to the common electrode line;
  • An insulating layer covering the first conductive pattern and the common electrode line, the insulating layer is provided with a via hole, the orthographic projection of the via hole on the base substrate and the common electrode line on the liner The orthographic projections on the base substrate do not overlap;
  • the second conductive pattern is located in the peripheral area and on the side of the insulating layer away from the first conductive pattern, and the second conductive pattern is electrically connected to the first conductive pattern through the via hole.
  • the common electrode wire is a copper wire.
  • the first conductive pattern is located on a side of the common electrode line close to the base substrate, or the first conductive pattern is located on a side of the common electrode line away from the base substrate.
  • the common electrode bus line is located in the peripheral area and surrounding the display area; the common electrode bus line is located on the side of the insulating layer away from the first conductive pattern, and is connected to the The second conductive pattern is electrically connected, and the first direction is perpendicular to the second direction.
  • the second conductive pattern is located on the side of the common electrode bus line away from the base substrate, or the two conductive patterns are located on the side of the common electrode bus line close to the base substrate.
  • the display area includes gate lines and data lines
  • the common electrode line is parallel to the gate line, and the common electrode line and the gate line are provided in the same layer and the same material;
  • the common electrode bus line and the data line are provided with the same layer and the same material.
  • the display area further includes a pixel area defined by the gate line and the data line, and each pixel area includes a pixel electrode and a common electrode;
  • the first conductive pattern and the common electrode are arranged in the same layer and the same material;
  • the second conductive pattern and the pixel electrode are arranged in the same layer and the same material.
  • embodiments of the present disclosure also provide a display panel, including the display panel described above.
  • embodiments of the present disclosure also provide a method for manufacturing a display substrate, the method including:
  • a common electrode line and a first conductive pattern electrically connected to each other are formed on the base substrate, wherein the common electrode line extends along the first direction and is located in the display area and the peripheral area, and the first conductive pattern is located in the Peripheral area
  • An insulating layer covering the first conductive pattern and the common electrode line is formed, the insulating layer is provided with a via hole, and the orthographic projection of the via hole on the base substrate and the common electrode line are in the same position.
  • the orthographic projections on the base substrate do not overlap;
  • a second conductive pattern is formed on the insulating layer, and the second conductive pattern is electrically connected to the first conductive pattern through the via hole.
  • the forming the common electrode line and the first conductive pattern electrically connected to each other on the base substrate includes:
  • a common electrode line is formed on the base substrate; a first conductive pattern is formed on the peripheral area and part of the common electrode line.
  • the method further includes:
  • the formation of a second conductive pattern on the insulating layer includes:
  • a second conductive pattern is formed on the peripheral area and part of the common electrode bus.
  • forming the common electrode line includes:
  • a gate line extending in the first direction and a common electrode line parallel to the gate line are formed in the display area.
  • a common electrode bus including:
  • a data line extending in the second direction and a common electrode bus located in the peripheral area are formed in the display area.
  • forming the first conductive pattern includes:
  • a common electrode is formed in the display area, and a first conductive pattern is formed in the peripheral area.
  • forming the second conductive pattern includes:
  • a pixel electrode is formed in the display area, and a second conductive pattern is formed in the peripheral area.
  • FIG. 1 is a top view of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a cross-sectional view of a display substrate provided by another embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a display substrate provided by another embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display substrate, as shown in FIG. 1 and FIG. 2, which includes a display area I and a peripheral area II arranged around the display area I.
  • the display substrate includes:
  • a common electrode line 110 extending in a first direction on the base substrate, the common electrode line 110 being located in the display area and the peripheral area;
  • the first conductive pattern 120 is located in the peripheral area and is electrically connected to the common electrode line 110;
  • the insulating layer 130 covering the first conductive pattern 120 and the common electrode line 110 is provided with a via 131, and the orthographic projection of the via 131 on the base substrate is the same as that of the common electrode line 110.
  • the orthographic projections of the electrode lines 110 on the base substrate do not overlap;
  • the second conductive pattern 140 is located in the peripheral area and on the side of the insulating layer 130 away from the first conductive pattern 120, and the second conductive pattern 140 passes through the via 131 and the first conductive pattern 120 electrical connections.
  • the common electrode line can be connected to other conductive patterns in the peripheral area.
  • the electrical connection between the common electrode bus lines of the layers so as to unify the common voltage of the common electrode wires, and enhance the display uniformity of the display device. Therefore, the technical solution provided by the present disclosure can unify the common voltage of each common electrode wiring, and enhance the display uniformity of the display device.
  • the insulating layer 130 is removed from the portion close to the display area I in FIG. 1, so that the common electrode line 110 can be seen.
  • the number of the above-mentioned common electrode lines 110 may be multiple, and a plurality of common electrode lines 110 extending in the first direction are arranged in parallel on the base substrate, wherein the portion of the common electrode line 110 located in the display area I is used to communicate with the pixel area. Connect the common electrode inside.
  • the multiple pixel regions in the display area I can be arranged in an array, wherein the first direction can be parallel to the row direction in the array arrangement, or can be parallel to the column direction in the array arrangement, which is not limited here. Assuming that the first direction is parallel to the row direction in the array arrangement, it may be that the common electrodes in the pixel regions of the same row are all electrically connected to the same common electrode line 110.
  • the part of the common electrode line 110 located in the peripheral area II may be one, that is, the common electrode line 110 is divided into two parts connected to each other.
  • the first part is located in the display area I
  • the second part is located in the peripheral area II
  • the second part passes through the peripheral area II.
  • the common voltage provided by the common electrode bus is provided to the first part as a reference voltage for each common electrode connected to the first part, wherein the transmission direction of the common voltage signal is the second part to the first part; the common electrode line 110 is located at the periphery
  • the part of the area II can also be two, that is, the common electrode line 110 is divided into three parts that are connected to each other.
  • the first part is located in the display area I, and the other two second parts are located in the peripheral area II on opposite sides, respectively.
  • the two second parts of the peripheral area II are simultaneously provided to the first part through the common voltage provided by the common electrode bus in the peripheral area II, as the reference voltage of each common electrode connected to the first part, wherein the transmission direction of the common voltage signal is two Two second parts are simultaneously transmitted to the first part.
  • both ends of the common electrode line jointly provide a common voltage signal for the first part of the display area I, which can reduce the transmission distance of the common voltage signal and reduce With voltage loss, the display uniformity effect of the display device is more ideal.
  • the above-mentioned first conductive pattern 120 is located in the peripheral area II and is used to connect the common electrode line 110 to the common electrode bus, so that each common electrode line of the display substrate is connected to the common electrode bus, thereby improving the display uniformity of the display substrate.
  • the above-mentioned insulating layer 130 may be an organic insulating layer or an inorganic insulating layer.
  • the orthographic projection of the via 131 opened in the insulating layer 130 on the base substrate does not overlap with the orthographic projection of the common electrode line 110 on the base substrate, and overlaps with the orthographic projection of the first conductive pattern 120 on the base substrate. Stacked.
  • the second conductive pattern 140 described above is located in the peripheral area II.
  • One end of the second conductive pattern 140 is electrically connected to the first conductive pattern 120 through a via hole, and the other end of the second conductive pattern 140 can be directly connected to the common electrode bus, or it can be It is indirectly connected to the common electrode bus through other conductive patterns, which is not limited here.
  • each common electrode line 110 may be arranged in the peripheral area II and located on the first side of the display area I, and each common electrode line 110 includes a first portion located in the display area I and a second portion located on the first side of the first portion. Part, the second part is electrically connected to the common electrode bus through the first conductive pattern 120 and the second conductive pattern 140; the above-mentioned common electrode bus may also be a closed pattern arranged in the peripheral area II and surrounding the display area I.
  • the electrode line 110 includes a first portion located in the display area I and a second portion located in the peripheral area II. The second portion may be located at any end or both ends of the first portion in the first direction, and each second portion passes through the first portion.
  • the conductive pattern 120 and the second conductive pattern 140 are electrically connected to the common electrode bus.
  • the common electrode wire is a copper wire.
  • Copper material has excellent electrical conductivity. Compared with other metal conductive materials such as aluminum material, it can not only reduce the delay of signal transmission, but also reduce the resistance of the wiring, thereby reducing the power consumption of the display device.
  • the common electrode line 110 is made of copper, if the orthographic projection of the via on the insulating layer 130 on the base substrate overlaps the common electrode line, copper will appear after the via is formed. It is exposed to react with the outside to cause deterioration, so that the connection between the subsequent second conductive pattern 140 and the deteriorated common electrode line 110 through the via hole will have a higher contact resistance, causing abnormal heating at the connection during the display process .
  • the first conductive pattern 120 can prevent the common electrode line of copper material from being directly exposed and deteriorating, and ensure that the contact resistance between the undeteriorated common electrode line and the second conductive pattern 140 is relatively high. Small, avoid abnormal heating at the connection during the display process, and improve the reliability of the display device.
  • the first conductive pattern is located on a side of the common electrode line close to the base substrate, or the first conductive pattern is located on a side of the common electrode line away from the base substrate.
  • the first conductive pattern 120 may be located on the side of the common electrode line 110 close to the base substrate, that is, after the first conductive pattern 120 is formed on the base substrate, the first conductive pattern 120 is formed on the base substrate.
  • the common electrode line connected to the conductive pattern 120; the first conductive pattern 120 may also be located on the side of the common electrode line 110 away from the base substrate, that is, after the common electrode line is formed on the base substrate, the line A first conductive pattern 120 connected to the common electrode line is formed on the base substrate.
  • the display substrate further includes a common electrode bus line, the common electrode bus line is located in the peripheral area and surrounds the display area; the common electrode bus line is located in the insulating layer away from the One side of the first conductive pattern is electrically connected to the second conductive pattern, and the first direction is perpendicular to the second direction.
  • the common electrode bus 150 is a closed pattern arranged in the peripheral area II and surrounding the display area I.
  • each common electrode line 110 extending to the peripheral area II is electrically connected to the common electrode bus line 150 through the first conductive pattern 120 and the second conductive pattern 140.
  • the second conductive pattern 140 is located on the side of the common electrode bus 150 away from the base substrate, or the second conductive pattern 140 is located on the side of the common electrode bus 150 close to the base substrate. One side.
  • the second conductive pattern 140 may be located on the side of the common electrode bus 150 close to the base substrate, that is, after the second conductive pattern 140 is formed on the base substrate, the second conductive pattern 140 is formed on the base substrate and the second conductive pattern 140 is formed on the base substrate.
  • the common electrode bus 150 connected to the conductive pattern 140; the second conductive pattern 140 may also be located on the side of the common electrode bus 150 away from the base substrate, that is, after the common electrode bus 150 is formed on the base substrate, A second conductive pattern 140 connected to the common electrode bus 150 is formed on the base substrate.
  • the second conductive pattern 140 and the common electrode bus line 150 are both located on the side of the insulating layer 130 away from the base substrate, and an inorganic passivation layer 160 may also be provided between the second conductive pattern 140 and the common electrode bus line 150, as shown in FIG. 3, the common electrode bus line 150 in FIG. 3 is located between the second conductive pattern 140 and the base substrate, and the inorganic passivation layer 161 is located between the second conductive pattern 140 and the common electrode bus line 150, and the inorganic passivation layer 160 is provided There is a through hole 161 penetrating the inorganic passivation layer 160, and the second conductive pattern 140 is electrically connected to the common electrode bus 150 through the through hole 161.
  • the display area I includes gate lines 170 and data lines 180;
  • the common electrode line 110 is parallel to the gate line 170, and the common electrode line 110 and the gate line 170 are provided in the same layer and the same material;
  • the common electrode bus 150 and the data line 180 are provided with the same layer and the same material.
  • the common electrode line 110 located in the display area I and the peripheral area II and the gate line 170 located in the display area I can be fabricated at the same time through a patterning process, that is, the entire first layer is formed on the base substrate. After the conductive material layer is exposed and etched using the mask 1, the common electrode line 110 and the gate line 170 parallel to each other are obtained at the same time. At this time, the common electrode line 110 and the gate line 170 are both the first conductive material, and both are in the layer where the first conductive material layer is located.
  • the first conductive material may be copper
  • the gate line 170 is a copper trace, which can reduce the delay of scanning signal transmission, and can also reduce the resistance of the gate line, thereby reducing the power consumption of the display device.
  • the common electrode bus 150 located in the peripheral area II and the data line 180 located in the display area I can be fabricated simultaneously through a patterning process, that is, after the entire second conductive material layer is formed on the base substrate, a mask is used 2 After exposure and etching, the data line 180 located in the display area I and the common electrode bus 150 located in the peripheral area II and surrounding the display area I are obtained at the same time. At this time, the common electrode bus 150 and the data line 180 are both the second conductive material, and both are in the layer where the second conductive material layer is located.
  • the manufacturing steps of the display substrate can be reduced, and the manufacturing efficiency can be improved; similarly, the data line 180 and the common electrode bus 150 are in the same layer and in the same layer.
  • the material production can also reduce the production steps of the display substrate and improve the production efficiency.
  • the display area I further includes a pixel area defined by the gate line 170 and the data line 180, and each pixel area includes a pixel electrode 190 and a common electrode (not shown in the figure). );
  • the first conductive pattern 120 and the common electrode are arranged in the same layer and the same material;
  • the second conductive pattern 140 and the pixel electrode 190 are provided in the same layer and the same material.
  • the first conductive pattern 120 located in the peripheral area II and the common electrode located in each display area I in the display area I can be fabricated at the same time through a patterning process, that is, the entire layer is formed on the base substrate.
  • the mask 3 is used for exposure and etching to simultaneously obtain the first conductive pattern 120 in the peripheral area II and the common electrode in the display area I.
  • the first conductive pattern 120 and the common electrode are both the third conductive material, and both are layers where the third conductive material layer is located.
  • the second conductive pattern 140 located in the peripheral area II and the pixel electrode 190 located in each display area I in the display area I can be fabricated simultaneously through a patterning process, that is, a whole layer of the fourth conductive material is formed on the base substrate After the layer is layered, the mask 4 is used for exposure and etching to simultaneously obtain the second conductive pattern 140 in the peripheral area II and the display electrode in the display area I. At this time, the second conductive pattern 140 and the pixel electrode 190 are both the third conductive material, and both are layers where the third conductive material layer is located.
  • the manufacturing steps of the display substrate can be reduced, and the manufacturing efficiency can be improved; similarly, the second conductive pattern 140 and the pixel electrode 190 are in the same layer and the same material.
  • the arrangement can also reduce the manufacturing steps of the display substrate and improve the manufacturing efficiency.
  • the embodiment of the present disclosure also provides a display panel including the display substrate as described above.
  • the embodiment of the present disclosure also provides a manufacturing method of a display substrate, the method including:
  • a common electrode line and a first conductive pattern that are electrically connected to each other are formed on the base substrate, wherein the common electrode line extends along the first direction and is located in the display area and a part of the peripheral area, and the first conductive pattern is located in the The peripheral area;
  • An insulating layer covering the first conductive pattern and the common electrode line is formed, the insulating layer is provided with a via hole, and the orthographic projection of the via hole on the base substrate and the common electrode line are in the same position.
  • the orthographic projections on the base substrate do not overlap;
  • a second conductive pattern is formed on the insulating layer, and the second conductive pattern is electrically connected to the first conductive pattern through the via hole.
  • the common electrode line can be connected to other conductive patterns in the peripheral area.
  • the electrical connection between the common electrode bus lines of the layers so as to unify the common voltage of the common electrode wires, and enhance the display uniformity of the display device. Therefore, the technical solution provided by the present disclosure can unify the common voltage of each common electrode wiring, and enhance the display uniformity of the display device.
  • the number of the above-mentioned common electrode lines 110 may be multiple, and multiple common electrode lines 110 extending along the first direction are arranged in parallel on the base substrate, wherein the common electrode lines 110 are located in the display area.
  • the part in I is used to connect with the common electrode in the pixel area.
  • the multiple pixel regions in the display area I can be arranged in an array, wherein the first direction can be parallel to the row direction in the array arrangement, or can be parallel to the column direction in the array arrangement, which is not limited here. Assuming that the first direction is parallel to the row direction in the array arrangement, it may be that the common electrodes in the pixel regions in the same row are all electrically connected to the same common electrode line 110.
  • the part of the common electrode line 110 located in the peripheral area II may be one, that is, the common electrode line 110 is divided into two parts connected to each other.
  • the first part is located in the display area I
  • the second part is located in the peripheral area II
  • the second part passes through the peripheral area II.
  • the common voltage provided by the common electrode bus is provided to the first part as a reference voltage for each common electrode connected to the first part, wherein the transmission direction of the common voltage signal is the second part to the first part; the common electrode line 110 is located at the periphery
  • the part of the area II can also be two, that is, the common electrode line 110 is divided into three parts connected to each other.
  • the first part is located in the display area I, and the other two second parts are located in the peripheral area II on opposite sides, respectively.
  • the two second parts of the peripheral area II are simultaneously provided to the first part through the common voltage provided by the common electrode bus in the peripheral area II, as the reference voltage of each common electrode connected to the first part, wherein the transmission direction of the common voltage signal is two Two second parts are simultaneously transmitted to the first part.
  • both ends of the common electrode line jointly provide a common voltage signal for the first part of the display area I, which can reduce the transmission distance of the common voltage signal and reduce With voltage loss, the display uniformity effect of the display device is more ideal.
  • the above-mentioned first conductive pattern 120 is located in the peripheral area II and is used to connect the common electrode line 110 to the common electrode bus, so that each common electrode line of the display substrate is connected to the common electrode bus, thereby improving the display uniformity of the display substrate.
  • the above-mentioned insulating layer 130 may be an organic insulating layer or an inorganic insulating layer.
  • the orthographic projection of the via 131 opened in the insulating layer 130 on the base substrate does not overlap with the orthographic projection of the common electrode line 110 on the base substrate, and overlaps with the orthographic projection of the first conductive pattern 120 on the base substrate. Stacked.
  • the second conductive pattern 140 described above is located in the peripheral area II.
  • One end of the second conductive pattern 140 is electrically connected to the first conductive pattern 120 through a via hole, and the other end of the second conductive pattern 140 can be directly connected to the common electrode bus, or it can be It is indirectly connected to the common electrode bus through other conductive patterns, which is not limited here.
  • each common electrode line 110 may be arranged in the peripheral area II and located on the first side of the display area I, and each common electrode line 110 includes a first portion located in the display area I and a second portion located on the first side of the first portion. Part, the second part is electrically connected to the common electrode bus through the first conductive pattern 120 and the second conductive pattern 140; the above-mentioned common electrode bus may also be a closed pattern arranged in the peripheral area II and surrounding the display area I.
  • the electrode line 110 includes a first portion located in the display area I and a second portion located in the peripheral area II. The second portion may be located at any end or both ends of the first portion in the first direction, and each second portion passes through the first portion.
  • the conductive pattern 120 and the second conductive pattern 140 are electrically connected to the common electrode bus.
  • the common electrode wire is a copper wire.
  • Copper material has excellent electrical conductivity. Compared with other metal conductive materials such as aluminum material, it can not only reduce the delay of signal transmission, but also reduce the resistance of the wiring, thereby reducing the power consumption of the display device.
  • the via hole will be formed.
  • the copper is exposed to react with the outside world and deteriorate, so that the connection between the second conductive pattern 140 and the deteriorated common electrode line 110 through the via hole will have a higher contact resistance, resulting in abnormal heat generation at the connection during the display process. problem.
  • the first conductive pattern 120 can prevent the common electrode line of copper material from being directly exposed and deteriorating, and ensure that the contact resistance between the undeteriorated common electrode line and the second conductive pattern 140 is relatively high. Small, avoid abnormal heating at the connection during the display process, and improve the reliability of the display device.
  • the forming the common electrode line and the first conductive pattern electrically connected to each other on the base substrate includes:
  • a common electrode line is formed on the base substrate; a first conductive pattern is formed on the peripheral area and part of the common electrode line.
  • the first conductive pattern 120 may be formed first, and then the common electrode line 110 connected to the first conductive pattern 120 is formed on the base substrate, that is, the first conductive pattern 120 is located on the common electrode line. Close to the side of the base substrate.
  • the common electrode line 110 is formed first, and then the first conductive pattern 120 connected to the common electrode line 110 is formed on the base substrate, that is, the first conductive pattern 120 is located on the common electrode line 110 away from the substrate.
  • the first conductive pattern 120 is located on the common electrode line 110 away from the substrate.
  • the method further includes:
  • the formation of a second conductive pattern on the insulating layer includes:
  • a second conductive pattern is formed on the peripheral area and part of the common electrode bus.
  • the common electrode bus 150 may be formed first, and then the second conductive pattern 140 connected to the common electrode bus 150 is formed on the base substrate. That is, the second conductive pattern 140 is located on the side of the common electrode bus 150 away from the base substrate.
  • forming the common electrode line includes:
  • a gate line extending in the first direction and a common electrode line parallel to the gate line are formed in the display area.
  • the common electrode line 110 located in the display area I and the peripheral area II and the gate line 170 located in the display area I can be fabricated at the same time through a patterning process, that is, the entire first layer is formed on the base substrate. After the conductive material layer is exposed and etched using the mask 1, the common electrode line 110 and the gate line 170 parallel to each other are obtained at the same time. At this time, the common electrode line 110 and the gate line 170 are both the first conductive material, and both are in the layer where the first conductive material layer is located.
  • the manufacturing steps of the display substrate can be reduced and the manufacturing efficiency can be improved.
  • forming a common electrode bus includes:
  • a data line 180 extending in the second direction and a common electrode bus located in the peripheral area are formed in the display area.
  • the common electrode bus 150 located in the peripheral area II and the data line 180 located in the display area I can be fabricated at the same time through a patterning process, that is, after the entire second conductive material layer is formed on the base substrate After the mask 2 is used for exposure and etching, the data line 180 located in the display area I and the common electrode bus 150 located in the peripheral area II and surrounding the display area I are obtained at the same time. At this time, the common electrode bus 150 and the data line 180 are both the second conductive material, and both are in the layer where the second conductive material layer is located.
  • the manufacturing steps of the display substrate can be reduced, and the manufacturing efficiency can be improved.
  • forming the first conductive pattern includes:
  • a common electrode is formed in the display area, and a first conductive pattern is formed in the peripheral area.
  • the first conductive pattern 120 located in the peripheral area II and the common electrode located in each display area I in the display area I can be fabricated at the same time through a patterning process, that is, the entire layer is formed on the base substrate.
  • the mask 3 is used for exposure and etching to simultaneously obtain the first conductive pattern 120 in the peripheral area II and the common electrode in the display area I.
  • the first conductive pattern 120 and the common electrode are both the third conductive material, and both are layers where the third conductive material layer is located.
  • the manufacturing steps of the display substrate can be reduced, and the manufacturing efficiency can be improved.
  • forming the first conductive pattern includes:
  • a common electrode is formed in the display area, and a first conductive pattern is formed in the peripheral area.
  • the second conductive pattern 140 located in the peripheral area II and the pixel electrode 190 located in each display area I in the display area I can be fabricated at the same time through a patterning process, that is, the entire layer is formed on the base substrate. After the fourth conductive material layer is exposed and etched using the mask 4, the second conductive pattern 140 in the peripheral area II and the display electrode in the display area I are simultaneously obtained. At this time, the second conductive pattern 140 and the pixel electrode 190 are both the third conductive material, and both are layers where the third conductive material layer is located.
  • the manufacturing steps of the display substrate can also be reduced, and the manufacturing efficiency can be improved.

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Abstract

一种显示基板及其制作方法、和显示装置，其中，显示基板，包括显示区域（Ⅰ）和设置于显示区域（Ⅰ）周边的外围区域（Ⅱ），包括：在衬底基板上沿第一方向延伸的公共电极线（110），公共电极线（110）位于显示区域（Ⅰ）和外围区域（Ⅱ）；第一导电图形（120），位于外围区域（Ⅱ）内，与公共电极线（110）电连接；覆盖第一导电图形（120）和公共电极线（110）的绝缘层（130），绝缘层（130）开设有过孔（131），过孔（131）在衬底基板上的正投影与公共电极线（110）在衬底基板上的正投影不交叠；第二导电图形（140），位于外围区域（Ⅱ）内且位于绝缘层（130）远离第一导电图形（120）一侧，第二导电图形（140）通过过孔（131）与第一导电图形（120）电连接。显示基板及其制作方法、和显示装置，能够增强显示装置显示的均一性。

Description

显示基板及其制作方法、和显示面板
相关申请的交叉引用
本申请主张在2020年03月27日在中国提交的中国专利申请号202010229050.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、和显示面板。
背景技术
目前的液晶显示(Liquid Crystal Display，简称LCD)装置中，在显示基板设置有加载了公共电压Vcom的公共电极走线，以向公共电极传输公共电压信号。相关技术中，显示装置的尺寸越来越大，因此需要在显示区的外围设计公共电极总线将各公共电极走线连接起来，以统一各公共电极走线的公共电压Vcom，增强显示装置显示的均一性。
发明内容
本公开实施例提供一种显示基板及其制作方法、和显示面板。
第一方面，本公开实施例提供一种显示基板，包括显示区域和设置于所述显示区域周边的外围区域，包括：
在衬底基板上沿第一方向延伸的公共电极线，所述公共电极线位于所述显示区域和外围区域；
第一导电图形，位于所述外围区域内，与所述公共电极线电连接；
覆盖所述第一导电图形和所述公共电极线的绝缘层，所述绝缘层开设有过孔，所述过孔在所述衬底基板上的正投影与所述公共电极线在所述衬底基板上的正投影不交叠；
第二导电图形，位于所述外围区域内且位于所述绝缘层远离所述第一导电图形一侧，所述第二导电图形通过所述过孔与所述第一导电图形电连接。
进一步地，所述公共电极线为铜走线。
进一步地，所述第一导电图形位于所述公共电极线靠近所述衬底基板的一侧，或者，所述第一导电图形位于所述公共电极线远离所述衬底基板的一侧。
进一步地，还包括公共电极总线，所述公共电极总线位于所述外围区域且包围所述显示区域设置；所述公共电极总线位于所述绝缘层远离所述第一导电图形一侧，并与所述第二导电图形电连接，所述第一方向与所述第二方向垂直。
进一步地，所述第二导电图形位于所述公共电极总线远离所述衬底基板的一侧，或者，所述二导电图形位于所述公共电极总线靠近所述衬底基板的一侧。
进一步地，所述显示区域包括栅线和数据线；
所述公共电极线与所述栅线平行，且所述公共电极线与所述栅线同层同材料设置；
所述公共电极总线与所述数据线同层同材料设置。
进一步地，所述显示区域还包括由所述栅线和所述数据线限定出的像素区域，每个像素区域内包括像素电极和公共电极；
所述第一导电图形与所述公共电极同层同材料设置；
所述第二导电图形与所述像素电极同层同材料设置。
第二方面，本公开实施例还提供一种显示面板，包括如上所述的显示面板。
第三方面，本公开实施例还提供一种显示基板的制作方法，所述方法包括：
提供一衬底基板，包括显示区域和包围所述显示区域设置的外围区域；
在所述衬底基板上形成相互电连接的公共电极线和第一导电图形，其中，所述公共电极线沿第一方向延伸且位于显示区域和外围区域，所述第一导电图形位于所述外围区域；
形成覆盖所述第一导电图形和所述公共电极线的绝缘层，所述绝缘层上开设有过孔，所述过孔在所述衬底基板上的正投影与所述公共电极线在所述 衬底基板上的正投影不交叠；
在所述绝缘层上形成第二导电图形，所述第二导电图形通过所述过孔与所述第一导电图形电连接。
进一步地，所述在所述衬底基板上形成相互电连接的公共电极线和第一导电图形，包括：
在所述衬底基板上形成第一导电图形；在所述显示区域和部分第一导电图形上形成公共电极线；或者，
在所述衬底基板上形成公共电极线；在所述外围区域和部分公共电极线上形成第一导电图形。
进一步地，在所述绝缘层上形成第二导电图形之前，还包括：
在所述绝缘层上形成公共电极总线，所述公共电极总线位于所述外围区域；
所述绝缘层上形成第二导电图形，包括：
在所述外围区域和部分所述公共电极总线上形成第二导电图形。
进一步地，形成公共电极线，包括：
通过一次构图工艺，在所述显示区域形成沿第一方向延伸的栅线和与所述栅线平行的公共电极线。
进一步地形成公共电极总线，包括：
通过一次构图工艺，在所述显示区域形成沿第二方向延伸的数据线和位于所述外围区域的公共电极总线。
进一步地，形成第一导电图形，包括：
通过一次构图工艺，在所述显示区域形成公共电极，在所述外围区域形成第一导电图形。
进一步地，形成第二导电图形，包括：
通过一次构图工艺，在所述显示区域形成像素电极，在所述外围区域形成第二导电图形。
附图说明
图1为本公开一实施例提供的显示基板的俯视图；
图2为本公开一实施例提供的显示基板的剖视图；
图3为本公开另一实施例提供的显示基板的剖视图；
图4为本公开另一实施例提供的显示基板的剖视图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种显示基板，如图1和图2所示，包括显示区域Ⅰ和设置于所述显示区域Ⅰ周边的外围区域Ⅱ，显示基板包括：
在衬底基板上沿第一方向延伸的公共电极线110，所述公共电极线110位于所述显示区域和外围区域；
第一导电图形120，位于所述外围区域内，与所述公共电极线110电连接；
覆盖所述第一导电图形120和所述公共电极线110的绝缘层130，所述绝缘层130开设有过孔131，所述过孔131在所述衬底基板上的正投影与所述公共电极线110在所述衬底基板上的正投影不交叠；
第二导电图形140，位于所述外围区域内且位于所述绝缘层130远离所述第一导电图形120一侧，所述第二导电图形140通过所述过孔131与所述第一导电图形120电连接。
本公开实施例中，通过与公共电极线电连接的第一导电图形，以及通过过孔与所述第一导电图形电连接的第二导电图形，能够在外围区域内实现公共电极线与位于其他层的公共电极总线之间的电连接，从而统一各公共电极走线的公共电压，增强显示装置显示的均一性。因此，本公开提供的技术方案能够统一各公共电极走线的公共电压，增强显示装置显示的均一性。
其中，图1中靠近显示区域Ⅰ的部分去除了绝缘层130，从而能够看到公共电极线110。
上述公共电极线110的数量可以是多根，多根沿第一方向延伸的公共电 极线110在衬底基板上平行设置，其中，公共电极线110位于显示区域Ⅰ内的部分用于与像素区域内的公共电极连接。
显示区域Ⅰ内的多个像素区域可以是呈阵列排布，其中，第一方向可以与阵列排布中的行方向平行，也可以是阵列排布中的列方向平行，此处不作限定。假设，第一方向与阵列排布中的行方向平行，则可以是位于同一行的像素区域中的公共电极均与同一根公共电极线110电连接。
公共电极线110中位于外围区域Ⅱ的部分可以是一个，即公共电极线110分为相互连接的两部分，第一部分位于显示区域Ⅰ，第二部分位于外围区域Ⅱ，第二部分通过外围区域Ⅱ中公共电极总线提供的公共电压提供给第一部分，作为与第一部分相连的各公共电极的参考电压，其中，公共电压信号的传输方向为第二部分向第一部分传输；公共电极线110中位于外围区域Ⅱ的部分也可以是两个，即公共电极线110分为相互连接的三部分，第一部分位于显示区域Ⅰ，另外的两个第二部分分别位于相对两侧的外围区域Ⅱ，位于两侧外围区域Ⅱ的两个第二部分同时通过外围区域Ⅱ中公共电极总线提供的公共电压提供给第一部分，作为与第一部分相连的各公共电极的参考电压，其中，公共电压信号的传输方向为两个第二部分同时向第一部分传输。
其中，公共电极线110中位于外围区域Ⅱ的第二部分为两个时，公共电极线的两端共同为显示区域Ⅰ内的第一部分提供公共电压信号，能够减少公共电压信号的传输距离，降低电压损耗，显示装置显示均一性的效果更理想。
上述第一导电图形120位于外围区域Ⅱ内，用于将公共电极线110与公共电极总线连接，使得显示基板每一根公共电极线均与公共电极总线连接，提高显示基板显示的均一性。
上述绝缘层130可以为有机绝缘层，也可以为无机绝缘层。绝缘层130上开设的过孔131在衬底基板上的正投影与公共电极线110在衬底基板上的正投影不交叠，且与第一导电图形120在衬底基板上的正投影交叠。
上述第二导电图形140位于外围区域Ⅱ内，第二导电图形140的一端通过过孔与第一导电图形120电连接，第二导电图形140的另一端可以直接与公共电极总线连接，也可以是间接通过其他导电图形与公共电极总线连接，此处不作限定。
需要说明的是，上述公共电极总线可以是设置于外围区域Ⅱ内且位于显示区域Ⅰ的第一侧，各公共电极线110包括位于显示区域Ⅰ的第一部分和位于第一部分第一侧的第二部分，第二部分均通过第一导电图形120和第二导电图形140与公共电极总线电连接；上述公共电极总线也可以是设置于外围区域Ⅱ内且环绕显示区域Ⅰ设置的封闭图形，各公共电极线110包括位于显示区域Ⅰ的第一部分和位于外围区域Ⅱ的第二部分，第二部分可以是位于第一部分在第一方向上的任意一端或两端，每一个第二部分均通过第一导电图形120和第二导电图形140与公共电极总线电连接。
进一步地，所述公共电极线为铜走线。
铜材料具有优良的导电性能，相较于铝材料等其他金属导电材料而言，不仅能够降低信号传输的延时量，还能够降低走线的电阻，从而降低显示装置的功耗。
然而，由于铜材料的性质较为活泼，公共电极线110采用铜走线后，若绝缘层130上的过孔在衬底基板上的正投影与公共电极线交叠，会出现过孔形成后铜暴露出来与外界发生反应而出现变质的情况，这样后续第二导电图形140通过过孔与变质的公共电极线110的连接处会有较高的接触电阻，造成显示过程中连接处发热异常的问题。
如图2所示，通过第一导电图形120能够避免铜材料的公共电极线直接暴露在外发生变质的情况发生，确保未变质的公共电极线与第二导电图形140之间连接处的接触电阻较小，避免显示过程中连接处发热异常的情况，提高显示装置的可靠性。
进一步地，所述第一导电图形位于所述公共电极线靠近所述衬底基板的一侧，或者，所述第一导电图形位于所述公共电极线远离所述衬底基板的一侧。
本实施例中，第一导电图形120可以是位于公共电极线110靠近衬底基板的一侧，即在衬底基板上先形成第一导电图形120之后，再在衬底基板上形成与第一导电图形120相连的公共电极线；第一导电图形120也可以是位于所述公共电极线110远离所述衬底基板的一侧，即在衬底基板上先形成公共电极线之后，再在衬底基板上形成与公共电极线相连的第一导电图形120。
进一步地，如图1和图2所示，显示基板还包括公共电极总线，所述公共电极总线位于所述外围区域且包围所述显示区域设置；所述公共电极总线位于所述绝缘层远离所述第一导电图形一侧，并与所述第二导电图形电连接，所述第一方向与所述第二方向垂直。
本实施例中，公共电极总线150是设置于外围区域Ⅱ内且环绕显示区域Ⅰ设置的封闭图形。
各公共电极线110延伸至外围区域Ⅱ的部分通过第一导电图形120和第二导电图形140与公共电极总线150电连接。
进一步地，所述第二导电图形140位于所述公共电极总线150远离所述衬底基板的一侧，或者，所述第二导电图形140位于所述公共电极总线150靠近所述衬底基板的一侧。
本实施例中，第二导电图形140可以是位于公共电极总线150靠近衬底基板的一侧，即在衬底基板上先形成第二导电图形140之后，再在衬底基板上形成与第二导电图形140相连的公共电极总线150；第二导电图形140也可以是位于所述公共电极总线150远离所述衬底基板的一侧，即在衬底基板上先形成公共电极总线150之后，再在衬底基板上形成与公共电极总线150相连的第二导电图形140。
其中，第二导电图形140和公共电极总线150均位于绝缘层130远离衬底基板的一侧，在第二导电图形140和公共电极总线150之间还可以设有无机钝化层160，如图3所示，图3中公共电极总线150位于第二导电图形140与衬底基板之间，且无机钝化层161位于第二导电图形140和公共电极总线150之间，无机钝化层160开设有贯穿无机钝化层160的通孔161，第二导电图形140通过过孔161与公共电极总线150电连接。
进一步地，如图4所示，所述显示区域Ⅰ包括栅线170和数据线180；
所述公共电极线110与所述栅线170平行，且所述公共电极线110与所述栅线170同层同材料设置；
所述公共电极总线150与所述数据线180同层同材料设置。
本实施例中，位于显示区域Ⅰ和外围区域Ⅱ的公共电极线110和位于显示区域Ⅰ内的栅线170可以通过一次构图工艺同时制作得到的，即在衬底基 板上形成整层的第一导电材料层后，利用掩膜版1进行曝光、刻蚀后同时得到相互平行的公共电极线110和栅线170。此时，公共电极线110和栅线170均为第一导电材料，且均处于第一导电材料层所在的层。
其中，第一导电材料可以为铜，栅线170为铜走线能够降低扫描信号传输的延时量，还能够降低栅线的电阻，从而降低显示装置的功耗。
位于外围区域Ⅱ的公共电极总线150和位于显示区域Ⅰ内的数据线180可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第二导电材料层后，利用掩膜版2进行曝光、刻蚀后同时得到位于显示区域Ⅰ内的数据线180和位于外围区域Ⅱ且包围显示区域Ⅰ设置的公共电极总线150。此时，公共电极总线150和数据线180均为第二导电材料，且均处于第二导电材料层所在的层。
本实施例中，通过将栅线170与公共电极线110同层且同材料制作，能够减少显示基板的制作步骤，提高制作效率；同样的，将数据线180与公共电极总线150同层且同材料制作，也能够减少显示基板的制作步骤，提高制作效率。
进一步地，如图4所示，所述显示区域Ⅰ还包括由所述栅线170和所述数据线180限定出的像素区域，每个像素区域内包括像素电极190和公共电极(图未示)；
所述第一导电图形120与所述公共电极同层同材料设置；
所述第二导电图形140与所述像素电极190同层同材料设置。
本实施例中，位于外围区域Ⅱ的第一导电图形120和位于显示区域Ⅰ内每一显示区域Ⅰ内的公共电极可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第三导电材料层后，利用掩膜版3进行曝光、刻蚀后同时得到在外围区域Ⅱ的第一导电图形120和显示区域Ⅰ内的公共电极。此时，第一导电图形120和公共电极均为第三导电材料，且均为第三导电材料层所在的层。
位于外围区域Ⅱ的第二导电图形140和位于显示区域Ⅰ内每一显示区域Ⅰ内的像素电极190可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第四导电材料层后，利用掩膜版4进行曝光、刻蚀后同时得到 在外围区域Ⅱ的第二导电图形140和显示区域Ⅰ内的显示电极。此时，第二导电图形140和像素电极190均为第三导电材料，且均为第三导电材料层所在的层。
本实施例中，通过将第一导电图形120与公共电极同层同材料设置，能够减少显示基板的制作步骤，提高制作效率；同样的，将第二导电图形140与像素电极190同层同材料设置，也能够减少显示基板的制作步骤，提高制作效率。
本公开实施例还提供了一种显示面板，包括如上所述的显示基板。
本公开实施例还提供一种显示基板的制作方法，所述方法包括：
提供一衬底基板，包括显示区域和包围所述显示区域设置的外围区域；
在所述衬底基板上形成相互电连接的公共电极线和第一导电图形，其中，所述公共电极线沿第一方向延伸且位于显示区域和部分外围区域，所述第一导电图形位于所述外围区域；
形成覆盖所述第一导电图形和所述公共电极线的绝缘层，所述绝缘层上开设有过孔，所述过孔在所述衬底基板上的正投影与所述公共电极线在所述衬底基板上的正投影不交叠；
在所述绝缘层上形成第二导电图形，所述第二导电图形通过所述过孔与所述第一导电图形电连接。
本公开实施例中，通过与公共电极线电连接的第一导电图形，以及通过过孔与所述第一导电图形电连接的第二导电图形，能够在外围区域内实现公共电极线与位于其他层的公共电极总线之间的电连接，从而统一各公共电极走线的公共电压，增强显示装置显示的均一性。因此，本公开提供的技术方案能够统一各公共电极走线的公共电压，增强显示装置显示的均一性。
如图1和图2所示，上述公共电极线110的数量可以是多根，多根沿第一方向延伸的公共电极线110在衬底基板上平行设置，其中，公共电极线110位于显示区域Ⅰ内的部分用于与像素区域内的公共电极连接。
显示区域Ⅰ内的多个像素区域可以是呈阵列排布，其中，第一方向可以与阵列排布中的行方向平行，也可以是阵列排布中的列方向平行，此处不作限定。假设，第一方向与阵列排布中的行方向平行，则可以是位于同一行的 像素区域中的公共电极均与同一根公共电极线110电连接。
公共电极线110中位于外围区域Ⅱ的部分可以是一个，即公共电极线110分为相互连接的两部分，第一部分位于显示区域Ⅰ，第二部分位于外围区域Ⅱ，第二部分通过外围区域Ⅱ中公共电极总线提供的公共电压提供给第一部分，作为与第一部分相连的各公共电极的参考电压，其中，公共电压信号的传输方向为第二部分向第一部分传输；公共电极线110中位于外围区域Ⅱ的部分也可以是两个，即公共电极线110分为相互连接的三部分，第一部分位于显示区域Ⅰ，另外的两个第二部分分别位于相对两侧的外围区域Ⅱ，位于两侧外围区域Ⅱ的两个第二部分同时通过外围区域Ⅱ中公共电极总线提供的公共电压提供给第一部分，作为与第一部分相连的各公共电极的参考电压，其中，公共电压信号的传输方向为两个第二部分同时向第一部分传输。
其中，公共电极线110中位于外围区域Ⅱ的第二部分为两个时，公共电极线的两端共同为显示区域Ⅰ内的第一部分提供公共电压信号，能够减少公共电压信号的传输距离，降低电压损耗，显示装置显示均一性的效果更理想。
上述第一导电图形120位于外围区域Ⅱ内，用于将公共电极线110与公共电极总线连接，使得显示基板每一根公共电极线均与公共电极总线连接，提高显示基板显示的均一性。
上述绝缘层130可以为有机绝缘层，也可以为无机绝缘层。绝缘层130上开设的过孔131在衬底基板上的正投影与公共电极线110在衬底基板上的正投影不交叠，且与第一导电图形120在衬底基板上的正投影交叠。
上述第二导电图形140位于外围区域Ⅱ内，第二导电图形140的一端通过过孔与第一导电图形120电连接，第二导电图形140的另一端可以直接与公共电极总线连接，也可以是间接通过其他导电图形与公共电极总线连接，此处不作限定。
需要说明的是，上述公共电极总线可以是设置于外围区域Ⅱ内且位于显示区域Ⅰ的第一侧，各公共电极线110包括位于显示区域Ⅰ的第一部分和位于第一部分第一侧的第二部分，第二部分均通过第一导电图形120和第二导电图形140与公共电极总线电连接；上述公共电极总线也可以是设置于外围区域Ⅱ内且环绕显示区域Ⅰ设置的封闭图形，各公共电极线110包括位于显 示区域Ⅰ的第一部分和位于外围区域Ⅱ的第二部分，第二部分可以是位于第一部分在第一方向上的任意一端或两端，每一个第二部分均通过第一导电图形120和第二导电图形140与公共电极总线电连接。
其中，所述公共电极线为铜走线。
铜材料具有优良的导电性能，相较于铝材料等其他金属导电材料而言，不仅能够降低信号传输的延时量，还能够降低走线的电阻，从而降低显示装置的功耗。
然而，由于铜材料的性质较为活泼，公共电极线采用铜走线后，若绝缘层130上的过孔在衬底基板上的正投影与第一公共电极线交叠，会出现过孔形成后铜暴露出来与外界发生反应而出现变质的情况，这样后续第二导电图形140通过过孔与变质的公共电极线110的连接处会有较高的接触电阻，造成显示过程中连接处发热异常的问题。
如图2所示，通过第一导电图形120能够避免铜材料的公共电极线直接暴露在外发生变质的情况发生，确保未变质的公共电极线与第二导电图形140之间连接处的接触电阻较小，避免显示过程中连接处发热异常的情况，提高显示装置的可靠性。
进一步地，所述在所述衬底基板上形成相互电连接的公共电极线和第一导电图形，包括：
在所述衬底基板上形成第一导电图形；在所述显示区域和部分第一导电图形上形成公共电极线；或者，
在所述衬底基板上形成公共电极线；在所述外围区域和部分公共电极线上形成第一导电图形。
本实施例中，可以是先形成第一导电图形120，之后再在衬底基板上形成与第一导电图形120相连的公共电极线110，即所述第一导电图形120位于所述公共电极线靠近所述衬底基板的一侧。
也可以是先形成公共电极线110，之后再在衬底基板上形成与公共电极线110相连的第一导电图形120，即所述第一导电图形120位于所述公共电极线110远离所述衬底基板的一侧。
进一步地，在所述绝缘层上形成第二导电图形之前，还包括：
在所述绝缘层上形成公共电极总线，所述公共电极总线位于所述外围区域；
所述绝缘层上形成第二导电图形，包括：
在所述外围区域和部分所述公共电极总线上形成第二导电图形。
本实施例中，可以是先形成公共电极总线150，之后再在衬底基板上形成与公共电极总线150相连的第二导电图形140。即第二导电图形140位于公共电极总线150远离所述衬底基板的一侧。
进一步地，形成公共电极线，包括：
通过一次构图工艺，在所述显示区域形成沿第一方向延伸的栅线和与所述栅线平行的公共电极线。
本实施例中，位于显示区域Ⅰ和外围区域Ⅱ的公共电极线110和位于显示区域Ⅰ内的栅线170可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第一导电材料层后，利用掩膜版1进行曝光、刻蚀后同时得到相互平行的公共电极线110和栅线170。此时，公共电极线110和栅线170均为第一导电材料，且均处于第一导电材料层所在的层。
通过将栅线170与公共电极线110同层且同材料制作，能够减少显示基板的制作步骤，提高制作效率。
进一步地，形成公共电极总线，包括：
通过一次构图工艺，在所述显示区域形成沿第二方向延伸的数据线180和位于外围区域公共电极总线。
本实施例中，位于外围区域Ⅱ的公共电极总线150和位于显示区域Ⅰ内的数据线180可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第二导电材料层后，利用掩膜版2进行曝光、刻蚀后同时得到位于显示区域Ⅰ内的数据线180和位于外围区域Ⅱ且包围显示区域Ⅰ设置的公共电极总线150。此时，公共电极总线150和数据线180均为第二导电材料，且均处于第二导电材料层所在的层。
通过将数据线180与公共电极总线150同层且同材料制作，也能够减少显示基板的制作步骤，提高制作效率。
进一步地，形成第一导电图形，包括：
通过一次构图工艺，在所述显示区域形成公共电极，在所述外围区域形成第一导电图形。
本实施例中，位于外围区域Ⅱ的第一导电图形120和位于显示区域Ⅰ内每一显示区域Ⅰ内的公共电极可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第三导电材料层后，利用掩膜版3进行曝光、刻蚀后同时得到在外围区域Ⅱ的第一导电图形120和显示区域Ⅰ内的公共电极。此时，第一导电图形120和公共电极均为第三导电材料，且均为第三导电材料层所在的层。
通过将第一导电图形120与公共电极同层同材料设置，能够减少显示基板的制作步骤，提高制作效率。
进一步地，形成第一导电图形，包括：
通过一次构图工艺，在所述显示区域形成公共电极，在所述外围区域形成第一导电图形。
本实施例中，位于外围区域Ⅱ的第二导电图形140和位于显示区域Ⅰ内每一显示区域Ⅰ内的像素电极190可以通过一次构图工艺同时制作得到的，即在衬底基板上形成整层的第四导电材料层后，利用掩膜版4进行曝光、刻蚀后同时得到在外围区域Ⅱ的第二导电图形140和显示区域Ⅰ内的显示电极。此时，第二导电图形140和像素电极190均为第三导电材料，且均为第三导电材料层所在的层。
通过将第二导电图形140与像素电极190同层同材料设置，也能够减少显示基板的制作步骤，提高制作效率。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置 改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视本公开的保护范围。

Claims (15)

  1. 一种显示基板，包括显示区域和设置于所述显示区域周边的外围区域，其中，包括：
    在衬底基板上沿第一方向延伸的公共电极线，所述公共电极线位于所述显示区域和外围区域；
    第一导电图形，位于所述外围区域内，与所述公共电极线电连接；
    覆盖所述第一导电图形和所述公共电极线的绝缘层，所述绝缘层开设有过孔，所述过孔在所述衬底基板上的正投影与所述公共电极线在所述衬底基板上的正投影不交叠；
    第二导电图形，位于所述外围区域内且位于所述绝缘层远离所述第一导电图形一侧，所述第二导电图形通过所述过孔与所述第一导电图形电连接。
  2. 根据权利要求1所述的显示基板，其中，所述公共电极线为铜走线。
  3. 根据权利要求1所述的显示基板，其中，所述第一导电图形位于所述公共电极线靠近所述衬底基板的一侧，或者，所述第一导电图形位于所述公共电极线远离所述衬底基板的一侧。
  4. 根据权利要求1所述的显示基板，其中，还包括公共电极总线，所述公共电极总线位于所述外围区域且包围所述显示区域设置；所述公共电极总线位于所述绝缘层远离所述第一导电图形一侧，并与所述第二导电图形电连接，所述第一方向与所述第二方向垂直。
  5. 根据权利要求4所述的显示基板，其中，所述第二导电图形位于所述公共电极总线远离所述衬底基板的一侧，或者，所述二导电图形位于所述公共电极总线靠近所述衬底基板的一侧。
  6. 根据权利要求4所述的显示基板，其中，所述显示区域包括栅线和数据线；
    所述公共电极线与所述栅线平行，且所述公共电极线与所述栅线同层同材料设置；
    所述公共电极总线与所述数据线同层同材料设置。
  7. 根据权利要求6所述的显示基板，其中，所述显示区域还包括由所述栅 线和所述数据线限定出的像素区域，每个像素区域内包括像素电极和公共电极；
    所述第一导电图形与所述公共电极同层同材料设置；
    所述第二导电图形与所述像素电极同层同材料设置。
  8. 一种显示面板，包括如权利要求1-7中任一项所述的显示基板。
  9. 一种显示基板的制作方法，所述方法包括：
    提供一衬底基板，包括显示区域和包围所述显示区域设置的外围区域；
    在所述衬底基板上形成相互电连接的公共电极线和第一导电图形，其中，所述公共电极线沿第一方向延伸且位于显示区域和外围区域，所述第一导电图形位于所述外围区域；
    形成覆盖所述第一导电图形和所述公共电极线的绝缘层，所述绝缘层上开设有过孔，所述过孔在所述衬底基板上的正投影与所述公共电极线在所述衬底基板上的正投影不交叠；
    在所述绝缘层上形成第二导电图形，所述第二导电图形通过所述过孔与所述第一导电图形电连接。
  10. 根据权利要求9所述的方法，其中，所述在所述衬底基板上形成相互电连接的公共电极线和第一导电图形，包括：
    在所述衬底基板上形成第一导电图形；在所述显示区域和部分第一导电图形上形成公共电极线；或者，
    在所述衬底基板上形成公共电极线；在所述外围区域和部分公共电极线上形成第一导电图形。
  11. 根据权利要求9所述的方法，其中，在所述绝缘层上形成第二导电图形之前，还包括：
    在所述绝缘层上形成公共电极总线，所述公共电极总线位于所述外围区域；
    所述绝缘层上形成第二导电图形，包括：
    在所述外围区域和部分所述公共电极总线上形成第二导电图形。
  12. 根据权利要求9所述的方法，其中，形成公共电极线，包括：
    通过一次构图工艺，在所述显示区域形成沿第一方向延伸的栅线和与所 述栅线平行的公共电极线。
  13. 根据权利要求11所述的方法，其中，形成公共电极总线，包括：
    通过一次构图工艺，在所述显示区域形成沿第二方向延伸的数据线和位于所述外围区域的公共电极总线。
  14. 根据权利要求9所述的方法，其中，形成第一导电图形，包括：
    通过一次构图工艺，在所述显示区域形成公共电极，在所述外围区域形成第一导电图形。
  15. 根据权利要求9所述的方法，其中，形成第二导电图形，包括：
    通过一次构图工艺，在所述显示区域形成像素电极，在所述外围区域形成第二导电图形。
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