WO2021031532A1 - 触控阵列基板及其制备方法 - Google Patents

触控阵列基板及其制备方法 Download PDF

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Publication number
WO2021031532A1
WO2021031532A1 PCT/CN2020/072587 CN2020072587W WO2021031532A1 WO 2021031532 A1 WO2021031532 A1 WO 2021031532A1 CN 2020072587 W CN2020072587 W CN 2020072587W WO 2021031532 A1 WO2021031532 A1 WO 2021031532A1
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Prior art keywords
layer
pixel electrode
touch
electrode
array substrate
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Application number
PCT/CN2020/072587
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English (en)
French (fr)
Inventor
颜源
许勇
艾飞
宋德伟
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/966,116 priority Critical patent/US12068330B2/en
Publication of WO2021031532A1 publication Critical patent/WO2021031532A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • This application relates to a display technology, in particular to a touch array substrate and a preparation method thereof.
  • the embodiments of the present application provide a touch array substrate and a preparation method thereof, so as to solve the technical problems of high production cost and long cycle of the existing touch array substrate.
  • An embodiment of the application provides a touch array substrate, which includes a substrate and a buffer layer provided on the substrate, wherein the touch array substrate includes:
  • An active layer disposed on the buffer layer, the active layer including a first region corresponding to the source of the thin film transistor and a second region corresponding to the drain of the thin film transistor;
  • An insulating layer arranged on the active layer and covering the active layer and the buffer layer;
  • a metal layer is correspondingly stacked on a plurality of base layers of the pixel electrode layer, and the metal layer includes touch signal lines, data lines, gates and gate lines;
  • a flat layer disposed on the metal layer and covering the metal layer, the pixel electrode and the insulating layer;
  • the common electrode layer is disposed on the flat layer, the common electrode layer includes a touch electrode, the source electrode and the drain electrode, the touch electrode is connected to the touch signal line, and the source electrode One end of the drain is connected to the first area, the other end of the source is connected to the data line, one end of the drain is connected to the second area, and the other end of the drain is connected to the pixel electrode Connected
  • the gate is connected to the gate line and is integrally formed; the extension direction of the gate line is perpendicular to the extension direction of the data line, and the gate line is spaced apart from the data line;
  • the common electrode layer further includes a plurality of connecting lines, and the gate lines in each row are connected by the connecting lines;
  • the plurality of base layers include a first base layer, a second base layer, and a third base layer.
  • the extension direction of the first base layer is consistent with the extension direction of the touch signal line.
  • the extension direction of the second base layer is consistent with the extension direction of the data.
  • the extension direction of the lines is the same, and the extension direction of the third base layer is the same as the extension direction of the gate lines;
  • the touch signal line is stacked on the first base layer, the data line is stacked on the second base layer, and the gate line is stacked on the third base layer.
  • An embodiment of the present application also provides a touch array substrate, which includes a substrate and a buffer layer provided on the substrate, the touch array substrate includes:
  • An active layer disposed on the buffer layer, the active layer including a first region corresponding to the source of the thin film transistor and a second region corresponding to the drain of the thin film transistor;
  • An insulating layer arranged on the active layer and covering the active layer and the buffer layer;
  • a metal layer is correspondingly stacked on a plurality of base layers of the pixel electrode layer, and the metal layer includes touch signal lines, data lines, gates and gate lines;
  • a flat layer disposed on the metal layer and covering the metal layer, the pixel electrode and the insulating layer;
  • the common electrode layer is disposed on the flat layer, the common electrode layer includes a touch electrode, the source electrode and the drain electrode, the touch electrode is connected to the touch signal line, and the source electrode One end of the drain is connected to the first area, the other end of the source is connected to the data line, one end of the drain is connected to the second area, and the other end of the drain is connected to the pixel electrode Connected.
  • the gate is connected to the gate line and formed integrally; the extension direction of the gate line is perpendicular to the extension direction of the data line, and the gate line and the data line Set apart
  • the common electrode layer further includes a plurality of connecting lines, and the gate lines in each row are connected by the connecting lines.
  • the multiple base layers include a first base layer, a second base layer, and a third base layer.
  • the extension direction of the first base layer is consistent with the extension direction of the touch signal line.
  • the extension direction of the second base layer is consistent with the extension direction of the data line, and the extension direction of the third base layer is consistent with the extension direction of the gate line;
  • the touch signal line is stacked on the first base layer, the data line is stacked on the second base layer, and the gate line is stacked on the third base layer.
  • the present application also relates to a method for preparing a touch array substrate, and the method includes:
  • a pixel electrode layer and a metal layer are sequentially formed on the insulating layer, and a mask is used to pattern the pixel electrode layer and the metal layer to form pixel electrodes, touch signal lines, data lines, and gates;
  • a patterned common electrode layer is formed on the flat layer to form a touch electrode, the source electrode, and the drain electrode, the touch electrode is connected to the touch signal line, and one end of the source electrode It is connected to the first area, the other end of the source electrode is connected to the data line, one end of the drain electrode is connected to the second area, and the other end of the drain electrode is connected to the pixel electrode.
  • the pixel electrode layer and the metal layer are sequentially formed on the insulating layer, and a photomask is used to pattern the pixel electrode layer and the metal layer to form Pixel electrodes, touch signal lines, data lines and gates, including:
  • a first halftone photomask is used to expose the first photoresist layer, and then the first photoresist layer is developed to form a patterned first photoresist layer;
  • the patterned first photoresist layer includes corresponding The first part of the metal layer where the gate, the data line, and the touch signal line are to be formed, the second part corresponding to the pixel electrode to be formed in the pixel electrode layer, and the first part corresponding to the active layer Area and the first through hole of the second area, the thickness of the first part is greater than the thickness of the second part;
  • etching the metal layer and the pixel electrode layer to form the gate, the data line and the touch signal line;
  • the active layer is lightly doped.
  • the first halftone mask includes a first light-transmitting portion and a second light-transmitting portion, and the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion.
  • the light transmittance of the light transmitting portion, the light transmittance of the first light transmitting portion is 100%, the first light transmitting portion corresponds to the first through hole to be formed, and the second light transmitting portion corresponds to the The pixel electrode to be formed in the pixel electrode layer.
  • the forming a patterned common electrode layer on the flat layer includes the following steps:
  • the hydrogen in the flat layer is used as a hydrogen source, and the active layer is subjected to hydrogenation treatment.
  • the forming a patterned common electrode layer on the flat layer includes the following steps:
  • a second photoresist layer is formed on the flat layer, and the second photoresist layer is patterned.
  • the patterned second photoresist layer includes a first region and a second region corresponding to the active layer.
  • the second through hole of the region, the third through hole corresponding to the pixel electrode, the fourth through hole corresponding to the touch signal line and the data line, the touch electrode to be formed corresponding to the common electrode layer, the source The third portion of the electrode and the drain and the fourth portion corresponding to the portion of the common electrode layer to be removed; the thickness of the third portion is smaller than the thickness of the fourth portion;
  • the step of forming a common electrode layer on the second photoresist layer includes:
  • a second halftone photomask is used to expose the second photoresist layer
  • the second halftone mask includes a third light-transmitting portion and a fourth light-transmitting portion, the light transmittance of the third light-transmitting portion is greater than the light transmittance of the fourth light-transmitting portion, and the first The light transmittance of the three light-transmitting portions is 100%, the third light-transmitting portion corresponds to the second, third, and fourth through-holes to be formed, and the fourth light-transmitting portion corresponds to the common The touch electrode to be formed on the electrode layer.
  • the touch array substrate and the preparation method of the present application share a photomask with the metal layer and the pixel electrode layer to form a gate, touch signal lines, data lines and pixel electrodes.
  • the process steps are saved; the technical problems of high production cost and long cycle of the existing touch-sensitive array substrate are solved.
  • FIG. 1 is a schematic flowchart of a manufacturing method of a touch array substrate according to an embodiment of the application
  • FIG. 2 is a schematic diagram of another process of the manufacturing method of the touch array substrate according to the embodiment of the application;
  • FIG. 3 is a schematic flowchart of step S3 of the method for manufacturing a touch array substrate according to an embodiment of the application;
  • FIG. 4 is a schematic flowchart of step S5 of the method for manufacturing a touch array substrate according to an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of a touch array substrate according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of a top view structure of a touch array substrate according to an embodiment of the application.
  • FIG. 1 is a schematic flow diagram of a method for manufacturing a touch array substrate according to an embodiment of the application
  • FIG. 2 is another schematic flow diagram of a method for manufacturing a touch array substrate according to an embodiment of the application.
  • a manufacturing method of a touch array substrate according to an embodiment of the present application includes:
  • Step S1 Provide a substrate
  • Step S2 sequentially forming a buffer layer, an active layer and an insulating layer on the substrate.
  • the active layer includes a first region corresponding to the source of the thin film transistor and a second region corresponding to the drain of the thin film transistor. area;
  • Step S3 A pixel electrode layer and a metal layer are sequentially formed on the insulating layer, and a mask is used to pattern the pixel electrode layer and the metal layer to form pixel electrodes, touch signal lines, data lines, and gates. pole;
  • Step S4 forming a flat layer on the metal layer
  • Step S5 A patterned common electrode layer is formed on the flat layer to form a touch electrode, the source electrode and the drain electrode, the touch electrode is connected to the touch signal line, and the source One end of the electrode is connected to the first area, the other end of the source electrode is connected to the data line, one end of the drain electrode is connected to the second area, and the other end of the drain electrode is connected to the pixel The electrodes are connected.
  • Step S1 Provide a substrate 11. Then go to step S2.
  • Step S2 forming a buffer layer 12, an active layer 13 and an insulating layer 14 on the substrate 11 in sequence.
  • the active layer 13 includes a first region a corresponding to the source of the thin film transistor and a second region b corresponding to the drain of the thin film transistor.
  • the buffer layer 12 and the amorphous silicon layer are sequentially formed on the substrate 11, the amorphous silicon layer is subjected to laser laser annealing treatment to form a low-temperature polysilicon layer, and then the layer is modified to form the active layer 13, and then there is An insulating layer 14 is formed on the source layer 13.
  • the insulating layer 14 covers the buffer layer 12 and the active layer 13.
  • a light shielding layer for shielding the active layer 12 is saved. Since the light shielding layer is saved, it is necessary to adjust the ion doping ratio of the source/drain region of the active layer 13 to overcome the weak electric property generated after the active layer is illuminated. Then go to step S3.
  • Step S3 A pixel electrode layer 15 and a metal layer 16 are sequentially formed on the insulating layer 14, and a photomask is used to pattern the pixel electrode layer 15 and the metal layer 16 to form a pixel electrode 151 and a touch signal Line 161, data line 162, and gate 163.
  • Step S3 includes:
  • Step S31 sequentially forming a pixel electrode layer 15, a metal layer 16 and a first photoresist layer 21 on the insulating layer 14;
  • Step S32 Expose the first photoresist layer 21 by using a first half-tone mask, and then develop the first photoresist layer 21 to form a patterned first photoresist layer 21;
  • a photoresist layer 21 includes a first portion 211 corresponding to the gate 163, data line 162, and touch signal line 161 to be formed in the metal layer 16, and a first portion 211 corresponding to the pixel electrode 151 to be formed in the pixel electrode layer 15.
  • Step S33 Using the patterned first photoresist layer 21 as a mask, etch the metal layer 16 and the pixel electrode layer 15 to form the gate 163, the data line 162 and the touch signal line 161;
  • Step S34 heavily doping the first region a and the second region b of the active layer 13 through the first through hole 213;
  • Step S35 Ashing the patterned first photoresist layer 21 to make the first portion 211 thinner and the second portion 212 disappear;
  • Step S36 etching and removing the exposed metal layer 16 so that the pixel electrode layer 15 forms a pixel electrode 151;
  • Step S37 removing the remaining first photoresist layer 21;
  • Step S38 lightly doping the active layer 13.
  • the first through hole 213 is used as the doping channel for the first region a and the second region b of the active layer 13, and the first through hole 213 defines the doped area of the active layer 13
  • the range, that is, the heavily doped region of the active layer 13 is defined by the patterned first photoresist layer 21.
  • the lightly doped region of the active layer 13 is defined by the patterned pixel electrode layer 15 and the metal layer 16.
  • a photomask is used to form the patterned pixel electrode layer 15 and the metal layer 16, which not only saves the insulating layer between the pixel electrode layer and the metal layer, but also saves process steps and a photomask compared with the prior art , Thereby reducing costs.
  • the gate 163 and the gate line 164 are connected and integrally formed, and their extension directions are the same.
  • the plurality of base layers include a first base layer, a second base layer, and a third base layer.
  • the extension direction of the first base layer is consistent with the extension direction of the touch signal line 161, and the extension direction of the second base layer is the same as that of the data line.
  • the extension direction of the 162 is the same, and the extension direction of the third base layer is the same as the extension direction of the gate line 164.
  • the touch signal line 161 is stacked on the first base layer
  • the data line 162 is stacked on the second base layer
  • the gate line 164 is stacked on the third base layer.
  • the first halftone mask includes a first light-transmitting portion and a second light-transmitting portion, and the light transmittance of the first light-transmitting portion is greater than the light transmittance of the second light-transmitting portion,
  • the light transmittance of the first light transmission portion is 100%, the first light transmission portion corresponds to the first through hole 213 to be formed, and the second light transmission portion corresponds to the pixel electrode layer 15 to be formed ⁇ pixel electrode 151.
  • Step S4 forming a flat layer on the metal layer 16. Specifically, a flat layer 17 is formed on the patterned metal layer 16. The flat layer 17 covers the metal layer 16, the pixel electrode layer 15 and the insulating layer 14; then the hydrogen in the flat layer 17 is used as a hydrogen source, and the active layer 13 is subjected to hydrogenation treatment. Then go to step S5.
  • Step S5 forming a patterned common electrode layer 18 on the flat layer 17 to form a touch electrode 181, the source electrode 182, and the drain electrode 183.
  • the touch electrode 181 is connected to the touch signal line 161.
  • One end of the source electrode 182 is connected to the first region a, and the other end of the source electrode 182 is connected to the data line 162.
  • One end of the drain electrode 183 is connected to the second region b, and the other end of the drain electrode 183 is connected to the pixel electrode 151.
  • step S5 includes:
  • a second photoresist layer 22 is formed on the flat layer 17, and the second photoresist layer 22 is patterned.
  • the patterned second photoresist layer 22 includes a pattern corresponding to the active layer 13
  • the thickness of the third portion 224 is less than the thickness of the fourth portion 225;
  • step S44 may be omitted.
  • the function of this step is to form a chamfer below the bottom surface of the second photoresist layer 22, which on the one hand facilitates the common electrode layer 18 on the fourth portion 225 and on the flat layer 17. The part is quickly disconnected; on the other hand, it is easy to peel off the second photoresist layer 22.
  • the patterned common electrode layer 18 further includes a connecting wire 184.
  • the gate lines 164 in each row are connected by the connecting line 184.
  • step S41 the connecting line 184 to be formed on the common electrode layer 18 also corresponds to the third portion 224 of the second photoresist layer 22. (Not shown in Figure 4)
  • a second half-tone mask is used to expose the second photoresist layer;
  • the second half-tone mask includes a third light-transmitting portion and a fourth light-transmitting portion, the third light-transmitting portion
  • the light transmittance is greater than the light transmittance of the fourth light transmission portion, the light transmittance of the third light transmission portion is 100%, and the third light transmission portion corresponds to the second through holes 221, the third The through hole 222 and the fourth through hole 223.
  • the fourth light transmission portion corresponds to the touch electrode 181 to be formed on the common electrode layer 18.
  • the common electrode layer 18 is a transparent conductive layer.
  • the material of the transparent conductive layer is silver.
  • the present application also relates to a touch array substrate 100, which includes a substrate 11 and a buffer layer 12, an active layer 13, an insulating layer 14, a pixel electrode layer 15, and The metal layer 16, the flat layer 17, and the common electrode layer 18.
  • the active layer 13 is provided on the buffer layer 12.
  • the active layer 13 includes a first region a corresponding to the source of the thin film transistor and a second region b corresponding to the drain of the thin film transistor.
  • the insulating layer 14 is disposed on the active layer 13 and covers the active layer 13 and the buffer layer 12.
  • the pixel electrode layer 15 is provided on the insulating layer 14.
  • the pixel electrode layer 15 includes a pixel electrode 151 and a plurality of base layers 152 arranged in the same layer as the pixel electrode 151.
  • the metal layer 16 is correspondingly stacked on the plurality of base layers 152 of the pixel electrode layer 15.
  • the metal layer 16 includes touch signal lines 161, data lines 162, gates 163 and gate lines 164.
  • the flat layer 17 is disposed on the metal layer 16 and covers the metal layer 16, the pixel electrode 15 and the insulating layer 14.
  • the common electrode layer 18 is provided on the flat layer 17.
  • the common electrode layer 18 includes a touch electrode 181, the source electrode 182 and the drain electrode 183.
  • the touch electrode 181 is connected to the touch signal line 161.
  • One end of the source electrode 182 is connected to the first region a, and the other end of the source electrode 182 is connected to the data line 162.
  • One end of the drain electrode 183 is connected to the second region b, and the other end of the drain electrode 183 is connected to the pixel electrode 151.
  • a plurality of via holes 171 are excavated in the flat layer 17.
  • the touch electrode 181 is connected to the touch signal line 161 through a via 171.
  • One end of the source electrode 182 is connected to the first region a through a via hole 171, and the other end of the source electrode 182 is connected to the data line 162 via a via hole 171.
  • One end of the drain electrode 183 is connected to the second region b through a via hole 171, and the other end of the drain electrode 183 is connected to the pixel electrode 151 through a via hole 171.
  • the metal layer 16 is stacked on the pixel electrode layer 15 and a photomask is shared in the process, which saves process steps, saves the number of photomasks, and reduces costs. And through a photomask manufacturing process, the touch signal line 161, the data line 162, the gate electrode 163, the gate line 164 and the pixel electrode 151 are formed at one time.
  • step S3 of the above-mentioned manufacturing method of the touch array substrate please refer to step S3 of the above-mentioned manufacturing method of the touch array substrate.
  • the gate electrode 163 is connected to the gate line 164 and is formed integrally.
  • the extension direction of the gate line 164 is perpendicular to the extension direction of the data line 162, and the gate line 164 is spaced apart from the data line 162.
  • the common electrode layer 18 further includes a plurality of connecting lines 184.
  • the gate lines 164 in each row are connected by the connecting line 184.
  • one end of the connecting line 184 is connected to one of the gate lines 164 through a via 171
  • the other end of the connecting line 184 is connected to the other gate line 164 through a via 171.
  • the plurality of base layers 152 include a first base layer, a second base layer, and a third base layer.
  • the extension direction of the first base layer is the same as that of the touch signal line 161.
  • the direction is the same.
  • the extension direction of the second base layer is consistent with the extension direction of the data line 162.
  • the extension direction of the third base layer is consistent with the extension direction of the gate line 164.
  • the touch signal line 161 is stacked on the first base layer
  • the data line 162 is stacked on the second base layer
  • the gate line 164 is stacked on the third base layer.
  • the touch array substrate and the preparation method of the present application share a photomask with the metal layer and the pixel electrode layer to form a gate, touch signal lines, data lines and pixel electrodes.
  • the process steps are saved; the technical problems of high production cost and long cycle of the existing touch-sensitive array substrate are solved.

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Abstract

一种触控阵列基板及其制备方法，在触控阵列基板中，缓冲层上依次设置有有源层、绝缘层、像素电极层、金属层、平坦层和公共电极层，有源层包括对应于源极的第一区域和对应于漏极的第二区域；像素电极层包括多个基层；金属层对应的叠设在基层上，金属层包括触控信号线、数据线和栅极；公共电极层包括触控电极、源极和漏极。

Description

触控阵列基板及其制备方法
本申请要求于2019年08月20日提交中国专利局、申请号为201910768751.0、发明名称为“触控阵列基板及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种显示技术，特别涉及一种触控阵列基板及其制备方法。
 背景技术
随着集成式触控显示面板的发展，人们对高分辨率的要求越来越高。因此需要精细的有源驱动矩阵（阵列基板）配合各像素区液晶进行偏转。
但是现有技术中的触控集成式的阵列基板的制备方法步骤较为繁琐，导致生产成本较高和周期较长。
 技术问题
本申请实施例提供一种触控阵列基板及其制备方法，以解决现有的触控式阵列基板生产成本较高和周期较长的技术问题。
 技术解决方案
本申请实施例提供一种触控阵列基板，其包括基板和设置在基板上的缓冲层，其中，所述触控阵列基板包括：
有源层，设置在所述缓冲层上，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
绝缘层，设置在所述有源层上并覆盖所述有源层和所述缓冲层；
像素电极层，设置在所述绝缘层上，所述像素电极层包括像素电极和与所述像素电极同层设置的多个基层；
金属层，对应的叠设在所述像素电极层的多个基层上，所述金属层包括触控信号线、数据线、栅极和栅线；
平坦层，设置在所述金属层上并覆盖所述金属层、像素电极和绝缘层；以及
公共电极层，设置在所述平坦层上，所述公共电极层包括触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连；
所述栅极与所述栅线相连且一体形成；所述栅线的延伸方向垂直于所述数据线的延伸方向，所述栅线与所述数据线相隔设置；
其中，所述公共电极层还包括多条连接线，每行的所述栅线通过所述连接线相连接；
所述多个基层包括第一基层、第二基层和第三基层，所述第一基层的延长方向与所述触控信号线的延伸方向一致，所述第二基层的延伸方向与所述数据线的延伸方向一致，所述第三基层的延伸方向与所述栅线的延伸方向一致；
所述触控信号线叠设在所述第一基层上，所述数据线叠设在所述第二基层上，所述栅线叠设在所述第三基层上。
本申请实施例还提供一种触控阵列基板，其包括基板和设置在基板上的缓冲层，所述触控阵列基板包括：
有源层，设置在所述缓冲层上，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
绝缘层，设置在所述有源层上并覆盖所述有源层和所述缓冲层；
像素电极层，设置在所述绝缘层上，所述像素电极层包括像素电极和与所述像素电极同层设置的多个基层；
金属层，对应的叠设在所述像素电极层的多个基层上，所述金属层包括触控信号线、数据线、栅极和栅线；
平坦层，设置在所述金属层上并覆盖所述金属层、像素电极和绝缘层；以及
公共电极层，设置在所述平坦层上，所述公共电极层包括触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连。
在本申请的触控阵列基板中，所述栅极与所述栅线相连且一体形成；所述栅线的延伸方向垂直于所述数据线的延伸方向，所述栅线与所述数据线相隔设置；
其中，所述公共电极层还包括多条连接线，每行的所述栅线通过所述连接线相连接。
在本申请的触控阵列基板中，所述多个基层包括第一基层、第二基层和第三基层，所述第一基层的延长方向与所述触控信号线的延伸方向一致，所述第二基层的延伸方向与所述数据线的延伸方向一致，所述第三基层的延伸方向与所述栅线的延伸方向一致；
所述触控信号线叠设在所述第一基层上，所述数据线叠设在所述第二基层上，所述栅线叠设在所述第三基层上。
本申请还涉及一种触控阵列基板的制备方法，所述制备方法包括：
提供一基板；
在所述基板上依次形成缓冲层、有源层和绝缘层，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
在所述绝缘层上依次形成像素电极层和金属层，并采用一光罩对所述像素电极层和金属层进行图案化处理，形成像素电极、触控信号线、数据线和栅极；
在所述金属层上形成平坦层；
在所述平坦层上形成图案化的公共电极层，以形成触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连。
在本申请的触控阵列基板的制备方法中，所述在所述绝缘层上依次形成像素电极层和金属层，并采用一光罩对所述像素电极层和金属层进行图案化处理，形成像素电极、触控信号线、数据线和栅极，包括：
依次在所述绝缘层上形成像素电极层、金属层和第一光阻层；
采用第一半色调光罩对所述第一光阻层进行曝光，随后对所述第一光阻层进行显影，形成图案化的第一光阻层；图案化的第一光阻层包括对应于所述金属层中待形成栅极、数据线和触控信号线的第一部分、对应于所述像素电极层中待形成像素电极的第二部分、以及对应于所述有源层的第一区域和第二区域的第一通孔，所述第一部分的厚度大于所述第二部分的厚度；
以图案化的第一光阻层为掩模，刻蚀所述金属层和像素电极层形成所述栅极、所述数据线和所述触控信号线；
通过所述第一通孔对所述有源层的第一区域和所述第二区域进行重掺杂处理；
灰化图案化的第一光阻层，使所述第一部分薄化和所述第二部分消失；
刻蚀去除裸露的金属层，使所述像素电极层形成像素电极；
去除剩余的第一光阻层；
对所述有源层进行轻掺杂处理。
在本申请的触控阵列基板的制备方法中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应待形成的第一通孔，所述第二透光部对应于所述像素电极层中待形成的像素电极。
在本申请的触控阵列基板的制备方法中，所述在所述平坦层上形成图案化的公共电极层，之前，包括步骤：
以所述平坦层的氢作为氢源，对应所述有源层进行氢化处理。
在本申请的触控阵列基板的制备方法中，所述在所述平坦层上形成图案化的公共电极层，包括以下步骤：
在所述平坦层上形成第二光阻层，并对所述第二光阻层进行图案化处理，图案化的第二光阻层包括对应于所述有源层的第一区域和第二区域的第二通孔、对应于所述像素电极的第三通孔、对应于所述触控信号线和数据线的第四通孔、对应于所述公共电极层待形成触控电极、源极和漏极的第三部分以及对应于所述公共电极层待去除部分的第四部分；所述第三部分的厚度小于所述第四部分的厚度；
以图案化的第二光阻层为掩模，刻蚀所述平坦层形成所述第二通孔、第三通孔和第四通孔；
灰化所述第二光阻层，去除所述第三部分；
在所述第二光阻层上形成公共电极层；
去除所述第二光阻层并位于所述第二光阻层上的所述公共电极层。
在本申请的触控阵列基板的制备方法中，所述在所述第二光阻层上形成公共电极层，之前包括步骤：
灰化所述平坦层，使所述第二光阻层的底面以下形成倒角。
在本申请的触控阵列基板的制备方法中，采用第二半色调光罩对所述第二光阻层进行曝光处理；
其中，所述第二半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应待形成的第二通孔、第三通孔和第四通孔，所述第四透光部对应于所述公共电极层待形成的触控电极。
 有益效果
相较于现有技术的触控阵列基板，本申请的触控阵列基板及其制备方法将金属层和像素电极层共用一光罩，形成栅极、触控信号线、数据线和像素电极，节省了工艺步骤；解决了现有的触控式阵列基板生产成本较高和周期较长的技术问题。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为本申请实施例的触控阵列基板的制备方法的流程示意图；
图2为本申请实施例的触控阵列基板的制备方法的另一流程示意图；
图3为本申请实施例的触控阵列基板的制备方法的步骤S3的流程示意图；
图4为本申请实施例的触控阵列基板的制备方法的步骤S5的流程示意图；
图5为本申请实施例的触控阵列基板的结构示意图；
图6为本申请实施例的触控阵列基板的俯视结构示意图。
 本发明的实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
请参照图1和图2，图1为本申请实施例的触控阵列基板的制备方法的流程示意图；图2为本申请实施例的触控阵列基板的制备方法的另一流程示意图。
本申请实施例的一种触控阵列基板的制备方法，所述制备方法包括：
步骤S1：提供一基板；
步骤S2：在所述基板上依次形成缓冲层、有源层和绝缘层，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
步骤S3：在所述绝缘层上依次形成像素电极层和金属层，并采用一光罩对所述像素电极层和金属层进行图案化处理，形成像素电极、触控信号线、数据线和栅极；
步骤S4：在所述金属层上形成平坦层；
步骤S5：在所述平坦层上形成图案化的公共电极层，以形成触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连。
下面对本申请实施例的触控阵列基板的制备方法进行阐述。
步骤S1：提供一基板11。随后转入步骤S2。
步骤S2：在所述基板11上依次形成缓冲层12、有源层13和绝缘层14。所述有源层13包括对应于薄膜晶体管的源极的第一区域a和对应于所述薄膜晶体管的漏极的第二区域b。
具体的，在基板11上依次形成缓冲层12和非晶硅层，对非晶硅层进行镭射激光退火处理以形成低温多晶硅层，接着对图层进行修饰处理形成有源层13，随后在有源层13上形成绝缘层14。绝缘层14覆盖缓冲层12和有源层13。
在本实施例中，节省了一遮挡有源层12的遮光层。由于节省了遮光层，则需要对有源层13的源/漏区域的部分进行离子掺杂比例的调整，以克服有源层被光照后产生的弱电性。随后转入步骤S3。
步骤S3：在所述绝缘层14上依次形成像素电极层15和金属层16，并采用一光罩对所述像素电极层15和金属层16进行图案化处理，形成像素电极151、触控信号线161、数据线162和栅极163。
具体的，请参照图3，步骤S3包括：
步骤S31：依次在所述绝缘层14上形成像素电极层15、金属层16和第一光阻层21；
步骤S32：采用第一半色调光罩对所述第一光阻层21进行曝光，随后对所述第一光阻层21进行显影，形成图案化的第一光阻层21；图案化的第一光阻层21包括对应于所述金属层16中待形成栅极163、数据线162和触控信号线161的第一部分211、对应于所述像素电极层15中待形成像素电极151的第二部分212、以及对应于所述有源层13的第一区域a和第二区域b的第一通孔213，所述第一部分211的厚度大于所述第二部分212的厚度；
步骤S33：以图案化的第一光阻层21为掩模，刻蚀所述金属层16和像素电极层15形成所述栅极163、所述数据线162和所述触控信号线161；
步骤S34：通过所述第一通孔213对所述有源层13的第一区域a和所述第二区域b进行重掺杂处理；
步骤S35：灰化图案化的第一光阻层21，使所述第一部分211薄化和所述第二部分212消失；
步骤S36：刻蚀去除裸露的金属层16，使所述像素电极层15形成像素电极151；
步骤S37：去除剩余的第一光阻层21；
步骤S38：对所述有源层13进行轻掺杂处理。
其中，在进行中掺杂处理时，以第一通孔213作为有源层13的第一区域a和第二区域b掺杂通道，第一通孔213界定了有源层13进行掺杂的范围，即以图案化的第一光阻层21界定出有源层13的重掺杂区。在进行轻掺杂时，去除第一光阻层21后，以图案化的像素电极层15和金属层16界定出有源层13的轻掺杂区。
采用一光罩便形成图案化的像素电极层15和金属层16，相较于现有技术不但节省了像素电极层和金属层之间的绝缘层，而且节省了工艺步骤和节省了一个光罩，进而降低了成本。
另外，请参照图5和图6，由于金属层16设置在像素电极层15上，所以在形成栅极163、数据线162、触控信号线161和栅线164时，栅线164、栅极163、数据线162和触控信号线161的覆盖像素电极层15的部分，其中该像素电极层15的部分定义为基层。栅极163和栅线164相连且一体成型，二者的延伸方向一致。
多个基层包括第一基层、第二基层和第三基层，所述第一基层的延长方向与所述触控信号线161的延伸方向一致，所述第二基层的延伸方向与所述数据线162的延伸方向一致，所述第三基层的延伸方向与所述栅线164的延伸方向一致。所述触控信号线161叠设在所述第一基层上，所述数据线162叠设在所述第二基层上，所述栅线164叠设在所述第三基层上。
在步骤S3中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应待形成的第一通孔213，所述第二透光部对应于所述像素电极层15中待形成的像素电极151。
随后转入步骤S4。
步骤S4：在所述金属层16上形成平坦层。具体的，在图案化的金属层16上形成平坦层17。平坦层17覆盖所述金属层16、像素电极层15和绝缘层14；随后以所述平坦层17的氢作为氢源，对应所述有源层13进行氢化处理。随后转入步骤S5。
步骤S5：在所述平坦层17上形成图案化的公共电极层18，以形成触控电极181、所述源极182和所述漏极183。
所述触控电极181与所述触控信号线161相连。所述源极182的一端与所述第一区域a相连，所述源极182的另一端与所述数据线162相连。所述漏极183的一端与所述第二区域b相连，所述漏极183的另一端与所述像素电极151相连。
具体的，请参照图4，步骤S5包括：
S51：在所述平坦层17上形成第二光阻层22，并对所述第二光阻层22进行图案化处理，图案化的第二光阻层22包括对应于所述有源层13的第一区域a和第二区域b的第二通孔221、对应于所述像素电极151的第三通孔222、对应于所述触控信号线161和数据线162的第四通孔223、对应于所述公共电极层18待形成触控电极181、源极182和漏极183的第三部分224以及对应于所述公共电极层18待去除部分的第四部分225。所述第三部分224的厚度小于所述第四部分225的厚度；
S52：以图案化的第二光阻层22为掩模，刻蚀所述平坦层17形成所述第二通孔221、第三通孔222和第四通孔223；
S53：灰化所述第二光阻层22，去除所述第三部分224；
S54：灰化所述平坦层17，使所述第二光阻层22的底面以下形成倒角。
S55：在所述第二光阻层22上形成公共电极层18；
S56：去除所述第二光阻层22并位于所述第二光阻层18上的所述公共电极层18。
在一些实施例中，可以省去步骤S44。在本实施例的步骤S44中，该步骤的作用在于所述第二光阻层22的底面以下形成倒角，一方面便于公共电极层18在第四部分225上的部分与在平坦层17上的部分快速地断开；另一方面便于剥离第二光阻层22。
请参照图6，图案化的公共电极层18还包括一连接线184。每行的所述栅线164通过所述连接线184相连接。
在步骤S41中，公共电极层18待形成的连接线184也对应于第二光阻层22的第三部分224。（图4未示出）
其中，采用第二半色调光罩对所述第二光阻层进行曝光处理；所述第二半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应待形成的第二通孔221、第三通孔222和第四通孔223。所述第四透光部对应于所述公共电极层18待形成的触控电极181。
所述公共电极层18为透明导电层。可选的，所述透明导电层的材质为银。
这样便完成了本申请的触控阵列基板的制备方法。
请参照图5和图6，本申请还涉及一种触控阵列基板100，其包括基板11和依次设置在基板11上的缓冲层12、有源层13、绝缘层14、像素电极层15、金属层16、平坦层17和公共电极层18。
有源层13设置在所述缓冲层12上。所述有源层13包括对应于薄膜晶体管的源极的第一区域a和对应于所述薄膜晶体管的漏极的第二区域b。
绝缘层14设置在所述有源层13上并覆盖所述有源层13和所述缓冲层12。
像素电极层15设置在所述绝缘层14上。所述像素电极层15包括像素电极151和与所述像素电极151同层设置的多个基层152。
金属层16对应的叠设在所述像素电极层15的多个基层152上。所述金属层16包括触控信号线161、数据线162、栅极163和栅线164。
平坦层17设置在所述金属层16上并覆盖所述金属层16、像素电极15和绝缘层14。
公共电极层18设置在所述平坦层17上。所述公共电极层18包括触控电极181、所述源极182和所述漏极183。所述触控电极181与所述触控信号线161相连。所述源极182的一端与所述第一区域a相连，所述源极182的另一端与所述数据线162相连。所述漏极183的一端与所述第二区域b相连，所述漏极183的另一端与所述像素电极151相连。
具体的，所述平坦层17中开挖有多个过孔171。所述触控电极181通过过孔171与所述触控信号线161相连。所述源极182的一端通过过孔171与所述第一区域a相连，所述源极182的另一端通过过孔171与所述数据线162相连。所述漏极183的一端通过过孔171与所述第二区域b相连，所述漏极183的另一端通过过孔171与所述像素电极151相连。
本申请实施例的触控阵列基板，将金属层16叠设在像素电极层15上，在工艺上共用一个光罩，节省了工艺的步骤，节省了光罩的数量，降低了成本。并通过一个光罩的制程，一次性形成触控信号线161、数据线162、栅极163、栅线164和像素电极151。具体的制程步骤请参照上述触控阵列基板的制备方法的步骤S3。
在本申请实施例的触控阵列基板100中，所述栅极163与所述栅线164相连且一体形成。所述栅线164的延伸方向垂直于所述数据线162的延伸方向，所述栅线164与所述数据线162相隔设置。
其中，所述公共电极层18还包括多条连接线184。每行的所述栅线164通过所述连接线184相连接。具体的，所述连接线184的一端通过过孔171与一所述栅线164相连，所述连接线184的另一端通过过孔171与另一所述栅线164相连。
在本申请实施例的触控阵列基板100中，所述多个基层152包括第一基层、第二基层和第三基层，所述第一基层的延长方向与所述触控信号线161的延伸方向一致。所述第二基层的延伸方向与所述数据线162的延伸方向一致。所述第三基层的延伸方向与所述栅线164的延伸方向一致。
所述触控信号线161叠设在所述第一基层上，所述数据线162叠设在所述第二基层上，所述栅线164叠设在所述第三基层上。
本申请实施例的阵列基板的制备方法的内容请参照上述阵列基板的制备方法的具体内容。
相较于现有技术的触控阵列基板，本申请的触控阵列基板及其制备方法将金属层和像素电极层共用一光罩，形成栅极、触控信号线、数据线和像素电极，节省了工艺步骤；解决了现有的触控式阵列基板生产成本较高和周期较长的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本申请的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本申请后附的权利要求的保护范围。

Claims (13)

  1. 一种触控阵列基板，其包括基板和设置在基板上的缓冲层，其中，所述触控阵列基板包括：
    有源层，设置在所述缓冲层上，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
    绝缘层，设置在所述有源层上并覆盖所述有源层和所述缓冲层；
    像素电极层，设置在所述绝缘层上，所述像素电极层包括像素电极和与所述像素电极同层设置的多个基层；
    金属层，对应的叠设在所述像素电极层的多个基层上，所述金属层包括触控信号线、数据线、栅极和栅线；
    平坦层，设置在所述金属层上并覆盖所述金属层、像素电极和绝缘层；以及
    公共电极层，设置在所述平坦层上，所述公共电极层包括触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连；
    所述栅极与所述栅线相连且一体形成；所述栅线的延伸方向垂直于所述数据线的延伸方向，所述栅线与所述数据线相隔设置；
    其中，所述公共电极层还包括多条连接线，每行的所述栅线通过所述连接线相连接；
    所述多个基层包括第一基层、第二基层和第三基层，所述第一基层的延长方向与所述触控信号线的延伸方向一致，所述第二基层的延伸方向与所述数据线的延伸方向一致，所述第三基层的延伸方向与所述栅线的延伸方向一致；
    所述触控信号线叠设在所述第一基层上，所述数据线叠设在所述第二基层上，所述栅线叠设在所述第三基层上。
  2. 一种触控阵列基板，其包括基板和设置在基板上的缓冲层，其中，所述触控阵列基板包括：
    有源层，设置在所述缓冲层上，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
    绝缘层，设置在所述有源层上并覆盖所述有源层和所述缓冲层；
    像素电极层，设置在所述绝缘层上，所述像素电极层包括像素电极和与所述像素电极同层设置的多个基层；
    金属层，对应的叠设在所述像素电极层的多个基层上，所述金属层包括触控信号线、数据线、栅极和栅线；
    平坦层，设置在所述金属层上并覆盖所述金属层、像素电极和绝缘层；以及
    公共电极层，设置在所述平坦层上，所述公共电极层包括触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连。
  3. 根据权利要求2所述的触控阵列基板，其中，所述栅极与所述栅线相连且一体形成；所述栅线的延伸方向垂直于所述数据线的延伸方向，所述栅线与所述数据线相隔设置；
    其中，所述公共电极层还包括多条连接线，每行的所述栅线通过所述连接线相连接。
  4. 根据权利要求2所述的触控阵列基板，其中，所述多个基层包括第一基层、第二基层和第三基层，所述第一基层的延长方向与所述触控信号线的延伸方向一致，所述第二基层的延伸方向与所述数据线的延伸方向一致，所述第三基层的延伸方向与所述栅线的延伸方向一致；
    所述触控信号线叠设在所述第一基层上，所述数据线叠设在所述第二基层上，所述栅线叠设在所述第三基层上。
  5. 一种触控阵列基板的制备方法，其中，所述制备方法包括：
    提供一基板；
    在所述基板上依次形成缓冲层、有源层和绝缘层，所述有源层包括对应于薄膜晶体管的源极的第一区域和对应于所述薄膜晶体管的漏极的第二区域；
    在所述绝缘层上依次形成像素电极层和金属层，并采用一光罩对所述像素电极层和金属层进行图案化处理，形成像素电极、触控信号线、数据线和栅极；
    在所述金属层上形成平坦层；
    在所述平坦层上形成图案化的公共电极层，以形成触控电极、所述源极和所述漏极，所述触控电极与所述触控信号线相连，所述源极的一端与所述第一区域相连，所述源极的另一端与所述数据线相连，所述漏极的一端与所述第二区域相连，所述漏极的另一端与所述像素电极相连。
  6. 根据权利要求5所述的触控阵列基板的制备方法，其中，所述在所述绝缘层上依次形成像素电极层和金属层，并采用一光罩对所述像素电极层和金属层进行图案化处理，形成像素电极、触控信号线、数据线和栅极，包括：
    依次在所述绝缘层上形成像素电极层、金属层和第一光阻层；
    采用第一半色调光罩对所述第一光阻层进行曝光，随后对所述第一光阻层进行显影，形成图案化的第一光阻层；图案化的第一光阻层包括对应于所述金属层中待形成栅极、数据线和触控信号线的第一部分、对应于所述像素电极层中待形成像素电极的第二部分、以及对应于所述有源层的第一区域和第二区域的第一通孔，所述第一部分的厚度大于所述第二部分的厚度；
    以图案化的第一光阻层为掩模，刻蚀所述金属层和像素电极层形成所述栅极、所述数据线和所述触控信号线；
    通过所述第一通孔对所述有源层的第一区域和所述第二区域进行重掺杂处理；
    灰化图案化的第一光阻层，使所述第一部分薄化和所述第二部分消失；
    刻蚀去除裸露的金属层，使所述像素电极层形成像素电极；
    去除剩余的第一光阻层；
    对所述有源层进行轻掺杂处理。
  7. 根据权利要求6所述的触控阵列基板的制备方法，其中，所述第一半色调光罩包括第一透光部和第二透光部，所述第一透光部的透光率大于所述第二透光部的透光率，所述第一透光部的透光率为100%，所述第一透光部对应待形成的第一通孔，所述第二透光部对应于所述像素电极层中待形成的像素电极。
  8. 根据权利要求5所述的触控阵列基板的制备方法，其中，所述在所述平坦层上形成图案化的公共电极层，之前，包括步骤：
    以所述平坦层的氢作为氢源，对应所述有源层进行氢化处理。
  9. 根据权利要求6所述的触控阵列基板的制备方法，其中，所述在所述平坦层上形成图案化的公共电极层，包括以下步骤：
    在所述平坦层上形成第二光阻层，并对所述第二光阻层进行图案化处理，图案化的第二光阻层包括对应于所述有源层的第一区域和第二区域的第二通孔、对应于所述像素电极的第三通孔、对应于所述触控信号线和数据线的第四通孔、对应于所述公共电极层待形成触控电极、源极和漏极的第三部分以及对应于所述公共电极层待去除部分的第四部分；所述第三部分的厚度小于所述第四部分的厚度；
    以图案化的第二光阻层为掩模，刻蚀所述平坦层形成所述第二通孔、第三通孔和第四通孔；
    灰化所述第二光阻层，去除所述第三部分；
    在所述第二光阻层上形成公共电极层；
    去除所述第二光阻层并位于所述第二光阻层上的所述公共电极层。
  10. 根据权利要求9所述的触控阵列基板的制备方法，其中，所述在所述第二光阻层上形成公共电极层，之前包括步骤：
    灰化所述平坦层，使所述第二光阻层的底面以下形成倒角。
  11. 根据权利要求9所述的触控阵列基板的制备方法，其中，采用第二半色调光罩对所述第二光阻层进行曝光处理；
    其中，所述第二半色调光罩包括第三透光部和第四透光部，所述第三透光部的透光率大于所述第四透光部的透光率，所述第三透光部的透光率为100%，所述第三透光部对应待形成的第二通孔、第三通孔和第四通孔，所述第四透光部对应于所述公共电极层待形成的触控电极。
  12. 根据权利要求6所述的触控阵列基板的制备方法，其中，所述公共电极层为透明导电层。
  13. 根据权利要求12所述的触控阵列基板的制备方法，其中，所述透明导电层的材质为银。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110620118B (zh) 2019-08-20 2021-03-16 武汉华星光电技术有限公司 触控阵列基板及其制备方法
CN113050825B (zh) * 2021-03-09 2024-03-12 昆山龙腾光电股份有限公司 触摸屏的制备方法及触摸屏
CN114995669B (zh) * 2022-05-24 2024-08-23 福建华佳彩有限公司 一种避免主动笔信号衰减的触控阵列基板及其制备方法
CN116056510B (zh) * 2023-03-31 2023-06-09 惠科股份有限公司 显示面板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104330935A (zh) * 2014-10-10 2015-02-04 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN104716144A (zh) * 2015-03-06 2015-06-17 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
US20160035752A1 (en) * 2013-09-27 2016-02-04 Lg Display Co., Ltd. Display Device and Method of Manufacturing the Same
CN105514119A (zh) * 2016-01-04 2016-04-20 武汉华星光电技术有限公司 Tft基板的制作方法及tft基板
CN107315296A (zh) * 2017-07-24 2017-11-03 武汉华星光电技术有限公司 Ltps阵列基板及内嵌式触摸屏
CN110620118A (zh) * 2019-08-20 2019-12-27 武汉华星光电技术有限公司 触控阵列基板及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI645557B (zh) * 2017-12-08 2018-12-21 友達光電股份有限公司 畫素陣列基板
US10896921B2 (en) * 2018-04-28 2021-01-19 Wuhan China Star Optoelectronics Technology Co., Ltd. Manufacturing method of array substrate
CN109037241B (zh) * 2018-07-27 2021-10-08 武汉华星光电技术有限公司 Ltps阵列基板及其制造方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160035752A1 (en) * 2013-09-27 2016-02-04 Lg Display Co., Ltd. Display Device and Method of Manufacturing the Same
CN104330935A (zh) * 2014-10-10 2015-02-04 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN104716144A (zh) * 2015-03-06 2015-06-17 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105514119A (zh) * 2016-01-04 2016-04-20 武汉华星光电技术有限公司 Tft基板的制作方法及tft基板
CN107315296A (zh) * 2017-07-24 2017-11-03 武汉华星光电技术有限公司 Ltps阵列基板及内嵌式触摸屏
CN110620118A (zh) * 2019-08-20 2019-12-27 武汉华星光电技术有限公司 触控阵列基板及其制备方法

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