WO2020186985A1 - 低温多晶硅基板及其制作方法、阵列基板及显示装置 - Google Patents

低温多晶硅基板及其制作方法、阵列基板及显示装置 Download PDF

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WO2020186985A1
WO2020186985A1 PCT/CN2020/076779 CN2020076779W WO2020186985A1 WO 2020186985 A1 WO2020186985 A1 WO 2020186985A1 CN 2020076779 W CN2020076779 W CN 2020076779W WO 2020186985 A1 WO2020186985 A1 WO 2020186985A1
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photoresist
shielding layer
light
polysilicon
film
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PCT/CN2020/076779
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English (en)
French (fr)
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赵永亮
许卓
崔星花
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Publication of WO2020186985A1 publication Critical patent/WO2020186985A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

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  • the embodiments of the present disclosure relate to a low-temperature polysilicon substrate and a manufacturing method thereof, an array substrate and a display device.
  • LTPS Low Temperature Poly-silicon
  • LTPS Low Temperature Poly-silicon
  • the embodiments of the present disclosure provide a low-temperature polysilicon substrate and a manufacturing method thereof, an array substrate, and a display device.
  • a method for manufacturing a low-temperature polysilicon substrate including: forming a light shielding layer film on a substrate; forming a polysilicon film on the light shielding layer film; and applying a patterning process to the light shielding layer film Patterning processing is performed with the polysilicon film to obtain a light shielding layer and a polysilicon layer; wherein the orthographic projection of the polysilicon layer on the light shielding layer is located in the region where the light shielding layer is located.
  • the material of the light shielding layer is molybdenum oxide.
  • the step of patterning the light-shielding layer film and the polysilicon film through a patterning process to obtain the light-shielding layer and the polysilicon layer includes: coating photoresist on the polysilicon film;
  • the photolithography process performs a patterning process on the photoresist to form a first photoresist completely reserved area and a first photoresist removal area;
  • the first etching process is used to remove the polysilicon in the first photoresist area
  • the thin film and the light-shielding layer film are etched; and the remaining photoresist in the completely reserved area of the first photoresist is removed to obtain the light-shielding layer and the polysilicon layer;
  • the etching gas used in the first etching process It is a mixed gas of Cl2, SF6 and O2.
  • the step of patterning the light-shielding layer film and the polysilicon film through a patterning process to obtain the light-shielding layer and the polysilicon layer includes: coating photoresist on the polysilicon film;
  • the second photolithography process performs patterning treatment on the photoresist to form a second photoresist completely reserved area and a second photoresist removal area;
  • the second etching process is used to perform a patterning process on the second photoresist removal area Etching the polysilicon film; using a third etching process to etch the light-shielding layer film in the second photoresist removal area; and removing the remaining photoresist in the second photoresist completely reserved area to obtain Light shielding layer and polysilicon layer;
  • the etching gas used in the second etching process is a mixed gas of Cl2 and SF6, and the etching gas used in the third etching process is a mixed gas of O2 and SF6;
  • the step of patterning the light-shielding layer film and the polysilicon film through a patterning process to obtain the light-shielding layer and the polysilicon layer includes: coating photoresist on the polysilicon film;
  • the third photolithography process performs patterning processing on the photoresist to form a third photoresist completely reserved area, a photoresist partially reserved area, and a third photoresist removal area; the fourth etching process is used to 3.
  • the polysilicon film and the light shielding layer film in the photoresist removal area are etched; the photoresist in the third photoresist completely reserved area and the photoresist partially reserved area is ashed to form a fourth photoresist Resist retention area and fourth photoresist removal area; use a fifth etching process to etch the polysilicon film in the fourth photoresist removal area; and remove the remaining light in the fourth photoresist retention area Resist to obtain a light-shielding layer and a polysilicon layer; wherein the etching gas used in the fourth etching process is a mixed gas of Cl2, SF6 and O2, and the etching gas used in the fifth etching process is The mixed gas of Cl2 and SF6, the mask used in the third photolithography process is a halftone mask.
  • the step of forming a polysilicon film on the light-shielding layer film includes: forming an amorphous silicon film on the light-shielding layer film; and performing a crystallization treatment on the amorphous silicon film to make the amorphous silicon film The silicon film is transformed into a polysilicon film.
  • a low-temperature polysilicon substrate including: a substrate; a light shielding layer formed on the substrate; and a polysilicon layer formed on the light shielding layer; wherein, the light shielding layer
  • the layer and the polysilicon layer are obtained by patterning the light-shielding layer film and the polysilicon film sequentially formed on the substrate through a patterning process; the orthographic projection of the polysilicon layer on the light-shielding layer is located at the In the area where the light-shielding layer is located.
  • the area of the polysilicon layer is smaller than the area of the light shielding layer.
  • the thickness of the light shielding layer is about To about
  • an array substrate including the low-temperature polysilicon substrate.
  • the array substrate further includes a thin film transistor and a signal line formed on the low-temperature polysilicon substrate, and the orthographic projection of the thin film transistor and the signal line on the light shielding layer is located in a region where the light shielding layer is located.
  • the signal lines include gate lines and data lines.
  • the array substrate further includes: a color resist layer disposed on the thin film transistor, a flat layer on the color resist layer, a common electrode layer on the flat layer, a passivation layer on the electrode layer, and a passivation layer on the electrode layer.
  • Pixel electrode formed on the chemical layer.
  • a display device including the array substrate;
  • the display device further includes spacers arranged between the array base and the pair of box substrates.
  • Figure 1 shows a schematic structural diagram of a low-temperature polysilicon substrate
  • FIG. 2 shows a flowchart of a method for manufacturing a low-temperature polysilicon substrate according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of a structure obtained after forming a light shielding layer film and a polysilicon film on a substrate in an embodiment of the present disclosure
  • FIG. 4 shows a flowchart of a manufacturing method of a low-temperature polysilicon substrate according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of the structure obtained after patterning the photoresist by the first photolithography process in this embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of the structure obtained after etching the polysilicon film and the light-shielding layer film in the first photoresist removal area by using the first etching process in this embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of the structure of the embodiment of the present disclosure in which the remaining photoresist in the completely reserved area of the first photoresist is removed to obtain the light shielding layer and the polysilicon layer;
  • FIG. 8 shows a flowchart of a manufacturing method of a low-temperature polysilicon substrate according to another embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of the structure obtained after etching the polysilicon film in the second photoresist removal area by using the second etching process in this other embodiment of the present disclosure
  • FIG. 10 shows a schematic diagram of the structure obtained by etching the light-shielding layer film in the second photoresist removal area by using the third etching process in this other embodiment of the present disclosure
  • FIG. 11 shows a schematic diagram of the structure of removing the remaining photoresist in the completely reserved area of the second photoresist to obtain the light shielding layer and the polysilicon layer in this other embodiment of the present disclosure
  • FIG. 12 shows a flowchart of a method for manufacturing a low-temperature polysilicon substrate according to another embodiment of the present disclosure
  • FIG. 13 shows a schematic diagram of the structure obtained after patterning the photoresist by using the third photolithography process in this still another embodiment of the present disclosure
  • FIG. 14 shows a schematic diagram of the structure obtained after etching the polysilicon film and the light-shielding layer film in the third photoresist removal area by using the fourth etching process in this still another embodiment of the present disclosure
  • FIG. 15 shows a schematic diagram of the structure obtained after ashing the photoresist in the third photoresist fully reserved area and the photoresist partially reserved area in this still another embodiment of the present disclosure
  • FIG. 16 shows a schematic diagram of the structure obtained by etching the polysilicon film in the fourth photoresist removal area by using the fifth etching process in this still another embodiment of the present disclosure
  • FIG. 17 shows a schematic structural view of removing the remaining photoresist in the fourth photoresist reserved area to obtain a light shielding layer and a polysilicon layer in another embodiment of the present disclosure
  • FIG. 18 shows a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 19 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • a light-shielding layer 12 is first formed on the substrate 11 through a patterning process.
  • the material of the light-shielding layer 12 is usually metal molybdenum.
  • the forming steps of the light-shielding layer 12 include: light-shielding film deposition , Photoresist patterning, light-shielding film etching, photoresist stripping, etc.; then, a buffer layer 13 covering the light-shielding layer 12 is formed, which is a composite film layer of silicon nitride and silicon oxide; finally, The polysilicon layer 14 is formed on the buffer layer 13 by a patterning process.
  • the formation steps of the polysilicon layer 14 mainly include: polysilicon film formation, photoresist patterning, polysilicon film etching, photoresist stripping, etc., of which only the channel region
  • the orthographic projection of the polysilicon layer 14 on the light shielding layer 12 is located in the area where the light shielding layer 12 is located.
  • the formation of the light shielding layer 12 and the polysilicon layer 14 respectively requires a patterning process.
  • the manufacturing process of the entire low-temperature polysilicon substrate is complicated, resulting in an increase in the manufacturing cost of the low-temperature polysilicon substrate.
  • Step 201 forming a light shielding layer film on the substrate.
  • a substrate 31 is provided.
  • the substrate 31 may be a PI (Polyimide) substrate or a glass substrate;
  • a light-shielding film 320 is formed on the substrate 31, and the light-shielding film 320 It can be formed by a sputtering process.
  • the material of the light shielding layer film 320 may be molybdenum oxide MoOx.
  • the color of molybdenum oxide is black, its own properties are stable, it will not react with silicon, and it is easy to obtain.
  • the material of the light-shielding film 320 can also be replaced by other materials, as long as the material of the light-shielding film 320 is black, and the material of the light-shielding film 320 does not react with silicon.
  • the material of the light-shielding film 320 can also be black resin. material.
  • the thickness of the light-shielding film 320 is relatively small, and the thickness of the light-shielding layer obtained by subsequent patterning of the light-shielding film 320 is also small, which can effectively reduce the thickness of the low-temperature polysilicon substrate. thickness.
  • the existing sputtering equipment can be used, and oxygen is introduced to form molybdenum oxide during the sputtering process, and no additional manufacturing equipment and sputtering materials are required. .
  • Step 202 forming a polysilicon film on the light shielding layer film.
  • a polysilicon film 330 is formed on the light-shielding film 320.
  • forming an amorphous silicon film on the light-shielding layer film For example, forming an amorphous silicon film on the light-shielding layer film; and performing a crystallization treatment on the amorphous silicon film so that the amorphous silicon film is converted into a polysilicon film.
  • An amorphous silicon film is formed on the light-shielding layer film 320. Since the formed amorphous silicon film contains hydrogen, the substrate 31 on which the amorphous silicon film and the light-shielding layer film 320 are formed needs to be placed in an annealing furnace for hydrogen removal.
  • the substrate 31 on which the amorphous silicon film and the light-shielding film 320 are formed is pre-cleaned to remove excess impurities;
  • the substrate 31 with the amorphous silicon film and the light-shielding layer film 320 is scanned by laser, and the amorphous silicon is crystallized by laser energy, that is, the amorphous silicon film is crystallized to convert the amorphous silicon film into a polysilicon film 330.
  • a solid-state laser or excimer laser can be used as the laser.
  • Step 203 patterning the light-shielding layer film and the polysilicon film through a patterning process to obtain a light-shielding layer and a polysilicon layer.
  • the light-shielding layer film 320 and the polysilicon film 330 are patterned through a patterning process to form the light-shielding layer 32 and the polysilicon layer 33, as shown in FIG. 5; wherein, the polysilicon layer 33 is on the light-shielding layer 32
  • the orthographic projection of is located in the area where the light-shielding layer 32 is located. In this way, the light-shielding layer 32 can achieve a light-shielding effect on the channel of the thin film transistor formed subsequently.
  • the orthographic projection of the polysilicon layer 33 on the light shielding layer 32 may overlap the light shielding layer 32.
  • the orthographic projection of the polysilicon layer 33 on the light shielding layer 32 can also be all located in the area where the light shielding layer 32 is located, and the area of the polysilicon layer 33 is smaller than the area of the light shielding layer 32, as shown in FIG. 11.
  • the material of the light shielding layer 32 is molybdenum oxide, and the thickness of the light shielding layer 32 is about To date
  • the light-shielding layer 32 and the polysilicon layer 33 can be obtained by only one patterning process, which simplifies the manufacturing process of the entire low-temperature polysilicon substrate.
  • the light-shielding layer 32 achieves a light-shielding effect.
  • it replaces the buffer layer in the low-temperature polysilicon substrate in the related art, and at the same time reduces the thickness of the low-temperature polysilicon substrate, thereby reducing the manufacturing cost of the low-temperature polysilicon substrate.
  • FIG. 4 there is shown a flowchart of a manufacturing method of a low-temperature polysilicon substrate according to an embodiment of the present disclosure.
  • step 203 may include:
  • Sub-step 2031 coating photoresist on the polysilicon film
  • Sub-step 2032 patterning the photoresist by using a first photolithography process to form a first photoresist completely reserved area and a first photoresist removal area;
  • Sub-step 2033 using a first etching process to etch the polysilicon film and the light-shielding film in the first photoresist removal area;
  • sub-step 2034 the remaining photoresist in the completely reserved area of the first photoresist is removed to obtain a light-shielding layer and a polysilicon layer.
  • the etching gas used in the first etching process is a mixed gas of Cl2, SF6 and O2.
  • 5 to 7 are schematic diagrams of the structure of manufacturing a low-temperature polysilicon substrate according to this embodiment of the disclosure.
  • a photoresist 40 is coated on the polysilicon film 330, and then the photoresist 40 is patterned using a first photolithography process to form a first photoresist completely reserved area M1 and a first photoresist Resist removal area M2.
  • the first photolithography process refers to exposing the photoresist 40 using a mask, and then developing the exposed photoresist 40.
  • the photoresist 40 can be a positive photoresist or a negative photoresist.
  • the photoresist 40 is a positive photoresist
  • the first photoresist completely reserved area M1 is an unexposed area
  • the first photoresist The resist removal area M2 is the exposed area.
  • the photoresist 40 in the unexposed area remains after development, and the photoresist 40 in the exposed area is removed after development; when the photoresist 40 is a negative photoresist,
  • the first photoresist completely reserved area M1 is the exposed area
  • the first photoresist removal area M2 is the unexposed area.
  • the photoresist 40 in the unexposed area is removed after development.
  • the photoresist in the exposed area is 40 is retained after development.
  • the polysilicon film 330 and the light-shielding layer film 320 in the first photoresist removal area M2 are etched by the first etching process.
  • the first etching process is a dry etching process, and the etching gas used is a mixed gas of Cl2, SF6 and O2.
  • the remaining photoresist 40 in the first photoresist completely reserved area M1 is removed, and the light shielding layer 32 and the polysilicon layer 33 are obtained.
  • the patterning process includes one photolithography process and one etching process, and the obtained orthographic projection of the polysilicon layer 33 on the light shielding layer 32 overlaps the light shielding layer 32.
  • FIG. 8 there is shown a flowchart of a manufacturing method of a low-temperature polysilicon substrate according to another embodiment of the present disclosure.
  • step 203 may include:
  • Sub-step 2035 coating photoresist on the polysilicon film
  • Sub-step 2036 patterning the photoresist by using a second photolithography process to form a second photoresist completely reserved area and a second photoresist removal area;
  • Sub-step 2037 using a second etching process to etch the polysilicon film in the second photoresist removal area
  • Sub-step 2038 using a third etching process to etch the light shielding layer film in the second photoresist removal area
  • sub-step 2039 the remaining photoresist in the completely reserved area of the second photoresist is removed to obtain a light-shielding layer and a polysilicon layer.
  • the etching gas used in the second etching process is a mixed gas of Cl2 and SF6.
  • the etching gas used in the third etching process is a mixed gas of O2 and SF6.
  • the etching duration of the second etching process is greater than that of the third etching process, or the concentration of the etching gas used in the second etching process is greater than the concentration of the etching gas used in the third etching process.
  • 9 to 11 are schematic diagrams of the structure of the low-temperature polysilicon substrate fabricated in this other embodiment of the disclosure.
  • a photoresist 40 is coated on the polysilicon film 330, and then the photoresist 40 is patterned by a second photolithography process to form a second photoresist completely reserved area and a second photoresist removal area.
  • the mask used is similar to the mask used in the first embodiment, and the second photoresist completely reserved area is similar In the first photoresist completely reserved area M1 shown in FIG. 5, the second photoresist removal area is similar to the first photoresist removal area M2 shown in FIG. 5. In order to avoid duplication, no additional The schematic diagram is shown.
  • the second etching process is used to etch the polysilicon film 330 in the second photoresist removal area.
  • the second etching process is a dry etching process, and the etching gas used is a mixed gas of Cl2 and SF6.
  • a third etching process is used to etch the light shielding layer film 320 in the second photoresist removal area.
  • the third etching process is a dry etching process, and the etching gas used is a mixed gas of O2 and SF6.
  • the remaining photoresist 40 in the completely reserved area of the second photoresist is removed to obtain the light shielding layer 32 and the polysilicon layer 33.
  • the patterning process includes one photolithography process and two etching processes, wherein the etching time of the second etching process is longer than that of the third etching process, or the etching time used in the second etching process
  • the concentration of the etching gas is greater than the concentration of the etching gas used in the third etching process.
  • the orthographic projection of the obtained polysilicon layer 33 on the light shielding layer 32 is all located in the area where the light shielding layer 32 is located, and the area of the polysilicon layer 33 is smaller than that of the light shielding layer 32. Area to achieve better shading effect.
  • FIG. 12 there is shown a flow chart of a manufacturing method of a low-temperature polysilicon substrate according to another embodiment of the present disclosure.
  • step 203 may include:
  • Sub-step 2040 coating photoresist on the polysilicon film
  • Sub-step 2041 using a third photolithography process to pattern the photoresist to form a third photoresist fully reserved area, a photoresist partially reserved area, and a third photoresist removal area;
  • Sub-step 2042 using a fourth etching process to etch the polysilicon film and the light shielding layer film in the third photoresist removal area;
  • Sub-step 2043 ashing the photoresist in the third photoresist completely reserved area and the photoresist partially reserved area to form a fourth photoresist reserved area and a fourth photoresist removed area;
  • Sub-step 2044 using a fifth etching process to etch the polysilicon film in the fourth photoresist removal area
  • sub-step 2045 the remaining photoresist in the fourth photoresist reserved area is removed to obtain a light-shielding layer and a polysilicon layer.
  • the etching gas used in the fourth etching process is a mixed gas of Cl2, SF6 and O2.
  • the etching gas used in the fifth etching process is a mixed gas of Cl2 and SF6.
  • the mask used in the third photolithography process is a halftone mask.
  • FIG. 13 to FIG. 17 are structural schematic diagrams of fabricating a low-temperature polysilicon substrate according to another embodiment of the disclosure.
  • a photoresist 40 is coated on the polysilicon film 330, and then the photoresist 40 is patterned by a third photolithography process to form a third photoresist completely reserved area M3, photoresist Part of the reserved area M4, and the third photoresist removal area M5.
  • the mask used in the third photolithography process is a halftone mask.
  • the photoresist 40 is a positive photoresist
  • the third photoresist completely reserved area M3 is an unexposed area
  • the photoresist partially reserved area M4 is a partially exposed area
  • the third photoresist removal area M5 is a completely exposed area.
  • the light transmittance of the mask pattern corresponding to the third photoresist removal area M5 is greater than the light transmittance of the mask pattern corresponding to the photoresist partially reserved area M4.
  • the photoresist 40 is exposed and developed through the halftone mask, so that the thickness of the photoresist 40 in the third photoresist completely reserved area M3 is greater than the thickness of the photoresist 40 in the photoresist partial reserved area M4.
  • a fourth etching process is used to etch the polysilicon film 330 and the light shielding layer film 320 in the third photoresist removal area M5 to form a pattern of the light shielding layer 32.
  • the pattern of the polysilicon layer 33 is not Completely formed, only a half-etched polysilicon pattern 321 can be formed.
  • the fourth etching process is a dry etching process, and the etching gas used is a mixed gas of Cl2, SF6 and O2,
  • the photoresist 40 in the third photoresist completely reserved area M3 and the photoresist partially reserved area M4 is ashed, so that the photoresist 40 in the photoresist partially reserved area M4 is completely removed , And the photoresist 40 in the third photoresist completely reserved area M3 is partially removed, forming a fourth photoresist reserved area M6 and a fourth photoresist removal area M7.
  • the photoresist 40 can be ashed by ultraviolet light or ozone.
  • the fifth etching process is used to etch the polysilicon film 330 in the fourth photoresist removal area M7, for example, the semi-etched polysilicon pattern 321 in the fourth photoresist removal area M7 is performed Etching.
  • the fifth etching process is a dry etching process, and the etching gas used is a mixed gas of Cl2 and SF6.
  • the remaining photoresist 40 in the fourth photoresist reserved area M6 is removed, and the light shielding layer 32 and the polysilicon layer 33 are obtained.
  • the patterning process includes a photolithography process, two etching processes, and an ashing process.
  • the orthographic projection of the polysilicon layer 33 on the light shielding layer 32 is all located in the region where the light shielding layer 32 is located, and the polysilicon layer 33 The area is smaller than the area of the light shielding layer 32.
  • the low-temperature polysilicon substrate shown in FIG. 17 has a larger distance between the edge of the light-shielding layer 32 and the edge of the polysilicon layer 33, so that the light-shielding effect is better.
  • a light-shielding layer film is formed on a substrate, and a polysilicon film is formed on the light-shielding layer film, and the light-shielding layer film and the polysilicon film are patterned through a patterning process to obtain the light-shielding layer and the polysilicon layer.
  • the orthographic projection of the polysilicon layer on the light shielding layer is located in the area where the light shielding layer is located.
  • the shading effect is achieved by the shading layer formed on the substrate, instead of the buffer layer in the low-temperature polysilicon substrate in the related art. When the shading layer film and the polysilicon film are patterned, only one patterning process can be used.
  • the light shielding layer and the polysilicon layer simplify the manufacturing process of the entire low-temperature polysilicon substrate, and at the same time reduce the thickness of the low-temperature polysilicon substrate, thereby reducing the manufacturing cost of the low-temperature polysilicon substrate.
  • the embodiment of the present disclosure provides a low temperature polysilicon substrate, including: a substrate 31; a light shielding layer 32 formed on the substrate 31; a polysilicon layer 33 formed on the light shielding layer 32; wherein the light shielding layer 32 and the polysilicon layer 33 are
  • the light shielding layer film 320 and the polysilicon film 330 sequentially formed on the substrate 31 are patterned through a patterning process; the orthographic projection of the polysilicon layer 33 on the light shielding layer 32 is located in the area where the light shielding layer 32 is located.
  • the orthographic projection of the polysilicon layer 33 on the light-shielding layer 32 overlaps with the light-shielding layer 32.
  • the orthographic projection of the polysilicon layer 33 on the light-shielding layer 32 is all located where the light-shielding layer 32 is located.
  • the area of the polysilicon layer 33 is smaller than the area of the light shielding layer 32.
  • the thickness of the light shielding layer 32 is about To about
  • the material of the light shielding layer 32 is molybdenum oxide.
  • the low-temperature polysilicon substrate of the embodiment of the present disclosure can be manufactured by using the above-mentioned manufacturing method of the low-temperature polysilicon substrate.
  • the light-shielding layer formed on the substrate is used to achieve the light-shielding effect while replacing the buffer layer in the low-temperature polysilicon substrate in the related art.
  • the light-shielding layer film and the polysilicon film only The light-shielding layer and the polysilicon layer can be obtained by one patterning process, which simplifies the manufacturing process of the entire low-temperature polysilicon substrate, and also reduces the thickness of the low-temperature polysilicon substrate, thereby reducing the production cost of the low-temperature polysilicon substrate.
  • the embodiment of the present disclosure also provides an array substrate, including the above-mentioned low-temperature polysilicon substrate.
  • FIG. 18 there is shown a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate further includes a thin film transistor 51 and a signal line formed on a low-temperature polysilicon substrate, and the orthographic projection of the thin film transistor 51 and the signal line on the light shielding layer 32 is located in the region where the light shielding layer 32 is located; wherein
  • the signal lines include gate lines 511, data lines 512, scan signal lines (not shown in FIG. 18), and the like.
  • the light shielding layer 32 By arranging the light shielding layer 32 in the embodiment of the present disclosure at the corresponding position of the polysilicon layer 33, it is also provided at the corresponding position of the thin film transistor 51 and the signal line, and the thin film transistor 51 and the signal line are positive on the light shielding layer 32.
  • the projection is located in the area where the light-shielding layer 32 is located. Therefore, the light-shielding layer 32 can shield the light leakage position of the pixel in the array substrate, instead of the black matrix in the related art display panel, and can save the black matrix manufacturing process.
  • the light-shielding layer 32 that blocks the pixel leakage is provided on the array substrate, when the array substrate and the box-matching substrate are assembled to form a display panel, there is no need to consider the accuracy of the box. Therefore, the light-shielding can be greatly reduced.
  • the deviation between the edge of the layer 32 and the light leakage position of the pixel can reduce the width of the light shielding layer 32, increase the aperture ratio and transmittance of the pixel, realize curved display, and reduce the power consumption of the display panel.
  • the polysilicon layer 33 is ion-doped, mainly including the trenches of the thin film transistor 51 (that is, the pixel transistor located in the pixel area). Doping with boron at the track position, light N-doping at the position adjacent to the channel region, heavy N-doping at the edge of the polysilicon layer 33, and then forming a gate insulating layer and a gate through a patterning process. Then, P-type doping is performed on the driving transistor position in the driving area, and the dielectric layer is formed after the doping is completed, and then the source and drain electrodes are formed through the patterning process to obtain the thin film transistor 51.
  • a color resist layer 52 is fabricated.
  • the color resist layer 52 includes a red color resist region, a green color resist region, and a blue color resist region.
  • a flat layer 53 is formed, and then a common layer is formed on the flat layer 53.
  • a passivation layer 55 is formed on the common electrode layer 54, and a pixel electrode 56 is formed on the passivation layer 55 through a patterning process, thereby obtaining the array substrate 50.
  • spacers 70 are formed on the counter substrate 60, and the counter substrate 60 on which the spacers 70 are formed and the array substrate 50 are aligned to obtain a display panel.
  • the black matrix and color resist layer are not provided on the box substrate 60, but the color resist layer 52 is fabricated on the side of the array substrate 50.
  • the light shielding layer 32 can achieve light leakage to the pixels in the array substrate. The position is shaded to replace the black matrix in the related art display panel. In this way, the manufacturing process steps of the black matrix can be reduced.
  • the array substrate 50 of the embodiments of the present disclosure can be applied not only in LCD (Liquid Crystal Display) display panels, but also in OLED (Organic Light Emitting Diode) display panels.
  • the embodiments of the present disclosure also provide a display device, such as an LCD liquid crystal display device and an organic light emitting diode display device, including the array substrate 50 of the foregoing embodiment and the cell substrate 60.
  • the display device may further include spacers 70 between the array substrate 50 and the box substrate 60.
  • the display device may be any device with display function, for example, it may be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • the light-shielding layer formed on the substrate achieves the light-shielding effect, instead of the buffer layer in the low-temperature polysilicon substrate of the related art, when patterning the light-shielding layer film and the polysilicon film, only The light-shielding layer and polysilicon layer can be obtained in one patterning process, which simplifies the manufacturing process of the entire low-temperature polysilicon substrate, while also reducing the thickness of the low-temperature polysilicon substrate, thereby reducing the production cost of the low-temperature polysilicon substrate; in addition, by setting the light-shielding layer At the corresponding positions of the thin film transistor and the signal line, and the orthographic projection of the thin film transistor and the signal line on the light-shielding layer is located in the area where the light-shielding layer is located, the light-shielding layer can realize the light shielding of the pixel leakage position in the array substrate instead of The related art displays the black matrix in the panel, thereby

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Abstract

一种低温多晶硅基板及其制作方法、阵列基板及显示装置。通过在衬底(31)上形成遮光层薄膜(320)，在遮光层薄膜(320)上形成多晶硅薄膜(330)，通过一次构图工艺对遮光层薄膜(320)和多晶硅薄膜(330)进行图案化处理，得到遮光层(32)和多晶硅层(33)，多晶硅层(33)在遮光层(32)上的正投影位于遮光层(32)所在的区域内。

Description

低温多晶硅基板及其制作方法、阵列基板及显示装置
相关申请的交叉引用
本申请要求于2019年03月15日向CNIPA提交的名称为“一种低温多晶硅基板及其制作方法、阵列基板”的中国专利申请No.201910199665.2的优先权，其全文通过引用合并于本文。
技术领域
本公开的实施例涉及一种低温多晶硅基板及其制作方法、阵列基板及显示装置。
背景技术
LTPS(Low Temperature Poly-silicon，低温多晶硅)具有较高的载流子迁移率，可以有效减小薄膜晶体管的面积，从而达到更高的开口率，且能够降低显示面板的功耗，因此，低温多晶硅基板被广泛的应用于显示面板中。
发明内容
本公开的实施例提供一种低温多晶硅基板及其制作方法、阵列基板及显示装置。
根据本公开至少一个实施例，提供一种低温多晶硅基板的制作方法，包括：在衬底上形成遮光层薄膜；在所述遮光层薄膜上形成多晶硅薄膜；通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层；其中，所述多晶硅层在所述遮光层上的正投影位于所述遮光层所在的区域内。
例如，所述遮光层的材料为氧化钼。
例如，所述通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，得到遮光层和多晶硅层的步骤，包括：在所述多晶硅薄膜上涂覆光刻胶；采用第一光刻工艺对所述光刻胶进行图案化处理，形成第一光刻胶完全保留区域和第一光刻胶去除区域；采用第一刻蚀工艺对所述第一光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀；以及去除所述第一光刻胶 完全保留区域剩余的光刻胶，以得到遮光层和多晶硅层；其中，所述第一刻蚀工艺所采用的刻蚀气体为Cl2、SF6和O2的混合气体。
例如，所述通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层的步骤，包括：在所述多晶硅薄膜上涂覆光刻胶；采用第二光刻工艺对所述光刻胶进行图案化处理，形成第二光刻胶完全保留区域和第二光刻胶去除区域；采用第二刻蚀工艺对所述第二光刻胶去除区域的多晶硅薄膜进行刻蚀；采用第三刻蚀工艺对所述第二光刻胶去除区域的遮光层薄膜进行刻蚀；以及去除所述第二光刻胶完全保留区域剩余的光刻胶，以得到遮光层和多晶硅层；其中，所述第二刻蚀工艺所采用的刻蚀气体为Cl2和SF6的混合气体，所述第三刻蚀工艺所采用的刻蚀气体为O2和SF6的混合气体；所述第二刻蚀工艺的刻蚀时长大于所述第三刻蚀工艺的刻蚀时长，或者，所述第二刻蚀工艺所采用的刻蚀气体的浓度大于所述第三刻蚀工艺所采用的刻蚀气体的浓度。
例如，所述通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层的步骤，包括：在所述多晶硅薄膜上涂覆光刻胶；采用第三光刻工艺对所述光刻胶进行图案化处理，形成第三光刻胶完全保留区域、光刻胶部分保留区域和第三光刻胶去除区域；采用第四刻蚀工艺对所述第三光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀；对所述第三光刻胶完全保留区域和所述光刻胶部分保留区域的光刻胶进行灰化处理，形成第四光刻胶保留区域和第四光刻胶去除区域；采用第五刻蚀工艺对所述第四光刻胶去除区域的多晶硅薄膜进行刻蚀；以及去除所述第四光刻胶保留区域剩余的光刻胶，以得到遮光层和多晶硅层；其中，所述第四刻蚀工艺所采用的刻蚀气体为Cl2、SF6和O2的混合气体，所述第五刻蚀工艺所采用的刻蚀气体为Cl2和SF6的混合气体，所述第三光刻工艺所采用的掩模板为半色调掩模板。
例如，所述在所述遮光层薄膜上形成多晶硅薄膜的步骤，包括：在所述遮光层薄膜上形成非晶硅薄膜；以及对所述非晶硅薄膜进行晶化处理，使得所述非晶硅薄膜转化为多晶硅薄膜。
根据本公开的至少一个实施例，还提供一种低温多晶硅基板，包括：衬 底；形成在所述衬底上的遮光层；以及形成在所述遮光层上的多晶硅层；其中，所述遮光层和所述多晶硅层是对依次形成在所述衬底上的遮光层薄膜和多晶硅薄膜通过一次构图工艺进行图案化处理后得到的；所述多晶硅层在所述遮光层上的正投影位于所述遮光层所在的区域内。
例如，所述多晶硅层的面积小于遮光层的面积。
例如，所述遮光层的厚度为约
Figure PCTCN2020076779-appb-000001
至约
Figure PCTCN2020076779-appb-000002
根据本公开的至少一个实施例，还提供一种阵列基板，包括所述低温多晶硅基板。
例如，所述阵列基板还包括形成在所述低温多晶硅基板上的薄膜晶体管和信号线，且所述薄膜晶体管和信号线在所述遮光层上的正投影位于所述遮光层所在的区域内。
例如，所述信号线包括栅线和数据线。
例如，所述阵列基板还包括：设置在薄膜晶体管上的色阻层，位于色阻层上的平坦层，位于平坦化层上的公共电极层，位于电极层上的钝化层，以及在钝化层上形成的像素电极。
根据本公开的至少一个实施例，还提供一种显示装置，包括所述阵列基板；
和与所述阵列基板相对设置的对盒基板。
例如，所述的显示装置还包括设置在所述阵列基本和所述对盒基板之间的隔垫物。
附图说明
以下将结合附图对本公开的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本公开的实施例，其中：
图1示出了一种低温多晶硅基板的结构示意图；
图2示出了本公开实施例的一种低温多晶硅基板的制作方法的流程图；
图3示出了本公开实施例在衬底上形成遮光层薄膜和多晶硅薄膜后得到的结构示意图；
图4示出了本公开一实施例的低温多晶硅基板的制作方法的流程图；
图5示出了本公开该实施例采用第一光刻工艺对光刻胶进行图案化处理后得到的结构示意图；
图6示出了本公开该实施例采用第一刻蚀工艺对第一光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀后得到的结构示意图；
图7示出了本公开的该实施例去除第一光刻胶完全保留区域剩余的光刻胶，以得到遮光层和多晶硅层的结构示意图；
图8示出了本公开另一实施例的低温多晶硅基板的制作方法的流程图；
图9示出了本公开该另一实施例采用第二刻蚀工艺对第二光刻胶去除区域的多晶硅薄膜进行刻蚀后得到的结构示意图；
图10示出了本公开该另一实施例采用第三刻蚀工艺对第二光刻胶去除区域的遮光层薄膜进行刻蚀后得到的结构示意图；
图11示出了本公开该另一实施例去除第二光刻胶完全保留区域剩余的光刻胶，以得到遮光层和多晶硅层的结构示意图；
图12示出了本公开又一实施例的低温多晶硅基板的制作方法的流程图；
图13示出了本公开该又一实施例采用第三光刻工艺对光刻胶进行图案化处理后得到的结构示意图；
图14示出了本公开该又一实施例采用第四刻蚀工艺对第三光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀后得到的结构示意图；
图15示出了本公开该又一实施例对第三光刻胶完全保留区域和光刻胶部分保留区域的光刻胶进行灰化处理后得到的结构示意图；
图16示出了本公开该又一实施例采用第五刻蚀工艺对第四光刻胶去除区域的多晶硅薄膜进行刻蚀后得到的结构示意图；
图17示出了本公开该又一实施例去除第四光刻胶保留区域剩余的光刻胶，以得到遮光层和多晶硅层的结构示意图；
图18示出了本公开实施例的一种阵列基板的结构示意图；以及
图19示出了本公开实施例的一种显示面板的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅是本公开一部分实施例，并不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在无需做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要注意的是，自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
除非另外定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1所示，在制作低温多晶硅基板时，首先在衬底11上通过构图工艺形成遮光层12，该遮光层12的材料通常采用金属钼，遮光层12的形成步骤包括：遮光层薄膜沉积、光刻胶图案化、遮光层薄膜刻蚀，光刻胶剥离等；然后，形成覆盖遮光层12的缓冲层13，该缓冲层13为氮化硅和氧化硅的复合膜层；最后，在缓冲层13上通过构图工艺形成多晶硅层14，多晶硅层14的形成步骤主要包括：多晶硅薄膜的形成、光刻胶图案化、多晶硅薄膜刻蚀，光刻胶剥离等，其中，只有沟道区域处的多晶硅层14在遮光层12上的正投影位于遮光层12所在的区域内。
但是，在低温多晶硅基板的这种制作过程中，遮光层12和多晶硅层14的形成分别需要采用一次构图工艺，整个低温多晶硅基板的制作工艺复杂，导致低温多晶硅基板的制作成本增加。
下面结合附图和示例实施方式对本公开作进一步详细的说明。
参照图2，示出了本公开实施例的一种低温多晶硅基板的制作方法的流程图，可以包括如下步骤：
步骤201，在衬底上形成遮光层薄膜。
如图3所示，提供一衬底31，例如，该衬底31可以为PI(Polyimide， 聚酰亚胺)基板或玻璃基板；在衬底31上形成遮光层薄膜320，该遮光层薄膜320可采用溅射工艺形成。
遮光层薄膜320的材料可以为氧化钼MoOx。
氧化钼的颜色为黑色，其本身性质稳定，不会与硅发生反应，且容易获取。
遮光层薄膜320的材料也可以用其他材料代替，只要遮光层薄膜320的材料颜色为黑色，且遮光层薄膜320的材料不与硅发生反应，例如，遮光层薄膜320的材料还可以为黑色树脂材料。
当遮光层薄膜320的材料为氧化钼时，遮光层薄膜320的厚度相对较小，后续对遮光层薄膜320进行图案化处理得到的遮光层的厚度也较小，可以有效减薄低温多晶硅基板的厚度。
当本公开实施例中的遮光层薄膜320的材料为氧化钼时，可以采用现有的溅射设备，在溅射过程中通入氧气形成氧化钼，不需要增加额外的制作设备和溅射材料。
步骤202，在所述遮光层薄膜上形成多晶硅薄膜。
如图3所示，在衬底31上形成遮光层薄膜320后，在遮光层薄膜320上形成多晶硅薄膜330。
例如，在所述遮光层薄膜上形成非晶硅薄膜；以及对所述非晶硅薄膜进行晶化处理，使得所述非晶硅薄膜转化为多晶硅薄膜。
在遮光层薄膜320上形成非晶硅薄膜，由于形成的非晶硅薄膜中含有氢，因此，需要将形成有非晶硅薄膜和遮光层薄膜320的衬底31放入退火炉中进行去氢处理，去除非晶硅薄膜中残留的氢，避免后续工艺产生氢爆；然后，对形成有非晶硅薄膜和遮光层薄膜320的衬底31进行预清洗，去除多余的杂质；之后，对形成有非晶硅薄膜和遮光层薄膜320的衬底31进行激光扫描，通过激光的能量使得非晶硅结晶，即对非晶硅薄膜进行晶化处理，将非晶硅薄膜转化为多晶硅薄膜330。例如，激光可以采用固态激光或准分子激光等。
步骤203，通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，得到遮光层和多晶硅层。
在本公开实施例中，通过一次构图工艺对遮光层薄膜320和多晶硅薄膜 330进行图案化处理，形成遮光层32和多晶硅层33，如图5所示；其中，多晶硅层33在遮光层32上的正投影位于遮光层32所在的区域内，以此方式，遮光层32可以实现对后续形成的薄膜晶体管的沟道起到遮光的作用。
例如，如图5所示，多晶硅层33在遮光层32上的正投影可以与遮光层32重叠。多晶硅层33在遮光层32上的正投影也可以全部位于遮光层32所在的区域内，且多晶硅层33的面积小于遮光层32的面积，如图11所示。
例如，遮光层32的材料为氧化钼，遮光层32的厚度为约
Figure PCTCN2020076779-appb-000003
至约
Figure PCTCN2020076779-appb-000004
在对遮光层薄膜320和多晶硅薄膜330进行图案化处理时，只需采用一次构图工艺就可得到遮光层32和多晶硅层33，简化了整个低温多晶硅基板的制作工艺，遮光层32在实现遮光效果的同时，代替相关技术中低温多晶硅基板中的缓冲层，同时也减小了低温多晶硅基板的厚度，从而可降低低温多晶硅基板的制作成本。
参照图4，示出了本公开一实施例的低温多晶硅基板的制作方法的流程图。
在本公开的该实施例中，步骤203可以包括：
子步骤2031，在所述多晶硅薄膜上涂覆光刻胶；
子步骤2032，采用第一光刻工艺对所述光刻胶进行图案化处理，形成第一光刻胶完全保留区域和第一光刻胶去除区域；
子步骤2033，采用第一刻蚀工艺对所述第一光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀；
子步骤2034，去除所述第一光刻胶完全保留区域剩余的光刻胶，得到遮光层和多晶硅层。
例如，第一刻蚀工艺所采用的刻蚀气体为Cl2、SF6和O2的混合气体。
图5至图7为本公开该实施例的制作低温多晶硅基板的结构示意图。
如图5所示，在多晶硅薄膜330上涂覆光刻胶40，然后，采用第一光刻工艺对光刻胶40进行图案化处理，形成第一光刻胶完全保留区域M1和第一光刻胶去除区域M2。第一光刻工艺指的是采用掩模板对光刻胶40进行曝光，然后对曝光后的光刻胶40进行显影。
光刻胶40可以为正性光刻胶或负性光刻胶，当光刻胶40为正性光刻胶时，第一光刻胶完全保留区域M1为未受曝光区域，第一光刻胶去除区域M2为受曝光区域，未受曝光区域的光刻胶40经显影后保留，受曝光区域的光刻胶40经显影后被去除；当光刻胶40为负性光刻胶时，第一光刻胶完全保留区域M1为受曝光区域，第一光刻胶去除区域M2为未受曝光区域，未受曝光区域的光刻胶40经显影后被去除，受曝光区域的光刻胶40经显影后保留。
如图6并参照图5所示，采用第一刻蚀工艺对第一光刻胶去除区域M2的多晶硅薄膜330和遮光层薄膜320进行刻蚀。第一刻蚀工艺为干法刻蚀工艺，所采用的刻蚀气体为Cl2、SF6和O2的混合气体。
如图7所示，去除第一光刻胶完全保留区域M1剩余的光刻胶40，得到遮光层32和多晶硅层33。
在本公开的该实施例中，在对遮光层薄膜320和多晶硅薄膜330进行图案化处理时，只需采用一次构图工艺就可得到遮光层32和多晶硅层33。例如，该构图工艺包括一次光刻工艺和一次刻蚀工艺，得到的多晶硅层33在遮光层32上的正投影与遮光层32重叠。
参照图8，示出了本公开另一实施例的低温多晶硅基板的制作方法的流程图。
在本公开的该实施例中，步骤203可以包括：
子步骤2035，在所述多晶硅薄膜上涂覆光刻胶；
子步骤2036，采用第二光刻工艺对所述光刻胶进行图案化处理，形成第二光刻胶完全保留区域和第二光刻胶去除区域；
子步骤2037，采用第二刻蚀工艺对所述第二光刻胶去除区域的多晶硅薄膜进行刻蚀；
子步骤2038，采用第三刻蚀工艺对所述第二光刻胶去除区域的遮光层薄膜进行刻蚀；
子步骤2039，去除所述第二光刻胶完全保留区域剩余的光刻胶，得到遮光层和多晶硅层。
第二刻蚀工艺所采用的刻蚀气体为Cl2和SF6的混合气体。第三刻蚀工 艺所采用的刻蚀气体为O2和SF6的混合气体。第二刻蚀工艺的刻蚀时长大于第三刻蚀工艺的刻蚀时长，或者，第二刻蚀工艺所采用的刻蚀气体的浓度大于第三刻蚀工艺所采用的刻蚀气体的浓度。
图9至图11为本公开该另一实施例制作低温多晶硅基板的结构示意图。
在多晶硅薄膜330上涂覆光刻胶40，然后，采用第二光刻工艺对光刻胶40进行图案化处理，形成第二光刻胶完全保留区域和第二光刻胶去除区域。
需要说明的是，采用第二光刻工艺对光刻胶40进行图案化处理时，所采用的掩模板与第一种实施例所采用的掩模板图案类似，第二光刻胶完全保留区域类似于图5所示的第一光刻胶完全保留区域M1，第二光刻胶去除区域类似于图5所示的第一光刻胶去除区域M2，为避免重复，在此不再通过额外的示意图进行示出。
如图9所示，采用第二刻蚀工艺对第二光刻胶去除区域的多晶硅薄膜330进行刻蚀。第二刻蚀工艺为干法刻蚀工艺，所采用的刻蚀气体为Cl2和SF6的混合气体。
如图10所示，采用第三刻蚀工艺对第二光刻胶去除区域的遮光层薄膜320进行刻蚀。第三刻蚀工艺为干法刻蚀工艺，所采用的刻蚀气体为O2和SF6的混合气体。
如图11所示，去除所述第二光刻胶完全保留区域剩余的光刻胶40，得到遮光层32和多晶硅层33。
在本公开的该另一实施例中，在对遮光层薄膜320和多晶硅薄膜330进行图案化处理时，只需采用一次构图工艺就可得到遮光层32和多晶硅层33。例如，该构图工艺包括一次光刻工艺和两次刻蚀工艺，其中，第二刻蚀工艺的刻蚀时长大于第三刻蚀工艺的刻蚀时长，或者，第二刻蚀工艺所采用的刻蚀气体的浓度大于第三刻蚀工艺所采用的刻蚀气体的浓度。
通过调节两次刻蚀工艺的气体浓度或者刻蚀时间，使得得到的多晶硅层33在遮光层32上的正投影全部位于遮光层32所在的区域内，且多晶硅层33的面积小于遮光层32的面积，实现更好的遮光效果。
参照图12，示出了本公开又一实施例的低温多晶硅基板的制作方法的流程图。
在本公开的该又一实施例中，步骤203可以包括：
子步骤2040，在所述多晶硅薄膜上涂覆光刻胶；
子步骤2041，采用第三光刻工艺对所述光刻胶进行图案化处理，形成第三光刻胶完全保留区域、光刻胶部分保留区域和第三光刻胶去除区域；
子步骤2042，采用第四刻蚀工艺对所述第三光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀；
子步骤2043，对所述第三光刻胶完全保留区域和所述光刻胶部分保留区域的光刻胶进行灰化处理，形成第四光刻胶保留区域和第四光刻胶去除区域；
子步骤2044，采用第五刻蚀工艺对所述第四光刻胶去除区域的多晶硅薄膜进行刻蚀；
子步骤2045，去除所述第四光刻胶保留区域剩余的光刻胶，以得到遮光层和多晶硅层。
第四刻蚀工艺所采用的刻蚀气体为Cl2、SF6和O2的混合气体。第五刻蚀工艺所采用的刻蚀气体为Cl2和SF6的混合气体。第三光刻工艺所采用的掩模板为半色调掩模板。
图13至图17为本公开的另一实施例制作低温多晶硅基板的结构示意图。
如图13所示，在多晶硅薄膜330上涂覆光刻胶40，然后，采用第三光刻工艺对光刻胶40进行图案化处理，形成第三光刻胶完全保留区域M3、光刻胶部分保留区域M4，和第三光刻胶去除区域M5。
第三光刻工艺所采用的掩模板为半色调掩模板，当光刻胶40为正性光刻胶时，第三光刻胶完全保留区域M3为未受曝光区域，光刻胶部分保留区域M4为部分受曝光区域，第三光刻胶去除区域M5为完全受曝光区域。第三光刻胶去除区域M5对应的掩模板图案的光线透过率大于光刻胶部分保留区域M4对应的掩模板图案的光线透过率。通过半色调掩模板对光刻胶40进行曝光显影，使得形成的第三光刻胶完全保留区域M3中光刻胶40的厚度大于光刻胶部分保留区域M4中光刻胶40的厚度。
如图14所示，采用第四刻蚀工艺对第三光刻胶去除区域M5的多晶硅薄膜330和遮光层薄膜320进行刻蚀，形成遮光层32的图案，此时，多晶硅层33的图案未完全形成，只能形成半刻蚀的多晶硅图案321。第四刻蚀工艺为 干法刻蚀工艺，所采用的刻蚀气体为Cl2、SF6和O2的混合气体，
如图15所示，对第三光刻胶完全保留区域M3和光刻胶部分保留区域M4的光刻胶40进行灰化处理，使得光刻胶部分保留区域M4的光刻胶40被完全去除，而第三光刻胶完全保留区域M3的光刻胶40被部分去除，形成第四光刻胶保留区域M6和第四光刻胶去除区域M7。可采用紫外线或臭氧等对光刻胶40进行灰化处理。
如图16所示，采用第五刻蚀工艺对第四光刻胶去除区域M7的多晶硅薄膜330进行刻蚀，例如，是对第四光刻胶去除区域M7的半刻蚀的多晶硅图案321进行刻蚀。第五刻蚀工艺为干法刻蚀工艺，所采用的刻蚀气体为Cl2和SF6的混合气体。
如图17所示，去除第四光刻胶保留区域M6剩余的光刻胶40，得到遮光层32和多晶硅层33。
在本公开的又一实施例中，在对遮光层薄膜320和多晶硅薄膜330进行图案化处理时，只需采用一次构图工艺就可得到遮光层32和多晶硅层33。例如，该构图工艺包括一次光刻工艺、两次刻蚀工艺和一次灰化工艺，得到的多晶硅层33在遮光层32上的正投影全部位于遮光层32所在的区域内，且多晶硅层33的面积小于遮光层32的面积。相对于图11所示的低温多晶硅基板，图17所示的低温多晶硅基板中遮光层32边缘与多晶硅层33边缘之间的距离更大，使得遮光效果更好。
在本公开实施例中，通过在衬底上形成遮光层薄膜，在遮光层薄膜上形成多晶硅薄膜，通过一次构图工艺对遮光层薄膜和多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层，多晶硅层在遮光层上的正投影位于遮光层所在的区域内。通过形成在衬底上的遮光层实现遮光效果的同时，代替相关技术中低温多晶硅基板中的缓冲层，在对遮光层薄膜和多晶硅薄膜进行图案化处理时，只需采用一次构图工艺就可得到遮光层和多晶硅层，简化了整个低温多晶硅基板的制作工艺，同时也减小了低温多晶硅基板的厚度，从而可降低低温多晶硅基板的制作成本。
本公开实施例提供了一种低温多晶硅基板，包括：衬底31；形成在衬底31上的遮光层32；形成在遮光层32上的多晶硅层33；其中，遮光层32和 多晶硅层33是对依次形成在衬底31上的遮光层薄膜320和多晶硅薄膜330通过一次构图工艺进行图案化处理后得到的；多晶硅层33在遮光层32上的正投影位于遮光层32所在的区域内。
如图7所示，多晶硅层33在遮光层32上的正投影与遮光层32重叠，如图11和图17所示，多晶硅层33在遮光层32上的正投影全部位于遮光层32所在的区域内，且多晶硅层33的面积小于遮光层32的面积。
遮光层32的厚度为约
Figure PCTCN2020076779-appb-000005
至约
Figure PCTCN2020076779-appb-000006
遮光层32的材料为氧化钼。
本公开实施例的低温多晶硅基板可以采用上述低温多晶硅基板的制作方法制成。
在本公开实施例中，通过形成在衬底上的遮光层实现遮光效果的同时，代替相关技术中低温多晶硅基板中的缓冲层，在对遮光层薄膜和多晶硅薄膜进行图案化处理时，只需采用一次构图工艺就可得到遮光层和多晶硅层，简化了整个低温多晶硅基板的制作工艺，同时也减小了低温多晶硅基板的厚度，从而可降低低温多晶硅基板的制作成本。
本公开实施例还提供了一种阵列基板，包括上述的低温多晶硅基板。
参照图18，示出了本公开实施例的一种阵列基板的结构示意图。
在本公开实施例中，阵列基板还包括形成在低温多晶硅基板上的薄膜晶体管51和信号线，且薄膜晶体管51和信号线在遮光层32上的正投影位于遮光层32所在的区域内；其中，信号线包括栅线511、数据线512和扫描信号线(在图18中未示出)等。
通过将本公开实施例中的遮光层32设置在多晶硅层33对应位置处的同时，还设置在薄膜晶体管51和信号线的对应位置处，且薄膜晶体管51和信号线在遮光层32上的正投影位于遮光层32所在的区域内，因此，遮光层32可实现对阵列基板中的像素漏光位置进行遮光，代替相关技术显示面板中的黑矩阵，可省去黑矩阵的制作工艺步骤。
此外，由于遮挡像素漏光的遮光层32设置在了阵列基板上，则后续在将阵列基板与对盒基板对盒形成显示面板时，无需考虑对盒精度的问题，因此，可大幅度减小遮光层32边缘到像素漏光位置的偏差，从而可减小遮光层32的宽度，提高像素的开口率和透过率，可实现曲面显示，并降低显示面板 所需的功耗。
例如，如图19所示，在衬底31上制作得到遮光层32和多晶硅层33后，对多晶硅层33进行离子掺杂，主要包括在薄膜晶体管51(即位于像素区域的像素晶体管)的沟道位置处进行硼掺杂，与沟道区域相邻的位置处进行N型轻掺杂，在多晶硅层33的边缘位置进行N型重掺杂，然后，通过构图工艺依次形成栅绝缘层和栅极，接着，对驱动区域的驱动晶体管位置处进行P型掺杂，掺杂完成后制作介电层，之后，通过构图工艺形成源漏电极，得到薄膜晶体管51。
在形成薄膜晶体管51后，制作色阻层52，色阻层52包括红色色阻区域、绿色色阻区域和蓝色色阻区域等，接着，形成平坦层53，然后，在平坦层53上形成公共电极层54，在公共电极层54上形成钝化层55，在钝化层55上通过构图工艺形成像素电极56，从而得到阵列基板50。
之后，在对盒基板60上形成隔垫物70，将形成有隔垫物70的对盒基板60与阵列基板50进行对盒，得到显示面板。
由图19可看出，对盒基板60上未设置有黑矩阵和色阻层，而是将色阻层52制作在阵列基板50侧，同时，遮光层32可实现对阵列基板中的像素漏光位置进行遮光，代替相关技术显示面板中的黑矩阵，以此方式，可减少黑矩阵的制作工艺步骤。
本公开实施例的阵列基板50不仅可以应用在LCD(Liquid Crystal Display，液晶显示器)显示面板中，还可以应用在OLED(Organic Light Emitting Diode，有机发光二极管)显示面板中。
本公开的实施例还提供一种显示装置，例如LCD液晶显示装置和有机发光二极管显示装置，包括前述实施例的阵列基板50，以及对盒基板60。该显示装置还可以包括位于阵列基板50和对盒基板60之间的隔垫物70。该显示装置可以是任何具有显示功能的装置，例如，可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例中，通过形成在衬底上的遮光层实现遮光效果的同时，代替相关技术低温多晶硅基板中的缓冲层，在对遮光层薄膜和多晶硅薄膜进 行图案化处理时，只需采用一次构图工艺就可得到遮光层和多晶硅层，简化了整个低温多晶硅基板的制作工艺，同时也减小了低温多晶硅基板的厚度，从而可降低低温多晶硅基板的制作成本；此外，通过将遮光层设置在薄膜晶体管和信号线的对应位置处，且薄膜晶体管和信号线在遮光层上的正投影位于遮光层所在的区域内，因此，遮光层可实现对阵列基板中的像素漏光位置进行遮光，代替相关技术显示面板中的黑矩阵，从而可减少黑矩阵的制作工艺步骤。
对于前述的方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本公开的实施例并不受所描述的动作顺序的限制，因为依据本公开的实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例为示例实施例，并不用于限制本公开。
本说明书中的各个实施例采用递进的方式进行了描述，每个实施例重点说明的是与其他实施例的不同之处，各个实施例之间相同相似的部分可以互相参照。
以上对本发明所提供的一种低温多晶硅基板及其制作方法、阵列基板，进行了详细介绍，本文中应用了示例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的内容，而不是用于限制本公开的范围。以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例，而这些新的实施例都应属于本公开的范围。
以上所述，仅为本公开的示例实施例，本公开的保护范围并不局限于此，任何熟悉本技术领域的普通技术人员在本公开实施例揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。

Claims (15)

  1. 一种低温多晶硅基板的制作方法，包括：
    在衬底上形成遮光层薄膜；
    在所述遮光层薄膜上形成多晶硅薄膜；
    通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层；
    其中，所述多晶硅层在所述遮光层上的正投影位于所述遮光层所在的区域内。
  2. 根据权利要求1所述的方法，其中，所述遮光层的材料为氧化钼。
  3. 根据权利要求1或2所述的方法，其中，所述通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，得到遮光层和多晶硅层的步骤，包括：
    在所述多晶硅薄膜上涂覆光刻胶；
    采用第一光刻工艺对所述光刻胶进行图案化处理，形成第一光刻胶完全保留区域和第一光刻胶去除区域；
    采用第一刻蚀工艺对所述第一光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀；以及
    去除所述第一光刻胶完全保留区域剩余的光刻胶，以得到遮光层和多晶硅层；
    其中，所述第一刻蚀工艺所采用的刻蚀气体为Cl2、SF6和O2的混合气体。
  4. 根据权利要求1或2所述的方法，其中，所述通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层的步骤，包括：
    在所述多晶硅薄膜上涂覆光刻胶；
    采用第二光刻工艺对所述光刻胶进行图案化处理，形成第二光刻胶完全保留区域和第二光刻胶去除区域；
    采用第二刻蚀工艺对所述第二光刻胶去除区域的多晶硅薄膜进行刻蚀；
    采用第三刻蚀工艺对所述第二光刻胶去除区域的遮光层薄膜进行刻蚀；以及
    去除所述第二光刻胶完全保留区域剩余的光刻胶，以得到遮光层和多晶硅层；
    其中，所述第二刻蚀工艺所采用的刻蚀气体为Cl2和SF6的混合气体，所述第三刻蚀工艺所采用的刻蚀气体为O2和SF6的混合气体；所述第二刻蚀工艺的刻蚀时长大于所述第三刻蚀工艺的刻蚀时长，或者，所述第二刻蚀工艺所采用的刻蚀气体的浓度大于所述第三刻蚀工艺所采用的刻蚀气体的浓度。
  5. 根据权利要求1或2所述的方法，其中，所述通过一次构图工艺对所述遮光层薄膜和所述多晶硅薄膜进行图案化处理，以得到遮光层和多晶硅层的步骤，包括：
    在所述多晶硅薄膜上涂覆光刻胶；
    采用第三光刻工艺对所述光刻胶进行图案化处理，形成第三光刻胶完全保留区域、光刻胶部分保留区域和第三光刻胶去除区域；
    采用第四刻蚀工艺对所述第三光刻胶去除区域的多晶硅薄膜和遮光层薄膜进行刻蚀；
    对所述第三光刻胶完全保留区域和所述光刻胶部分保留区域的光刻胶进行灰化处理，形成第四光刻胶保留区域和第四光刻胶去除区域；
    采用第五刻蚀工艺对所述第四光刻胶去除区域的多晶硅薄膜进行刻蚀；以及
    去除所述第四光刻胶保留区域剩余的光刻胶，以得到遮光层和多晶硅层；
    其中，所述第四刻蚀工艺所采用的刻蚀气体为Cl2、SF6和O2的混合气体，所述第五刻蚀工艺所采用的刻蚀气体为Cl2和SF6的混合气体，所述第三光刻工艺所采用的掩模板为半色调掩模板。
  6. 根据权利要求1-5任一项所述的方法，其中，所述在所述遮光层薄膜上形成多晶硅薄膜的步骤，包括：
    在所述遮光层薄膜上形成非晶硅薄膜；以及
    对所述非晶硅薄膜进行晶化处理，使得所述非晶硅薄膜转化为多晶硅薄 膜。
  7. 一种低温多晶硅基板，包括：
    衬底；
    形成在所述衬底上的遮光层；以及
    形成在所述遮光层上的多晶硅层；
    其中，所述遮光层和所述多晶硅层是对依次形成在所述衬底上的遮光层薄膜和多晶硅薄膜通过一次构图工艺进行图案化处理后得到的；所述多晶硅层在所述遮光层上的正投影位于所述遮光层所在的区域内。
  8. 根据权利要求7所述的低温多晶硅基板，其中，所述多晶硅层的面积小于遮光层的面积。
  9. 根据权利要求7或8所述的低温多晶硅基板，其中，所述遮光层的厚度为约
    Figure PCTCN2020076779-appb-100001
    至约
    Figure PCTCN2020076779-appb-100002
  10. 一种阵列基板，包括如权利要求7或8所述的低温多晶硅基板。
  11. 根据权利要求10所述的阵列基板，还包括形成在所述低温多晶硅基板上的薄膜晶体管和信号线，且所述薄膜晶体管和信号线在所述遮光层上的正投影位于所述遮光层所在的区域内。
  12. 根据权利要求11所述的阵列基板，其中，所述信号线包括栅线和数据线。
  13. 根据权利要求11或12所述的阵列基板，还包括：设置在薄膜晶体管上的色阻层，位于色阻层上的平坦层，位于平坦化层上的公共电极层，位于电极层上的钝化层，以及在钝化层上形成的像素电极。
  14. 一种显示装置，包括权利要求10-13任一项所述的阵列基板和与所述阵列基板相对设置的对盒基板。
  15. 根据权利要求14所述的显示装置，还包括设置在所述阵列基本和所述对盒基板之间的隔垫物。
PCT/CN2020/076779 2019-03-15 2020-02-26 低温多晶硅基板及其制作方法、阵列基板及显示装置 WO2020186985A1 (zh)

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