CN108074938B - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
CN108074938B
CN108074938B CN201610999719.XA CN201610999719A CN108074938B CN 108074938 B CN108074938 B CN 108074938B CN 201610999719 A CN201610999719 A CN 201610999719A CN 108074938 B CN108074938 B CN 108074938B
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layer
substrate
shielding structure
light shielding
active layer
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CN108074938A (zh
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姚琪
曹占锋
张锋
李海旭
班圣光
刘英伟
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201610999719.XA priority Critical patent/CN108074938B/zh
Priority to US15/745,062 priority patent/US10209558B2/en
Priority to EP17825714.3A priority patent/EP3543778B1/en
Priority to PCT/CN2017/097746 priority patent/WO2018086397A1/zh
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L21/02524—Group 14 semiconducting materials
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    • H01L21/02587—Structure
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G02F1/133531—Polarisers characterised by the arrangement of polariser or analyser axes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/13356—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements
    • G02F1/133565—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements inside the LC elements, i.e. between the cell substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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    • G02F1/133567—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements on the back side
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Abstract

一种阵列基板及其制造方法、显示装置。该阵列基板包括：基板、有源层、偏振板和遮光结构；有源层，设置于基板上；偏振板，与基板层叠设置，且设置在有源层的面向基板的一侧；遮光结构，设置于基板与有源层之间，其中，遮光结构具有偏振特性，且遮光结构的偏振方向与偏振板的偏振方向大致垂直。该阵列基板采用具有与偏振板的偏振方向大致垂直的偏振特性的遮光结构，既可以避免一般的遮光层厚度和坡度角引起的有源层的晶化不良，又可以简化工艺，降低成本，提升良率。

Description

阵列基板及其制造方法、显示装置
技术领域
本发明至少一实施例涉及一种阵列基板及其制造方法、显示装置。
背景技术
现有产品以n型金属氧化物半导体(nMOS)低温多晶硅-液晶显示器(LTPS-LCD)为例，通常采用9步图案化工艺进行生产，一般在有源层形成之前，采用钼等金属材料作为遮光层形成在基板上。现有技术中，一方面形成遮光层的金属材料的厚度及坡度会影响有源层的晶化效果，另一方面多步图案化工艺会增加成本并影响良率。
发明内容
本发明的至少一实施例提供一种阵列基板及其制造方法、显示装置。该阵列基板的遮光结构具有与偏振板的偏振方向大致垂直的偏振特性，既可以避免一般的遮光层厚度和坡度角引起的有源层的晶化不良，又可以简化工艺，降低成本。
本发明的至少一实施例提供一种阵列基板。该阵列基板包括基板、有源层、偏振板和遮光结构；有源层，设置于基板上；偏振板，与基板层叠设置，且设置在有源层的面向基板的一侧；遮光结构，设置于基板与有源层之间，该遮光结构具有偏振特性，且遮光结构的偏振方向与偏振板的偏振方向大致垂直。
本发明的至少一实施例提供一种阵列基板的制造方法，包括：在基板的一侧贴附偏振板；在基板上形成偏振层；在偏振层上形成半导体层；将偏振层和半导体层图案化，被图案化的半导体层形成有源层，被图案化的偏振层形成遮光结构，该遮光结构的偏振方向与偏振板的偏振方向大致垂直。
本发明的至少一实施例提供一种显示装置，包括上述任一种阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种阵列基板制造工艺中图案化工艺流程图；
图2a为本发明一实施例提供的一种阵列基板；
图2b为本发明一实施例提供的另一种阵列基板；
图2c为本发明另一实施例提供的一种阵列基板；
图3为本发明一实施例提供的一种阵列基板制造方法示意图；
图4为本发明一实施例提供的一种阵列基板制造图案化工艺流程图；
图5a-5i为本发明一实施例提供的一种阵列基板各步图案化工艺后截面示意图。
附图标记：101-基板；102-有源层；1021-半导体层；103-偏振板；104-遮光结构；1041-偏振层；105-缓冲层；106-绝缘层；110-栅绝缘层；111-栅极；112-接触孔；1131-源极；1132-漏极；114平坦化层；1141-过孔；1142-过孔；115-公共电极；116-钝化层；117-像素电极；118-公共电极线；119-层间绝缘层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种阵列基板制造工艺中图案化工艺流程图。如图1所示，以n型金属氧化物半导体(nMOS)低温多晶硅-液晶显示器(LTPS-LCD)为例，包括：基板、遮光层、缓冲层、有源层、栅绝缘层、栅电极、层间绝缘层、源漏电极、平坦化层、公共电极、钝化层和像素电极。为了制作此阵列基板，通常需要利用9张掩膜板进行9次构图工艺，分别是：
S01：利用遮光层掩膜板(Mask 1)通过构图工艺形成遮光层；
S02：利用有源层掩膜板(Mask 2)通过构图工艺对半导体层进行刻蚀形成有源层；
S03：利用栅电极掩膜板(Mask 3)通过构图工艺形成栅电极；
S04：利用接触孔掩膜板(Mask 4)通过构图工艺形成用于连接源漏电极与有源层的接触孔；
S05：利用源漏电极掩膜板(Mask 5)通过构图工艺形成源/漏电极；
S06：利用平坦化层掩膜板(Mask 6)通过构图工艺对平坦化层处理形成过孔，用以露出漏极和公共电极线；
S07：利用公共电极掩膜板(Mask 7)通过构图工艺形成公共电极；
S08：利用钝化层掩膜板(Mask 8)通过构图工艺对钝化层处理形成过孔，用以露出漏极；
S09：利用像素电极掩膜板(Mask 9)通过构图工艺形成像素电极，使像素电极与漏极电连接。
在步骤S01中利用遮光层掩膜板(Mask 1)通过构图工艺形成遮光层。一方面，采用钼等金属材料在基板上形成整面遮光层，针对不同产品中的每个产品都需要一块掩膜板，对遮光层采用大面积湿刻的方法进行图案化刻蚀，刻蚀后的遮光层的尺寸一般大于后续形成的有源层尺寸，并且很难与有源层同时图案化形成。另一方面，遮光层的厚度和坡度角也会影响后续有源层晶化的效果。
本发明至少一个实施例提供了一种阵列基板，该阵列基板包括基板、有源层、偏振板和遮光结构；有源层，设置于基板上；偏振板，与基板层叠设置，且设置在有源层的面向基板的一侧；遮光结构，设置于基板与有源层之间，遮光结构具有偏振特性，且遮光结构的偏振方向与偏振板的偏振方向大致垂直。这里“大致垂直”是指严格垂直和近似垂直，保证遮光结构和偏振板的结合可以起到遮光效果。该阵列基板中的遮光结构的偏振方向与偏振板的偏振方向大致垂直，从而使得在后续形成液晶盒后，有源层靠近基板的一侧的背光源无光线射入有源层，以避免背光源照射有源层产生光生漏电流。
本发明的至少一实施例提供一种阵列基板的制造方法，包括：在基板的一侧贴附偏振板；在基板上形成偏振层；在偏振层上形成半导体层；将偏振层和半导体层图案化，被图案化的半导体层形成有源层，被图案化的偏振层形成遮光结构，该遮光结构的偏振方向与偏振板的偏振方向大致垂直。在该阵列基板的制造方法中由于利用偏振层形成遮光结构，所形成的遮光结构厚度较薄，可以避免因遮光结构的厚度和坡度角引起有源层后续的晶化不良。
本发明的至少一实施例提供一种显示装置，包括上述任一种阵列基板。该显示装置采用上述阵列基板，可以避免有源层被光照射产生光生漏电流，提升了良率。
以下通过几个实施例予以说明。
实施例一
本发明实施例提供了一种阵列基板，如图2a所示，阵列基板包括：基板101、有源层102、偏振板103和遮光结构104；有源层102，设置于基板101上；偏振板103，与基板101层叠设置，且设置在有源层102的面向基板101的一侧；遮光结构104，设置于基板101与有源层102之间，遮光结构104具有偏振特性，且遮光结构104的偏振方向与偏振板103的偏振方向大致垂直。基板101上的遮光结构104的偏振方向与基板101远离遮光结构104一侧的偏振板103的偏振方向大致垂直，当光源从偏振板103远离基板101的一侧入射时，偏振板103吸收了与其偏光轴大致垂直方向的光，因此从偏振板103出射的光是与偏振板103的偏振方向相同的线偏振光。当该线偏振光透过基板101入射到遮光结构104时，由于遮光结构104的偏振方向与偏振板103的偏振方向大致垂直，该线偏振光的偏振方向与遮光结构104的偏振方向大致垂直，该线偏振光不能通过遮光结构104。因此，遮光结构104与偏振板103的配合起到了良好的遮光效果，偏振板103远离基板101的一侧的背光源无光线射入有源层102，以避免背光照射有源层102而产生光生漏电流，从而提高显示质量。需要说明的是，本实施例以液晶显示面板为例，并不限于此。
例如，如图2a所示，有源层102在基板101上的正投影落入遮光结构104在基板101上的正投影内，且有源层102和遮光结构104在基板101上的正投影均落入偏振板103在基板101上的正投影内。例如，有源层102和遮光结构104在基板上101的正投影彼此重叠，如图2a所示，遮光结构104的图案与有源层102的图案的形状与尺寸相同，彼此重叠，即遮光结构104与有源层102可以通过一步图案化工艺形成具有相同形状与尺寸的图案。与一般的图案化工艺流程相比，利用一步图案化工艺形成遮光结构104与有源层102，可以有效减少单独对遮光结构图案化的步骤，从而节省成本并提高了良率。
例如，当背光光源入射到偏振板103时，与偏振板103的偏光轴平行方向的光可以通过，因此从偏振板103出射的光是与偏振板103的偏振方向相同的线偏振光。当该线偏振光入射到遮光结构104时，由于遮光结构104的偏振方向与偏振板103的偏振方向大致垂直，该线偏振光的偏振方向与遮光结构104的偏振方向大致垂直，该线偏振光不能通过遮光结构104，因此，遮光结构104与偏振板103的配合用于遮挡入射到有源层102的光。一般利用材料的不透明性进行遮光的遮光层，为了达到良好的遮光效果，其厚度往往约几百～几千埃。这种较厚的遮光层在图案化过程中会产生一定的坡度角，影响后续有源层的晶化效果。而本实施例中具有偏振特性的遮光结构104的厚度例如为50埃-200埃，相比于一般的遮光层减少了厚度方面的影响，也避免了坡度角的产生，从而可以保证后续有源层102的晶化效果。
例如，遮光结构104的材料例如包括金属或含有导电物质的树脂。该遮光结构104的材料可以与一般的遮光层选用的金属材料相同，包括：钼、铝、铬或银等；也可以是含有导电物质的树脂层，该导电物质可以为纳米级的金属丝线，包括银丝、铝线等，或者金属粉末状的添加剂等。本实施例对遮光结构104的材料并不限定，也可以是具有纳米级的透明或不透明的非导电材料。
例如，遮光结构104具有纳米尺寸的光栅图案，可以通过纳米压印或者激光直接成型技术等方法制作而成，本实施例不限于此。例如，遮光结构104的光栅图案的周期可以为60nm-300nm。例如，遮光结构104的光栅图案为平行排列的狭缝，大致垂直狭缝延伸方向的光可以透过，狭缝的透光方向与偏振板103的透光轴方向大致垂直，从偏振板103出射的线偏振光的方向与遮光结构104的光栅图案中狭缝的透光方向大致垂直，从而不能通过遮光结构104，因此，遮光结构104与偏振板103的配合用于遮挡入射到有源层102中的光线。
在上述实施例中，偏振板103设置在基板101的远离有源层102的一侧，但根据本发明的实施例并不限于此。图2b为本发明一实施例提供的另一种阵列基板。例如，如图2b所示，偏振板103设置于基板101与有源层102之间。本实施例不限于此，偏振板103可以与有源层102形成在基板101的同一侧，只需要偏振板103和遮光结构104均形成在有源层102靠近基板101的一侧即可。例如，在大致垂直于基板101的方向上，遮光结构104和偏振板103形成在有源层102和基板101之间，并且遮光结构104和偏振板103在该方向上的次序可以变换。在这些结构中，由于遮光结构104和偏振板103的偏振方向大致垂直，在二者的结合作用下，可以起到遮挡光线的作用。例如，在这些结构中，偏振板103可以以偏光膜层的形式形成。
实施例二
本实施例提供了一种阵列基板，如图2c所示，该阵列基板除了与实施例一相同的部分外，还包括缓冲层105，该缓冲层105设置于遮光结构104与有源层102之间。缓冲层的材料可以选用氧化物、氮化物或氧氮化合物等。如图2c所示，缓冲层105与遮光结构104以及有源层102的图案的形状与尺寸相同，即缓冲层105与遮光结构104以及有源层102可通过一步图案化工艺形成具有相同形状与尺寸的图案。例如，缓冲层105为绝缘缓冲层，一方面可以对有源层102和遮光结构104起到绝缘作用，另一方面能够使后续在缓冲层105上形成的有源层102晶化的效果更好。
实施例三
本实施例提供了一种阵列基板的制造方法，如图3所示，包括如下步骤。
S1：在基板的一侧贴附偏振板；
S2：在基板上形成偏振层；
S3：在偏振层上形成半导体层；
S4：将偏振层和半导体层图案化，被图案化的半导体层形成有源层，被图案化的偏振层形成遮光结构。
在本实施例提供的一种阵列基板的制造方法中，遮光结构的偏振方向与偏振板的偏振方向大致垂直。例如，在步骤S1中在基板的一侧贴附偏振板，步骤S2中在基板上形成偏振层，该偏振层形成在基板远离偏振板的一侧，但根据本发明的实施例并不限于此。例如，偏振板也可以与偏振层形成在基板的同一侧，且形成在有源层的面向基板的一侧，并且偏振层和偏振板在该方向上的次序可以变换。由于偏光层和偏振板的偏振方向大致垂直，在二者的结合作用下，可以起到遮挡光线的作用。
采用本实施例提供的阵列基板的制造方法，例如，可以利用一次图案化工艺将偏振层和半导体层图案化，被图案化的偏振层形成遮光结构，被图案化的半导体层形成有源层。因此，本实施例与一般图案化工艺步骤相比，省去了单独图案化偏振层形成遮光结构的步骤。本实施例不限于此，偏振层和半导体层也可以分步图案化。
如图4所示，本实施例实现了8步图案化工艺，无需制作遮光结构的掩膜板，可以节省成本并提高良率。
S01：利用有源层掩膜板(Mask 1)通过一次图案化工艺将偏振层和半导体层图案化，被图案化的偏振层形成遮光结构，被图案化的半导体层形成有源层；
S02：利用栅电极掩膜板(Mask 2)通过构图工艺形成栅电极；
S03：利用接触孔掩膜板(Mask 3)通过构图工艺，刻蚀层间绝缘层和栅绝缘层，形成用于连接源漏电极与有源层的接触孔；
S04：利用源漏电极掩膜板(Mask 4)通过构图工艺在接触孔形成源漏电极；
S05：利用平坦化层掩膜板(Mask 5)通过构图工艺对平坦化层处理形成过孔，用以露出漏极和公共电极线；
S06：利用公共电极掩膜板(Mask 6)通过构图工艺形成公共电极；
S07：利用钝化层掩膜板(Mask 7)通过构图工艺对钝化层处理形成过孔，用以露出漏极；
S08：利用像素电极掩膜板(Mask 8)通过构图工艺形成像素电极，使像素电极与漏极电连接。
图5a-5i示出了制作流程中各个阶段的结构示意图。如图5a所示，在基板101上依次形成绝缘层106、偏振层1041、缓冲层105和半导体层1021。例如，基板101可以由玻璃、聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯中的一种或多种材料制成。偏振层1041是形成于基板101上的整面偏振层，偏振层1041的偏振方向与基板101远离偏振层1041一侧的偏振板103的偏振方向大致垂直。
例如，偏振层1041采用纳米压印的方法形成光栅图案。例如，纳米压印技术是通过模板，将图形转移到相应的衬底上，转移的媒介通常是一层很薄的聚合物膜，通过热压或者辐照等方法使其结构硬化从而保留下转移的图形。该纳米压印模板预先根据偏振所需的平行排列的狭缝组成的光栅图案来制作，该模板可以采用石英、玻璃或塑料来制作。本实施例不限于纳米压印的方法，还可以采用激光直接成型技术等方法。例如，偏振层1041的光栅图案为平行排列的狭缝，大致垂直狭缝延伸方向的光可以透过。狭缝的透光方向与偏振板103的透光轴方向大致垂直，从偏振板103出射的线偏振光的方向与偏振层1041的光栅图案中的狭缝延伸方向平行，从而不能通过偏振层1041。因此，偏振层1041与偏振板103的配合起到了良好的遮光效果，偏振板103远离基板101的一侧的背光源无光线射入有源层102，以避免背光照射有源层102。需要说明的是，本实施例以液晶显示面板为例，不限于此。
例如，偏振层1041上形成半导体层1021包括：在偏振层1041上沉积非晶硅层，利用准分子激光退火的方式将非晶硅层晶化形成多晶硅层，本实施例的半导体层1021为多晶硅层。将非晶硅层晶化形成多晶硅层的方法还可以是金属诱发结晶工艺、选择性激光烧结、连续横向固化工艺等方法，本实施例并不限定。例如，根据本发明的实施例还可以包括金属氧化物半导体有源层等。
如图5b所示，使用有源层掩膜板(Mask 1)对半导体层1021和偏振层1041进行图案化，例如采用干法刻蚀一次图案化形成有源层102和遮光结构104，即在对半导体层1021进行图案化时，将刻蚀半导体层1021之后形成的有源层102下部的偏振层1041保留，裸露部分的偏振层1041刻蚀掉，而保留的那部分偏振层1041即形成遮光结构104。本实施例的刻蚀方法不限于此，还可以采用激光刻蚀等高精度刻蚀方法。
例如，遮光结构104的材料例如包括金属或含有导电物质的树脂。该遮光结构104的材料可以与一般的遮光层选用的金属材料相同，包括：钼、铝、铬或银等都可以；也可以是含有导电物质的树脂层，该导电物质可以为纳米级的金属丝线，包括银丝、铝线等，或者金属粉末状的添加剂等。本实施例对遮光结构104的材料并不限定，也可以是具有纳米级的透明或不透明的非导电材料。
例如，遮光结构104例如采用纳米压印的方法形成光栅图案。例如，遮光结构104的光栅图案为平行排列的狭缝，大致垂直狭缝延伸方向的光可以透过，狭缝的透光方向与偏振板103的透光轴方向大致垂直，因此，遮光结构104与偏振板103的配合用于遮挡入射到有源层102的光。
例如，本实施例提供的阵列基板的制造方法还包括：在遮光结构104与有源层102之间形成缓冲层105。如图5b所示，缓冲层105与遮光结构104以及有源层102的图案的形状与尺寸相同，即缓冲层105与遮光结构104以及有源层102可通过一步图案化工艺形成具有相同形状与尺寸的图案。缓冲层105的材料可以选用氧化物、氮化物或氧氮化合物等。缓冲层105一方面可以对有源层102和遮光结构104起到绝缘作用，另一方面能够使后续在缓冲层105上形成的有源层102晶化的效果更好。
如图5c所示，利用栅电极掩膜板(Mask 2)通过构图工艺在栅绝缘层110上将其上形成的导电层图案化形成栅电极111和公共电极线118，随后形成层间绝缘层119。栅绝缘层110和层间绝缘层119可以选用氧化物、氮化物或氮氧化合物等材料，栅电极111可以采用铝、铜、铬、钼、钛等金属材料中的任一种或者几种组合的合金，本实施例不限于此。本实施例中的栅极结构是双栅型薄膜晶体管，但并不限于此，还可以是单栅型薄膜晶体管。并且本实施例以顶栅型薄膜晶体管为例，利用遮光结构104与偏振板103配合，对栅极111靠近基板101一侧的有源层102进行遮光，从而使得在后续形成液晶盒后，有源层102靠近基板101的一侧的背光源无光线射入有源层102，以避免背光源照射有源层102产生光生漏电流，但本发明并不限于此，也可以是底栅型薄膜晶体管。
如图5d所示，利用接触孔掩膜板(Mask 3)通过构图工艺,刻蚀层间绝缘层119和栅绝缘层110形成用于连接源电极1131和漏电极1132与有源层102的接触孔112。
如图5e所示，利用源漏电极掩膜板(Mask 4)通过构图工艺在接触孔112形成源电极1131和漏电极1132，源电极1131和漏电极1132可以采用铝、铜、铬、钼、钛等金属材料中的任一种或者几种组合的合金，本实施例不限于此。
如图5f所示，利用平坦化层掩膜板(Mask 5)通过构图工艺对平坦化层114处理形成过孔1141和过孔1142，用以露出漏极1132和公共电极线118，露出的漏极1132与后续形成的像素电极117电连接，露出的公共电极线118与后续形成的公共电极115电连接。平坦化层114的材料可以是有机材料，例如聚酰亚胺等材料，本实施例不限于此。
如图5g所示，利用公共电极掩膜板(Mask 6)通过构图工艺对铟锡氧化层形成公共电极115，公共电极115的材料不限于铟锡氧化物。
如图5h所示，利用钝化层掩膜板(Mask 7)通过构图工艺对钝化层116处理形成过孔，用以露出漏极1132。钝化层116可以选用氧化物、氮化物或氮氧化合物等材料，本实施例不限于此。
如图5i所示，利用像素电极掩膜板(Mask 8)通过构图工艺形成像素电极117，使像素电极117与漏极1132电连接，像素电极117可以是铟锡氧化物等材料，本实施例不限于此。
需要说明的是，上述的具体流程与结构仅仅是根据本发明的一些示例性流程和结构。在利用具有偏振特性的遮光结构的基础上，可以结合或替换其他任何合适的流程和结构。例如，如实施例一中所述，除了偏振板103形成于基板101的下表面侧之外，其还可以形成在基板101的上表面侧。在这种情况下，需要制作流程的相应改变，这里不再赘述。
实施例四
本实施例提供一种显示装置，包括：上述任一种阵列基板。该显示装置采用上述阵列基板，既可以避免有源层被光源照射产生光生漏电流，又因为一步图案化工艺形成有源层和遮光结构，降低了成本并提升了良率。
例如，显示装置可以是液晶显示装置，背光源设置于基板与有源层相反的一侧。本实施例不限于此，还可以是有机发光二极管显示装置等。
有以下几点需要说明：
(1)除非另作定义，本发明实施例以及附图中，同一标号代表同一含义。
(2)本发明实施例附图中，只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (15)

1.一种阵列基板，包括：
基板；
有源层，设置于所述基板上；
偏振板，与所述基板层叠设置，且设置在所述有源层的面向所述基板的一侧；
遮光结构，设置于所述基板与所述有源层之间；
其中，所述遮光结构具有偏振特性，且所述遮光结构的偏振方向与所述偏振板的偏振方向大致垂直，所述有源层在所述基板上的正投影落入所述遮光结构在所述基板上的正投影内，且所述有源层和所述遮光结构在所述基板上的正投影均落入所述偏振板在所述基板上的正投影内，所述有源层和所述遮光结构利用一次图案化工艺图案化以使得所述有源层和所述遮光结构在所述基板上的正投影彼此重叠。
2.根据权利要求1所述的阵列基板，其中，所述遮光结构的厚度为50埃-200埃。
3.根据权利要求1所述的阵列基板，其中，所述偏振板设置于所述基板远离所述有源层的一侧。
4.根据权利要求1所述的阵列基板，其中，所述偏振板设置于所述基板与所述有源层之间。
5.根据权利要求1所述的阵列基板，其中，所述遮光结构的材料包括金属或含有导电物质的树脂。
6.根据权利要求1-5任一项所述的阵列基板，其中，所述遮光结构具有纳米尺寸的光栅图案。
7.根据权利要求1所述的阵列基板，还包括缓冲层，设置于所述遮光结构与所述有源层之间。
8.一种阵列基板的制造方法，包括：
在基板的一侧贴附偏振板；
在所述基板上形成偏振层；
在所述偏振层上形成半导体层；
利用一次图案化工艺将所述偏振层和所述半导体层图案化，被图案化的所述半导体层形成有源层，被图案化的所述偏振层形成遮光结构，
其中，所述遮光结构的偏振方向与所述偏振板的偏振方向大致垂直。
9.根据权利要求8所述的阵列基板的制造方法，其中，在所述偏振层上形成半导体层包括：
在所述偏振层上沉积非晶硅层，利用激光退火的方式将所述非晶硅层晶化形成多晶硅层，其中所述半导体层为所述多晶硅层。
10.根据权利要求8所述的阵列基板的制造方法，其中，所述遮光结构的厚度为50埃-200埃。
11.根据权利要求8所述的阵列基板的制造方法，其中，所述遮光结构的材料包括金属或含有导电物质的树脂。
12.根据权利要求8-11中任一项所述的阵列基板的制造方法，其中，所述遮光结构具有纳米尺寸的光栅图案。
13.根据权利要求12所述的阵列基板的制造方法，其中，通过纳米压印方法形成所述具有纳米尺寸的光栅图案。
14.根据权利要求8所述的阵列基板的制造方法，还包括：在所述遮光结构与所述有源层之间形成缓冲层，所述缓冲层与所述有源层在一次图案化工艺中被图案化。
15.一种显示装置，包括：如权利要求1-7中任一项所述的阵列基板。
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