WO2018086397A1 - 阵列基板及其制造方法、显示面板以及显示装置 - Google Patents

阵列基板及其制造方法、显示面板以及显示装置 Download PDF

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WO2018086397A1
WO2018086397A1 PCT/CN2017/097746 CN2017097746W WO2018086397A1 WO 2018086397 A1 WO2018086397 A1 WO 2018086397A1 CN 2017097746 W CN2017097746 W CN 2017097746W WO 2018086397 A1 WO2018086397 A1 WO 2018086397A1
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substrate
polarization structure
polarization
layer
active layer
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PCT/CN2017/097746
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English (en)
French (fr)
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姚琪
曹占锋
张锋
李海旭
班圣光
刘英伟
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京东方科技集团股份有限公司
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Priority to EP17825714.3A priority Critical patent/EP3543778B1/en
Priority to US15/745,062 priority patent/US10209558B2/en
Publication of WO2018086397A1 publication Critical patent/WO2018086397A1/zh

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    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • At least one embodiment of the present disclosure is directed to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • nMOS n-type metal oxide semiconductor
  • LTPS-LCD low-temperature polysilicon-liquid crystal display
  • a metal material such as molybdenum is used before the formation of the active layer.
  • a light shielding layer is formed on the substrate.
  • the light shielding layer is formed by patterning the entire surface metal layer formed on the substrate, and the entire metal layer is easily produced to cause an abnormal discharge phenomenon.
  • At least one embodiment of the present disclosure provides an array substrate, a method of fabricating the same, a display panel, and a display device.
  • At least one embodiment of the present disclosure provides an array substrate.
  • the array substrate includes a substrate, an active layer and a first polarization structure, and an active layer disposed on the substrate; the first polarization structure is disposed on a side of the active layer facing the substrate, and the first polarization structure is on the substrate.
  • the orthographic projection at least partially overlaps the orthographic projection of the active layer on the substrate.
  • the first polarization structure is disposed between the substrate and the active layer.
  • the orthographic projection of the active layer on the substrate falls within the orthographic projection of the first polarization structure on the substrate.
  • the orthographic projection of the active layer and the first polarization structure on the substrate substantially completely coincides.
  • the first polarization structure has a thickness of 50 angstroms. -200 angstroms.
  • the array substrate provided in the example of the embodiment further includes:
  • a second polarization structure disposed on the substrate and disposed on a side of the active layer facing the substrate
  • the polarization direction of the first polarization structure and the second polarization structure is substantially perpendicular, and the orthographic projections of the active layer and the first polarization structure on the substrate fall within the orthographic projection of the second polarization structure on the substrate.
  • the second polarization structure is disposed between the substrate and the active layer.
  • the second polarization structure has a nano-sized grating pattern.
  • the material of the first polarization structure includes a metal or a resin containing a conductive substance.
  • the first polarization structure has a nano-sized grating pattern.
  • the array substrate provided in the example of the embodiment further includes a buffer layer disposed between the first polarization structure and the active layer.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming a polarizing layer on a substrate; forming a semiconductor layer on the substrate; patterning the polarizing layer and the semiconductor layer, and forming the patterned semiconductor layer to be active
  • the layer, the patterned polarizing layer forms a first polarization structure, and the orthographic projection of the first polarization structure on the substrate at least partially overlaps the orthographic projection of the active layer on the substrate.
  • the semiconductor layer is formed on a side of the polarizing layer away from the substrate.
  • the polarizing layer and the semiconductor layer are patterned by a single patterning process.
  • the first polarization structure has a thickness of 50 angstroms to 200 angstroms.
  • the material of the first polarization structure includes a metal or a resin containing a conductive substance.
  • the first polarization structure has a nano-sized grating pattern.
  • the first polarization structure having a nano-sized grating pattern is formed by a nanoimprint method.
  • the method further includes: forming a buffer layer between the first polarization structure and the active layer, at least one of the buffer layer and the active layer and the first polarization structure Patterned in a single patterning process.
  • the method for manufacturing the array substrate provided in the example of the embodiment further includes:
  • the polarization directions of the first polarization structure and the second polarization structure are substantially perpendicular, and the orthographic projections of the active layer and the first polarization structure on the substrate both fall within the orthographic projection of the second polarization structure on the substrate.
  • the second polarization structure is formed between the active layer and the substrate.
  • the second polarization structure is formed by a nanoimprint method, and the second polarization structure has a nano-sized grating pattern.
  • At least one embodiment of the present disclosure provides a display panel including the array substrate in an example in which the portion does not include the second polarization structure, and a second polarization structure disposed on a side of the active layer facing the substrate,
  • the polarization directions of the first polarization structure and the second polarization structure are substantially perpendicular, and the orthographic projections of the active layer and the first polarization structure on the substrate both fall within the orthographic projection of the second polarization structure on the substrate.
  • At least one embodiment of the present disclosure provides a display panel including the above array substrate including a second polarization structure.
  • At least one embodiment of the present disclosure provides a display device including any of the above array substrates.
  • 1 is a flow chart of a patterning process in an array substrate manufacturing process
  • FIG. 2a is a schematic diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2b is a schematic diagram of an array substrate according to another example of an embodiment of the present disclosure.
  • 2c is a schematic diagram of an array substrate according to another example of an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of an array substrate according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a flow chart of a patterning process for fabricating an array substrate according to an embodiment of the present disclosure
  • 5a-5j are schematic cross-sectional views showing a patterning process of each step of an array substrate according to an embodiment of the present disclosure.
  • FIG. 1 is a flow chart of a patterning process in an array substrate manufacturing process.
  • an n-type metal oxide semiconductor (nMOS) low temperature polysilicon liquid crystal display (LTPS-LCD) is exemplified, including: a substrate, a light shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate electrode, An interlayer insulating layer, a source/drain electrode, a planarization layer, a common electrode, a passivation layer, and a pixel electrode.
  • nMOS n-type metal oxide semiconductor
  • LTPS-LCD low temperature polysilicon liquid crystal display
  • the light shielding layer is formed by a patterning process using a light shielding layer mask (Mask 1) in step S01.
  • a metal material such as molybdenum forms a light-shielding layer on the substrate, which is prone to abnormal discharge.
  • a mask is needed, and the light-shielding layer is patterned by large-area wet etching, and the size of the etched light-shielding layer is generally larger than the size of the active layer formed later. And it is difficult to form a pattern simultaneously with the active layer.
  • the thickness of the light shielding layer and the slope angle also affect the effect of crystallization of the subsequent active layer.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate, an active layer, and a first polarization structure, an active layer disposed on the substrate; and a first polarization structure disposed on the substrate facing the active layer One side, and the orthographic projection of the first polarization structure on the substrate at least partially overlaps the orthographic projection of the active layer on the substrate.
  • the array substrate provided in this embodiment is applied to, for example, a liquid crystal display panel
  • the polarization direction of the first polarization structure is substantially perpendicular to the polarization direction of the polarization plate in the liquid crystal display panel to ensure the combination of the first polarization structure and the polarization plate.
  • the light-shielding effect can be achieved such that the backlight of the active layer close to the side of the substrate is not incident on the active layer to prevent the backlight from illuminating the active layer to generate photo-generated leakage current.
  • the first polarization structure is used to replace the traditional metal light shielding layer, which can effectively avoid the abnormal discharge phenomenon caused by the first polarization structure of the light shielding effect.
  • the polarization direction of the first polarization structure is substantially perpendicular to the polarization direction of the polarizing plate.
  • substantially perpendicular means strictly vertical and approximately vertical, ensuring that the combination of the first polarizing structure and the polarizing plate can provide a light blocking effect.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming a polarizing layer on a substrate; forming a semiconductor layer on the substrate; patterning the polarizing layer and the semiconductor layer, and forming the patterned semiconductor layer to be active a layer, the patterned polarizing layer forms a first polarization structure, and the first polarization structure
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the active layer on the substrate.
  • the first polarization structure is formed by using the polarizing layer, the formed first polarization structure is thin, and the formation of the first polarization structure due to the thickness and the slope angle of the first polarization structure can be avoided. Subsequent crystallization of the active layer is poor.
  • At least one embodiment of the present disclosure provides a display device including any of the above array substrates.
  • the display device adopts the above array substrate, which can prevent the active layer from being irradiated with light to generate photo-induced leakage current, thereby improving the yield.
  • At least one embodiment of the present disclosure provides a display panel.
  • the array substrate the method of manufacturing the same, the display panel, and the display device will be described below by way of several embodiments.
  • FIG. 2a is a schematic diagram of an array substrate according to an example of an embodiment of the present disclosure.
  • the array substrate includes: a substrate 101, an active layer 102, and a first polarization. Structure 104.
  • the active layer 102 is disposed on the substrate 101.
  • the first polarization structure 104 is disposed on a side of the active layer 102 facing the substrate 101, and the orthographic projection of the first polarization structure 104 on the substrate 101 is opposite to the active layer 102.
  • the orthographic projections on the substrate 101 at least partially overlap.
  • the first polarization structure disposed on the side of the active layer facing the substrate may include: the first polarization structure is disposed between the active layer and the substrate, or the first polarization structure is disposed on the substrate away from the active layer.
  • the first polarization structure between the substrate and the active layer is described by taking the first polarization structure between the substrate and the active layer as an example.
  • FIG. 2b is a schematic diagram of an array substrate according to another example of an embodiment of the present disclosure.
  • a second polarization structure 103 a first polarization
  • the structure 104 is substantially perpendicular to the polarization direction of the second polarization structure 103, and the orthographic projections of the active layer 102 and the first polarization structure 104 on the substrate 101 both fall within the orthographic projection of the second polarization structure 103 on the substrate 101.
  • the polarization direction of the first polarization structure 104 on the side of the substrate 101 facing the active layer 102 is substantially perpendicular to the polarization direction of the second polarization structure 103 on the side of the substrate 101 away from the first polarization structure 104, when the light source is from the second polarization structure.
  • the second polarization structure 103 absorbs light substantially perpendicular to the transmission axis thereof, and thus the light emitted from the second polarization structure 103 is the same as the polarization direction of the second polarization structure 103. polarized light.
  • the linearly polarized light When the linearly polarized light is incident on the first polarization structure 104 through the substrate 101, due to the polarization direction of the first polarization structure 104 and the second polarization structure 103 The polarization direction is substantially perpendicular, and the polarization direction of the linearly polarized light is substantially perpendicular to the polarization direction of the first polarization structure 104, and the linearly polarized light cannot pass through the first polarization structure 104. Therefore, the cooperation of the first polarization structure 104 and the second polarization structure 103 provides a good light-shielding effect, and the backlight of the second polarization structure 103 away from the substrate 101 is light-injected into the active layer 102 to avoid backlight illumination.
  • the source layer 102 generates a photo-generated leakage current, thereby improving display quality. It should be noted that the present embodiment is exemplified by a liquid crystal display panel, and is not limited thereto.
  • the orthographic projection of the active layer 102 on the substrate 101 falls within the orthographic projection of the first polarization structure 104 on the substrate 101, and the active layer 102 and the first polarization structure 104 are on the substrate 101.
  • the orthographic projections all fall within the orthographic projection of the second polarization structure 103 on the substrate 101.
  • the orthographic projections of the active layer 102 and the first polarization structure 104 on the substrate 101 completely coincide.
  • the pattern of the first polarization structure 104 and the pattern of the active layer 102 are the same in shape and size, overlapping each other.
  • the first polarization structure 104 and the active layer 102 may form a pattern having the same shape and size by a one-step patterning process.
  • the first polarization structure 104 and the active layer 102 are formed by a one-step patterning process, which can effectively reduce the step of patterning the first polarization structure separately, thereby saving cost and improving yield.
  • the backlight source when incident on the second polarization structure 103, light in a direction parallel to the transmission axis of the second polarization structure 103 can pass, and thus the light emitted from the second polarization structure 103 is the polarization direction and the second polarization structure 103.
  • the linearly polarized light of the same polarization direction when the backlight source is incident on the second polarization structure 103, light in a direction parallel to the transmission axis of the second polarization structure 103 can pass, and thus the light emitted from the second polarization structure 103 is the polarization direction and the second polarization structure 103.
  • the linearly polarized light of the same polarization direction when the backlight source is incident on the second polarization structure 103, light in a direction parallel to the transmission axis of the second polarization structure 103 can pass, and thus the light emitted from the second polarization structure 103 is the polarization direction and the second polarization structure 103.
  • the polarization direction of the first polarization structure 104 is substantially perpendicular to the polarization direction of the second polarization structure 103, the polarization direction of the linearly polarized light and the polarization of the first polarization structure 104 The direction is substantially vertical and the linearly polarized light cannot pass through the first polarization structure 104. Therefore, the cooperation of the first polarization structure 104 and the second polarization structure 103 serves to block light incident on the active layer 102.
  • the light-shielding layer which is shielded by the opacity of the material is used in a thickness of about several hundred to several thousand angstroms in order to achieve a good light-shielding effect.
  • the thicker light-shielding layer will have a certain slope angle during the patterning process, which affects the crystallization effect of the subsequent active layer.
  • the thickness of the first polarization structure 104 having polarization characteristics in this embodiment is, for example, 50 angstroms to 200 angstroms, which reduces the influence on the thickness of the general light shielding layer, and also avoids the generation of the slope angle, thereby ensuring the subsequent The crystallization effect of the active layer 102.
  • the material of the first polarizing structure 104 includes, for example, a metal or a resin containing a conductive substance.
  • the material of the first polarizing structure 104 may be the same as the metal material selected for the general light shielding layer, including molybdenum, aluminum, chromium or silver, or a resin layer containing a conductive material, which may be a nano-scale metal. Wires, including silver wire, aluminum wire, etc., or metal powder additives. This embodiment is first
  • the material of the polarization structure 104 is not limited, and may be a transparent or opaque non-conductive material having a nanometer order.
  • the first polarization structure 104 has a nano-sized grating pattern, which can be fabricated by a method such as nanoimprinting or laser direct structuring, and the embodiment is not limited thereto.
  • the period of the grating pattern of the first polarization structure 104 may be from 60 nm to 300 nm.
  • the grating pattern of the first polarization structure 104 is a slit arranged in parallel, and light extending substantially perpendicular to the direction in which the slit extends can be transmitted, and the direction of the linearly polarized light emitted from the second polarization structure 103 and the grating of the first polarization structure 104
  • the extending direction of the slits in the pattern is substantially parallel so as not to pass through the first polarizing structure 104, and therefore, the cooperation of the first polarizing structure 104 and the second polarizing structure 103 serves to block light incident into the active layer 102.
  • the second polarization structure 103 may also have a nanometer-sized grating pattern, which may be fabricated by a method such as nanoimprinting or laser direct structuring, and the embodiment is not limited thereto.
  • the second polarization structure 103 may be a metal wire grid structure. The second polarization structure 103 using the metal wire grid structure can replace the polarizing plate in the liquid crystal display panel, and can not only reduce the thickness of the display panel, but also eliminate the process of attaching the polarizing plate in the manufacturing process of the display panel.
  • the second polarization structure 103 is disposed on the side of the substrate 101 remote from the active layer 102, but the embodiment according to the present disclosure is not limited thereto.
  • 2c is a schematic diagram of an array substrate in another example according to an embodiment of the present disclosure.
  • the second polarization structure 103 is disposed between the substrate 101 and the active layer 102.
  • the embodiment is not limited thereto, and the second polarization structure 103 may be disposed on the same side of the substrate 101 as the active layer 102, and only the second polarization structure 103 and the first polarization structure 104 are required to be disposed on the active layer 102 near the substrate 101.
  • One side can be.
  • the first polarization structure 104 and the second polarization structure 103 are disposed between the active layer 102 and the substrate 101, and the first polarization structure 104 and the second polarization structure 103 are in the direction
  • the second polarization structure disposed between the substrate and the active layer in the present example may have a nano-sized grating pattern, which may be fabricated by a method such as nanoimprinting or laser direct structuring.
  • the second polarization structure may be a metal wire grid structure.
  • the second polarization structure disposed inside the array substrate using the metal wire grid structure can replace the polarizing plate in the liquid crystal display panel, thereby not only reducing the thickness of the display panel, but also eliminating the polarization attached to the display panel manufacturing process. Board process. It should be noted that when the second polarization structure is a metal nanostructure, an insulating layer should be disposed between the first polarization structure and the second polarization structure.
  • the second polarization structure 103 may also be formed in the form of a polarizing film layer.
  • the present embodiment provides an array substrate.
  • the array substrate includes a buffer layer 105 in addition to the same portion as the first embodiment. That is, unlike FIG. 2b, the buffer layer 105 is disposed on the buffer layer 105.
  • the first polarization structure 104 is between the active layer 102.
  • the material of the buffer layer may be an oxide, a nitride or an oxynitride or the like. It should be noted that the embodiment is described by taking the first polarization structure between the substrate and the active layer as an example. As shown in FIG.
  • the buffer layer 105 has the same shape and size as the patterns of the first polarization structure 104 and the active layer 102, that is, the buffer layer 105 and the first polarization structure 104 and the active layer 102 can be formed by a one-step patterning process. A pattern having the same shape and size.
  • the buffer layer 105 is an insulating buffer layer, which can insulate the active layer 102 and the first polarization structure 104 on the one hand, and crystallize the active layer 102 formed on the buffer layer 105 on the other hand. better.
  • the second polarizing structure 103 may not be included in the array substrate in this embodiment, or the second polarizing structure 103 in this embodiment may also be disposed at a position as shown in FIG. 2c.
  • This embodiment provides a method for manufacturing an array substrate, as shown in FIG. 3, including the following steps.
  • the semiconductor layer is formed on the side of the polarizing layer away from the substrate, and the embodiment includes but is not limited thereto.
  • the semiconductor layer may also be formed on the side of the substrate away from the polarizing layer, but the embodiment is described by taking the semiconductor layer on the side of the polarizing layer away from the substrate.
  • the polarizing layer and the semiconductor layer can be patterned by a single patterning process, the patterned polarizing layer forms a first polarization structure, and the patterned semiconductor layer forms an active layer.
  • this embodiment eliminates the step of separately patterning the polarizing layer to form the first polarizing structure as compared to the general patterning process step.
  • the embodiment is not limited thereto, and the polarizing layer and the semiconductor layer may also be patterned stepwise.
  • the present embodiment implements an 8-step patterning process, which eliminates the need to fabricate a mask of the first polarization structure, thereby saving cost and improving yield.
  • Figures 5a-5j show the structure of the various stages in the production process.
  • an insulating layer 106, a polarizing layer 1041, a buffer layer 105, and a semiconductor layer 1021 are sequentially formed on the substrate 101.
  • the substrate 101 may be made of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. Made of one or more materials.
  • the polarizing layer 1041 is a full-surface polarizing layer formed on the substrate 101.
  • the polarizing layer 1041 forms a grating pattern by nanoimprinting.
  • nanoimprint technology uses a template to transfer a pattern onto a corresponding substrate.
  • the transferred medium is usually a thin layer of polymer film, which is hardened by hot pressing or irradiation to retain the transfer.
  • the nanoimprint template is pre-made according to a grating pattern consisting of parallel-arranged slits required for polarization, and the template can be made of quartz, glass or plastic.
  • This embodiment is not limited to the method of nanoimprinting, and a method such as a laser direct structuring technique can also be employed.
  • the grating pattern of the polarizing layer 1041 is a slit arranged in parallel, and light extending in a direction substantially perpendicular to the slit can be transmitted.
  • forming the semiconductor layer 1021 on the polarizing layer 1041 includes: depositing an amorphous silicon layer on the polarizing layer 1041, and crystallizing the amorphous silicon layer to form a polysilicon layer by means of excimer laser annealing.
  • the semiconductor layer 1021 of the embodiment is polysilicon.
  • the method of crystallizing the amorphous silicon layer to form the polysilicon layer may also be a metal induced crystallization process, a selective laser sintering process, a continuous lateral solidification process, or the like.
  • a metal oxide semiconductor active layer or the like may also be included in accordance with an embodiment of the present disclosure.
  • FIG. 5b is a schematic diagram of an array substrate forming stage provided by another example of the embodiment.
  • a second polarization structure 103 may be formed on a side of the substrate 101 away from the polarizing layer 1041.
  • the second polarization structure 103 is substantially perpendicular to the polarization direction of the polarization layer 1041.
  • the direction of the linearly polarized light emitted from the second polarizing structure 103 is substantially parallel to the slit extending direction in the grating pattern of the polarizing layer 1041, so that the polarizing layer 1041 cannot pass.
  • the cooperation of the polarizing layer 1041 and the second polarizing structure 103 serves as a good light blocking effect, and the backlight of the second polarizing structure 103 away from the substrate 101 is light-injected into the active layer 102 to prevent the backlight from illuminating the active layer. 102.
  • the liquid crystal display panel is taken as an example in this embodiment, and is not limited thereto.
  • a second polarization structure may be attached to one side of the substrate, or a second polarization structure having a nano-sized grating pattern may be formed on one side of the substrate by nanoimprinting or the like.
  • the second polarization structure is formed on the side of the substrate away from the polarizing layer, but is not limited thereto.
  • the second polarization structure may also be formed on the same side of the substrate as the polarizing layer, and formed between the active layer and the substrate, and the order of the polarizing layer and the second polarizing structure in the direction may be changed.
  • the second polarizing structure and the polarizing layer are formed on the same side of the substrate, and a metal material is also used, it is also necessary to form an insulating layer between the second polarizing structure and the polarizing layer. Since the polarization directions of the polarizing layer and the second polarization structure are substantially perpendicular, the combination of the two can function to block light.
  • 5c-5j are schematic diagrams each including a second polarization structure on the array substrate, and the second polarization structure is located on a side of the substrate away from the polarization layer, but is not limited thereto.
  • the array substrate does not include the second polarization structure, or the second polarization structure is located on the side of the substrate facing the polarization layer. As shown in FIG.
  • the semiconductor layer 1021 and the polarizing layer 1041 are patterned using an active layer mask (Mask 1), for example, patterned by dry etching to form the active layer 102 and the first polarizing structure 104, That is, when the semiconductor layer 1021 is patterned, the polarizing layer 1041 of the lower portion of the active layer 102 formed after etching the semiconductor layer 1021 is left, and the exposed portion of the polarizing layer 1041 is etched away, and the remaining portion of the polarizing layer 1041 is A first polarization structure 104 is formed.
  • the etching method of this embodiment is not limited thereto, and a high-precision etching method such as laser etching may also be employed.
  • the material of the first polarizing structure 104 includes, for example, a metal or a resin containing a conductive substance.
  • the material of the first polarizing structure 104 may be the same as that of the general light shielding layer, including: molybdenum, aluminum, chromium or silver; or a resin layer containing a conductive material, the conductive material may be nanometer-scale
  • the metal wire includes silver wire, aluminum wire, etc., or a metal powder additive. This embodiment is not limited to the material of the first polarization structure 104, and may also be transparent or opaque with nanometer order. Non-conductive material.
  • the first polarization structure 104 forms a grating pattern, for example, by nanoimprinting.
  • the grating pattern of the first polarization structure 104 is a slit arranged in parallel, and the light extending substantially perpendicular to the slit may be transmitted, and the direction of the linearly polarized light emitted from the second polarization structure 103 and the grating pattern of the polarizing layer 1041
  • the slits extend in a substantially parallel direction, and therefore, the cooperation of the first polarization structure 104 and the second polarization structure 103 serves to block light incident on the active layer 102.
  • the method for fabricating the array substrate provided by the embodiment further includes: forming a buffer layer 105 between the first polarization structure 104 and the active layer 102, and at least the buffer layer 105 and the active layer 102 and the first polarization structure 104.
  • One is patterned in a single patterning process.
  • the present embodiment is described by taking the same shape and size of the buffer layer 105 and the patterns of the first polarization structure 104 and the active layer 102, that is, the buffer layer 105 and the first polarization structure 104 and the active layer.
  • 102 may form patterns having the same shape and size by a one-step patterning process.
  • the material of the buffer layer 105 may be an oxide, a nitride or an oxynitride or the like.
  • the buffer layer 105 can on the one hand insulate the active layer 102 and the first polarization structure 104, and on the other hand, can further effect the subsequent crystallization of the active layer 102 formed on the buffer layer 105.
  • a conductive layer formed thereon is patterned on the gate insulating layer 110 by a patterning process using a gate electrode mask (Mask 2) to form a gate electrode 111 and a common electrode line 118, and then an interlayer insulating layer is formed. 119.
  • the gate insulating layer 110 and the interlayer insulating layer 119 may be made of a material such as an oxide, a nitride or an oxynitride, and the gate electrode 111 may be any one or a combination of metal materials such as aluminum, copper, chromium, molybdenum, and titanium.
  • the alloy is not limited to this embodiment.
  • the gate structure in this embodiment is a double gate thin film transistor, but is not limited thereto, and may be a single gate thin film transistor.
  • the top-gate thin film transistor is taken as an example, and the first polarizing structure 104 is matched with the second polarizing structure 103 to shield the active layer 102 on the side of the substrate 111 close to the substrate 101, thereby forming a liquid crystal in the subsequent process.
  • the backlight of the side of the active layer 102 near the substrate 101 is not incident on the active layer 102 to prevent the backlight from illuminating the active layer 102 to generate a photo-current leakage current.
  • the disclosure is not limited thereto, and may be Bottom-gate thin film transistor.
  • the interlayer insulating layer 119 and the gate insulating layer 110 are formed by a patterning process using a contact hole mask (Mask 3) for connecting the source electrode 1131 and the drain electrode 1132 to the active layer 102. Hole 112.
  • a contact hole mask Mosk 3
  • a source electrode 1131 and a drain electrode 1132 are formed in the contact hole 112 by a patterning process using a source/drain electrode mask (Mask 4), and the source electrode 1131 and the drain electrode 1132 may be made of aluminum, copper, or the like.
  • the alloy of any one or a combination of metal materials such as chromium, molybdenum or titanium is not limited thereto.
  • the planarization layer 114 is processed by a patterning process to form via holes 1141 and via holes 1142 by using a planarization layer mask (Mask 5) for exposing the drain 1132 and the common electrode line 118 to expose the drain.
  • the pole 1132 is electrically connected to the subsequently formed pixel electrode 117, and the exposed common electrode line 118 is electrically connected to the subsequently formed common electrode 115.
  • the material of the planarization layer 114 may be an organic material such as polyimide or the like, and the embodiment is not limited thereto.
  • the common electrode 115 is formed on the indium tin oxide layer by a patterning process using a common electrode mask (Mask 6), and the material of the common electrode 115 is not limited to indium tin oxide.
  • the passivation layer 116 is processed to form via holes by a patterning process using a passivation mask (Mask 7) to expose the drain 1132.
  • the passivation layer 116 may be selected from materials such as oxides, nitrides, or oxynitrides, and the embodiment is not limited thereto.
  • the pixel electrode 117 is formed by a patterning process using a pixel electrode mask (Mask 8), and the pixel electrode 117 is electrically connected to the drain electrode 1132.
  • the pixel electrode 117 may be a material such as indium tin oxide. Not limited to this.
  • any other suitable flow and structure may be combined or substituted on the basis of the first polarization structure having polarization characteristics.
  • the second polarization structure 103 in addition to the second polarization structure 103 being formed on the lower surface side of the substrate 101, it may be formed on the upper surface side of the substrate 101. In this case, the corresponding changes in the production process are required, and will not be described here.
  • the embodiment provides a display panel including an array substrate without a second polarization structure, and a second polarization structure disposed on a side of the substrate away from the active layer, and a polarization direction of the first polarization structure and the second polarization structure. Substantially perpendicular, and the orthographic projections of the active layer and the first polarization structure on the substrate both fall within the orthographic projection of the second polarization structure on the substrate.
  • the second polarization structure in this embodiment serves as a polarizing plate on the side of the backlight in a general display panel.
  • the second polarization structure in this embodiment may be a polarizing plate, or may be a film layer having a nano-sized grating pattern similar to the first polarization structure, for example, may be a metal wire grid structure.
  • the second polarization structure in this embodiment adopts a metal wire grid structure
  • it can replace the general process of attaching a polarizing plate, and the thickness of the second polarization structure using the metal wire grid structure can reach a nanometer order.
  • the second polarizing structure is used instead of the bias
  • the display panel of the vibration plate has a thin thickness.
  • the embodiment provides a display panel.
  • the display panel includes an array substrate provided with a second polarization structure, and the second polarization structure can replace the polarizing plate of the display panel near the backlight side, thereby saving the process steps of attaching the polarizing plate. .
  • the second polarization structure in this embodiment may be a polarizing plate, or may be a film layer having a nano-sized grating pattern similar to the first polarization structure, for example, may be a metal wire grid structure.
  • the thickness of the second polarization structure can reach a nanometer order, and the second polarization structure is used instead of the polarization with respect to a display panel including a common polarizing plate.
  • the display panel of the board has a relatively thin thickness.
  • the embodiment provides a display device, including: any one of the above array substrates.
  • the display device is described by taking the above array substrate with a first polarization structure disposed between the substrate and the active layer, which can avoid the abnormal discharge phenomenon of the first polarization structure, and form the active layer by the one-step patterning process.
  • the first polarization structure reduces cost and increases yield.
  • the display device may be a liquid crystal display device, and the backlight is disposed on a side of the substrate away from the active layer.
  • the embodiment is not limited thereto, and may be an organic light emitting diode display device or the like.

Abstract

一种阵列基板及其制造方法、显示装置。该阵列基板包括：基板(101)、有源层(102)和第一偏振结构(104)，有源层(102)，设置于基板(101)上；第一偏振结构(104)，设置于有源层(102)的面向基板(101)的一侧，且第一偏振结构(104)在基板(101)上的正投影与有源层(102)在基板(101)上的正投影至少部分重叠。该第一偏振结构替代传统的金属遮光层，可以有效避免起遮光作用的第一偏振结构产生异常放电现象。

Description

阵列基板及其制造方法、显示面板以及显示装置
本申请要求于2016年11月14日递交的中国专利申请第201610999719.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一实施例涉及一种阵列基板及其制造方法、显示面板以及显示装置。
背景技术
现有产品以n型金属氧化物半导体(nMOS)低温多晶硅-液晶显示器(LTPS-LCD)为例，通常采用9步图案化工艺进行生产，一般在有源层形成之前，采用钼等金属材料作为遮光层形成在基板上。现有技术中遮光层是通过对形成在基板上的整面金属层图案化而形成的，而整面金属层的制作，容易产生异常放电现象。
发明内容
本公开的至少一实施例提供一种阵列基板及其制造方法、显示面板以及显示装置。
本公开的至少一实施例提供一种阵列基板。该阵列基板包括基板、有源层和第一偏振结构，有源层，设置于基板上；第一偏振结构，设置于有源层的面向基板的一侧，且第一偏振结构在基板上的正投影与有源层在基板上的正投影至少部分重叠。
例如，在本实施例一示例提供的阵列基板，第一偏振结构设置于基板与有源层之间。
例如，在本实施例一示例提供的阵列基板，有源层在基板上的正投影落入第一偏振结构在基板上的正投影内。
例如，在本实施例一示例提供的阵列基板，有源层和第一偏振结构在基板上的正投影大致完全重合。
例如，在本实施例一示例提供的阵列基板，第一偏振结构的厚度为50埃 -200埃。
例如，在本实施例一示例提供的阵列基板，还包括：
第二偏振结构，与基板层叠设置，且设置在有源层的面向基板的一侧，
其中，第一偏振结构与第二偏振结构的偏振方向大致垂直，有源层和第一偏振结构在基板上的正投影均落入第二偏振结构在基板上的正投影内。
例如，在本实施例一示例提供的阵列基板，第二偏振结构设置于基板与有源层之间。
例如，在本实施例一示例提供的阵列基板，第二偏振结构具有纳米尺寸的光栅图案。
例如，在本实施例一示例提供的阵列基板，第一偏振结构的材料包括金属或含有导电物质的树脂。
例如，在本实施例一示例提供的阵列基板，第一偏振结构具有纳米尺寸的光栅图案。
例如，在本实施例一示例提供的阵列基板，还包括：缓冲层，设置于第一偏振结构与有源层之间。
本公开的至少一实施例提供一种阵列基板的制造方法，包括：在基板上形成偏振层；在基板上形成半导体层；将偏振层和半导体层图案化，被图案化的半导体层形成有源层，被图案化的偏振层形成第一偏振结构，且第一偏振结构在基板上的正投影与有源层在基板上的正投影至少部分重叠。
例如，在本实施例一示例提供的阵列基板的制造方法，半导体层形成在偏振层远离基板的一侧。
例如，在本实施例一示例提供的阵列基板的制造方法，利用一次图案化工艺将偏振层和半导体层图案化。
例如，在本实施例一示例提供的阵列基板的制造方法，第一偏振结构的厚度为50埃-200埃。
例如，在本实施例一示例提供的阵列基板的制造方法，第一偏振结构的材料包括金属或含有导电物质的树脂。
例如，在本实施例一示例提供的阵列基板的制造方法，第一偏振结构具有纳米尺寸的光栅图案。
例如，在本实施例一示例提供的阵列基板的制造方法，通过纳米压印方法形成具有纳米尺寸的光栅图案的第一偏振结构。
例如，在本实施例一示例提供的阵列基板的制造方法，还包括：在第一偏振结构与有源层之间形成缓冲层，缓冲层与有源层和第一偏振结构的至少之一在一次图案化工艺中被图案化。
例如，在本实施例一示例提供的阵列基板的制造方法，还包括：
在有源层的面向基板的一侧形成第二偏振结构，
其中，第一偏振结构与第二偏振结构的偏振方向大致垂直，且有源层和第一偏振结构在基板上的正投影均落入第二偏振结构在基板上的正投影内。
例如，在本实施例一示例提供的阵列基板的制造方法，第二偏振结构形成在有源层与基板之间。
例如，在本实施例一示例提供的阵列基板的制造方法，通过纳米压印方法形成第二偏振结构，且第二偏振结构具有纳米尺寸光栅图案。
本公开的至少一实施例提供一种显示面板，包括上述部分不包括第二偏振结构的示例中的阵列基板，以及设置在有源层的面向基板的一侧的第二偏振结构，
其中，第一偏振结构与第二偏振结构的偏振方向大致垂直，且有源层和第一偏振结构在基板上的正投影均落入第二偏振结构在基板上的正投影内。
本公开的至少一实施例提供一种显示面板，包括上述包括第二偏振结构的阵列基板。
本公开的至少一实施例提供一种显示装置，包括上述任一种阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板制造工艺中图案化工艺流程图；
图2a为本公开一实施例一示例提供的一种阵列基板示意图；
图2b为本公开一实施例另一示例提供的一种阵列基板示意图；
图2c为本公开一实施例另一示例提供的一种阵列基板示意图；
图2d为本公开另一实施例提供的一种阵列基板示意图；
图3为本公开一实施例提供的一种阵列基板制造方法示意图；
图4为本公开一实施例提供的一种阵列基板制造图案化工艺流程图；
图5a-5j为本公开一实施例提供的一种阵列基板各步图案化工艺后截面示意图。
附图标记：101-基板；102-有源层；1021-半导体层；103-第二偏振结构；104-第一偏振结构；1041-偏振层；105-缓冲层；106-绝缘层；110-栅绝缘层；111-栅极；112-接触孔；1131-源极；1132-漏极；114平坦化层；1141-过孔；1142-过孔；115-公共电极；116-钝化层；117-像素电极；118-公共电极线；119-层间绝缘层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种阵列基板制造工艺中图案化工艺流程图。如图1所示，以n型金属氧化物半导体(nMOS)低温多晶硅-液晶显示器(LTPS-LCD)为例，包括：基板、遮光层、缓冲层、有源层、栅绝缘层、栅电极、层间绝缘层、源漏电极、平坦化层、公共电极、钝化层和像素电极。为了制作此阵列基板，通常需要利用9张掩膜板进行9次构图工艺，分别是：
S01：利用遮光层掩膜板(Mask 1)通过构图工艺形成遮光层；
S02：利用有源层掩膜板(Mask 2)通过构图工艺对半导体层进行刻蚀形成有源层；
S03：利用栅电极掩膜板(Mask 3)通过构图工艺形成栅电极；
S04：利用接触孔掩膜板(Mask 4)通过构图工艺形成用于连接源漏电极与有源层的接触孔；
S05：利用源漏电极掩膜板(Mask 5)通过构图工艺形成源/漏电极；
S06：利用平坦化层掩膜板(Mask 6)通过构图工艺对平坦化层处理形成过孔，用以露出漏极和公共电极线；
S07：利用公共电极掩膜板(Mask 7)通过构图工艺形成公共电极；
S08：利用钝化层掩膜板(Mask 8)通过构图工艺对钝化层处理形成过孔，用以露出漏极；
S09：利用像素电极掩膜板(Mask 9)通过构图工艺形成像素电极，使像素电极与漏极电连接。
在步骤S01中利用遮光层掩膜板(Mask 1)通过构图工艺形成遮光层。一方面，采用钼等金属材料在基板上形成整面遮光层，很容易产生异常放电现象。并且针对不同产品中的每个产品都需要一块掩膜板，对遮光层采用大面积湿刻的方法进行图案化刻蚀，刻蚀后的遮光层的尺寸一般大于后续形成的有源层尺寸，并且很难与有源层同时图案化形成。另一方面，遮光层的厚度和坡度角也会影响后续有源层晶化的效果。
本公开至少一个实施例提供了一种阵列基板，该阵列基板包括基板、有源层和第一偏振结构，有源层，设置于基板上；第一偏振结构，设置于有源层的面向基板的一侧，且第一偏振结构在基板上的正投影与有源层在基板上的正投影至少部分重叠。本实施例提供的阵列基板在应用到例如液晶显示面板时，其中的第一偏振结构的偏振方向与液晶显示面板中的偏振板的偏振方向大致垂直，以保证第一偏振结构与偏振板的结合可以起到遮光效果，从而使有源层靠近基板的一侧的背光源无光线射入有源层，以避免背光源照射有源层产生光生漏电流。本实施例采用第一偏振结构替代传统的金属遮光层，可以有效避免起遮光作用的第一偏振结构产生异常放电现象。第一偏振结构的偏振方向与偏振板的偏振方向大致垂直。这里“大致垂直”是指严格垂直和近似垂直，保证第一偏振结构和偏振板的结合可以起到遮光效果。
本公开的至少一实施例提供一种阵列基板的制造方法，包括：在基板上形成偏振层；在基板上形成半导体层；将偏振层和半导体层图案化，被图案化的半导体层形成有源层，被图案化的偏振层形成第一偏振结构，且第一偏振结构 在基板上的正投影与有源层在基板上的正投影至少部分重叠。在该阵列基板的制造方法中由于利用偏振层形成第一偏振结构，所形成的第一偏振结构厚度较薄，可以避免因第一偏振结构的厚度和坡度角引起形成在第一偏振结构上的有源层后续的晶化不良。
本公开的至少一实施例提供一种显示装置，包括上述任一种阵列基板。该显示装置采用上述阵列基板，可以避免有源层被光照射产生光生漏电流，提升了良率。
本公开的至少一实施例提供一种显示面板。
以下通过几个实施例对阵列基板及其制造方法、显示面板以及显示装置予以说明。
实施例一
本公开实施例提供了一种阵列基板，图2a为本公开一实施例的一示例提供的阵列基板的示意图，如图2a所示，阵列基板包括：基板101、有源层102和第一偏振结构104。有源层102，设置于基板101上；第一偏振结构104，设置于有源层102的面向基板101的一侧，且第一偏振结构104在基板101上的正投影与有源层102在基板101上的正投影至少部分重叠。
需要说明的是，第一偏振结构设置于有源层的面向基板的一侧可以包括：第一偏振结构设置于有源层和基板之间，或者，第一偏振结构设置于基板远离有源层的一侧。本示例以第一偏振结构设置于基板与有源层之间为例进行描述。
例如，图2b为本公开一实施例的另一示例提供的阵列基板的示意图，如图2b所示，在有源层102的面向基板101的一侧设置有第二偏振结构103，第一偏振结构104与第二偏振结构103的偏振方向大致垂直，有源层102和第一偏振结构104在基板101上的正投影均落入第二偏振结构103在基板101上的正投影内。
例如，基板101面向有源层102一侧的第一偏振结构104的偏振方向与基板101远离第一偏振结构104一侧的第二偏振结构103的偏振方向大致垂直，当光源从第二偏振结构103远离基板101的一侧入射时，第二偏振结构103吸收了与其透光轴大致垂直方向的光，因此从第二偏振结构103出射的光是与第二偏振结构103的偏振方向相同的线偏振光。当该线偏振光透过基板101入射到第一偏振结构104时，由于第一偏振结构104的偏振方向与第二偏振结构103 的偏振方向大致垂直，该线偏振光的偏振方向与第一偏振结构104的偏振方向大致垂直，该线偏振光不能通过第一偏振结构104。因此，第一偏振结构104与第二偏振结构103的配合起到了良好的遮光效果，第二偏振结构103远离基板101的一侧的背光源无光线射入有源层102，以避免背光照射有源层102而产生光生漏电流，从而提高显示质量。需要说明的是，本实施例以液晶显示面板为例，并不限于此。
例如，如图2b所示，有源层102在基板101上的正投影落入第一偏振结构104在基板101上的正投影内，且有源层102和第一偏振结构104在基板101上的正投影均落入第二偏振结构103在基板101上的正投影内。例如，有源层102和第一偏振结构104在基板上101的正投影完全重合，如图2b所示，第一偏振结构104的图案与有源层102的图案的形状与尺寸相同，彼此重叠，即第一偏振结构104与有源层102可以通过一步图案化工艺形成具有相同形状与尺寸的图案。与一般的图案化工艺流程相比，利用一步图案化工艺形成第一偏振结构104与有源层102，可以有效减少单独对第一偏振结构图案化的步骤，从而节省成本并提高了良率。
例如，当背光光源入射到第二偏振结构103时，与第二偏振结构103的透光轴平行方向的光可以通过，因此从第二偏振结构103出射的光是偏振方向与第二偏振结构103的偏振方向相同的线偏振光。当该线偏振光入射到第一偏振结构104时，由于第一偏振结构104的偏振方向与第二偏振结构103的偏振方向大致垂直，该线偏振光的偏振方向与第一偏振结构104的偏振方向大致垂直，该线偏振光不能通过第一偏振结构104，因此，第一偏振结构104与第二偏振结构103的配合用于遮挡入射到有源层102的光。一般利用材料的不透明性进行遮光的遮光层，为了达到良好的遮光效果，其厚度往往约几百～几千埃。这种较厚的遮光层在图案化过程中会产生一定的坡度角，影响后续有源层的晶化效果。而本实施例中具有偏振特性的第一偏振结构104的厚度例如为50埃-200埃，相比于一般的遮光层减少了厚度方面的影响，也避免了坡度角的产生，从而可以保证后续有源层102的晶化效果。
例如，第一偏振结构104的材料例如包括金属或含有导电物质的树脂。该第一偏振结构104的材料可以与一般的遮光层选用的金属材料相同，包括：钼、铝、铬或银等；也可以是含有导电物质的树脂层，该导电物质可以为纳米级的金属丝线，包括银丝、铝线等，或者金属粉末状的添加剂等。本实施例对第一 偏振结构104的材料并不限定，也可以是具有纳米级的透明或不透明的非导电材料。
例如，第一偏振结构104具有纳米尺寸的光栅图案，可以通过纳米压印或者激光直接成型技术等方法制作而成，本实施例不限于此。例如，第一偏振结构104的光栅图案的周期可以为60nm-300nm。例如，第一偏振结构104的光栅图案为平行排列的狭缝，大致垂直狭缝延伸方向的光可以透过，从第二偏振结构103出射的线偏振光的方向与第一偏振结构104的光栅图案中狭缝的延伸方向大致平行，从而不能通过第一偏振结构104，因此，第一偏振结构104与第二偏振结构103的配合用于遮挡入射到有源层102中的光线。
例如，第二偏振结构103也可以具有纳米尺寸的光栅图案，可以通过纳米压印或者激光直接成型技术等方法制作而成，本实施例不限于此。例如，第二偏振结构103可以为金属线栅结构。采用金属线栅结构的第二偏振结构103可以替代液晶显示面板中的偏振板，既可以起到减薄显示面板厚度的效果，又可以省去显示面板制作工艺中贴附偏振板的工艺。
在上述实施例中，第二偏振结构103设置在基板101的远离有源层102的一侧，但根据本公开的实施例并不限于此。图2c为本公开一实施例提供的另一示例中的阵列基板的示意图。例如，如图2c所示，第二偏振结构103设置于基板101与有源层102之间。本实施例不限于此，第二偏振结构103可以与有源层102设置在基板101的同一侧，只需要第二偏振结构103和第一偏振结构104均设置在有源层102靠近基板101的一侧即可。例如，在垂直于基板101的方向上，第一偏振结构104和第二偏振结构103设置在有源层102和基板101之间，并且第一偏振结构104和第二偏振结构103在该方向上的次序可以变换。例如，本示例中设置在基板与有源层之间的第二偏振结构可以具有纳米尺寸的光栅图案，可以通过纳米压印或者激光直接成型技术等方法制作而成。例如，第二偏振结构可以为金属线栅结构。采用金属线栅结构的设置在阵列基板内部的第二偏振结构可以替代液晶显示面板中的偏振板，既可以起到减薄显示面板厚度的效果，又可以省去显示面板制作工艺中贴附偏振板的工艺。需要说明的是，当第二偏振结构为金属纳米结构时，在第一偏振结构与第二偏振结构之间还应设置绝缘层。
在这些结构中，由于第一偏振结构104和第二偏振结构103的偏振方向大致垂直，在二者的结合作用下，可以起到遮挡光线的作用。例如，在这些结构 中，第二偏振结构103还可以以偏光膜层的形式形成。
实施例二
本实施例提供了一种阵列基板，如图2d所示，该阵列基板除了与实施例一相同的部分外，还包括缓冲层105，即，与图2b不同的是：该缓冲层105设置于第一偏振结构104与有源层102之间。缓冲层的材料可以选用氧化物、氮化物或氧氮化合物等。需要说明的是，本实施例以第一偏振结构设置于基板与有源层之间为例进行描述。如图2d所示，缓冲层105与第一偏振结构104以及有源层102的图案的形状与尺寸相同，即缓冲层105与第一偏振结构104以及有源层102可通过一步图案化工艺形成具有相同形状与尺寸的图案。例如，缓冲层105为绝缘缓冲层，一方面可以对有源层102和第一偏振结构104起到绝缘作用，另一方面能够使后续在缓冲层105上形成的有源层102晶化的效果更好。
例如，本实施例中的阵列基板中也可以不包括第二偏振结构103，或者本实施例中的第二偏振结构103也可以设置为如图2c所示的位置。
实施例三
本实施例提供了一种阵列基板的制造方法，如图3所示，包括如下步骤。
S1：在基板上形成偏振层；
S2：在基板上形成半导体层；
S3：将偏振层和半导体层图案化，被图案化的半导体层形成有源层，被图案化的偏振层形成第一偏振结构，且第一偏振结构在基板上的正投影与有源层在基板上的正投影至少部分重叠。
例如，半导体层形成在偏振层远离基板的一侧，本实施例包括但不限于此。例如，半导体层还可以形成在基板远离偏振层的一侧，但本实施例以半导体层形成在偏振层远离基板的一侧为例进行描述。
采用本实施例提供的阵列基板的制造方法，例如，可以利用一次图案化工艺将偏振层和半导体层图案化，被图案化的偏振层形成第一偏振结构，被图案化的半导体层形成有源层。因此，本实施例与一般图案化工艺步骤相比，省去了单独图案化偏振层形成第一偏振结构的步骤。本实施例不限于此，偏振层和半导体层也可以分步图案化。
如图4所示，本实施例实现了8步图案化工艺，无需制作第一偏振结构的掩膜板，可以节省成本并提高良率。
S01：利用有源层掩膜板(Mask 1)通过一次图案化工艺将偏振层和半导体层图案化，被图案化的偏振层形成第一偏振结构，被图案化的半导体层形成有源层；
S02：利用栅电极掩膜板(Mask 2)通过构图工艺形成栅电极；
S03：利用接触孔掩膜板(Mask 3)通过构图工艺，刻蚀层间绝缘层和栅绝缘层，形成用于连接源漏电极与有源层的接触孔；
S04：利用源漏电极掩膜板(Mask 4)通过构图工艺在接触孔形成源漏电极；
S05：利用平坦化层掩膜板(Mask 5)通过构图工艺对平坦化层处理形成过孔，用以露出漏极和公共电极线；
S06：利用公共电极掩膜板(Mask 6)通过构图工艺形成公共电极；
S07：利用钝化层掩膜板(Mask 7)通过构图工艺对钝化层处理形成过孔，用以露出漏极；
S08：利用像素电极掩膜板(Mask 8)通过构图工艺形成像素电极，使像素电极与漏极电连接。
图5a-5j示出了制作流程中各个阶段的结构示意图。如图5a所示，在基板101上依次形成绝缘层106、偏振层1041、缓冲层105和半导体层1021。例如，基板101可以由玻璃、聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯中的一种或多种材料制成。偏振层1041是形成于基板101上的整面偏振层。
例如，偏振层1041采用纳米压印的方法形成光栅图案。例如，纳米压印技术是通过模板，将图形转移到相应的衬底上，转移的媒介通常是一层很薄的聚合物膜，通过热压或者辐照等方法使其结构硬化从而保留下转移的图形。该纳米压印模板预先根据偏振所需的平行排列的狭缝组成的光栅图案来制作，该模板可以采用石英、玻璃或塑料来制作。本实施例不限于纳米压印的方法，还可以采用激光直接成型技术等方法。例如，偏振层1041的光栅图案为平行排列的狭缝，大致垂直狭缝延伸方向的光可以透过。
例如，偏振层1041上形成半导体层1021包括：在偏振层1041上沉积非晶硅层，利用准分子激光退火的方式将非晶硅层晶化形成多晶硅层，本实施例的半导体层1021为多晶硅层。将非晶硅层晶化形成多晶硅层的方法还可以是金属诱发结晶工艺、选择性激光烧结、连续横向固化工艺等方法，本实施例并 不限定。例如，根据本公开的实施例还可以包括金属氧化物半导体有源层等。
例如，图5b为本实施例的另一示例提供的阵列基板形成阶段示意图，如图5b所示，与图5a不同的是：可以在基板101远离偏振层1041的一侧形成第二偏振结构103，第二偏振结构103与偏振层1041的偏振方向大致垂直。从第二偏振结构103出射的线偏振光的方向与偏振层1041的光栅图案中的狭缝延伸方向大致平行，从而不能通过偏振层1041。因此，偏振层1041与第二偏振结构103的配合起到了良好的遮光效果，第二偏振结构103远离基板101的一侧的背光源无光线射入有源层102，以避免背光照射有源层102。需要说明的是，本实施例以液晶显示面板为例，不限于此。
例如，可以在基板的一侧贴附第二偏振结构，也可以在基板的一侧通过纳米压印等方式形成具纳米尺寸光栅图案的第二偏振结构。图5b中以第二偏振结构形成在基板远离偏振层的一侧为例，但不限于此。例如，第二偏振结构也可以与偏振层形成在基板的同一侧，且形成在有源层与基板之间，并且偏振层和第二偏振结构在该方向上的次序可以变换。当第二偏振结构与偏振层形成在基板的同一侧，且也采用金属材料时，还需要在第二偏振结构与偏振层之间形成绝缘层。由于偏光层和第二偏振结构的偏振方向大致垂直，在二者的结合作用下，可以起到遮挡光线的作用。
图5c-图5j为均以阵列基板上包括第二偏振结构为例的示意图，且第二偏振结构位于基板远离偏振层的一侧，但不限于此。例如，还可以是阵列基板上不包括第二偏振结构，或者，第二偏振结构位于基板面向偏振层的一侧。如图5c所示，使用有源层掩膜板(Mask 1)对半导体层1021和偏振层1041进行图案化，例如采用干法刻蚀一次图案化形成有源层102和第一偏振结构104，即在对半导体层1021进行图案化时，将刻蚀半导体层1021之后形成的有源层102下部的偏振层1041保留，裸露部分的偏振层1041刻蚀掉，而保留的那部分偏振层1041即形成第一偏振结构104。本实施例的刻蚀方法不限于此，还可以采用激光刻蚀等高精度刻蚀方法。
例如，第一偏振结构104的材料例如包括金属或含有导电物质的树脂。该第一偏振结构104的材料可以与一般的遮光层选用的金属材料相同，包括：钼、铝、铬或银等都可以；也可以是含有导电物质的树脂层，该导电物质可以为纳米级的金属丝线，包括银丝、铝线等，或者金属粉末状的添加剂等。本实施例对第一偏振结构104的材料并不限定，也可以是具有纳米级的透明或不透明的 非导电材料。
例如，第一偏振结构104例如采用纳米压印的方法形成光栅图案。例如，第一偏振结构104的光栅图案为平行排列的狭缝，大致垂直狭缝延伸方向的光可以透过，从第二偏振结构103出射的线偏振光的方向与偏振层1041的光栅图案中的狭缝延伸方向大致平行，因此，第一偏振结构104与第二偏振结构103的配合用于遮挡入射到有源层102的光。
例如，本实施例提供的阵列基板的制造方法还包括：在第一偏振结构104与有源层102之间形成缓冲层105，缓冲层105与有源层102和第一偏振结构104的至少之一在一次图案化工艺中被图案化。如图5c所示，本实施例以缓冲层105与第一偏振结构104以及有源层102的图案的形状与尺寸相同为例进行描述，即缓冲层105与第一偏振结构104以及有源层102可通过一步图案化工艺形成具有相同形状与尺寸的图案。缓冲层105的材料可以选用氧化物、氮化物或氧氮化合物等。缓冲层105一方面可以对有源层102和第一偏振结构104起到绝缘作用，另一方面能够使后续在缓冲层105上形成的有源层102晶化的效果更好。
如图5d所示，利用栅电极掩膜板(Mask 2)通过构图工艺在栅绝缘层110上将其上形成的导电层图案化形成栅电极111和公共电极线118，随后形成层间绝缘层119。栅绝缘层110和层间绝缘层119可以选用氧化物、氮化物或氮氧化合物等材料，栅电极111可以采用铝、铜、铬、钼、钛等金属材料中的任一种或者几种组合的合金，本实施例不限于此。本实施例中的栅极结构是双栅型薄膜晶体管，但并不限于此，还可以是单栅型薄膜晶体管。并且本实施例以顶栅型薄膜晶体管为例，利用第一偏振结构104与第二偏振结构103配合，对栅极111靠近基板101一侧的有源层102进行遮光，从而使得在后续形成液晶盒后，有源层102靠近基板101的一侧的背光源无光线射入有源层102，以避免背光源照射有源层102产生光生漏电流，但本公开并不限于此，也可以是底栅型薄膜晶体管。
如图5e所示，利用接触孔掩膜板(Mask 3)通过构图工艺，刻蚀层间绝缘层119和栅绝缘层110形成用于连接源电极1131和漏电极1132与有源层102的接触孔112。
如图5f所示，利用源漏电极掩膜板(Mask 4)通过构图工艺在接触孔112形成源电极1131和漏电极1132，源电极1131和漏电极1132可以采用铝、铜、 铬、钼、钛等金属材料中的任一种或者几种组合的合金，本实施例不限于此。
如图5g所示，利用平坦化层掩膜板(Mask 5)通过构图工艺对平坦化层114处理形成过孔1141和过孔1142，用以露出漏极1132和公共电极线118，露出的漏极1132与后续形成的像素电极117电连接，露出的公共电极线118与后续形成的公共电极115电连接。平坦化层114的材料可以是有机材料，例如聚酰亚胺等材料，本实施例不限于此。
如图5h所示，利用公共电极掩膜板(Mask 6)通过构图工艺对铟锡氧化层形成公共电极115，公共电极115的材料不限于铟锡氧化物。
如图5i所示，利用钝化层掩膜板(Mask 7)通过构图工艺对钝化层116处理形成过孔，用以露出漏极1132。钝化层116可以选用氧化物、氮化物或氮氧化合物等材料，本实施例不限于此。
如图5j所示，利用像素电极掩膜板(Mask 8)通过构图工艺形成像素电极117，使像素电极117与漏极1132电连接，像素电极117可以是铟锡氧化物等材料，本实施例不限于此。
需要说明的是，上述的具体流程与结构仅仅是根据本公开的一些示例性流程和结构。在利用具有偏振特性的第一偏振结构的基础上，可以结合或替换其他任何合适的流程和结构。例如，如实施例一中所述，除了第二偏振结构103形成于基板101的下表面侧之外，其还可以形成在基板101的上表面侧。在这种情况下，需要制作流程的相应改变，这里不再赘述。
实施例四
本实施例提供一种显示面板，显示面板包括没有设置第二偏振结构的阵列基板，以及设置在基板远离有源层一侧的第二偏振结构，第一偏振结构与第二偏振结构的偏振方向大致垂直，且有源层和第一偏振结构在基板上的正投影均落入第二偏振结构在基板上的正投影内。
本实施例中的第二偏振结构起到了一般的显示面板中靠近背光源一侧的偏振板的效果。例如，本实施例中的第二偏振结构可以是偏振板，也可以是与第一偏振结构相似的具有纳米尺寸光栅图案的膜层，例如，可以为金属线栅结构。
例如，本实施例中的第二偏振结构采用金属线栅结构时，可以替代一般的贴附偏振板的工艺，并且，采用金属线栅结构的第二偏振结构的厚度可以达到纳米量级，相对于包括普通的偏振板的显示面板，采用该第二偏振结构代替偏 振板的显示面板具有较薄的厚度。
实施例五
本实施例提供一种显示面板，显示面板包括设置有第二偏振结构的阵列基板，且该第二偏振结构可以替代显示面板靠近背光源一侧的偏振板，节省了贴附偏振板的工艺步骤。
例如，本实施例中的第二偏振结构可以是偏振板，也可以是与第一偏振结构相似的具有纳米尺寸光栅图案的膜层，例如，可以为金属线栅结构。
例如，本实施例中的第二偏振结构采用金属线栅结构时，该第二偏振结构的厚度可以达到纳米量级，相对于包括普通的偏振板的显示面板，采用该第二偏振结构代替偏振板的显示面板具有较薄的厚度。
实施例六
本实施例提供一种显示装置，包括：上述任一种阵列基板。该显示装置采用上述的阵列基板以第一偏振结构设置于基板与有源层之间为例进行描述，既可以避免第一偏振结构产生异常放电现象，又因为一步图案化工艺形成有源层和第一偏振结构，降低了成本并提升了良率。
例如，显示装置可以是液晶显示装置，背光源设置于基板远离有源层的一侧。本实施例不限于此，还可以是有机发光二极管显示装置等。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一标号代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种阵列基板，包括：
    基板；
    有源层，设置于所述基板上；
    第一偏振结构，设置于所述有源层的面向所述基板的一侧，且所述第一偏振结构在所述基板上的正投影与所述有源层在所述基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述第一偏振结构设置于所述基板与所述有源层之间。
  3. 根据权利要求1或2所述的阵列基板，其中，所述有源层在所述基板上的正投影落入所述第一偏振结构在所述基板上的正投影内。
  4. 根据权利要求3所述的阵列基板，其中，所述有源层和所述第一偏振结构在所述基板上的正投影大致完全重合。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，所述第一偏振结构的厚度为50埃-200埃。
  6. 根据权利要求1-5中任一项所述的阵列基板，其中，所述第一偏振结构的材料包括金属或含有导电物质的树脂。
  7. 根据权利要求1-6中任一项所述的阵列基板，其中，所述第一偏振结构具有纳米尺寸的光栅图案。
  8. 根据权利要求1-7中任一项所述的阵列基板，还包括：
    第二偏振结构，与所述基板层叠设置，且设置在所述有源层的面向所述基板的一侧，
    其中，所述第一偏振结构与所述第二偏振结构的偏振方向大致垂直，且所述有源层和所述第一偏振结构在所述基板上的正投影均落入所述第二偏振结构在所述基板上的正投影内。
  9. 根据权利要求8所述的阵列基板，其中，所述第二偏振结构设置于所述基板与所述有源层之间。
  10. 根据权利要求8或9所述的阵列基板，其中，所述第二偏振结构具有纳米尺寸的光栅图案。
  11. 根据权利要求1-10中任一项所述的阵列基板，还包括：
    缓冲层，设置于所述第一偏振结构与所述有源层之间。
  12. 一种阵列基板的制造方法，包括：
    在基板上形成偏振层；
    在所述基板上形成半导体层；
    将所述偏振层和所述半导体层图案化，被图案化的所述半导体层形成有源层，被图案化的所述偏振层形成第一偏振结构，且所述第一偏振结构在所述基板上的正投影与所述有源层在所述基板上的正投影至少部分重叠。
  13. 根据权利要求12所述的阵列基板的制造方法，其中，所述半导体层形成在所述偏振层远离所述基板的一侧。
  14. 根据权利要求13所述的阵列基板的制造方法，其中，利用一次图案化工艺将所述偏振层和所述半导体层图案化。
  15. 根据权利要求12-14中任一项所述的阵列基板的制造方法，其中，所述第一偏振结构的厚度为50埃-200埃。
  16. 根据权利要求12-15中任一项所述的阵列基板的制造方法，其中，所述第一偏振结构的材料包括金属或含有导电物质的树脂。
  17. 根据权利要求12-16中任一项所述的阵列基板的制造方法，其中，所述第一偏振结构具有纳米尺寸的光栅图案。
  18. 根据权利要求17所述的阵列基板的制造方法，其中，通过纳米压印方法形成所述具有纳米尺寸的光栅图案的所述第一偏振结构。
  19. 根据权利要求13或14所述的阵列基板的制造方法，还包括：
    在所述第一偏振结构与所述有源层之间形成缓冲层，所述缓冲层与所述有源层和所述第一偏振结构的至少之一在一次图案化工艺中被图案化。
  20. 根据权利要求12-19中任一项所述的阵列基板的制造方法，还包括：
    在所述有源层的面向所述基板的一侧形成第二偏振结构，
    其中，所述第一偏振结构与所述第二偏振结构的偏振方向大致垂直，且所述有源层和所述第一偏振结构在所述基板上的正投影均落入所述第二偏振结构在所述基板上的正投影内。
  21. 根据权利要求20所述的阵列基板的制造方法，其中，所述第二偏振结构形成在所述有源层与所述基板之间。
  22. 根据权利要求20或21所述的阵列基板的制造方法，其中，通过纳米压印方法形成所述第二偏振结构，且所述第二偏振结构具有纳米尺寸光栅图 案。
  23. 一种显示面板，包括权利要求1-7中任一项所述的阵列基板以及设置在所述有源层的面向所述基板的一侧的第二偏振结构，
    其中，所述第一偏振结构与所述第二偏振结构的偏振方向大致垂直，且所述有源层和所述第一偏振结构在所述基板上的正投影均落入所述第二偏振结构在所述基板上的正投影内。
  24. 一种显示面板，包括权利要求8-10中任一项所述的阵列基板。
  25. 一种显示装置，包括：如权利要求1-11中任一项所述的阵列基板。
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