WO2019174195A1 - 低温多晶硅、薄膜晶体管及阵列基板的制作方法 - Google Patents

低温多晶硅、薄膜晶体管及阵列基板的制作方法 Download PDF

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WO2019174195A1
WO2019174195A1 PCT/CN2018/103164 CN2018103164W WO2019174195A1 WO 2019174195 A1 WO2019174195 A1 WO 2019174195A1 CN 2018103164 W CN2018103164 W CN 2018103164W WO 2019174195 A1 WO2019174195 A1 WO 2019174195A1
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temperature polysilicon
layer
low
thin film
film transistor
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PCT/CN2018/103164
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US16/088,673 priority Critical patent/US10699905B2/en
Publication of WO2019174195A1 publication Critical patent/WO2019174195A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating low temperature polysilicon, a thin film transistor, and an array substrate.
  • Thin Film Transistor is the main driving component in current liquid crystal display (LCD) and Active Matrix Organic Light-Emitting Diode (AMOLED). Directly related to the display performance of flat panel display devices.
  • the thin film transistor has various structures, and the material of the thin film transistor for preparing the corresponding structure is also various. According to the material of the active layer, the thin film transistor can be classified into an amorphous silicon thin film transistor, a polysilicon thin film transistor, or the like.
  • a method of fabricating a polysilicon thin film transistor generally employs a method of fabricating low temperature polysilicon (LTPS), in which an amorphous silicon layer is usually formed by chemical vapor deposition (CVD), and the amorphous silicon layer is further subjected to crystallization treatment.
  • LTPS low temperature polysilicon
  • ELA excimer laser annealing
  • the amorphous silicon liquid When the amorphous silicon liquid is cooled, the amorphous silicon liquid gradually crystallizes depending on the crystal nucleus. A polysilicon layer is formed.
  • excimer laser annealing is mainly performed by laser irradiation and crystallization. The biggest defect of this crystallization is that the uniformity is poor and it is difficult to apply to large-sized panels.
  • the existing low-temperature polysilicon fabrication process is as shown in FIG. 1.
  • a buffer layer 20 is formed on the glass substrate 10 by chemical vapor deposition.
  • the buffer layer 20 may be a SiNx/SiO 2 double-layer structure or SiNx having a thickness of 1000 ⁇ to 2000 ⁇ . /SiNO/SiO 2 three-layer structure, then forming an amorphous silicon layer 30 having a thickness of 300 angstroms to 800 angstroms on the buffer layer 20 by chemical vapor deposition, and finally using an excimer laser annealing device at room temperature and atmospheric pressure, that is, the laser 40
  • the amorphous silicon layer 30 is subjected to laser annealing crystallization treatment to form a polysilicon layer.
  • Another object of the present invention is to provide a method for fabricating a low temperature polysilicon thin film transistor to enhance the crystallization effect of polycrystalline silicon.
  • a further object of the present invention is to provide a method for fabricating a low temperature polysilicon thin film transistor array substrate to enhance the crystallization effect of polysilicon.
  • the present invention provides a method for fabricating low temperature polysilicon, comprising:
  • the semipermeable membrane mask includes a light transmissive substrate and a patterned semipermeable membrane disposed on the surface of the substrate.
  • the patterned semi-permeable membrane corresponds to a non-silicon island region of the amorphous silicon layer.
  • the buffer layer has a thickness of 1000 angstroms to 2000 angstroms.
  • the buffer layer is a SiNx/SiO 2 double layer structure.
  • the buffer layer is a SiNx/SiNO/SiO 2 three-layer structure.
  • the amorphous silicon layer has a thickness of 300 angstroms to 800 angstroms.
  • the substrate is a light transmissive marble substrate.
  • the invention also provides a method for fabricating a low-temperature polysilicon thin film transistor, which is characterized in that the low-temperature polysilicon layer is fabricated by using the low-temperature polysilicon fabrication method described in any of the above.
  • the invention also provides a method for fabricating a low temperature polysilicon thin film transistor array substrate, and the low temperature polysilicon thin film transistor is fabricated by using the above low temperature polysilicon thin film transistor fabrication method.
  • the method for fabricating the low-temperature polysilicon, the thin film transistor and the array substrate of the invention can make the polycrystalline silicon have better crystallization effect, improve the electrical performance of the polysilicon thin film transistor, and at the same time improve the dry etching efficiency of the polysilicon layer, and release the production of polycrystalline silicon. Capacity.
  • FIG. 1 is a schematic view of a conventional low temperature polysilicon fabrication process
  • FIG. 2 is a schematic view showing a process of producing low-temperature polysilicon according to a preferred embodiment of the method for fabricating low-temperature polysilicon according to the present invention
  • FIG 3 is a schematic view showing the structure of a low-temperature polysilicon fabricated by a preferred embodiment of the low-temperature polysilicon fabrication method of the present invention.
  • FIG. 2 it is a schematic diagram of a low temperature polysilicon fabrication process according to a preferred embodiment of the low temperature polysilicon fabrication method of the present invention.
  • the low temperature polysilicon fabrication method of the present invention provides an annealing method for improving the crystal uniformity of the polysilicon layer, which mainly comprises:
  • a SiNx/SiO 2 double layer structure or SiNx/ having a thickness of 1000 ⁇ to 2000 ⁇ may be formed on the glass substrate, that is, the substrate 10 by chemical vapor deposition.
  • An amorphous silicon layer 30 is formed on the buffer layer 20; an amorphous silicon layer 30 may be deposited on the buffer layer 20 by chemical vapor deposition, and the amorphous silicon layer 30 may have a thickness of 300 angstroms to 800 angstroms.
  • the amorphous silicon layer 30 is subjected to an excimer laser annealing treatment under the shielding of the semipermeable membrane mask 50 to convert the amorphous silicon layer 30 into a polysilicon layer; an excimer laser is emitted by the laser 40, and then semi-transparent.
  • the amorphous silicon layer 30 is subjected to laser annealing under the occlusion of the film mask 50.
  • the semipermeable membrane mask 50 includes a light transmissive substrate 51 and a patterned semipermeable membrane 52 disposed on the surface of the substrate 51.
  • the semi-transmissive film mask 50 is the same as the conventional photolithographic mask design method.
  • the substrate 51 may be a light-transmissive marble substrate, and partially absorbs laser energy by the semi-permeable membrane 52, thereby generating illumination on the amorphous silicon layer 30. Temperature gradient.
  • the semipermeable membrane region on the semipermeable membrane mask 50 corresponds to the non-silicon island region of the active layer, and the non-semipermeable membrane of the semipermeable membrane mask 50 The region corresponds to the silicon island region of the active layer, that is, the patterned semi-permeable film 52 corresponds to the non-silicon island region of the amorphous silicon layer 30.
  • the semi-permeable membrane mask 50 full-open laser irradiation can be performed in the silicon island region, and the semi-transmissive film is annealed in other regions, so that the temperature of the silicon island region of the amorphous silicon layer 30 is greater than that of other regions.
  • the low-temperature polysilicon fabrication method of the present invention may further comprise the usual steps in the prior art, such as dehydrogenation treatment of the amorphous silicon layer, and details are not described herein again.
  • FIG. 3 is a schematic view showing the structure of a low-temperature polysilicon fabricated by a preferred embodiment of the low-temperature polysilicon fabrication method of the present invention, showing the amorphous silicon layer 30 on the substrate 10 and the buffer layer 20 shown in FIG. structure. Since the temperature in the silicon island region is greater than the temperature in other regions, the temperature gradient makes the silicon island region crystallize better, and the polysilicon 31 in the silicon island region is formed, which can improve the electrical properties of the polysilicon thin film transistor.
  • the polysilicon 32 in the non-silicon island region is formed, so that etching is easier, the dry etching efficiency of the polysilicon layer can be improved, and the production capacity of the polycrystalline silicon can be released.
  • the method for fabricating the low-temperature polysilicon, the thin film transistor and the array substrate of the invention can make the polycrystalline silicon have better crystallization effect, improve the electrical performance of the polysilicon thin film transistor, and at the same time improve the dry etching efficiency of the polysilicon layer, and release the production of polycrystalline silicon. Capacity.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明涉及一种低温多晶硅、薄膜晶体管及阵列基板的制作方法。该低温多晶硅制作方法包括：提供基板，在所述基板上形成缓冲层；在所述缓冲层上形成非晶硅层；在半透膜掩模板的遮挡下对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层转变为多晶硅层；所述半透膜掩模板包括透光的衬底和设于所述衬底表面的图案化的半透膜。本发明还提供了相应的低温多晶硅薄膜晶体管及阵列基板的制作方法。本发明的低温多晶硅、薄膜晶体管及阵列基板的制作方法可以使得多晶硅结晶效果更好，改善多晶硅薄膜晶体管的电性能，同时又能提升多晶硅层的干法刻蚀效率，释放生产制造多晶硅的产能。

Description

低温多晶硅、薄膜晶体管及阵列基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅、薄膜晶体管及阵列基板的制作方法。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是目前液晶显示装置(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode，AMOLED)中的主要驱动元件，直接关系平板显示装置的显示性能。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，根据有源层的材料不同，可以将薄膜晶体管分为非晶硅薄膜晶体管、多晶硅薄膜晶体管等类型。
多晶硅薄膜晶体管与非晶硅薄膜晶体管相比，具有更高的电子迁移率、更快的反应时间和更高的分辨率，目前已广泛应用于显示装置，作为驱动电路部分的开关元件。多晶硅薄膜晶体管的制作方法一般采用制作低温多晶硅(LTPS)的方法，其中通常采用化学气相沉积(CVD)形成非晶硅层，再对该非晶硅层进行结晶化处理。目前一般采用准分子激光退火(ELA)技术进行结晶化，非晶硅层被308纳米激光照射后熔化形成非晶硅液体，非晶硅液体冷却时，非晶硅液体依附晶核逐渐结晶生长而形成多晶硅层。目前的准分子激光退火主要还是整面性进行激光照射结晶，这种结晶最大的缺陷就是均一性较差，较难应用于大尺寸面板。
现有的低温多晶硅制作过程如图1所示，首先采用化学气相沉积法在玻璃基板10上形成缓冲层20，缓冲层20可以为厚度1000埃～2000埃的SiNx/SiO 2双层结构或SiNx/SiNO/SiO 2三层结构，然后采用化学气相沉积法在缓冲层20上形成厚度300埃～800埃的非晶硅层30，最后在室温和大气压下采用准分子激光退火设备也就是激光器40对非晶硅层30进行激光退火结晶化处理，形成多晶硅层。
发明内容
因此，本发明的目的在于提供一种低温多晶硅制作方法，提升多晶硅结晶效果。
本发明的另一目的在于提供一种低温多晶硅薄膜晶体管制作方法，提 升多晶硅结晶效果。
本发明的再一目的在于提供一种低温多晶硅薄膜晶体管阵列基板制作方法，提升多晶硅结晶效果。
为实现上述目的，本发明提供了一种低温多晶硅制作方法，包括：
提供基板，在所述基板上形成缓冲层；
在所述缓冲层上形成非晶硅层；
在半透膜掩模板的遮挡下对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层转变为多晶硅层；
所述半透膜掩模板包括透光的衬底和设于所述衬底表面的图案化的半透膜。
其中，所述图案化的半透膜对应于非晶硅层的非硅岛区。
其中，所述缓冲层厚度为1000埃～2000埃。
其中，所述缓冲层为SiNx/SiO 2双层结构。
其中，所述缓冲层为SiNx/SiNO/SiO 2三层结构。
其中，所述非晶硅层厚度为300埃～800埃。
其中，所述衬底为透光的大理石衬底。
本发明还提供了一种低温多晶硅薄膜晶体管制作方法，应用上述任一项所述的低温多晶硅制作方法制作低温多晶硅层。
本发明还提供了一种低温多晶硅薄膜晶体管阵列基板制作方法，应用上述的低温多晶硅薄膜晶体管制作方法制作低温多晶硅薄膜晶体管。
综上，本发明的低温多晶硅、薄膜晶体管及阵列基板的制作方法可以使得多晶硅结晶效果更好，改善多晶硅薄膜晶体管的电性能，同时又能提升多晶硅层的干法刻蚀效率，释放生产制造多晶硅的产能。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的低温多晶硅制作过程示意图；
图2为本发明低温多晶硅制作方法一较佳实施例的低温多晶硅制作过程示意图；
图3为本发明低温多晶硅制作方法一较佳实施例制作完成的低温多晶硅结构示意图。
具体实施方式
参见图2，其为本发明低温多晶硅制作方法一较佳实施例的低温多晶硅制作过程示意图。本发明的低温多晶硅制作方法提供了一种提高多晶硅层结晶均匀性的退火方法，主要包括：
提供基板10，在所述基板10上形成缓冲层20；首先，可以采用化学气相沉积法在玻璃衬底即基板10上形成厚度为1000埃～2000埃的SiNx/SiO 2双层结构或SiNx/SiNO/SiO 2三层结构缓冲层。
在所述缓冲层20上形成非晶硅层30；可以采用化学气相沉积法在缓冲层20上沉积非晶硅层30，非晶硅层30厚度可以为300埃～800埃。
在半透膜掩模板50的遮挡下对所述非晶硅层30进行准分子激光退火处理，使所述非晶硅层30转变为多晶硅层；利用激光器40发出准分子激光，然后在半透膜掩模板50的遮挡下对非晶硅层30进行激光退火。
半透膜掩模板50包括透光的衬底51和设于所述衬底51表面的图案化的半透膜52。半透膜掩模板50与传统的光刻掩模板设计方法相同，衬底51可以为透光的大理石衬底，利用半透膜52进行部分吸收激光能量，进而在非晶硅层30上产生照射温度梯度。因为最终形成的多晶硅层即为薄膜晶体管的有源层，所以半透膜掩模板50上的半透膜区域与有源层的非硅岛区对应，半透膜掩模板50的非半透膜区域与有源层的硅岛区对应，也就是图案化的半透膜52对应于非晶硅层30的非硅岛区。通过采用半透膜掩模板50，可以在硅岛区进行全开激光照射，其他区域进行半透膜遮挡退火，使得非晶硅层30的硅岛区温度大于其他区域的温度。
为提升制作效果，本发明低温多晶硅制作方法还可以包括现有制程中的常用步骤，例如对非晶硅层进行去氢处理，在此不再赘述。
参见图3，其为本发明低温多晶硅制作方法一较佳实施例制作完成的低温多晶硅结构示意图，展示了图2所示的基板10及缓冲层20上的非晶硅层30经退火完成后的结构。由于硅岛区温度大于其他区域的温度，因此温度梯度使得硅岛区结晶效果更好，形成硅岛区的多晶硅31，可以改善多晶硅薄膜晶体管的电性能。同时由于非硅岛区的温度较低，结晶度较差，形成非硅岛区的多晶硅32，因此更容易进行刻蚀，可以提升多晶硅层的干法刻蚀效率，释放生产制造多晶硅的产能。
应用本发明低温多晶硅制作方法，可以相应制作多晶硅结晶效果更好的低温多晶硅薄膜晶体管及阵列基板。
综上，本发明的低温多晶硅、薄膜晶体管及阵列基板的制作方法可以使得多晶硅结晶效果更好，改善多晶硅薄膜晶体管的电性能，同时又能提 升多晶硅层的干法刻蚀效率，释放生产制造多晶硅的产能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (9)

  1. 一种低温多晶硅制作方法，包括：
    提供基板，在所述基板上形成缓冲层；
    在所述缓冲层上形成非晶硅层；
    在半透膜掩模板的遮挡下对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层转变为多晶硅层；
    所述半透膜掩模板包括透光的衬底和设于所述衬底表面的图案化的半透膜。
  2. 如权利要求1所述的低温多晶硅制作方法，其中，所述图案化的半透膜对应于非晶硅层的非硅岛区。
  3. 如权利要求1所述的低温多晶硅制作方法，其中，所述缓冲层厚度为1000埃～2000埃。
  4. 如权利要求1所述的低温多晶硅制作方法，其中，所述缓冲层为SiNx/SiO 2双层结构。
  5. 如权利要求1所述的低温多晶硅制作方法，其中，所述缓冲层为SiNx/SiNO/SiO 2三层结构。
  6. 如权利要求1所述的低温多晶硅制作方法，其中，所述非晶硅层厚度为300埃～800埃。
  7. 如权利要求1所述的低温多晶硅制作方法，其中，所述衬底为透光的大理石衬底。
  8. 一种低温多晶硅薄膜晶体管制作方法，应用如权利要求1所述的低温多晶硅制作方法制作低温多晶硅层。
  9. 一种低温多晶硅薄膜晶体管阵列基板制作方法，应用如权利要求8所述的低温多晶硅薄膜晶体管制作方法制作低温多晶硅薄膜晶体管。
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