WO2018032579A1 - 一种tft基板的制备方法 - Google Patents

一种tft基板的制备方法 Download PDF

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Publication number
WO2018032579A1
WO2018032579A1 PCT/CN2016/100576 CN2016100576W WO2018032579A1 WO 2018032579 A1 WO2018032579 A1 WO 2018032579A1 CN 2016100576 W CN2016100576 W CN 2016100576W WO 2018032579 A1 WO2018032579 A1 WO 2018032579A1
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Prior art keywords
layer
depositing
insulating layer
amorphous silicon
tft substrate
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PCT/CN2016/100576
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English (en)
French (fr)
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张晓星
周星宇
徐源竣
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深圳市华星光电技术有限公司
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Priority to US15/323,648 priority Critical patent/US10192903B2/en
Publication of WO2018032579A1 publication Critical patent/WO2018032579A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate.
  • Low temperature polysilicon (LTPS) technology is the manufacturing technology of the new generation of TFT substrate.
  • a-Si amorphous silicon
  • Poly-Si has excellent electrical properties and has good driving ability for active matrix organic light-emitting diodes. Therefore, AMOLED display backplanes based on low temperature polysilicon quarters are currently widely used.
  • the AMOLED display backplane based on pure LTPS technology or oxide technology is a widely used backplane fabrication method. Both have good electrical performance and can have good AMOLED driving capability.
  • the new SPC crystallization method has better uniformity and low leakage, as well as better stability, and has become a better way for AMOLED backplane fabrication.
  • LTPS is currently crystallized by ELA (excimer laser annealing) technology, which uses a laser to instantaneously illuminate the surface of amorphous silicon to dissolve and recrystallize.
  • ELA excimer laser annealing
  • ELA crystallization technology can not effectively control the crystal lattice uniformity and crystal lattice direction, so the crystallization condition is uneven on the distribution of the whole substrate, resulting in uneven long-range display of the display effect, mura appears, and leakage occurs. high.
  • the present application relates to a method of fabricating a TFT substrate.
  • the invention provides a method for preparing a TFT substrate, comprising:
  • Step 101 providing a substrate, the substrate comprising a driving TFT region and a display TFT region, and depositing a buffer layer on the substrate;
  • Step 102 depositing a first amorphous silicon layer on the buffer layer, and performing an excimer laser annealing treatment (ELA scan) on the first amorphous silicon layer to convert the first amorphous silicon layer into crystal First polysilicon layer;
  • ELA scan excimer laser annealing treatment
  • Step 103 depositing a gate insulating layer on the first active layer and the buffer layer,
  • M1 layer a first metal layer (M1 layer) on the gate insulating layer, respectively forming a first gate electrode at a position corresponding to the first active layer as a top gate structure; corresponding to the first active layer Forming a second gate electrode at the position as a bottom gate structure;
  • Step 104 performing ion implantation on the gate insulating layer by using the first gate electrode and the second gate electrode as a shielding layer;
  • Step 105 depositing an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode, and depositing a second amorphous silicon layer on the interlayer insulating layer, and then on the second amorphous silicon Performing ion implantation on the layer, and then performing solid phase crystallization (SPC) on the second amorphous silicon layer to convert the second amorphous silicon layer into a second polysilicon layer;
  • SPC solid phase crystallization
  • Step 106 forming a first via and a second via corresponding to the first active layer on the gate insulating layer and the interlayer insulating layer, and corresponding to the second gate electrode on the interlayer insulating layer Forming a third via;
  • Step 107 depositing a source/drain electrode layer (M2 layer), and patterning the source/drain electrode layer while forming a channel on the surface of the second active layer;
  • Step 108 depositing a passivation layer, patterning the passivation layer, and then depositing a planarization layer on the passivation layer, and forming a fourth via hole at a position on the flat layer at the display TFT region, Four via holes extending to the surface of the source/drain electrode layer;
  • Step 109 depositing an anode electrode on the flat layer, the anode electrode is in contact with the source/drain electrode layer via a fourth via hole, and then depositing a pixel defining layer, and performing pattern definition, that is, completing preparation of the TFT substrate.
  • the substrate is a glass substrate.
  • the material of the buffer layer is silicon oxide, silicon nitride or a combination of the two.
  • the gate insulating layer has a thickness of 50 nm to 500 nm.
  • a preferred gate insulating layer has a thickness of from 100 nm to 200 nm.
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the interlayer insulating layer has a thickness of 100 nm to 300 nm.
  • a preferred interlayer insulating layer has a thickness of 200 nm.
  • the second amorphous silicon layer is ion implanted, and the implanted B ions.
  • the passivation layer has a thickness of 50 nm to 300 nm.
  • a preferred passivation layer has a thickness of from 100 nm to 200 nm.
  • the flat layer has a thickness of 100 nm to 500 nm.
  • a preferred flat layer has a thickness of from 200 nm to 300 nm.
  • the pixel defining layer has a thickness of 300 nm to 900 nm.
  • a preferred pixel defining layer has a thickness of from 400 nm to 500 nm.
  • the present invention manufactures an active layer of a driving TFT region and a display TFT region in a TFT substrate by different techniques to meet the requirements of different TFTs. It is shown that the TFT region requires a short switching time and a leakage current, and the driving TFT region requires sufficient electron mobility and current output uniformity to improve the uniformity of illumination.
  • the invention performs excimer laser annealing treatment on the amorphous silicon layer of the driving TFT region, obtains the LTPS TFT, and performs solid phase crystallization (SPC) on the amorphous silicon layer of the display TFT region to obtain the SPC poly TFT to satisfy the display panel. Characteristics of different TFTs.
  • the TFT region of the display TFT region adopts LTPS TFT, which has the advantages of correspondingly fast and small device.
  • the driving TFT region adopts SPC poly TFT, which can be made into a current-constant OLED device with high mobility, good reliability and small parasitic capacitance. .
  • the combination of the two can effectively solve the problem of uneven picture and reduced power consumption. It can save process costs and improve the uniformity of OLED illumination.
  • FIG. 2 is a schematic view showing deposition of a buffer layer on a substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic view showing deposition of a first amorphous silicon layer on a buffer layer in an embodiment of the present invention
  • FIG. 4 is a schematic diagram of forming a first active layer in a driving TFT region according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of depositing a gate insulating layer and a first metal layer on a first active layer and a buffer layer according to an embodiment of the present invention
  • FIG. 6 is a schematic view showing ion implantation of a gate insulating layer in an embodiment of the present invention.
  • FIG. 7 is a schematic view showing deposition of an interlayer insulating layer and a second amorphous silicon layer on a gate insulating layer, a first gate electrode, and a second gate electrode in an embodiment of the present invention
  • FIG. 8 is a schematic diagram of forming a second active layer at a position corresponding to a second gate electrode in an embodiment of the present invention
  • FIG. 9 is a schematic view showing a via hole formed in a first active layer and a second gate electrode according to an embodiment of the present invention.
  • FIG. 10 is a schematic view showing a deposition source/drain electrode layer in an embodiment of the present invention.
  • FIG. 11 is a schematic view showing an immersion passivation layer and a flat layer in an embodiment of the present invention.
  • FIG. 12 is a schematic structural view of a TFT substrate prepared in an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method according to an embodiment of the present invention.
  • a method for fabricating a TFT substrate according to the present invention will be described in detail with reference to FIG.
  • a substrate 1 is provided, the substrate including a driving TFT region and a display TFT region, on which a buffer layer 2 is deposited.
  • the substrate is a glass substrate.
  • the buffer layer is deposited by physical vapor deposition, chemical vapor deposition, or plasma-assisted chemical vapor deposition.
  • FIG. 2 is a schematic diagram of depositing a buffer layer on a substrate according to an embodiment of the present invention, where 1 is a substrate and 2 is a buffer layer.
  • the material of the buffer layer 2 is silicon oxide, silicon nitride or a combination of the two.
  • Preferred in this embodiment is silicon oxide.
  • a first amorphous silicon layer 21 is deposited on the buffer layer 2, and the first amorphous silicon layer 21 is subjected to an excimer laser annealing process (ELA scan) to make the first
  • ELA scan excimer laser annealing process
  • FIG. 3 is a schematic diagram of depositing a first amorphous silicon layer on a buffer layer according to an embodiment of the present invention, where 1 is a substrate, 2 is a buffer layer, and 21 is a first amorphous silicon layer.
  • the first polysilicon layer is patterned to obtain a first active layer 3 located in the driving TFT region.
  • FIG. 4 is a schematic diagram of forming a first active layer in a driving TFT region according to an embodiment of the present invention, where 1 is a substrate, 2 is a buffer layer, and 3 is a first active layer.
  • the first amorphous silicon layer is deposited by spin coating or printing or the like.
  • the polysilicon layer is described as a material layer of the active layer.
  • a gate insulating layer 4 is deposited on the first active layer 3 and the buffer layer 2,
  • first metal layer M1 layer
  • first gate electrode 51 at a position corresponding to the first active layer 3, respectively, as a top gate structure
  • second gate electrode 52 is formed at the position of the active layer 3 as a bottom gate structure.
  • FIG. 5 is a schematic diagram of depositing a gate insulating layer and a first metal layer on a first active layer and a buffer layer according to an embodiment of the present invention, wherein 1 is a substrate, 2 is a buffer layer, and 3 is a first The active layer, 4 is a gate insulating layer, 51 is a first gate electrode, and 52 is a second gate electrode.
  • the gate insulating layer is deposited by spin coating or printing.
  • the gate insulating layer is an inorganic insulating layer or an organic insulating layer, the inorganic insulating layer is silicon dioxide, silicon nitride or the like, and the organic insulating layer is polyvinylpyrrolidone, polyimide, propylene or the like.
  • the surface of the gate insulating layer may be subjected to plasma treatment to repair defects of the surface of the gate insulating layer.
  • step 104 the gate insulating layer 4 is ion implanted by using the first gate electrode 51 and the second gate electrode 52 as a shielding layer;
  • FIG. 6 is a schematic diagram of ion implantation of a gate insulating layer according to an embodiment of the present invention, wherein 1 is a substrate, 2 is a buffer layer, 3 is a first active layer, and 4 is a gate insulating layer. 51 is the first gate electrode, 52 It is a second gate electrode.
  • step 105 an interlayer insulating layer 6 is deposited on the gate insulating layer 4, the first gate electrode 51 and the second gate electrode 52, and a second amorphous silicon layer 61 is deposited on the interlayer insulating layer 6, and then Ion implantation of the second amorphous silicon layer 61, followed by solid phase crystallization (SPC) of the second amorphous silicon layer 61 to convert the second amorphous silicon layer into a second polycrystalline silicon Floor;
  • SPC solid phase crystallization
  • FIG. 7 is a schematic diagram of depositing an interlayer insulating layer and a second amorphous silicon layer on a gate insulating layer, a first gate electrode, and a second gate electrode according to an embodiment of the present invention, wherein 1 is a substrate, 2 As a buffer layer, 3 is a first active layer, 4 is a gate insulating layer, 51 is a first gate electrode, 52 is a second gate electrode, 6 is an interlayer insulating layer, and 61 is a second amorphous silicon layer.
  • FIG. 8 is a schematic diagram of forming a second active layer on a second gate electrode according to an embodiment of the present invention, where 1 is a substrate, 2 is a buffer layer, 3 is a first active layer, and 4 is a gate insulating layer.
  • the layer 51 is a first gate electrode, 52 is a second gate electrode, 6 is an interlayer insulating layer, and 7 is a second active layer.
  • solid phase crystallization is performed using a rapid thermal annealing (RTA) method. It has the advantages of short use time, low heat consumption, large output and easy control of the process. Moreover, the polycrystalline silicon has less defects and less internal stress after crystallization.
  • RTA rapid thermal annealing
  • the effects of quantum effects are: a, increase the bulk diffusion and surface diffusion coefficient at any processing temperature; b, shorten the time of the heat treatment process; c, reduce the microscopic defect density, thereby improving the material properties.
  • a first via 71 and a second via 72 are formed on the gate insulating layer 4 and the interlayer insulating layer 6 corresponding to the first active layer 3, in the interlayer insulating layer 6 Forming a third via 73 corresponding to the second gate electrode 52;
  • FIG. 9 is a schematic diagram of forming via holes on the first active layer 3 and the second gate electrode 52 in the embodiment of the present invention, where 1 is a substrate, 2 is a buffer layer, and 3 is a first active layer. 4 is a gate insulating layer, 51 is a first gate electrode, 52 is a second gate electrode, 6 is an interlayer insulating layer, 7 is a second active layer, 71 is a first via, and 72 is a second via , 73 is the third via.
  • step 107 the source and drain electrode layer 8 (M2 layer) is deposited, and the source and drain electrode layer 8 is patterned while forming a channel 74 on the surface of the second active layer 7;
  • FIG. 10 is a schematic view showing a deposition source/drain electrode layer according to an embodiment of the present invention, wherein 1 is a substrate, 2 is a buffer layer, 3 is a first active layer, 4 is a gate insulating layer, and 51 is first.
  • the gate electrode 52 is a second gate electrode, 6 is an interlayer insulating layer, 7 is a second active layer, 74 is a channel, and 8 is a source-drain electrode layer.
  • step 108 the passivation layer 9 is immersed, and the passivation layer 9 is patterned, and then a planarization layer 10 is deposited on the passivation layer 9, and a position on the flat layer 10 at the position of the display TFT region is formed.
  • a fourth via 100 extending to the surface of the source/drain electrode layer 8;
  • FIG. 11 is a schematic diagram of an immersion passivation layer and a planarization layer according to an embodiment of the present invention, wherein 1 is a substrate, 2 is a buffer layer, 3 is a first active layer, 4 is a gate insulating layer, and 51 is a first gate electrode, 52 is a second gate electrode, 6 is an interlayer insulating layer, 7 is a second active layer, 8 is a source-drain electrode layer, 9 is a passivation layer, 10 is a flat layer, and 100 is a fourth pass. hole.
  • step 109 an anode electrode 11 is deposited on the flat layer 10, and the anode electrode 11 is in contact with the source/drain electrode layer via the fourth via 100, and then the pixel defining layer 12 is deposited and patterned to be completed. Preparation of a TFT substrate.
  • 12 is a schematic structural view of a TFT substrate prepared in an embodiment of the present invention, where 1 is a substrate, 2 is a buffer layer, 3 is a first active layer, 4 is a gate insulating layer, and 51 is first.
  • Gate electrode, 52 is the second gate electrode, 6 is the interlayer insulating layer, 7 is the second active layer, 8 is the source-drain electrode layer, 9 is the passivation layer, 10 is the flat layer, 11 is the anode electrode, 12 is Pixel definition layer.
  • the display TFT region requires a short switching time and leakage current, and the driving TFT region requires sufficient electron mobility and current output uniformity to improve the uniformity of illumination. Therefore, in the present invention, the amorphous silicon layer of the driving TFT region is subjected to excimer laser annealing treatment to obtain an LTPS TFT, and the amorphous silicon layer of the display TFT region is subjected to solid phase crystallization (SPC) to obtain an SPC poly TFT. Meet the characteristics of the display panel for different TFTs.
  • SPC solid phase crystallization
  • the TFT region of the display TFT region adopts LTPS TFT, which has the advantages of correspondingly fast and small device.
  • the driving TFT region adopts SPC poly TFT, which can be made into a current-constant OLED device with high mobility, good reliability and small parasitic capacitance. .
  • the combination of the two can effectively solve the problem of uneven picture and reduced power consumption. It can save process costs and improve the uniformity of OLED illumination.

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Abstract

提供一种TFT基板的制备方法，TFT基板中含有驱动TFT区域和显示TFT区域，两个TFT区域采用不同的制造技术，以满足不同TFT的需求。TFT基板的制备方法主要包括制作第一非晶硅层（21），得到驱动TFT区域；制作第二非晶硅层（61），得到显示TFT区域；然后沉积钝化层（9）、平坦层（10），进一步处理完成TFT基板的制备。

Description

一种TFT基板的制备方法
相关申请的交叉引用
本申请要求享有于2016年8月17日提交的名称为“一种TFT基板的制备方法”的中国专利申请CN201610683532.9的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制备方法。
背景技术
低温多晶硅(LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。多晶硅(Poly-Si)具有优异的电学性能，对于主动式矩阵有机发光二极管具有较好的驱动能力。因此，基于低温多晶硅季度的AMOLED显示背板目前被广泛使用。
基于单纯的LTPS技术或者oxide技术的AMOLED显示背板是目前广为应用的背板制作方法，两者均有较好的电学性能可以有很好的AMOLED驱动能力。另外新的SPC结晶方式有较好的均一性和低的漏电，以及较好的稳定性，也成为AMOLED的背板制作较好的方式。
LTPS目前由ELA(excimer laser annealing)技术结晶，利用激光的瞬间脉冲照射到非晶硅表面，使其溶化并重新结晶。但是ELA结晶技术对于晶格的均一性和晶格结晶方向不能做到有效控制，所以结晶状况在整个基板的分布上很不均匀，造成显示效果画面的长程不均一，有mura出现，且漏电较高。
发明内容
针对上述现有技术中的问题，本申请一种TFT基板的制备方法。
本发明提供一种TFT基板的制备方法，包括：
步骤101：提供基板，所述基板包括驱动TFT区域和显示TFT区域，在所述基板上沉积缓冲层；
步骤102：在所述缓冲层上沉积第一非晶硅层，并对所述第一非晶硅层进行准分子激光退火处理(ELA scan)，使所述第一非晶硅层结晶转变为第一多晶硅层；
对所述第一多晶硅层进行图案化处理，得到位于所述驱动TFT区域的第一有源层；
步骤103：在所述第一有源层及缓冲层上沉积栅极绝缘层，
在所述栅极绝缘层上沉积并图案化第一金属层(M1层)，分别对应第一有源层的位置处形成第一栅电极，作为顶栅结构；对应位置第一有源层的位置处形成第二栅电极，作为底栅结构；
步骤104：利用第一栅电极和第二栅电极作为遮挡层，对栅极绝缘层进行离子植入；
步骤105：然后在栅极绝缘层、第一栅电极和第二栅电极上沉积层间绝缘层，并在所述层间绝缘层上沉积第二非晶硅层，然后对第二非晶硅层进行离子植入，接着对所述第二非晶硅层进行固相晶化(SPC)，使所述第二非晶硅层结晶转变为第二多晶硅层；
对所述第二多晶硅层进行图案化处理，形成第二有源层，第二有源层位于与第二栅电极相对应的位置处；
步骤106：在所述栅极绝缘层和层间绝缘层上对应所述第一有源层形成第一过孔和第二过孔，在所述层间绝缘层上对应所述第二栅电极形成第三过孔；
步骤107：沉积源漏电极层(M2层)，并对源漏电极层进行图案化，同时在第二有源层表面形成沟道；
步骤108：沉积钝化层，并对钝化层图案化，然后在钝化层上沉积平坦层，在所述平坦层上位于所述显示TFT区域的位置处形成第四过孔，所述第四过孔延伸至源漏电极层表面；
步骤109：在所述平坦层上沉积阳极电极，阳极电极经由第四过孔与所述源漏电极层相接触，然后沉积像素定义层，并进行图形定义，即完成TFT基板的制备。
进一步的，所述基板为玻璃基板。
进一步的，所述缓冲层的材料为氧化硅、氮化硅或二者的组合。
进一步的，所述栅极绝缘层的厚度为50nm～500nm。
优选的栅极绝缘层的厚度为100nm～200nm。
进一步的，所述层间绝缘层的材料为氧化硅、氮化硅或二者的组合。
进一步的，所述层间绝缘层的厚度为100nm～300nm。
优选的层间绝缘层的厚度为200nm。
进一步的，对第二非晶硅层进行离子植入，植入的为B离子。
进一步的，所述钝化层的厚度为50nm～300nm。
优选的钝化层的厚度为100nm～200nm。
进一步的，所述平坦层的厚度为100nm～500nm。
优选的平坦层的厚度为200nm～300nm。
进一步的，所述像素定义层的厚度为300nm～900nm。
优选的像素定义层的厚度为400nm～500nm。
本发明的有益效果：
本发明将TFT基板中驱动TFT区域和显示TFT区域的主动层用不同的技术制造，以满足不同TFT的需求。其中显示TFT区域需要较短的开关时间和漏电流，而驱动TFT区域需要足够的电子迁移率和电流输出均一性，以提高发光均一程度。本发明针对驱动TFT区域的非晶硅层进行准分子激光退火处理，获得LTPS TFT，同时对显示TFT区域的非晶硅层进行固相晶化(SPC)，获得SPC poly TFT，来满足显示面板对不同TFT的特性要求。显示TFT区域采用LTPS的TFT，发挥其相应快速，器件较小的优势；而驱动TFT区域采用SPC poly TFT，可以做成电流恒定型的OLED器件，并且迁移率高，可靠性好，寄生电容小。二者配合，可以有效解决画面不均和降低功耗的要求。既可以节省制程支出，又可以提高OLED发光均一性。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为本发明实施例的方法流程图；
图2为本发明实施例中在基板上沉积缓冲层的示意图；
图3为本发明实施例中在缓冲层上沉积第一非晶硅层的示意图；
图4为本发明实施例中位于驱动TFT区域形成第一有源层的示意图；
图5为本发明实施例中在第一有源层及缓冲层上沉积栅极绝缘层和第一金属层的示意图；
图6为本发明实施例中对栅极绝缘层进行离子植入的示意图；
图7为本发明实施例中在栅极绝缘层、第一栅电极和第二栅电极上沉积层间绝缘层及第二非晶硅层的示意图；
图8为本发明实施例中在第二栅电极相对应的位置处形成第二有源层的示意图；
图9为本发明实施例中在第一有源层和第二栅电极形成过孔的示意图；
图10为本发明实施例中沉积源漏电极层的示意图；
图11为本发明实施例中沉浸钝化层和平坦层的示意图；
图12为本发明实施例中制备的TFT基板的结构示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示为根据本发明的一个实施例的方法流程图，以下参考图1来对本发明所述的TFT基板的制备方法进行详细说明。
在步骤101中，提供基板1，所述基板包括驱动TFT区域和显示TFT区域，在所述基板上沉积缓冲层2。
具体的，所述基板为玻璃基板。
具体的，通过物理气相沉积法、化学气相沉积法或是电浆辅助化学气相沉积法沉积缓冲层。
如图2所示，图2为本发明实施例中在基板上沉积缓冲层的示意图，1为基板，2为缓冲层。
具体的，所述缓冲层2的材料为氧化硅、氮化硅或二者的组合。
本实施例优选的是氧化硅。
接下来在步骤102中，在所述缓冲层2上沉积第一非晶硅层21，并对所述第一非晶硅层21进行准分子激光退火处理(ELA scan)，使所述第一非晶硅层结晶转变为第一多晶硅层；
如图3所示，图3为本发明实施例中在缓冲层上沉积第一非晶硅层的示意图，1为基板，2为缓冲层，21为第一非晶硅层。
对所述第一多晶硅层进行图案化处理，得到位于所述驱动TFT区域的第一有源层3。
如图4所示，图4为本发明实施例中位于驱动TFT区域形成第一有源层的示意图，1为基板，2为缓冲层，3为第一有源层。
具体的，通过旋涂或者打印等方式沉积第一非晶硅层。
对所述非晶硅层进行准分子激光退火处理(ELA scan)以形成所述多晶硅层，以将所述非晶硅层熔融使所述非晶硅层内的硅分子再结晶，以形成所述多晶硅层，以作为有源层的材质层。
在步骤103中，在所述第一有源层3及缓冲层2上沉积栅极绝缘层4，
在所述栅极绝缘层4上沉积并图案化第一金属层(M1层)，分别对应第一有源层3的位置处形成第一栅电极51，作为顶栅结构；对应未设置第一有源层3的位置处形成第二栅电极52，作为底栅结构。
如图5所示，图5为本发明实施例中在第一有源层及缓冲层上沉积栅极绝缘层和第一金属层的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极。
具体的，通过旋涂或者打印等方式沉积栅极绝缘层。
所述栅极绝缘层为无机绝缘层或者有机绝缘层，无机绝缘层为二氧化硅、氮化硅等，有机绝缘层为聚乙烯吡咯烷酮、聚酰亚胺、丙烯等。
具体的，还可以对栅极绝缘层表面进行等离子体处理，以修复该栅极绝缘层表面的缺陷。
在步骤104中，利用第一栅电极51和第二栅电极52作为遮挡层，对栅极绝缘层4进行离子植入；
如图6所示，图6为本发明实施例中对栅极绝缘层进行离子植入的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52 为第二栅电极。
步骤105中，在栅极绝缘层4、第一栅电极51和第二栅电极52上沉积层间绝缘层6，并在所述层间绝缘层6上沉积第二非晶硅层61，然后对第二非晶硅层61进行离子植入，接着对所述第二非晶硅层61进行固相晶化(SPC)，使所述第二非晶硅层结晶转变为第二多晶硅层；
如图7所示，图7为本发明实施例中在栅极绝缘层、第一栅电极和第二栅电极上沉积层间绝缘层及第二非晶硅层的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极，6为层间绝缘层，61为第二非晶硅层。
对所述第二多晶硅层61进行图案化处理，形成第二有源层7，第二有源层7位于与第二栅电极52相对应的位置处；
如图8所示，图8为本发明实施例中在第二栅电极形成第二有源层的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极，6为层间绝缘层，7为第二有源层。
具体的，采用快速热退火(RTA)方法进行固相晶化。具有用时短、耗热少、产量大、过程容易控制的优点。而且晶化后的多晶硅缺陷少、内应力少。在快速热处理过程中，量子效应的作用有：a、在任何处理温度下，增大体扩散和表面扩散系数；b、缩短热处理过程的时间；c、减小微观缺陷密度，从而改善材料性能。
在步骤106中，在所述栅极绝缘层4和层间绝缘层6上对应所述第一有源层3形成第一过孔71和第二过孔72，在所述层间绝缘层6上对应所述第二栅电极52形成第三过孔73；
如图9所示，图9为本发明实施例中在第一有源层3和第二栅电极52上方形成过孔的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极，6为层间绝缘层，7为第二有源层，71为第一过孔，72为第二过孔，73为第三过孔。
在步骤107中，沉积源漏电极层8(M2层)，并对源漏电极层8进行图案化，同时在第二有源层7表面形成沟道74；
如图10所示，图10为本发明实施例中沉积源漏电极层的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极，6为层间绝缘层，7为第二有源层，74为沟道，8为源漏电极层。
在步骤108中，沉浸钝化层9，并对钝化层9图案化，然后在钝化层9上沉积平坦层10，在所述平坦层10上位于所述显示TFT区域的位置处形成第四过孔100，所述第四过孔100延伸至源漏电极层8表面；
如图11所示，图11为本发明实施例中沉浸钝化层和平坦层的示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极，6为层间绝缘层，7为第二有源层，8为源漏电极层，9为钝化层，10为平坦层，100为第四过孔。
在步骤109中，在所述平坦层10上沉积阳极电极11，阳极电极11经由第四过孔100与所述源漏电极层相接触，然后沉积像素定义层12，并进行图形定义，即完成TFT基板的制备。
如图12所示，图12为本发明实施例中制备的TFT基板的结构示意图，1为基板，2为缓冲层，3为第一有源层，4为栅极绝缘层，51为第一栅电极，52为第二栅电极，6为层间绝缘层，7为第二有源层，8为源漏电极层，9为钝化层，10为平坦层，11为阳极电极，12为像素定义层。
显示TFT区域需要较短的开关时间和漏电流，而驱动TFT区域需要足够的电子迁移率和电流输出均一性，以提高发光均一程度。因此，其中本发明针对驱动TFT区域的非晶硅层进行准分子激光退火处理，获得LTPS TFT，同时对显示TFT区域的非晶硅层进行固相晶化(SPC)，获得SPC poly TFT，来满足显示面板对不同TFT的特性要求。显示TFT区域采用LTPS的TFT，发挥其相应快速，器件较小的优势；而驱动TFT区域采用SPC poly TFT，可以做成电流恒定型的OLED器件，并且迁移率高，可靠性好，寄生电容小。二者配合，可以有效解决画面不均和降低功耗的要求。既可以节省制程支出，又可以提高OLED发光均一性。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (10)

  1. 一种TFT基板的制备方法，其中，包括：
    步骤101：提供基板，所述基板包括驱动TFT区域和显示TFT区域，在所述基板上沉积缓冲层；
    步骤102：在所述缓冲层上沉积第一非晶硅层，并对所述第一非晶硅层进行准分子激光退火处理，使所述第一非晶硅层结晶转变为第一多晶硅层；
    对所述第一多晶硅层进行图案化处理，得到位于所述驱动TFT区域的第一有源层；
    步骤103：在所述第一有源层及缓冲层上沉积栅极绝缘层，
    在所述栅极绝缘层上沉积并图案化第一金属层，分别对应第一有源层的位置处形成第一栅电极，对应未设置第一有源层的位置处形成第二栅电极；
    步骤104：利用第一栅电极和第二栅电极作为遮挡层，对栅极绝缘层进行离子植入；
    步骤105：然后在栅极绝缘层、第一栅电极和第二栅电极上沉积层间绝缘层，并在所述层间绝缘层上沉积第二非晶硅层，然后对第二非晶硅层进行离子植入，接着对所述第二非晶硅层进行固相晶化，使所述第二非晶硅层结晶转变为第二多晶硅层；
    对所述第二多晶硅层进行图案化处理，形成第二有源层，第二有源层位于与第二栅电极相对应的位置处；
    步骤106：在所述栅极绝缘层和层间绝缘层上对应所述第一有源层形成第一过孔和第二过孔，在所述层间绝缘层上对应所述第二栅电极形成第三过孔；
    步骤107：沉积源漏电极层，并对源漏电极层进行图案化，同时在第二有源层表面形成沟道；
    步骤108：沉积钝化层，并对钝化层图案化，然后在钝化层上沉积平坦层，在所述平坦层上位于所述显示TFT区域的位置处形成第四过孔，所述第四过孔延伸至源漏电极层表面；
    步骤109：在所述平坦层上沉积阳极电极，阳极电极经由第四过孔与所述源漏电极层相接触，然后沉积像素定义层，并进行图形定义，即完成TFT基板的制备。
  2. 如权利要求1所述的TFT基板的制备方法，其中，所述基板为玻璃基板。
  3. 如权利要求1所述的TFT基板的制备方法，其中，所述缓冲层的材料为氧化硅、氮化硅或二者的组合。
  4. 如权利要求3所述的TFT基板的制备方法，其中，所述栅极绝缘层的厚度为50nm～500nm。
  5. 如权利要求2所述的TFT基板的制备方法，其中，所述层间绝缘层的材料为氧化硅、氮化硅或二者的组合。
  6. 如权利要求5所述的TFT基板的制备方法，其中，所述层间绝缘层的厚度为100nm～300nm。
  7. 如权利要求2所述的TFT基板的制备方法，其中，对第二非晶硅层进行离子植入，植入的为B离子。
  8. 如权利要求7所述的TFT基板的制备方法，其中，所述钝化层的厚度为50nm～300nm。
  9. 如权利要求2所述的TFT基板的制备方法，其中，所述平坦层的厚度为100nm～500nm。
  10. 如权利要求9所述的TFT基板的制备方法，其中，所述像素定义层的厚度为300nm～900nm。
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