WO2017031937A1 - 氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法 - Google Patents

氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法 Download PDF

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WO2017031937A1
WO2017031937A1 PCT/CN2016/071546 CN2016071546W WO2017031937A1 WO 2017031937 A1 WO2017031937 A1 WO 2017031937A1 CN 2016071546 W CN2016071546 W CN 2016071546W WO 2017031937 A1 WO2017031937 A1 WO 2017031937A1
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thin film
oxide semiconductor
semiconductor thin
film
layer
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French (fr)
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孔祥永
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京东方科技集团股份有限公司
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the invention belongs to the technical field of display, and particularly relates to a method for preparing an oxide semiconductor film and a method for preparing a thin film transistor.
  • oxide thin film transistors have been widely used due to their high electron mobility, low preparation temperature, good uniformity, transparency to visible light and low threshold voltage.
  • the material of the oxide active layer of the oxide thin film transistor is generally a metal oxide, which is poor in stability and is susceptible to oxygen, hydrogen, and water in an etching environment. Therefore, in order to prevent the oxide active layer from being affected when etching the source and the drain of the oxide thin film transistor, an etch stop layer (ESL) is added to protect the oxide active layer.
  • ESL etch stop layer
  • an etch barrier layer is added, that is, a process of forming an etch barrier layer is added in the preparation process of the oxide thin film transistor, and at this time, if the etch barrier layer is formed
  • Insufficient control for example, resulting in a non-uniform thickness of the etch stop layer, may affect the characteristics of the oxide thin film transistor. Therefore, the addition of the etch barrier layer not only complicates the fabrication process of the oxide thin film transistor, increases the manufacturing cost, but also reduces the productivity and yield of the manufactured substrate.
  • the oxide active layer of the oxide thin film transistor can be made of a crystalline oxide active layer, thereby avoiding the addition of an etch barrier. Layer, but this crystalline oxide active layer needs to be formed by directly heating the oxide semiconductor film to crystallize it, the crystallization temperature is high, the preparation process is difficult, and it is easy to affect other layers during crystallization. Therefore, how to reduce the crystallization temperature of the oxide active layer has become a problem in the field Solved technical problems.
  • the technical problem to be solved by the present invention includes providing a method for preparing an oxide semiconductor thin film having a low crystallization temperature and optimizing performance, and a method for preparing the thin film transistor, in view of the above problems existing in the preparation method of the conventional thin film transistor.
  • the technical solution adopted to solve the technical problem of the present invention includes providing a method for preparing an oxide semiconductor film, which comprises the following steps:
  • an oxide semiconductor thin film is formed and annealed to crystallize the oxide semiconductor thin film.
  • the method for preparing the oxide semiconductor film further includes:
  • the formed inducing layer film is annealed.
  • the annealing temperature is 300 ° C to 600 ° C when the formed inducing layer film is annealed.
  • the thickness of the inducing layer film is 5 nm to 50 nm; and the thickness of the oxide semiconductor film is 30 nm to 200 nm.
  • the annealing temperature is 300 ° C to 500 ° C when the oxide semiconductor film is annealed.
  • the method for preparing the oxide semiconductor film further comprises:
  • the inducing layer film is formed on the buffer layer.
  • the buffer layer comprises at least one layer structure formed of silicon oxide or silicon nitride.
  • the buffer layer has a thickness of from 150 nm to 300 nm.
  • the material of the inducing layer film is zinc oxide.
  • the material of the oxide semiconductor thin film is any one of indium gallium zinc oxide, indium zinc oxide, indium tin oxide, and indium gallium tin oxide.
  • the crystallization of the oxide semiconductor thin film is specifically an oxide semiconductor thin film in which an oxide semiconductor thin film is converted into a polycrystalline oxide semiconductor thin film or a C-axis crystal preferentially grown.
  • a technical solution adopted to solve the technical problem of the present invention includes providing a method of fabricating a thin film transistor, comprising the steps of forming an active layer, the step of forming an active layer comprising:
  • a pattern including an active layer is formed on the substrate on which the crystallized oxide semiconductor film is formed by a patterning process.
  • the method further comprises:
  • the inducing layer film is formed on the gate insulating layer.
  • the method for preparing the thin film transistor includes:
  • a source/drain metal thin film is formed on the substrate on which the crystallized oxide semiconductor film is formed, and a pattern including a source and a drain is formed by a patterning process.
  • an oxide film is induced by an inducing layer film, and then the oxide semiconductor film is annealed to be crystallized, and the oxide semiconductor film is directly heated to be crystallized.
  • the heating temperature ie, the crystallization temperature
  • the crystallization temperature is much lower, thereby reducing the difficulty in the preparation process of the oxide semiconductor film.
  • FIG. 1 is a flow chart showing a method of preparing an oxide semiconductor thin film according to Embodiment 1 of the present invention
  • FIG. 2 is a flow chart showing a method of preparing an oxide semiconductor thin film according to Embodiment 2 of the present invention
  • FIG. 3 is a flow chart showing a method of fabricating a thin film transistor according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic view of an array substrate according to Embodiment 3 of the present invention.
  • the embodiment provides a method for preparing an oxide semiconductor film 3, which includes the following steps 1 and 2:
  • Step 1 On the substrate 1, the inducing layer film 2 is formed by a method of thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering or sol-gel.
  • the substrate 1 can refer to a substrate on which no film layer is formed, such as white glass, or a substrate on which other film layers or patterns are formed, such as a liner on which the buffer layer 4 is formed. bottom.
  • the material of the inducing layer film 2 is preferably zinc oxide (ZnO), and the thickness is preferably in the range of 5 to 50 nm. It should be noted that, due to the material itself, at least part of the material has been crystallized during the deposition process, so the inducing layer film 2 formed in the first step can be understood as an at least partially crystallized inducing layer. film.
  • Step 2 forming an oxide semiconductor thin film 3 on the substrate 1 which has completed the above step one by using a method of thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, or the like, and Annealing treatment is carried out at an annealing temperature of 300 to 500 ° C, so that the oxide semiconductor thin film 3 is crystallized under the induction of the inducing layer film 2, specifically, the oxide semiconductor thin film 3 is converted into a polycrystalline oxide semiconductor thin film, or a C-axis. A preferentially grown oxide semiconductor film.
  • the material of the oxide semiconductor thin film 3 may include In (indium), Ga (gallium), At least three of elements such as Zn (zinc), O (oxygen), and Sn (tin) are formed on the substrate 1 which has completed the above step 1 by a process such as sputtering. Further, the oxide semiconductor thin film 3 must contain oxygen and two or more other elements, for example, including Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), and oxidation. Indium Tin Oxide (ITO), or Indium Gallium Tin Oxide (IGTO). The material of the oxide semiconductor thin film 3 is preferably IGZO or IZO, and the thickness is preferably controlled within a range of 30 to 200 nm.
  • the oxide semiconductor thin film 3 is made.
  • the temperature required for crystallization is much higher than the temperature required for the oxide semiconductor thin film 3 to be crystallized after the induction layer film 2 is first induced in the present embodiment.
  • the heating temperature is about 800 ° C
  • zinc oxide is used as the After the oxide semiconductor thin film 3 is induced by the material of the inducing layer film 2, the oxide semiconductor thin film 3 is annealed to be crystallized, and the annealing temperature is 300 to 500 ° C, so that the process difficulty is greatly reduced.
  • the oxide thin film 3 formed on the inducing layer film 2 is induced by the inducing layer film 2, and the oxide semiconductor thin film 3 is grown in the crystal orientation of the inducing layer film 2.
  • a polycrystalline oxide semiconductor thin film or a C-axis crystal preferentially grown oxide semiconductor thin film is obtained.
  • the crystallization temperature of the oxide semiconductor thin film is low, so the preparation method has low process difficulty and can be obtained.
  • the present embodiment provides a method for preparing an oxide semiconductor film 3, which includes the following steps 1 to 3.
  • Step 1 On the substrate 1, using sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron return
  • the buffer layer 4 is formed by a method such as spin resonance chemical vapor deposition.
  • the buffer layer 4 includes at least one layer of silicon oxide or silicon nitride, and has a thickness of preferably 150 to 300 nm. The reason why the buffer layer 4 is so thick is to form an effective heat-resistant layer and to maintain the heat so as to sufficiently crystallize the oxide semiconductor thin film 3 formed in the subsequent step.
  • Step 2 On the substrate 1 which completes the above step 1, the induction layer is formed by thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering or sol-gel preparation.
  • the film 2 is annealed to the formed inducing layer film 2 at an annealing temperature of 300 to 600 ° C to sufficiently crystallize the inducing layer film 2 to better induce the oxide semiconductor film 3 in a subsequent step and to cause it. Crystallization.
  • the material of the inducing layer film 2 is preferably zinc oxide (ZnO), and the thickness is preferably in the range of 5 to 50 nm. It should be noted that, due to the material itself, at least part of the material has been crystallized during the deposition process, and then the inducing layer film 2 is annealed to sufficiently crystallize the inducing layer film 2. Therefore, the inducing layer film 2 formed in the second step can be understood as the crystallized inducing layer film 2.
  • Step 3 On the substrate 1 which has completed the above step 2, the oxide semiconductor thin film 3 is formed by thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, or the like, and Annealing treatment is carried out at an annealing temperature of 300 to 500 ° C, so that the oxide semiconductor thin film 3 is crystallized under the induction of the inducing layer film 2, specifically, the oxide semiconductor thin film 3 is converted into a polycrystalline oxide semiconductor thin film, or a C-axis. A preferentially grown oxide semiconductor film.
  • the material of the oxide semiconductor thin film 3 may include at least three of elements such as In (indium), Ga (gallium), Zn (zinc), O (oxygen), and Sn (tin), and is formed by a process such as sputtering. On the substrate 1 of the above step two is completed. Further, the oxide semiconductor thin film 3 must contain oxygen and two or more other elements, including, for example, Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), and oxidation. Indium Tin Oxide (ITO) or Indium Gallium Tin Oxide (IGTO). Oxide half The material of the conductor film 3 is preferably IGZO or IZO, and the thickness is preferably controlled within the range of 30 to 200 nm.
  • the oxide thin film 3 formed on the inducing layer film 2 is induced by the inducing layer film 2, and the oxide semiconductor thin film 3 is grown in the crystal orientation of the inducing layer film 2.
  • a polycrystalline oxide semiconductor thin film or a C-axis crystal preferentially grown oxide semiconductor thin film is obtained, and in particular, a buffer layer 4 is formed before the deposition inducing layer thin film 2 is formed (that is, the buffer layer 4 is formed on the substrate 1 and the inducing layer).
  • the films 2) to form an effective heat-resistant layer, so that the oxide semiconductor film 3 formed in the subsequent step can be sufficiently crystallized, and the crystallization temperature of the oxide semiconductor film is low in the preparation method, so the preparation method The process is less difficult and an oxide semiconductor film 3 with optimized performance can be obtained.
  • the present embodiment provides a method of fabricating a thin film transistor including the step of forming an oxide semiconductor thin film in Embodiment 1 or 2. Specifically, a bottom gate type thin film transistor is prepared as an example for description.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may further include printing, inkjet, and the like for forming a predetermined pattern.
  • lithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, etc., including a film forming, exposure, and developing process.
  • the corresponding patterning process can be selected in accordance with the structure that is desired to be formed in the present invention.
  • the method for preparing the bottom gate thin film transistor includes the following steps 1 to 4.
  • Step 1 On the substrate 1, a gate metal film is deposited by magnetron sputtering, and a pattern including the gate 5 of the thin film transistor is formed by a patterning process.
  • the gate metal layer film may be one or more of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • Al aluminum
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • a multilayer composite formed of a single layer or a plurality of materials formed of the materials preferably a single layer film formed of Mo, Al or an alloy containing Mo or Al or a multilayer composite formed of a plurality of materials thereof membrane.
  • Step 2 On the substrate 1 which has completed the above step 1, the gate insulating layer 6 is formed by a thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering or the like.
  • the gate insulating layer 6 may be silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • AlOx aluminum oxide
  • Step 3 On the substrate 1 on which the above step 2 is completed, the inducing layer film 2 and the oxide semiconductor film 3 are sequentially formed, and the oxide semiconductor film 3 is annealed to form a crystallized oxide semiconductor film.
  • the step 3 can be implemented by using the preparation method in the embodiment 1, or can be implemented by using the preparation method in the embodiment 2, and the step 3 is not described in detail here. Since the gate insulating layer 6 is provided under the oxide semiconductor thin film 3, the gate insulating layer 6 can have the same heat insulating effect as the buffer layer 4. Therefore, the step of fabricating the buffer layer 4 can be omitted in the third step.
  • Step 4 On the substrate 1 which completes the above step 3, a source/drain metal layer film 70 is first formed, and then the photoresist 80 is coated and exposed by a halftone mask or a gray scale mask to form a thin film transistor. a pattern of the active layer 20, the source 7-1, and the drain 7-2, wherein the active layer 20 is a crystalline active layer, and the source 7-1 passes through the source contact region and the drain 7-2 through the drain contact The region is in contact with the active layer 20.
  • the source/drain metal layer film 70 may be one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu) or A variety of materials are formed, preferably formed of Mo, Al or an alloy containing Mo or Al.
  • the passivation layer 9 and the pixel electrode 10 may be sequentially formed, and the pixel electrode 10 and the drain electrode 7-2 are brought into contact to form an array substrate, as shown in FIG.
  • the crystallized active layer is formed under the induction of the thin film of the inducing layer, so that the oxide semiconductor thin film can be crystallized without high-temperature treatment, and formed into a crystalline active layer in a subsequent step, Moreover, it is not necessary to form an etch barrier layer, thereby making the preparation process easier to implement.

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Abstract

提供一种氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法，属于显示技术领域，其可解决现有的氧化物薄膜晶体管中的氧化物半导体薄膜的晶化温度很高，制备工艺难度大的问题。该氧化物半导体薄膜的制备方法包括如下步骤：在基底（1）上形成诱导层薄膜（2）；在形成有诱导层薄膜（2）的基底（1）上，形成氧化物半导体薄膜（3），并进行退火处理，以使氧化物半导体薄膜（3）晶化。

Description

氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法 技术领域
本发明属于显示技术领域，具体涉及氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法。
背景技术
随着显示技术的不断发展，氧化物薄膜晶体管因其具有电子迁移率高、制备温度低、均一性好、对可见光透明和阈值电压低等特点而得到广泛应用。
现有技术在制作氧化物薄膜晶体管时，氧化物薄膜晶体管的氧化物有源层的材料一般为金属氧化物，其稳定性差，易受到刻蚀环境中的氧气、氢气及水的影响。因此，为了防止在刻蚀氧化物薄膜晶体管的源极和漏极时影响到氧化物有源层，增设了刻蚀阻挡层(Etch Stop Layer，ESL)，用以保护氧化物有源层。
发明人发现现有技术中至少存在如下问题：由于增设了刻蚀阻挡层，即在氧化物薄膜晶体管的制备工艺中增加了制作刻蚀阻挡层的工序，此时若刻蚀阻挡层的制作工序控制不到位，例如导致制作出的刻蚀阻挡层的厚度不均一，则可能影响氧化物薄膜晶体管的特性。因此，增设刻蚀阻挡层不仅导致氧化物薄膜晶体管的制作工艺变得复杂、制造成本增加，同时使得制造的基板的产能及良品率降低。
为了解决现有技术中在氧化物薄膜晶体管内增设刻蚀阻挡层而带来的问题，可使氧化物薄膜晶体管的氧化物有源层采用结晶的氧化物有源层，从而避免增设刻蚀阻挡层，但是这种结晶的氧化物有源层需通过直接加热氧化物半导体薄膜使其晶化而形成，晶化温度很高，制备工艺难度大，且晶化时很容易对其他膜层产生影响，因此如何降低氧化物有源层的晶化温度成为本领域亟待 解决的技术问题。
发明内容
本发明所要解决的技术问题包括，针对现有的薄膜晶体管的制备方法存在的上述的问题，提供一种晶化温度较低、性能优化的氧化物半导体薄膜的制备方法和薄膜晶体管的制备方法。
解决本发明技术问题所采用的技术方案包括提供一种氧化物半导体薄膜的制备方法，其包括如下步骤：
在基底上形成诱导层薄膜；
在形成有诱导层薄膜的基底上，形成氧化物半导体薄膜，并进行退火处理，以使氧化物半导体薄膜晶化。
优选的是，在所述形成氧化物半导体薄膜的步骤之前，所述氧化物半导体薄膜的制备方法还包括：
对形成的诱导层薄膜进行退火处理。
进一步优选的是，在对形成的诱导层薄膜进行退火处理时，退火温度为300℃至600℃。
优选的是，所述诱导层薄膜的厚度为5nm至50nm；所述氧化物半导体薄膜的厚度为30nm至200nm。
优选的是，在对所述氧化物半导体薄膜进行退火处理时，退火温度为300℃至500℃。
优选的是，在所述形成诱导层薄膜的步骤之前，所述氧化物半导体薄膜的制备方法还包括：
在基底上形成缓冲层，
所述诱导层薄膜形成在缓冲层上。
进一步优选的是，所述缓冲层包括氧化硅或氮化硅形成的至少一层结构。
进一步优选的是，所述缓冲层的厚度为150nm至300nm。
优选的是，所述诱导层薄膜的材料为氧化锌。
优选的是，所述氧化物半导体薄膜的材料为氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的任意一种。
优选的是，所述使氧化物半导体薄膜晶化具体为：使氧化物半导体薄膜转化为多晶氧化物半导体薄膜，或者C轴晶向择优生长的氧化物半导体薄膜。
解决本发明技术问题所采用的技术方案包括提供一种薄膜晶体管的制备方法，其包括形成有源层的步骤，所述形成有源层的步骤包括：
在基底上形成诱导层薄膜；
在形成有诱导层薄膜的基底上，形成氧化物半导体薄膜，并进行退火处理，以使氧化物半导体薄膜晶化；
对形成有晶化的氧化物半导体薄膜的基底采用构图工艺形成包括有源层的图形。
优选的是，在所述形成诱导层薄膜的步骤之前还包括：
在基底上，通过构图工艺形成包括薄膜晶体管栅极的图形；
在形成有栅极的基底上，形成栅极绝缘层，
所述诱导层薄膜形成在栅极绝缘层上。
优选的是，在使氧化物半导体薄膜晶化后，在形成所述有源层的图形的同时，所述薄膜晶体管的制备方法还包括：
在形成有晶化的氧化物半导体薄膜的基底上形成源漏金属薄膜，并通过构图工艺形成包括源极和漏极的图形。
本发明具有如下有益效果：
本发明的氧化物半导体薄膜的制备方法先采用诱导层薄膜对氧化物半导体薄膜进行诱导，再对氧化物半导体薄膜进行退火处理使其晶化，较直接对氧化物半导体薄膜进行加热使其晶化而言，加热温度(即晶化温度)要低很多，从而降低了氧化物半导体薄膜制备工艺的难度。
附图说明
图1为根据本发明的实施例1的氧化物半导体薄膜的制备方法的流程图；
图2为根据本发明的实施例2的氧化物半导体薄膜的制备方法的流程图；
图3为根据本发明的实施例3的薄膜晶体管的制备方法的流程图；以及
图4为根据本发明的实施例3的阵列基板的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图1所示，本实施例提供了一种氧化物半导体薄膜3的制备方法，包括如下步骤一和步骤二：
步骤一、在基底1上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射或者溶胶-凝胶等制备方法，形成诱导层薄膜2。
其中，基底1既可以指代其上没有形成任何膜层的衬底，例如白玻璃，也可以指代其上形成有其他膜层或者图案的衬底，例如其上形成有缓冲层4的衬底。诱导层薄膜2的材料优选为氧化锌(ZnO)，厚度优选在5～50nm的范围内。需要说明的是，诱导层薄膜2由于材料本身的原因，至少部分材料在沉积的过程中就已经发生了晶化，故步骤一中形成的诱导层薄膜2可以理解为至少部分晶化的诱导层薄膜。
步骤二、在完成上述步骤一的基底1上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等制备方法，形成氧化物半导体薄膜3，并进行退火处理，退火温度为300～500℃，使得氧化物半导体薄膜3在诱导层薄膜2的诱导下晶化，具体为，使氧化物半导体薄膜3转化为多晶氧化物半导体薄膜，或者C轴晶向择优生长的氧化物半导体薄膜。
其中，氧化物半导体薄膜3的材料可以包含In(铟)、Ga(镓)、 Zn(锌)、O(氧)和Sn(锡)等元素中的至少三种，并通过溅射等工艺形成在完成上述步骤一的基底1上。而且，氧化物半导体薄膜3中必须包含氧元素和其他两种或两种以上的元素，例如包含氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)、氧化铟锌(Indium Zinc Oxide，IZO)、氧化铟锡(Indium Tin Oxide，ITO)、或氧化铟镓锡(Indium Gallium Tin Oxide，IGTO)等。氧化物半导体薄膜3的材料优选为IGZO或IZO，厚度优选控制在30～200nm的范围内。
需要说明的是，如果不采用诱导层薄膜2对氧化物半导体薄膜3进行诱导，而直接对氧化物半导体薄膜3进行加热(即现有技术中所采用的方式)，则使氧化物半导体薄膜3晶化所需的温度要远高于本实施例中先采用诱导层薄膜2进行诱导之后再对氧化物半导体薄膜3进行加热以使其晶化所需的温度。具体地，假若氧化物半导体薄膜3的材料采用氧化铟镓锌(IGZO)，并直接对氧化铟镓锌材料进行加热以使其晶化，该加热温度大概需要800℃，而若采用氧化锌作为诱导层薄膜2的材料对氧化物半导体薄膜3进行诱导之后，再对氧化物半导体薄膜3进行退火处理以使其晶化，该退火温度为300～500℃，故极大地降低了工艺难度。
本实施例的氧化物半导体薄膜3的制备方法采用诱导层薄膜2对形成在诱导层薄膜2上的氧化物半导体薄膜3进行诱导，使氧化物半导体薄膜3按照诱导层薄膜2的晶向进行生长，得到多晶氧化物半导体薄膜，或者C轴晶向择优生长的氧化物半导体薄膜，该制备方法中氧化物半导体薄膜的晶化温度较低，故该制备方法的工艺难度较低，且可以得到性能优化的氧化物半导体薄膜3。
实施例2：
如图2所示，本实施例提供了一种氧化物半导体薄膜3的制备方法，包括如下步骤一至步骤三。
步骤一、在基底1上，采用溅射、热蒸发、等离子体增强化学气相沉积、低压化学气相沉积、大气压化学气相沉积或电子回 旋谐振化学气相沉积等方法，形成缓冲层4。
其中，缓冲层4包括氧化硅或氮化硅形成的至少一层结构，厚度优选为150～300nm。之所以制备如此厚的缓冲层4是为了形成有效的阻热层，起到保温的作用，以使在后续步骤中形成的氧化物半导体薄膜3能够充分晶化。
步骤二、在完成上述步骤一的基底1上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射或者溶胶-凝胶等制备方法，形成诱导层薄膜2，并对形成的诱导层薄膜2进行退火处理，退火温度为300～600℃，以使诱导层薄膜2充分晶化，以便在后续步骤中更好地诱导氧化物半导体薄膜3并使其晶化。
其中，该诱导层薄膜2的材料优选为氧化锌(ZnO)，厚度优选在5～50nm的范围内。需要说明的是，诱导层薄膜2由于材料本身的原因，至少部分材料在沉积的过程中就已经发生了晶化，而后再对诱导层薄膜2进行退火处理，以使诱导层薄膜2充分晶化，故步骤二中形成的诱导层薄膜2可以理解为晶化的诱导层薄膜2。
步骤三、在完成上述步骤二的基底1上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等制备方法，形成氧化物半导体薄膜3，并进行退火处理，退火温度为300～500℃，使得氧化物半导体薄膜3在诱导层薄膜2的诱导下晶化，具体为，使氧化物半导体薄膜3转化为多晶氧化物半导体薄膜，或者C轴晶向择优生长的氧化物半导体薄膜。
其中，氧化物半导体薄膜3的材料可以包含In(铟)、Ga(镓)、Zn(锌)、O(氧)和Sn(锡)等元素中的至少三种，并通过溅射等工艺形成在完成上述步骤二的基底1上。而且，氧化物半导体薄膜3中必须包含氧元素和其他两种或两种以上的元素，如包括氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)、氧化铟锌(Indium Zinc Oxide，IZO)、氧化铟锡(Indium Tin Oxide，ITO)或氧化铟镓锡(Indium Gallium Tin Oxide，IGTO)等。氧化物半 导体薄膜3的材料优选为IGZO或IZO，厚度优选控制在30～200nm的范围内。
本实施例的氧化物半导体薄膜3的制备方法采用诱导层薄膜2对形成在诱导层薄膜2上的氧化物半导体薄膜3进行诱导，使氧化物半导体薄膜3按照诱导层薄膜2的晶向进行生长，得到多晶氧化物半导体薄膜，或者C轴晶向择优生长的氧化物半导体薄膜，特别地，在沉积诱导层薄膜2之前还形成有缓冲层4(即缓冲层4形成在基底1与诱导层薄膜2之间)，以形成有效的阻热层，使得在后续步骤中形成的氧化物半导体薄膜3能够充分晶化，该制备方法中氧化物半导体薄膜的晶化温度较低，故该制备方法的工艺难度较低，且可以得到性能优化的氧化物半导体薄膜3。
实施例3：
如图3所示，本实施例提供了一种薄膜晶体管的制备方法，其包括实施例1或2中形成氧化物半导体薄膜的步骤。具体地，以制备底栅型薄膜晶体管为例进行说明。
需要说明的是，在本发明实施例中，构图工艺，可只包括光刻工艺，或，包括光刻工艺和刻蚀工艺，此外，还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所需形成的结构来选择相应的构图工艺。
所述底栅型薄膜晶体管的制备方法包括如下步骤一至步骤四。
步骤一、在基底1上，采用磁控溅射的方法沉积一层栅极金属层薄膜，并通过构图工艺形成包括薄膜晶体管栅极5的图形。
其中，所述栅极金属层薄膜可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的单层或它们中的多种材料形成的多层复合叠层，优选为Mo、Al或含Mo、Al的合金形成的单层膜或它们中的多种材料形成的多层复合膜。
步骤二、在完成上述步骤一的基底1上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子体辅助化学气相淀积、溅射等制备方法形成栅极绝缘层6。
其中，栅极绝缘层6可以为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或任意两种材料形成的多层复合膜。
步骤三、在完成上述步骤二的基底1上，依次形成诱导层薄膜2和氧化物半导体薄膜3，并对该氧化物半导体薄膜3进行退火处理，以形成晶化的氧化物半导体薄膜。
其中，该步骤三可以采用实施例1中的制备方法来实现，也可以采用实施例2中的制备方法来实现，在此不再对该步骤三进行详细的描述。因为在氧化物半导体薄膜3下方已设置有栅极绝缘层6，该栅极绝缘层6可以起到与缓冲层4同样的保温作用，故该步骤三中可省略缓冲层4的制作步骤。
步骤四、在完成上述步骤三的基底1上，先形成源漏金属层薄膜70，再涂覆光刻胶80，并采用半色调掩模板或者灰阶掩模板进行曝光，以形成包括薄膜晶体管的有源层20、源极7-1和漏极7-2的图形，其中有源层20为结晶的有源层，且源极7-1通过源接触区、漏极7-2通过漏接触区与有源层20接触。
其中，所述源漏金属层薄膜70可以由钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成，优先由Mo、Al或含Mo、Al的合金形成。
至此完成底栅型薄膜晶体管的制备。在该薄膜晶体管的基础上还可以依次形成钝化层9和像素电极10，并使像素电极10与漏极7-2相接触，以形成阵列基板，如图4所示。
在本实施例中，结晶的有源层是在诱导层薄膜的诱导作用下形成的，因此无需高温处理就可使得氧化物半导体薄膜晶化，并在后续步骤中形成为结晶的有源层，而且也无需形成刻蚀阻挡层，进而使得制备工艺更容易实现。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种氧化物半导体薄膜的制备方法，其特征在于，包括如下步骤：
    在基底上形成诱导层薄膜；
    在形成有所述诱导层薄膜的基底上，形成氧化物半导体薄膜，并进行退火处理，以使所述氧化物半导体薄膜晶化。
  2. 根据权利要求1所述的氧化物半导体薄膜的制备方法，其特征在于，在所述形成氧化物半导体薄膜的步骤之前还包括：
    对形成的诱导层薄膜进行退火处理。
  3. 根据权利要求2所述的氧化物半导体薄膜的制备方法，其特征在于，在对形成的诱导层薄膜进行退火处理时，退火温度为300℃至600℃。
  4. 根据权利要求1所述的氧化物半导体薄膜的制备方法，其特征在于，所述诱导层薄膜的厚度为5nm至50nm；所述氧化物半导体薄膜的厚度为30nm至200nm。
  5. 根据权利要求1所述的氧化物半导体薄膜的制备方法，其特征在于，在对所述氧化物半导体薄膜进行退火处理时，退火温度为300℃至500℃。
  6. 根据权利要求1-5中任一项所述的氧化物半导体薄膜的制备方法，其特征在于，在所述形成诱导层薄膜的步骤之前还包括：
    在基底上形成缓冲层，
    所述诱导层薄膜形成在所述缓冲层上。
  7. 根据权利要求6所述的氧化物半导体薄膜的制备方法，其 特征在于，所述缓冲层包括氧化硅或氮化硅形成的至少一层结构。
  8. 根据权利要求6所述的氧化物半导体薄膜的制备方法，其特征在于，所述缓冲层的厚度为150nm至300nm。
  9. 根据权利要求1-5中任一项所述的氧化物半导体薄膜的制备方法，其特征在于，所述诱导层薄膜的材料为氧化锌。
  10. 根据权利要求1-5中任一项所述的氧化物半导体薄膜的制备方法，其特征在于，所述氧化物半导体薄膜的材料为氧化铟镓锌、氧化铟锌、氧化铟锡、氧化铟镓锡中的任意一种。
  11. 根据权利要求1-5中任一项所述的氧化物半导体薄膜的制备方法，其特征在于，所述使氧化物半导体薄膜晶化具体为：使氧化物半导体薄膜转化为多晶氧化物半导体薄膜，或者C轴晶向择优生长的氧化物半导体薄膜。
  12. 一种薄膜晶体管的制备方法，其包括形成有源层的步骤，其特征在于，所述形成有源层的步骤包括：
    在基底上形成诱导层薄膜；
    在形成有所述诱导层薄膜的基底上，形成氧化物半导体薄膜，并进行退火处理，以使所述氧化物半导体薄膜晶化；
    对形成有晶化的氧化物半导体薄膜的基底采用构图工艺形成包括有源层的图形。
  13. 根据权利要求12所述的薄膜晶体管的制备方法，其特征在于，在所述形成诱导层薄膜的步骤之前还包括：
    在基底上，通过构图工艺形成包括薄膜晶体管栅极的图形；
    在形成有栅极的基底上，形成栅极绝缘层，
    所述诱导层薄膜形成在栅极绝缘层上。
  14. 根据权利要求12所述的薄膜晶体管的制备方法，其特征在于，在使所述氧化物半导体薄膜晶化后，在形成所述有源层的图形的同时，所述制备方法还包括：
    在形成有晶化的氧化物半导体薄膜的基底上形成源漏金属薄膜，并通过构图工艺形成包括源极和漏极的图形。
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