WO2015161619A1 - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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WO2015161619A1
WO2015161619A1 PCT/CN2014/086701 CN2014086701W WO2015161619A1 WO 2015161619 A1 WO2015161619 A1 WO 2015161619A1 CN 2014086701 W CN2014086701 W CN 2014086701W WO 2015161619 A1 WO2015161619 A1 WO 2015161619A1
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layer film
active layer
oxide active
inducing
substrate
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PCT/CN2014/086701
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English (en)
French (fr)
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王东方
陈江博
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京东方科技集团股份有限公司
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Priority to US14/435,772 priority Critical patent/US9754970B2/en
Publication of WO2015161619A1 publication Critical patent/WO2015161619A1/zh

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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
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    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the invention belongs to the technical field of display device manufacturing, and particularly relates to a thin film transistor and a preparation method thereof, an array substrate and a display device.
  • oxide thin film transistors are increasingly used by people because of their high electron mobility, low preparation temperature, good uniformity, transparency to visible light, and low threshold voltage. .
  • an etch stop layer is added to protect the oxide active layer.
  • the inventors have found that at least the following problems exist in the prior art: the addition of an etch barrier layer increases the fabrication process of the oxide thin film transistor, and if the fabrication of the etch barrier layer is not controlled, for example, The thickness of the etch stop layer is not uniform, which may affect the characteristics of the oxide thin film transistor. Therefore, the manufacturing process of the oxide thin film transistor not only becomes complicated, the manufacturing cost increases, and the productivity and yield of the manufactured array substrate are lowered.
  • the oxide active layer of the oxide thin film transistor uses a crystalline oxide active layer, but the crystallization temperature is high, and it is easy It affects other film layers, so reducing the crystallization temperature of the oxide active layer is expected for the application of the oxide thin film transistor.
  • the technical problems to be solved by the present invention include: targeting existing thin film transistors
  • the above problems existing in the preparation provide a thin film transistor which reduces the crystallization temperature of the oxide active layer in the preparation process, a method for fabricating the same, an array substrate, and a display device.
  • the present invention provides a method of fabricating a thin film transistor, comprising the steps of: forming an inducing layer film on a substrate and an oxide active layer film in contact therewith, the oxide active layer film being located above or below the inducing layer film; The substrate of the step is heated, and the oxide active layer film is crystallized by the induction of the inducing layer film to form a crystalline oxide active layer.
  • the crystalline oxide active layer formed in the method for producing a thin film transistor of the embodiment of the present invention is formed by inducing an effect of inducing a thin film, in which case the oxide active layer (thin film) can be crystallized without requiring high temperature, thereby The preparation process is easier to implement.
  • the step of forming an inducing layer film on the substrate and the oxide active layer film in contact therewith may include sequentially forming the inducing layer film and the oxide active layer film on the substrate .
  • the method further comprises: forming a pattern including a gate electrode by a patterning process on the substrate.
  • the step of crystallizing the oxide active layer film by the induction of the inducing layer film to form the crystalline oxide active layer includes: forming a substrate on which the inducing layer film and the oxide active layer film are sequentially formed Heating, the oxide active layer film is crystallized by the induction of the inducing layer film to form a crystalline oxide active layer film, and the inducing layer film is formed as an oxide inducing layer; and On the substrate of the step, a pattern including the crystalline oxide active layer is formed by a patterning process.
  • the step of crystallizing the oxide active layer film by the induction of the inducing layer film to form the crystalline oxide active layer includes: a substrate in which the inducing layer film and the oxide active layer film are sequentially formed Forming a patterned oxide active layer film by a patterning process; and heating the substrate performing the above steps to crystallize the patterned oxide active layer film by the induction of the inducing layer film.
  • the crystalline oxide active layer is formed, and the inducing layer film is formed as an oxide inducing layer.
  • the step of forming an inducing layer film on the substrate and the oxide active layer film in contact therewith may include sequentially forming the oxide active layer film and the inducing layer film on the substrate .
  • the step of crystallizing the oxide active layer film by the induction of the inducing layer film to form the crystalline oxide active layer includes: a substrate on which the oxide active layer film and the inducing layer film are sequentially formed Heating, the oxide active layer film is crystallized by the induction of the inducing layer film to form a crystalline oxide active layer film, and the inducing layer film is formed as an oxide inducing layer film; and is completed On the substrate of the above step, a pattern including the crystalline oxide active layer and the oxide inducing layer is formed by a patterning process.
  • forming the crystalline oxide active layer and the oxide inducing layer further comprising: forming a pattern including a gate by a patterning process.
  • the material of the inducing layer film may be a metal having a hexagonal lattice structure or a hexagonal lattice-derived structure
  • the step of forming the crystalline oxide active layer includes: forming the induced layer film and the oxide
  • the substrate of the active layer film is placed in an oxygen-containing gas atmosphere and heated so that the oxide active layer film is formed as the crystalline oxide active layer film under the action of the inducing layer film.
  • the metal having a hexagonal lattice structure or a hexagonal lattice-derived structure is any one of aluminum, magnesium, and titanium.
  • the heating temperature (crystallization temperature) in the step of forming the crystalline oxide active layer ranges from 450 ° C to 700 ° C, and the oxygen content of the oxygen-containing gas is from 5% to 40%.
  • the material of the inducing layer film may be an insulating non-metal having a hexagonal lattice structure or a hexagonal lattice-derived structure.
  • the insulating non-metal having a hexagonal lattice structure or a hexagonal lattice-derived structure is any one of alumina, magnesia, cerium oxide, zirconium oxide, and titanium oxide.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, comprising the steps of: forming an inducing layer film on a substrate and an oxide active layer film in contact therewith, the oxide active layer film being located above or below the inducing layer film, and passing Forming a pattern to form a patterned inducing layer film and a patterned oxide active layer film; and heating the substrate for performing the above steps, by inducing the patterned inducing layer
  • the patterned oxide active layer film is crystallized to form a crystalline oxide active layer.
  • the step of forming the patterned inducing layer film and the patterned oxide active layer film may include sequentially forming the inducing layer film and the oxide active layer film on a substrate And forming the patterned inducing layer film and the patterned oxide active layer film by a patterning process on the substrate on which the above steps are completed.
  • the method further comprises: forming a pattern including the gate electrode by a patterning process on the substrate.
  • the step of forming the patterned inducing layer film and the patterned oxide active layer film may include sequentially forming the oxide active layer film and the inducing layer film on a substrate And forming the patterned inducing layer film and the patterned oxide active layer film by a patterning process on the substrate on which the above steps are completed.
  • the method further includes: forming a pattern including the gate by a patterning process.
  • the material of the inducing layer film may be a metal having a hexagonal lattice structure or a hexagonal lattice-derived structure
  • the step of forming the crystalline oxide active layer includes: forming the patterned inducing layer film and the The substrate of the patterned oxide active layer film is placed in an oxygen-containing gas atmosphere and heated such that the patterned oxide active layer film is formed under the action of the patterned inducing layer film
  • the oxide active layer is crystallized, and the patterned inducing layer film is formed as an oxide inducing layer.
  • the metal having a hexagonal lattice structure or a hexagonal lattice-derived structure is any one of aluminum, magnesium, and titanium.
  • the heating temperature in the step of forming the crystalline oxide active layer ranges from 450 ° C to 700 ° C, and the oxygen content of the oxygen-containing gas is from 5% to 40%.
  • the material of the inducing layer film may be an insulating non-metal having a hexagonal lattice structure or a hexagonal lattice-derived structure.
  • the insulating non-metal having a hexagonal lattice structure or a hexagonal lattice-derived structure is Any one of alumina, magnesia, cerium oxide, zirconium oxide, and titanium oxide.
  • the present invention also provides a thin film transistor which is prepared by the above preparation method.
  • the present invention also provides an array substrate comprising the above thin film transistor.
  • the present invention also provides a display device including the above array substrate.
  • FIGS. 1A to 1E are flowcharts showing a method of manufacturing a thin film transistor of Embodiment 1 of the present invention.
  • FIGS. 2A to 2E are flowcharts showing a method of manufacturing a thin film transistor of Embodiment 4 of the present invention.
  • the present embodiment provides a method for fabricating a thin film transistor, which may be a top gate thin film transistor or a bottom gate thin film transistor, which can be understood by those skilled in the art.
  • the main difference between the gate thin film transistor and the bottom gate thin film transistor is that the gate 2 of the top gate thin film transistor is disposed above the active layer (the crystalline oxide active layer 5), and the gate of the bottom gate thin film transistor The pole 2 is disposed under the active layer (the crystalline oxide active layer 5), and the other layers of the thin film transistor are not greatly different.
  • the preparation method of the bottom-gate thin film transistor will be described as an example. The method specifically includes the following steps 1 to 5.
  • Step 1 Depositing a gate metal layer film on the substrate 1 by magnetron sputtering, and forming a pattern of a metal layer including the gate electrode 2 of the thin film transistor and the gate line (not shown) by a patterning process, such as Figure 1A shows.
  • the substrate 1 may refer to a substrate that does not form any film layer, such as white glass, and may also refer to a substrate formed with other film layers or patterns, for example, forming.
  • the patterning process generally includes processes such as photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the above steps include: first forming a gate metal layer film, coating a photoresist to cover the gate metal layer film; exposing by using a mask to form an exposed region and a non-exposed region; performing development to remove the exposed region of the photoresist ( A positive photoresist is taken as an example), and the photoresist in the non-exposed area is left; the gate metal film is etched, and the gate metal film of the non-exposed area is not etched due to the protection of the photoresist; The photoresist forms a pattern including the gate electrode 2 of the thin film transistor and the gate metal layer of the gate line.
  • the gate metal layer film may be one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu) or among them.
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • Al aluminum
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • Step 2 on the substrate 1 which completes the above steps, using thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, etc., sequentially forming the inducing layer film 3 and located in the induction
  • the oxide active layer film 4 above and in contact with the layer film 3 is as shown in Figs. 1B and 1C.
  • the material of the inducing layer film 3 may be a metal material having a hexagonal lattice structure or a hexagonal lattice-derived structure, such as aluminum, magnesium, titanium or the like which can be oxidized to a metal having superior insulating properties. Further, the material of the inducing layer film 3 may also be a non-metal material having a hexagonal lattice structure or a hexagonal lattice-derived structure, such as alumina, magnesia, cerium oxide, zirconium oxide, titanium oxide, or the like.
  • the oxide active layer film 4 may be a film containing elements such as In (indium), Ga (gallium), Zn (zinc), O (oxygen), and Sn (tin) formed by sputtering, and the film must contain oxygen. And two or more other elements, for example, the oxide active layer film 4 may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO) Any of the materials. In the present embodiment, the material of the oxide semiconductor active layer is, for example, IGZO and IZO, and the thickness thereof is controlled to be 10 to 100 nm.
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • InSnO indium tin oxide
  • InGaSnO indium gallium tin oxide
  • the material of the oxide semiconductor active layer is, for example, IGZO and IZO, and the thickness thereof is controlled to be 10
  • Step 3 heating the substrate 1 which has completed the above steps, and crystallization of the oxide active layer film 4 to form a crystalline oxide by inducing the induction of the thin film 3 Active layer film.
  • the step of forming the crystalline oxide active layer film specifically includes: placing the substrate 1 on which the metal Al inducing layer film 3 and the IGZO oxide active layer film 4 are formed in an oxygen-containing gas atmosphere and heating, the temperature.
  • the range is from 450 ° C to 700 ° C, the time may be selected from 10 minutes to 2 hours depending on the temperature, and the oxygen content of the oxygen-containing gas is from 5% to 40%, so that the IGZO oxide active layer film 4 is in the metal Al-inducing layer film.
  • the film is formed as a crystalline IGZO oxide active layer film by the action of 3, and the metal Al-inducing layer film 3 is formed as a dense Al 2 O 3 oxide inducing layer 7. Since Al 2 O 3 is an insulating layer material, it also functions as a gate insulating layer.
  • the non-metal inducing layer film 3 and the oxide active layer film 4 may be directly heated at this time to The oxide active layer film 4 is crystallized into a crystalline oxide active layer film.
  • the non-metal oxide inducing layer 7 is also an insulating layer, and can also function as a gate insulating layer.
  • Step 4 For the substrate 1 which has completed the above steps, a pattern including the crystalline oxide active layer 5 is formed by a patterning process as shown in FIG. 1D.
  • Step 5 forming a source/drain metal layer film on the substrate 1 that completes the above steps, and forming a pattern including the source 6-1 and the drain 6-2 of the thin film transistor by a patterning process, and the source 6-1, the drain The pole 6-2 is in contact with the crystalline oxide active layer 5 through the source and drain contact regions, respectively, as shown in Fig. 1E.
  • the source/drain metal layer film may be one or more materials selected from the group consisting of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu). It is formed, for example, of Mo, Al, or an alloy material containing Mo or Al.
  • the crystalline oxide active layer 5 is formed by inducing the induction of the thin film 3, in which case the oxide active layer (film) 4 can be crystallized without requiring high temperature, thereby making the preparation process easier. achieve.
  • the present embodiment provides a method for fabricating a thin film transistor similar to that of the first embodiment.
  • the difference between the embodiment and the first embodiment is that the third step and the fourth step of the first embodiment are replaced in the embodiment:
  • the induced layer film 3 and the substrate 1 of the oxide active layer film 4 located above and in contact with the inducing layer film 3 are patterned to form a patterned oxide active layer film 4; and by inducing the formation of the film 3
  • the effect causes the patterned oxide active layer film 4 to be crystallized to form the crystalline oxide active layer 5.
  • the materials of the inducing layer film 3 and the oxide active layer film 4 are the same as those in the embodiment 1, and the method of induction is also the same. In the present embodiment, simply, step three and step four in the embodiment 1 are reversed.
  • This embodiment provides a method for fabricating a thin film transistor similar to that of Embodiment 1.
  • This embodiment differs from Embodiment 1 in that step 2 of Embodiment 1 is replaced by the following steps in the present embodiment: forming a gate insulating layer And sequentially depositing an oxide active layer film 4 and an inducing layer film 3 located above and in contact with the oxide active layer film 4; heating the substrate 1 which completes the above steps, causing oxides by inducing the induction of the film 3
  • the source layer film 4 is crystallized to form a crystalline oxide active layer film; and a pattern including the oxide inducing layer 7 and the crystalline oxide active layer 5 is formed by a patterning process.
  • the oxide inducing layer 7 is disposed above the crystalline oxide active layer 5.
  • the pattern of the oxide inducing layer 7 and the pattern of the crystalline oxide active layer 5 may overlap each other in a direction perpendicular to the substrate 1.
  • the material of each layer of the thin film transistor and the preparation method of the other film layers are the same as in the first embodiment.
  • the present embodiment provides a method for fabricating a thin film transistor.
  • the steps shown in FIG. 2A to FIG. 2C are similar to the first to third embodiments, except that the preparation method is further Includes the following steps.
  • a patterned inducing layer film 3 and a patterned oxide active layer are formed by a patterning process.
  • Film 4 is shown in Figure 2D.
  • the patterned inducing layer film 3 is formed as an oxide inducing layer 7, as shown in Fig. 2E.
  • a thin film of source and drain metal layers is deposited, and a pattern including a source 6-1 and a drain 6-2 of the thin film transistor is formed by a patterning process, and a source 6-1 and a drain 6- are formed.
  • 2 is in contact with the crystalline oxide active layer 5 through the source and drain contact regions, respectively, as shown in Fig. 2E.
  • an inducing layer film 3 and an oxide active layer film 4 are sequentially deposited on a substrate 1 on which a gate electrode 2 is formed, and a patterned inducing layer is formed by a patterning process.
  • the film 3 and the patterned oxide active layer film 4. The substrate 1 is then heated to form a crystalline oxide active layer 5 and an oxide inducing layer 7. That is, the oxide inducing layer 7 is provided under the crystalline oxide active layer 5. Since the oxide inducing layer 7 is insulative, it is not necessary to prepare a gate insulating layer as a bottom gate type thin film transistor at this time.
  • an oxide active layer film 4 and an inducing layer film 3 may be sequentially deposited on the substrate 1 on which the gate electrode 2 is formed, and a patterned inducing layer film 3 and patterning are formed by a patterning process.
  • the oxide active layer film 4 is then heated, and the patterned oxide active layer film 4 is crystallized to form crystals under the induction of the patterned inducing layer film 3.
  • the oxide active layer 5 is formed, and the patterned inducing layer film 3 is formed as an oxide inducing layer 7. That is, at this time, the oxide inducing layer 7 is provided over the crystalline oxide active layer 5.
  • a gate insulating layer is further formed after the gate electrode 2 is formed to electrically isolate the gate electrode 2 from the crystalline oxide active layer 5.
  • the pattern of the oxide inducing layer 7 and the pattern of the crystalline oxide active layer 5 may overlap each other in a direction perpendicular to the substrate 1.
  • the bottom gate type thin film crystal is used.
  • the preparation method of the tube is described as an example.
  • the top gate type thin film transistor can also be prepared by the above method. The most important difference between the two is that the order of preparing the crystalline oxide active layer 5 and the gate electrode 2 is different. It is to be noted that, in the preparation of the top gate type thin film transistor, if the oxide inducing layer 7 formed is disposed over the crystalline oxide active layer 5, since the oxide inducing layer 7 functions as a gate insulating layer, It is not necessary to prepare a gate insulating layer between the crystalline oxide active layer 5 and the gate electrode 2. The other preparation steps are similar to those of the bottom gate type thin film transistor and will not be described in detail herein.
  • This embodiment provides a thin film transistor which is prepared by any one of the methods 1 to 4.
  • the thin film transistor in this embodiment may be of a top gate type or a bottom gate type.
  • the crystal oxide active layer can be prepared without excessively high temperature in the process, thereby making the process easier to implement.
  • This embodiment provides an array substrate including the thin film transistor described in Embodiment 5.
  • This embodiment provides a display device including the array substrate described in Embodiment 6.
  • the display device can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种薄膜晶体管及其制备方法、阵列基板、显示装置。该薄膜晶体管的制备方法包括：在基底（1）上形成诱导层薄膜（3）和与其接触的氧化物有源层薄膜（4），氧化物有源层薄膜（4）位于诱导层薄膜（3）上方或下方；以及对完成上述步骤的基底（1）进行加热，通过诱导层薄膜（3）的诱导作用使得氧化物有源层薄膜（4）晶化以形成结晶氧化物有源层（5）。

Description

薄膜晶体管及其制备方法、阵列基板、显示装置 技术领域
本发明属于显示装置制造技术领域，具体涉及薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
随着显示技术的不断发展，由于氧化物薄膜晶体管具有电子迁移率高、制备温度低、均一性好、对可见光透明、以及阈值电压低等特点，氧化物薄膜晶体管越来越受到人们的广泛使用。
现有技术中在制造氧化物薄膜晶体管时，由于氧化物薄膜晶体管的氧化物有源层的材料为金属氧化物，故其稳定性差，易受到刻蚀环境中氧气、氢气及水的影响。因此，为了防止在刻蚀氧化物薄膜晶体管的源极和漏极时氧化物有源层受到影响，增设了刻蚀阻挡层(Etch Stop Layer，ESL)以用来保护氧化物有源层。
发明人发现，现有技术中至少存在如下问题：由于增设了刻蚀阻挡层，即增加了氧化物薄膜晶体管的制备工艺步骤，此时若刻蚀阻挡层的制作环节控制不到位，例如制作出的刻蚀阻挡层的厚度不均一，则可能影响氧化物薄膜晶体管的特性。因此，氧化物薄膜晶体管的制造工艺不仅变得复杂、制造成本增加，同时制造的阵列基板的产能及良品率降低。为了解决现有技术中氧化物薄膜晶体管中需要设置刻蚀阻挡层的问题，一般，氧化物薄膜晶体管的氧化物有源层采用结晶的氧化物有源层，但是晶化温度很高，很容易对其他膜层产生影响，因此降低氧化物有源层的晶化温度对于氧化物薄膜晶体管的应用备受期待。
发明内容
本发明所要解决的技术问题包括，针对现有的薄膜晶体管制 备中存在的上述的问题，提供一种在制备过程中降低氧化物有源层的晶化温度的薄膜晶体管及其制备方法、阵列基板、显示装置。
本发明提供一种薄膜晶体管的制备方法，包括步骤：在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜，氧化物有源层薄膜位于诱导层薄膜上方或下方；以及对完成上述步骤的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述氧化物有源层薄膜晶化以形成结晶氧化物有源层。
本发明实施例的薄膜晶体管的制备方法中形成的结晶氧化物有源层是通过诱导层薄膜的诱导作用形成的，此时无需高温也能够使得氧化物有源层(薄膜)晶化，从而使得制备工艺更容易实现。
在所述制备方法中，所述在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜的步骤可以包括：在基底上依次形成所述诱导层薄膜和所述氧化物有源层薄膜。
在基底上依次形成所述诱导层薄膜和所述氧化物有源层薄膜之前还包括：在基底上通过构图工艺形成包括栅极的图形。
所述通过诱导层薄膜的诱导作用使得氧化物有源层薄膜晶化以形成结晶氧化物有源层的步骤包括：对依次形成有所述诱导层薄膜和所述氧化物有源层薄膜的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述氧化物有源层薄膜晶化以形成结晶氧化物有源层薄膜，并且所述诱导层薄膜形成为氧化物诱导层；以及在完成上述步骤的基底上，通过构图工艺形成包括所述结晶氧化物有源层的图形。
所述通过诱导层薄膜的诱导作用使得氧化物有源层薄膜晶化以形成结晶氧化物有源层的步骤包括：在依次形成有所述诱导层薄膜和所述氧化物有源层薄膜的基底上，通过构图工艺形成图形化的氧化物有源层薄膜；以及对完成上述步骤的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述图形化的氧化物有源层薄膜晶化以形成所述结晶氧化物有源层，并且所述诱导层薄膜形成为氧化物诱导层。
在所述制备方法中，所述在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜的步骤可以包括：在基底上依次形成所述氧化物有源层薄膜和所述诱导层薄膜。
所述通过诱导层薄膜的诱导作用使得氧化物有源层薄膜晶化以形成结晶氧化物有源层的步骤包括：对依次形成有所述氧化物有源层薄膜和所述诱导层薄膜的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述氧化物有源层薄膜晶化以形成结晶氧化物有源层薄膜，并且所述诱导层薄膜形成为氧化物诱导层薄膜；以及在完成上述步骤的基底上，通过构图工艺形成包括所述结晶氧化物有源层和氧化物诱导层的图形。
在形成所述结晶氧化物有源层和所述氧化物诱导层之后还包括：通过构图工艺形成包括栅极的图形。
所述诱导层薄膜的材料可以为具有六方晶格结构或六方晶格衍生结构的金属，并且所述形成结晶氧化物有源层的步骤包括：将形成有所述诱导层薄膜和所述氧化物有源层薄膜的基底置于含氧气体气氛并进行加热，使得所述氧化物有源层薄膜在所述诱导层薄膜的作用下形成为所述结晶氧化物有源层薄膜。
所述具有六方晶格结构或六方晶格衍生结构的金属为铝、镁、钛中的任意一种。
所述形成结晶氧化物有源层的步骤中的加热温度(晶化温度)的范围为450℃～700℃、含氧气体的氧气含量为5％～40％。
所述诱导层薄膜的材料可以为具有六方晶格结构或六方晶格衍生结构的绝缘非金属。
所述具有六方晶格结构或六方晶格衍生结构的绝缘非金属为氧化铝、氧化镁、氧化钆、氧化锆、氧化钛中的任意一种。
本发明实施例提供一种薄膜晶体管的制备方法，包括步骤：在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜，氧化物有源层薄膜位于诱导层薄膜上方或下方，并且通过构图工艺形成图形化的诱导层薄膜和图形化的氧化物有源层薄膜；以及对完成上述步骤的基底进行加热，通过所述图形化的诱导层的诱导作 用使得所述图形化的氧化物有源层薄膜晶化以形成结晶氧化物有源层。
在所述制备方法中，所述形成图形化的诱导层薄膜和图形化的氧化物有源层薄膜的步骤可以包括：在基底上依次形成所述诱导层薄膜和所述氧化物有源层薄膜；以及在完成上述步骤的基底上，通过一次构图工艺形成所述图形化的诱导层薄膜和所述图形化的氧化物有源层薄膜。
在基底上形成所述诱导层薄膜之前还包括：在基底上通过构图工艺形成包括栅极的图形。
在所述制备方法中，所述形成图形化的诱导层薄膜和图形化的氧化物有源层薄膜的步骤可以包括：在基底上依次形成所述氧化物有源层薄膜和所述诱导层薄膜；以及在完成上述步骤的基底上，通过一次构图工艺形成所述图形化的诱导层薄膜和所述图形化的氧化物有源层薄膜。
在形成所述结晶氧化物有源层的图形之后还包括：通过构图工艺形成包括栅极的图形。
所述诱导层薄膜的材料可以为具有六方晶格结构或六方晶格衍生结构的金属，并且所述形成结晶氧化物有源层的步骤包括：将形成有所述图形化的诱导层薄膜和所述图形化的氧化物有源层薄膜的基底置于含氧气体气氛并进行加热，使得所述图形化的氧化物有源层薄膜在所述图形化的诱导层薄膜的作用下形成为所述结晶氧化物有源层，并且所述图形化的诱导层薄膜形成为氧化物诱导层。
所述具有六方晶格结构或六方晶格衍生结构的金属为铝、镁、钛中的任意一种。
所述形成结晶氧化物有源层的步骤中的加热温度的范围为450℃～700℃、含氧气体的氧气含量为5％～40％。
所述诱导层薄膜的材料可以为具有六方晶格结构或六方晶格衍生结构的绝缘非金属。
所述具有六方晶格结构或六方晶格衍生结构的绝缘非金属为 氧化铝、氧化镁、氧化钆、氧化锆、氧化钛中的任意一种。
本发明还提供一种薄膜晶体管，该薄膜晶体管是由上述制备方法制备的。
本发明还提供一种阵列基板，其包括上述薄膜晶体管。
本发明还提供一种显示装置，其包括上述阵列基板。
附图说明
图1A至图1E为本发明的实施例1的薄膜晶体管的制备方法的流程图。
图2A至图2E为本发明的实施例4的薄膜晶体管的制备方法的流程图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
结合图1A至图1E所示，本实施例提供一种薄膜晶体管的制备方法，该薄膜晶体管可以为顶栅型薄膜晶体管也可以为底栅型薄膜晶体管，本领域技术人员可以理解的是，顶栅型薄膜晶体管与底栅型薄膜晶体管的最主要的区别是，顶栅型薄膜晶体管的栅极2设于有源层(结晶氧化物有源层5)上方，而底栅型薄膜晶体管的栅极2设于有源层(结晶氧化物有源层5)下方，薄膜晶体管的其他膜层并无较大区别。下述方法中仅仅是以底栅型薄膜晶体管的制备方法为例进行说明。该方法具体包括以下步骤一至步骤五。
步骤一、在基底1上采用磁控溅射的方法沉积一层栅极金属层薄膜，通过构图工艺形成包括薄膜晶体管的栅极2以及栅极线(未图示)的金属层的图形，如图1A所示。
需要说明的是，基底1既可以指没有形成任何膜层的基底，如白玻璃，也可以指形成有其他膜层或者图案的基底，例如形成 有缓冲层的基底。构图工艺通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。上述步骤即包括：先形成栅极金属层薄膜，涂覆光刻胶覆盖栅极金属层薄膜；利用掩模板曝光，形成曝光区和非曝光区；进行显影以去除曝光区的光刻胶(以正性光刻胶为例)，并且保留非曝光区的光刻胶；刻蚀栅极金属层薄膜，非曝光区的栅极金属层薄膜由于光刻胶的保护而未被刻蚀；最后剥离光刻胶，形成包括薄膜晶体管的栅极2以及栅极线的栅极金属层的图形。
所述栅极金属层薄膜可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中的多种形成的单层或多层复合叠层，例如为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
步骤二、在完成上述步骤的基底1上，采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等制备方法，依次形成诱导层薄膜3和位于诱导层薄膜3上方并与其接触的氧化物有源层薄膜4，如图1B和图1C所示。
诱导层薄膜3的材料可以为具有六方晶格结构或六方晶格衍生结构的金属材料，该金属例如为铝、镁、钛等可氧化为具有优越的绝缘性能的金属。此外，诱导层薄膜3的材料也可以是具有六方晶格结构或六方晶格衍生结构的非金属材料，非金属材料例如为氧化铝、氧化镁、氧化钆、氧化锆、氧化钛等。
氧化物有源层薄膜4可以是通过溅射形成的包含In(铟)、Ga(镓)、Zn(锌)、O(氧)、Sn(锡)等元素的薄膜，薄膜中必须包含氧元素和其他两种或两种以上的元素，例如，氧化物有源层薄膜4可以包括氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化铟锡(InSnO)、氧化铟镓锡(InGaSnO)等中的任意一种材料。在本实施例中，氧化物半导体有源层的材料例如为IGZO和IZO，其厚度控制在10～100nm。
步骤三、对完成上述步骤的基底1进行加热，通过诱导层薄膜3的诱导作用使得氧化物有源层薄膜4晶化以形成结晶氧化物 有源层薄膜。
在所述诱导层薄膜3的材料为具有六方晶格结构或六方晶格衍生结构的金属的情况下，以金属铝(Al)做诱导层薄膜3的材料，IGZO做氧化物有源层薄膜4为例，上述形成结晶氧化物有源层薄膜的步骤具体包括：将形成有金属Al诱导层薄膜3和IGZO氧化物有源层薄膜4的基底1置于含氧气体气氛中并进行加热，温度范围为450℃～700℃、时间根据温度的不同可以选择为10分钟到2小时、含氧气体的氧气含量为5％～40％，使得IGZO氧化物有源层薄膜4在金属Al诱导层薄膜3的作用下形成为结晶IGZO氧化物有源层薄膜，同时金属Al诱导层薄膜3形成为致密Al2O3氧化物诱导层7。由于Al2O3为绝缘层物质，同时充当了栅极绝缘层的作用。
若所述诱导层薄膜3的材料为具有六方晶格结构或六方晶格衍生结构的非金属，此时可以直接对非金属的诱导层薄膜3和氧化物有源层薄膜4进行加热，以将氧化物有源层薄膜4晶化为结晶氧化物有源层薄膜。此时非金属氧化物诱导层7也是绝缘层，也可以充当栅极绝缘层的作用。
步骤四、对完成上述步骤的基底1，通过构图工艺形成包括结晶氧化物有源层5的图形，如图1D所示。
步骤五、在完成上述步骤的基底1上，形成源漏金属层薄膜，并通过构图工艺形成包括薄膜晶体管的源极6-1、漏极6-2的图形，且源极6-1、漏极6-2分别通过源、漏接触区与结晶氧化物有源层5接触，如图1E所示。
所述源漏金属层薄膜可以由钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成，例如由Mo、Al或含Mo、Al的合金材料形成。
在本实施例中，结晶氧化物有源层5是通过诱导层薄膜3的诱导作用形成的，此时无需高温也能够使得氧化物有源层(薄膜)4晶化，从而使得制备工艺更容易实现。
实施例2：
本实施例提供一种与实施例1相似的薄膜晶体管的制备方法，本实施例与实施例1的区别在于，实施例1的步骤三和步骤四在本实施例中替换为：在依次形成有诱导层薄膜3和位于诱导层薄膜3上方并与其接触的氧化物有源层薄膜4的基底1上，通过构图工艺形成图形化的氧化物有源层薄膜4；以及通过诱导层薄膜3的诱导作用使得所述图形化的氧化物有源层薄膜4晶化以形成结晶氧化物有源层5。
诱导层薄膜3和氧化物有源层薄膜4的材料与实施例1中的材料是一样的，诱导的方法也是相同的。在本实施例中，简单地说，就是将实施例1中的步骤三与步骤四颠倒。
实施例3：
本实施例提供一种与实施例1相似的薄膜晶体管的制备方法，本实施例与实施例1的区别在于，实施例1的步骤二在本实施例中替换为以下步骤：形成栅极绝缘层；依次沉积氧化物有源层薄膜4和位于氧化物有源层薄膜4上方并与其接触的诱导层薄膜3；对完成上述步骤的基底1加热，通过诱导层薄膜3的诱导作用使得氧化物有源层薄膜4晶化以形成结晶氧化物有源层薄膜；以及通过构图工艺形成包括氧化物诱导层7和结晶氧化物有源层5的图形。
在本实施例中，氧化物诱导层7设置在结晶氧化物有源层5上方。例如，氧化物诱导层7的图形和结晶氧化物有源层5的图形可以在垂直于基底1的方向上彼此重叠。薄膜晶体管的各层材料以及其他膜层的制备方法与实施例1是相同的。
实施例4：
结合图2A至图2E所示，本实施例提供一种薄膜晶体管的制备方法，该制备方法中的如图2A至图2C所示的步骤与实施例1～3相似，区别在于该制备方法还包括以下步骤。
在形成有诱导层薄膜3和位于诱导层薄膜3上方并与其接触的氧化物有源层薄膜4的基底1上，通过构图工艺形成图形化的诱导层薄膜3和图形化的氧化物有源层薄膜4，如图2D所示。
对该基底1进行加热，在所述图形化的诱导层薄膜3的诱导作用下使得所述图形化的氧化物有源层薄膜4晶化以形成为结晶氧化物有源层5，并且所述图形化的诱导层薄膜3形成为氧化物诱导层7，如图2E所示。
在完成上述步骤的基底1上，沉积源漏金属层薄膜，并通过构图工艺形成包括薄膜晶体管的源极6-1、漏极6-2的图形，且源极6-1、漏极6-2分别通过源、漏接触区与结晶氧化物有源层5接触，如图2E所示。
在所述制备方法中，如图2A至图2E所示，在形成有栅极2的基底1上依次沉积诱导层薄膜3和氧化物有源层薄膜4，通过构图工艺形成图形化的诱导层薄膜3和图形化的氧化物有源层薄膜4。然后对该基底1进行加热，从而形成结晶氧化物有源层5和氧化物诱导层7。也就是说，氧化物诱导层7设于结晶氧化物有源层5下方。由于氧化物诱导层7是绝缘的，此时作为底栅型薄膜晶体管，无需制备栅极绝缘层。
作为上述制备方法的一种变型例，在形成有栅极2的基底1上可以依次沉积氧化物有源层薄膜4和诱导层薄膜3，通过构图工艺形成图形化的诱导层薄膜3和图形化的氧化物有源层薄膜4，然后对该基底1进行加热，在所述图形化的诱导层薄膜3的诱导作用下使得所述图形化的氧化物有源层薄膜4晶化以形成为结晶氧化物有源层5，并且所述图形化的诱导层薄膜3形成为氧化物诱导层7。也就是说，此时氧化物诱导层7设于结晶氧化物有源层5上方。在该底栅型薄膜晶体管的变型例中，在形成栅极2后还需制备栅极绝缘层，以将栅极2与结晶氧化物有源层5电隔离。
在本实施例中，例如，氧化物诱导层7的图形和结晶氧化物有源层5的图形可以在垂直于基底1的方向上彼此重叠。
需要说明的是，在实施例1至4中仅仅是以底栅型薄膜晶体 管的制备方法为例进行说明的，当然也可以采用上述方法制备顶栅型薄膜晶体管，两者最主要的区别就是制备结晶氧化物有源层5与栅极2的顺序不同。还需要说明的是，在制备顶栅型薄膜晶体管时，若所形成的氧化物诱导层7设置在结晶氧化物有源层5的上方时，由于氧化物诱导层7用作栅极绝缘层，在结晶氧化物有源层5与栅极2之间无需再制备栅极绝缘层。其他制备步骤与底栅型薄膜晶体管的制备步骤相似，在此不详细描述。
实施例5：
本实施例提供一种薄膜晶体管，该薄膜晶体管是由实施例1～4中任意一种方法制备的。
本实施例中的薄膜晶体管可以是顶栅型也可以是底栅型。
由于该薄膜晶体管是采用实施例1～4中任意一种方法制备的，故其工艺上无需过高温度也能够制备结晶的氧化物有源层，从而使得工艺更容易实现。
实施例6：
本实施例提供一种阵列基板，该阵列基板包括实施例5中所述的薄膜晶体管。
在该阵列基板上还包括数据线、栅线等本领域技术人员所公知的其他结构，在此不详细描述。
实施例7：
本实施例提供一种显示装置，该显示装置包括实施例6中所述的阵列基板。
该显示装置可以应用于：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
此外，本实施例的显示装置中还可以包括其他常规结构，如显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (26)

  1. 一种薄膜晶体管的制备方法，其特征在于，包括步骤：
    在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜，氧化物有源层薄膜位于诱导层薄膜上方或下方；以及
    对完成上述步骤的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述氧化物有源层薄膜晶化以形成结晶氧化物有源层。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜的步骤包括：
    在基底上依次形成所述诱导层薄膜和所述氧化物有源层薄膜。
  3. 根据权利要求2所述的薄膜晶体管的制备方法，其特征在于，在基底上依次形成所述诱导层薄膜和所述氧化物有源层薄膜之前还包括：
    在基底上通过构图工艺形成包括栅极的图形。
  4. 根据权利要求2或3所述的薄膜晶体管的制备方法，其特征在于，所述通过诱导层薄膜的诱导作用使得氧化物有源层薄膜晶化以形成结晶氧化物有源层的步骤包括：
    对依次形成有所述诱导层薄膜和所述氧化物有源层薄膜的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述氧化物有源层薄膜晶化以形成结晶氧化物有源层薄膜，并且所述诱导层薄膜形成为氧化物诱导层；以及
    在完成上述步骤的基底上，通过构图工艺形成包括所述结晶氧化物有源层的图形。
  5. 根据权利要求2或3所述的薄膜晶体管的制备方法，其特征在于，所述通过诱导层薄膜的诱导作用使得氧化物有源层薄膜晶化以形成结晶氧化物有源层的步骤包括：
    在依次形成有所述诱导层薄膜和所述氧化物有源层薄膜的基底上，通过构图工艺形成图形化的氧化物有源层薄膜；以及
    对完成上述步骤的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述图形化的氧化物有源层薄膜晶化以形成所述结晶氧化物有源层，并且所述诱导层薄膜形成为氧化物诱导层。
  6. 根据权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜的步骤包括：
    在基底上依次形成所述氧化物有源层薄膜和所述诱导层薄膜。
  7. 根据权利要求6所述的薄膜晶体管的制备方法，其特征在于，所述通过诱导层薄膜的诱导作用使得氧化物有源层薄膜晶化以形成结晶氧化物有源层的步骤包括：
    对依次形成有所述氧化物有源层薄膜和所述诱导层薄膜的基底进行加热，通过所述诱导层薄膜的诱导作用使得所述氧化物有源层薄膜晶化以形成结晶氧化物有源层薄膜，并且所述诱导层薄膜形成为氧化物诱导层薄膜；以及
    在完成上述步骤的基底上，通过构图工艺形成包括所述结晶氧化物有源层和氧化物诱导层的图形。
  8. 根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，在形成所述结晶氧化物有源层和所述氧化物诱导层之后还包括：
    通过构图工艺形成包括栅极的图形。
  9. 根据权利要求1至8中任意一项所述的薄膜晶体管的制备方法，其特征在于，所述诱导层薄膜的材料为具有六方晶格结构或六方晶格衍生结构的金属，并且
    所述形成结晶氧化物有源层的步骤包括：
    将形成有所述诱导层薄膜和所述氧化物有源层薄膜的基底置于含氧气体气氛并进行加热，使得所述氧化物有源层薄膜在所述诱导层薄膜的作用下形成为所述结晶氧化物有源层薄膜。
  10. 根据权利要求9所述的薄膜晶体管的制备方法，其特征在于，所述具有六方晶格结构或六方晶格衍生结构的金属为铝、镁、钛中的任意一种。
  11. 根据权利要求9所述的薄膜晶体管的制备方法，其特征在于，所述形成结晶氧化物有源层的步骤中的加热温度的范围为450℃～700℃、含氧气体的氧气含量为5％～40％。
  12. 根据权利要求1至8中任意一项所述的薄膜晶体管的制备方法，其特征在于，所述诱导层薄膜的材料为具有六方晶格结构或六方晶格衍生结构的绝缘非金属。
  13. 根据权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述具有六方晶格结构或六方晶格衍生结构的绝缘非金属为氧化铝、氧化镁、氧化钆、氧化锆、氧化钛中的任意一种。
  14. 一种薄膜晶体管的制备方法，其特征在于，包括步骤：
    在基底上形成诱导层薄膜和与其接触的氧化物有源层薄膜，氧化物有源层薄膜位于诱导层薄膜上方或下方，并且通过构图工艺形成图形化的诱导层薄膜和图形化的氧化物有源层薄膜；以及
    对完成上述步骤的基底进行加热，通过所述图形化的诱导层薄膜的诱导作用使得所述图形化的氧化物有源层薄膜晶化以形成 结晶氧化物有源层。
  15. 根据权利要求14所述的薄膜晶体管的制备方法，其特征在于，所述形成图形化的诱导层薄膜和图形化的氧化物有源层薄膜的步骤包括：
    在基底上依次形成所述诱导层薄膜和所述氧化物有源层薄膜；以及
    在完成上述步骤的基底上，通过一次构图工艺形成所述图形化的诱导层薄膜和所述图形化的氧化物有源层薄膜。
  16. 根据权利要求15所述的薄膜晶体管的制备方法，其特征在于，在基底上形成所述诱导层薄膜之前还包括：
    在基底上通过构图工艺形成包括栅极的图形。
  17. 根据权利要求14所述的薄膜晶体管的制备方法，其特征在于，所述形成图形化的诱导层薄膜和图形化的氧化物有源层薄膜的步骤包括：
    在基底上依次形成所述氧化物有源层薄膜和所述诱导层薄膜；以及
    在完成上述步骤的基底上，通过一次构图工艺形成所述图形化的诱导层薄膜和所述图形化的氧化物有源层薄膜。
  18. 根据权利要求17所述的薄膜晶体管的制备方法，其特征在于，在形成所述结晶氧化物有源层的图形之后还包括：
    通过构图工艺形成包括栅极的图形。
  19. 根据权利要求14至18中任意一种所述的薄膜晶体管的制备方法，其特征在于，所述诱导层薄膜的材料为具有六方晶格结构或六方晶格衍生结构的金属，并且
    所述形成结晶氧化物有源层的步骤包括：
    将形成有所述图形化的诱导层薄膜和所述图形化的氧化物有源层薄膜的基底置于含氧气体气氛并进行加热，使得所述图形化的氧化物有源层薄膜在所述图形化的诱导层薄膜的作用下形成为所述结晶氧化物有源层，并且所述图形化的诱导层薄膜形成为氧化物诱导层。
  20. 根据权利要求19所述的薄膜晶体管的制备方法，其特征在于，所述具有六方晶格结构或六方晶格衍生结构的金属为铝、镁、钛中的任意一种。
  21. 根据权利要求19所述的薄膜晶体管的制备方法，其特征在于，所述形成结晶氧化物有源层的步骤中的加热温度的范围为450℃～700℃、含氧气体的氧气含量为5％～40％。
  22. 根据权利要求14至18中任意一种所述的薄膜晶体管的制备方法，其特征在于，所述诱导层薄膜的材料为具有六方晶格结构或六方晶格衍生结构的绝缘非金属。
  23. 根据权利要求22所述的薄膜晶体管的制备方法，其特征在于，所述具有六方晶格结构或六方晶格衍生结构的绝缘非金属为氧化铝、氧化镁、氧化钆、氧化锆、氧化钛中的任意一种。
  24. 一种薄膜晶体管，其特征在于，所述薄膜晶体管是由权利要求1～23中任一项所述的制备方法制备的。
  25. 一种阵列基板，其特征在于，包括权利要求24所述的薄膜晶体管。
  26. 一种显示装置，其特征在于，包括权利要求25所述的阵列基板。
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