WO2015165196A1 - 薄膜晶体管及其制备方法、显示基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、显示基板、显示装置 Download PDF

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WO2015165196A1
WO2015165196A1 PCT/CN2014/086920 CN2014086920W WO2015165196A1 WO 2015165196 A1 WO2015165196 A1 WO 2015165196A1 CN 2014086920 W CN2014086920 W CN 2014086920W WO 2015165196 A1 WO2015165196 A1 WO 2015165196A1
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oxide
protective layer
thin film
active layer
film transistor
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PCT/CN2014/086920
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English (en)
French (fr)
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赵策
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京东方科技集团股份有限公司
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Priority to US14/443,554 priority Critical patent/US20150311345A1/en
Publication of WO2015165196A1 publication Critical patent/WO2015165196A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, a display substrate, and a display device.
  • FIG. 1 is a schematic structural view of an oxide (eg, an indium gallium zinc oxide (IGZO)) thin film transistor, including a substrate 1 and a gate 2 disposed on the substrate 1.
  • oxide eg, an indium gallium zinc oxide (IGZO)
  • the gate 2 is provided
  • the gate insulating layer 3 is provided with an indium gallium zinc oxide (IGZO) active layer 4 on the gate insulating layer 3, and an etch stop layer 5 is disposed on the active layer 4 for protecting the active layer 4 and preventing engraving
  • the etching region etches the active region of the active layer 4, and the source and drain electrodes 6 are provided on the etch barrier layer 5.
  • IGZO indium gallium zinc oxide
  • a bottom gate structure as shown in FIG. 1 is often used, and an etch barrier layer 5 made of an insulating material is used to protect the indium gallium zinc oxide ( The active region of IGZO is not corroded by the etching liquid of the source and drain electrodes 6. Since the etch barrier layer 5 is formed of an insulating material, it is necessary to form a via hole between the active layer 4 and the source and drain electrodes 6, and the active layer 4 and the source and drain electrodes 6 are electrically connected through the via hole.
  • the fabrication process adds a patterning process step of separately forming the etch barrier layer 5, resulting in a complicated process of the indium gallium zinc oxide (IGZO) thin film transistor, a prolonged fabrication cycle, a reduced yield, and an increased production cost.
  • IGZO indium gallium zinc oxide
  • the object of the present invention is to solve the prior art thin film transistor and a preparation method thereof,
  • the etching barrier layer requires a separate patterning process, the process is complicated, the production cycle is prolonged, the yield rate is lowered, and the production cost is high, and the process is simple, the cycle is short, the yield rate is high, and the production cost is high.
  • the invention provides a method for preparing a thin film transistor, comprising the steps of: forming an oxide active layer film and a protective layer film on a substrate, wherein the protective layer film is made of a tin oxide material, and is oxidized by one patterning process.
  • the active layer film and the protective layer film are patterned to form a pattern of the oxide active layer and the protective layer; the source and drain electrode films are formed on the protective layer, and the source and drain electrode films are patterned by a patterning process.
  • Forming a pattern of source and drain electrodes Forming a pattern of source and drain electrodes; and performing annealing under an oxygen-containing atmosphere such that a material of the oxide active layer diffuses through a contact surface between the oxide active layer and the protective layer a protective layer to form a transition region in the protective layer, and a material of the protective layer is diffused to the oxide active layer through the contact surface to form in the oxide active layer A transition region for reducing the off-state current of the thin film transistor.
  • the protective layer further includes a non-transition region remote from the oxide active layer, the non-transition region being prepared from a tin oxide-containing material.
  • the protective layer consists of a transition zone.
  • the tin oxide-based material may be any one of indium tin zinc oxide, aluminum tin zinc oxide, zinc tin oxide, gallium oxide tin, indium gallium tin oxide, or indium tin oxide.
  • the material of the oxide active layer may be indium gallium zinc oxide.
  • the transition region may comprise an indium gallium zinc tin zinc material.
  • the oxygen-containing atmosphere in the step of annealing under an oxygen-containing atmosphere is an oxygen partial pressure atmosphere or a pure oxygen atmosphere in the range of 1% to 99%.
  • the annealing in the step of annealing under an oxygen-containing atmosphere is carried out at an annealing temperature in the range of 100 to 900 °C.
  • the protective layer is prepared by deposition under an oxygen-containing atmosphere, and the oxygen-containing atmosphere is an oxygen partial pressure atmosphere or a pure oxygen atmosphere in the range of 1% to 99%.
  • the present invention also provides a thin film transistor comprising: an oxide active layer, a protective layer over the oxide active layer, and source and drain electrodes, the protective layer including a tin oxide-based material, the oxide active layer including a transition region in a portion in contact with the protective layer, and the protective layer including a transition in a portion in contact with the oxide active layer The region, the transition region is used to reduce the off-state current of the thin film transistor.
  • the protective layer further includes a non-transition region away from the oxide active layer, the transition region comprising a material formed by combining a material of the tin oxide-based material and the oxide active layer, wherein the non-transition region is Prepared from tin oxide-containing materials.
  • the protective layer is composed of a transition region containing a material in which a tin oxide-based material and a material of the oxide active layer are bonded to each other.
  • One side of the protective layer is in contact with the oxide active layer, and the other side of the protective layer is in contact with the source and the drain, and the oxide active layer is electrically connected to the source and drain electrodes respectively through the protective layer. connection.
  • the tin oxide-based material may be any one of indium tin zinc oxide, aluminum tin zinc oxide, zinc tin oxide, gallium oxide tin, indium gallium tin oxide, or indium tin oxide.
  • the material of the oxide active layer may be indium gallium zinc oxide.
  • the thickness of the protective layer may range from 1 to 100 nm.
  • the oxide active layer may have a thickness ranging from 5 to 200 nm.
  • the transition region formed by the combination of the tin oxide-based material and the material of the oxide active layer includes an indium gallium zinc tin zinc material.
  • the present invention also provides a display substrate comprising the above-described thin film transistor.
  • the present invention also provides a display device comprising the above display substrate.
  • the protective layer is made of a tin oxide-based material that is insensitive to conventional source and drain electrode etching liquids, when the source and drain electrodes are formed, it is located in the oxide active layer.
  • the tin oxide-based protective layer protects the oxide active layer from the source and drain electrode etching solutions.
  • the tin oxide-based protective layer is a semiconductor material compared with the insulating etch barrier layer used in the prior art, and has a good electrical matching with the oxide active layer and the source and drain electrodes, thereby realizing source and leakage. There is no need to make vias when electrically connecting the poles to the oxide active layer.
  • the protective layer and the oxide active layer can be formed by one patterning process. Compared with the prior art, the illumination process formed by the etch barrier layer is omitted, and the patterning process is reduced, so that the process of the product is simple and the fabrication cycle is short. High yield and low production cost.
  • annealing under an oxygen-containing atmosphere can repair the damage of the active layer by the plasma when the deposition source and the drain electrode film are repaired, and at the same time, a transition is formed in each of the respective portions where the oxide active layer and the protective layer are in contact with each other. A region that reduces the off-state current of the thin film transistor.
  • FIG. 1 is a schematic structural view of an oxide thin film transistor in the prior art.
  • FIG. 2 is a schematic view showing the structure after forming a gate electrode in the method of fabricating the oxide thin film transistor of Embodiment 1 of the present invention.
  • FIG. 3 is a schematic view showing the structure after forming a gate insulating layer in the method of fabricating the oxide thin film transistor of Embodiment 1 of the present invention.
  • FIG. 4 is a schematic view showing the structure after forming an oxide active layer and a protective layer in the method for fabricating an oxide thin film transistor according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic view showing the structure after forming source and drain electrodes and annealing in the method for fabricating an oxide thin film transistor according to Embodiment 1 of the present invention.
  • Ids-Vgs transfer current characteristic curve of an indium gallium zinc oxide (IGZO) thin film transistor in Example 1 of the present invention.
  • Fig. 7 is a graph showing the transition current characteristic curve (Ids-Vgs) of the indium gallium zinc oxide (IGZO) thin film transistor of Example 1 of the present invention after annealing.
  • Fig. 8 is a view showing the configuration of an oxide thin film transistor in Embodiment 2 of the present invention.
  • This embodiment provides a method for preparing a thin film transistor, including the following steps: Forming an oxide active layer film and a protective layer film on the substrate, the material of the protective layer film is a tin oxide-based material, and patterning the oxide active layer film and the protective layer film by a single patterning process to form a pattern of an oxide active layer and a protective layer; forming a source and a drain electrode film on the protective layer, patterning the source and drain electrode films by a patterning process to form a pattern of source and drain electrodes; and under an oxygen-containing atmosphere Annealing is performed such that a material of the oxide active layer diffuses to the protective layer through a contact surface between the oxide active layer and the protective layer to form a transition region in the protective layer And a material of the protective layer is diffused to the oxide active layer through the contact surface to form a transition region in the oxide active layer, the transition region for reducing a thin film transistor Off state current.
  • the protective layer is made of a tin oxide-based material that is insensitive to conventional source and drain electrode etching liquids, oxidation of the oxide active layer is performed when the source and drain electrodes are formed.
  • the tin-based protective layer protects the oxide active layer from the source and drain electrode etchants.
  • the tin oxide-based protective layer is a semiconductor material, and has a good electrical matching with the oxide active layer and the source and drain electrodes, thus realizing the source and drain electrodes and
  • the electrical connection between the oxide active layers does not require the preparation of via holes, and the protective layer and the oxide active layer can be formed by one patterning process, which eliminates the need for separate formation of the etch barrier layer compared to the prior art.
  • the patterning process reduces the number of patterning processes, resulting in a simple process, short production cycle, high yield, and low production cost. Further, annealing under an oxygen-containing atmosphere can repair the damage of the active layer by the plasma when the deposition source and the drain electrode film are repaired.
  • the off-state current of the thin film transistor which is not formed by the annealing process in an oxygen-containing atmosphere is very high, the switching characteristics of the thin film transistor are poor, and the material of the oxide active layer is performed when the annealing process is performed under an oxygen-containing atmosphere.
  • the material of the protective layer is diffused at the interface between the two, and a transition region is formed in each of the portions where the two are in contact, thereby reducing the off-state current of the thin film transistor.
  • the protective layer may further include a non-transition region remote from the oxide active layer, the non-transition region being prepared from a tin oxide-containing material. Controlling the thickness of the protective layer and the annealing process conditions such that a partial region of the protective layer is formed as a structure of the transition region, that is, a portion of the protective layer close to the active layer is a transition region, and a portion away from the active layer Divided into non-transition areas.
  • the material of the active layer does not diffuse to the non-transition region of the protective layer, and the non-transition region of the protective layer is composed of a tin oxide-based material.
  • the protective layer may be composed of a transition region, that is, in the method of fabricating the thin film transistor of the present embodiment, the material of the oxide active layer may be controlled by controlling the thickness of the protective layer and the annealing process conditions. Diffusion to the entire tin oxide protective layer, so that the protective layer is completely transformed into a transition region.
  • the tin oxide-based material may be any one of indium tin zinc oxide, aluminum tin zinc oxide, zinc tin oxide, gallium oxide tin, indium gallium tin oxide, or indium tin oxide.
  • the material of the oxide active layer may be indium gallium zinc oxide.
  • the oxygen-containing atmosphere is an oxygen partial pressure atmosphere or a pure oxygen atmosphere in the range of 1% to 99%, and annealing under an oxygen-containing atmosphere is advantageous for repairing damage of the active layer.
  • the annealing is performed at an annealing temperature in the range of 100 to 900 ° C, and annealing is performed at this temperature, so that the material of the protective layer passes through the protective layer and the oxide active layer.
  • a contact surface is diffused to the oxide active layer, thereby forming a transition region in a portion of the oxide active layer that is in contact with the protective layer, and the material of the oxide active layer is diffused through the contact surface to
  • the protective layer forms a transition region in a portion of the protective layer that is in contact with the oxide active layer, thereby reducing the off-state current of the thin film transistor.
  • the protective layer may be prepared by depositing in an oxygen-containing atmosphere, wherein the oxygen-containing atmosphere is in an oxygen partial pressure atmosphere or a pure oxygen atmosphere in a range of 1% to 99%, and the oxygen content of the protective layer is deposited under an oxygen-containing atmosphere. High, oxygen-rich material layer. Annealing in an oxygen-containing atmosphere, part of the oxygen in the oxygen-rich protective layer moves to the oxide active layer, or the oxygen inside the active layer moves to bond with the metal in the oxide active layer, so that the active layer is obtained Repair to improve the characteristics of the thin film transistor.
  • the following is an example of a method for fabricating a thin film transistor having a bottom gate type and an oxide active layer as IGZO. It should be understood that the method is also applicable to a top gate type thin film transistor, and the preparation method includes the following steps 1 to 4.
  • step 1 a metal gate is fabricated.
  • the base substrate 1 is first cleaned and then subjected to magnetron sputtering.
  • a gate metal film is deposited and formed into a pattern of the gate 2 by a patterning process (including photoresist coating, masking, exposure, development, etching, photoresist stripping, etc.).
  • the gate electrode 2 and the connection metal may be made of a metal material or an alloy material such as Cr, Ti, Mo, W, Al, or Cu, and other composite conductive materials.
  • the above gate metal film may be one or more layers having a thickness ranging from 1 to 1000 nm. In this embodiment, for example, the thickness of the gate metal film is 700 nm.
  • step 2 a gate insulating layer is formed.
  • the gate insulating layer 3 is deposited by a chemical vapor deposition (CVD) technique, and a pattern of the gate insulating layer 3 is formed by a patterning process.
  • the gate insulating layer 3 may be made of one or more insulating materials of SiOx, SiNx, SiONx, AlOx, or the like. In this embodiment, the gate insulating layer 3 is made of SiOx.
  • the gate insulating layer 3 may be one or more layers having a thickness ranging from 1 to 500 nm. In this embodiment, for example, the thickness of the gate insulating layer is 300 nm.
  • step 3 an active layer and a protective layer are formed.
  • an indium gallium zinc oxide (IGZO) active layer 4 is first deposited by magnetron sputtering, and then a nano-thickness protective layer 5 is deposited under an oxygen-containing atmosphere.
  • the oxygen-containing atmosphere has an oxygen partial pressure range of 1%-99% atmosphere. In this embodiment, for example, the partial pressure of oxygen is 50%.
  • the protective layer 5 formed by deposition in an oxygen-containing atmosphere has a high oxygen content, so that part of the oxygen in the oxygen-rich protective layer 5 can be moved to active in a subsequent annealing process in an oxygen-containing atmosphere.
  • the layer 4, or the oxygen inside the active layer 4 is bonded to the metal inside the active layer 4, thereby repairing the active layer 4, thereby improving the characteristics of the thin film transistor.
  • the thickness of the protective layer 5 ranges from 1 to 100 nm.
  • the thickness of the protective layer 5 is 50 nm, and the protective layer 5 can be prepared using a tin oxide-based material.
  • the tin oxide-based material is insensitive to the conventional source and drain electrode etching liquid.
  • the tin oxide-based protective layer on the oxide active layer can protect the oxide active layer from source and leakage. The effect of the polar etchant.
  • the tin oxide-based material may be indium tin zinc oxide (ITZO), aluminum tin zinc (ATZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), indium gallium tin oxide (IGTO), indium tin oxide ( Any of ITO).
  • ITZO indium tin zinc oxide
  • ATZO aluminum tin zinc
  • ZTO zinc tin oxide
  • GTO gallium tin oxide
  • IGTO indium gallium tin oxide
  • ITO indium tin oxide
  • the protective layer 5 is prepared using an indium tin zinc oxide (ITZO) material.
  • a patterning process is employed to form the patterned oxide active layer 4 and the patterned protective layer 5, so that the active layer 4 is covered by the protective layer 5, which can be avoided. Corrosion of the oxide active layer 4 (indium gallium zinc oxide) by the metal etching solution when the source and the drain are formed.
  • the protective layer can also prevent the etching liquid from damaging the oxide active layer under the protective layer.
  • the ITZO protective layer 5 is a semiconductor material layer which has a good electrical matching with the oxide active layer 4 and the source and drain electrodes, thus the source and drain electrodes. It is not necessary to prepare via holes when electrically connected to the oxide active layer 4. Moreover, the protective layer 5 and the oxide active layer 4 can be formed by a single patterning process, which eliminates the need for the etch barrier layer to separately form a desired illumination process, and reduces the patterning process, thereby making the product The process is simple, the production cycle is short, the yield is high, and the production cost is low. In this embodiment, a method for fabricating a thin film transistor using ITZO as a protective layer is specifically described. It should be understood that since the specific fabrication method and technical effect are basically the same, a thin film transistor including a protective layer formed of other tin oxide-based materials also falls. It is within the scope of protection of the present invention.
  • step 4 the source and drain are fabricated and annealed.
  • a source and drain electrode metal film is deposited by a magnetron sputtering technique, and a pattern of source and drain electrodes 6 is formed by a patterning process.
  • the source and drain electrodes 6 and the connection metal may be prepared by using a metal material or an alloy material such as Cr, Ti, Mo, W, Al, Cu or the like and other composite conductive materials.
  • the source and drain electrodes 6 may be one or more layers having a thickness ranging from 1 to 1000 nm. In this embodiment, for example, the thickness of the source and drain electrodes 6 is 800 nm.
  • annealing is performed in an oxygen-containing atmosphere at an annealing temperature in the range of 100 to 900 ° C, and the oxygen-containing atmosphere is an atmosphere having an oxygen partial pressure of 1% to 99%.
  • the annealing temperature ranges from 300 to 500 ° C and the partial pressure of oxygen is 60%.
  • Annealing in an oxygen-containing atmosphere allows the oxide active layer to be repaired by oxygen, which improves the performance of the thin film transistor.
  • other atmospheres capable of repairing the active layer by oxygen may be used, which is not limited herein.
  • the plasma may cause damage to the oxide active layer 4, such as when the oxide active layer 4 is indium gallium zinc oxide.
  • the plasma may damage the O-In, O-Ga, O-Zn bonds in the IGZO material, for example, the above-mentioned bond cleavage causes oxygen to diffuse. Annealing in an oxygen-containing atmosphere enables partial oxygen in the oxygen-rich protective layer 5 to move to the inside of the active layer 4 or the active layer 4 to bond with the metal inside the active layer 4 to activate Layer 4 is repaired to improve the characteristics of the thin film transistor.
  • FIG. 6 shows a transfer characteristic curve of a thin film transistor obtained by an oxygen-free atmosphere annealing process. As can be seen from FIG. 6, the off-state current of the thin film transistor obtained by the oxygen-free atmosphere annealing process is large, almost open.
  • Fig. 7 is a view showing a transfer characteristic curve of a thin film transistor obtained by annealing in an oxygen-containing atmosphere. As can be seen from Fig. 7, the thin film transistor of this embodiment is annealed in an oxygen-containing atmosphere, and the off-state current is compared. There is a significant decrease before annealing (refer to FIG. 6), so that the transition region formed by annealing in an oxygen-containing atmosphere can lower the off-state current of the thin film transistor.
  • the above protective layer 5 may be entirely composed of the transition region 8, that is, the thickness of the protective layer and the annealing process conditions may be controlled such that the oxide active layer material diffuses to the entire tin oxide-based protective layer, thereby protecting The layer is completely transformed into a transition zone 8.
  • controlling the thickness of the protective layer and the annealing process conditions may also form a partial region of the protective layer 5 as a structure of the transition region 8, that is, a portion close to the active layer 4 is a transition region 8, and a portion away from the active layer 4
  • the material of the active layer 4 does not diffuse to the non-transition region of the protective layer, and the non-transition region of the protective layer is composed of a tin oxide-based material.
  • a method of fabricating a thin film transistor is described by taking an oxide active layer as IGZO and a protective layer as ITZO.
  • oxide active layer materials such as zinc oxynitride
  • other tin oxide systems are used.
  • the protective layer material is used, the patterning process can also be reduced, and the annealing in the oxygen-containing atmosphere can also repair the damage of the active layer by the plasma when the deposition source and the drain electrode film are repaired, and the oxide active layer and the protective layer are in contact with each other.
  • a transition region is formed in each of the respective portions to reduce the off-state current of the thin film transistor. Therefore, a method of preparing a thin film transistor using other oxide active layer materials (such as zinc oxynitride) and other tin oxide-based protective layer materials is also within the scope of the present invention.
  • the present embodiment provides a thin film transistor including: an oxide active layer 4, a protective layer 5 over the oxide active layer 4, and source and drain electrodes 6, the protective layer including a tin oxide-based material including a transition region 8 in a portion of the oxide active layer 4 in contact with the protective layer 5, and a portion of the protective layer 5 in contact with the oxide active layer 4 A transition region 8 is included, which is used to reduce the off-state current of the thin film transistor.
  • a thin film transistor including: an oxide active layer 4, a protective layer 5 over the oxide active layer 4, and source and drain electrodes 6, the protective layer including a tin oxide-based material including a transition region 8 in a portion of the oxide active layer 4 in contact with the protective layer 5, and a portion of the protective layer 5 in contact with the oxide active layer 4 A transition region 8 is included, which is used to reduce the off-state current of the thin film transistor.
  • the protective layer 5 further includes a non-transition region away from the oxide active layer 4, and the transition region 8 includes a tin oxide-based material and a material of the oxide active layer which is annealed and diffused to form a mutual bond.
  • the material, the non-transition region is prepared from a tin oxide-containing material.
  • This embodiment is described by taking a bottom gate type thin film transistor as an example, and it should be understood that it is also applicable to a top gate type thin film transistor.
  • the protective layer 5 can be formed by the transition region 8 , that is to say that all the protective layers 5 are formed by the transition region 8 .
  • the transition region 8 includes a material in which a tin oxide-based material and a material of the oxide active layer are formed by diffusion and diffusion.
  • One side of the protective layer 5 is in contact with the oxide active layer 4, and the other side of the protective layer 5 is in contact with the source and drain electrodes 6.
  • the oxide active layer 4 is electrically connected to the source and drain electrodes 6 through a protective layer 5, respectively.
  • the tin oxide-based material may be indium tin zinc oxide (ITZO), aluminum tin zinc (ATZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), indium gallium tin oxide (IGTO), indium tin oxide ( Any of ITO).
  • ITZO indium tin zinc oxide
  • ATZO aluminum tin zinc
  • ZTO zinc tin oxide
  • GTO gallium tin oxide
  • IGTO indium gallium tin oxide
  • ITO indium tin oxide
  • the material of the oxide active layer 4 may be indium gallium zinc oxide (IGZO).
  • semiconductor or compound semiconductors of other elements may be used to prepare the active layer, and other amorphous, polycrystalline, single crystal, and mixed-state semiconductors may also be used to prepare the active layer.
  • the protective layer 5 has a thickness ranging from 1 to 100 nm.
  • the active layer 4 has a thickness ranging from 5 to 200 nm.
  • the tin oxide-based material and the material of the oxide active layer 4 are annealed to form a transition region material layer containing indium gallium zinc tin oxide, and the transition region formed It can reduce the off-state current of the thin film transistor.
  • the transition region 8 of the thin film transistor in the present embodiment is formed by combining a material of the protective layer 5 which is annealed by diffusion and a material of the oxide active layer 4, and a thin film transistor obtained by an annealing process without an oxygen-containing atmosphere.
  • the thin film transistor of the present embodiment has a lower off-state current, and the characteristics of the thin film transistor are excellent.
  • the protective layer 5 is prepared by using a tin oxide-based material, the tin oxide-based material has a good barrier effect on the source and drain etching liquids, and in the process of fabricating the thin film transistor, the protective layer is disposed so that the oxide active layer The performance of 4 is not affected by the source and drain etchants, and the protective layer 5 made of a tin oxide-based material can protect the oxide active layer 4 from the source and drain etchants. The influence on the oxide active layer 4 when the functional layer is subsequently prepared is prevented, for example, the effect of sputtering of the source and drain electrodes 6 on the oxide active layer 4.
  • the etch barrier layer 5 of the prior art is generally prepared by using an insulating material, so that a via hole is formed on the etch barrier layer 5, and the active layer 4 and the source and drain electrodes 6 are electrically connected through the via hole, A separate patterning process for making the etch stop layer 5 is required.
  • the protective layer 5 in this embodiment is prepared by using a tin oxide-based material and has semiconductor properties. Therefore, it is not necessary to form via holes in the protective layer 5, and the protective layer 5 and the oxide active layer 4 can be performed by one patterning process.
  • the patterning process reduces the patterning process, simplifies the process of the thin film transistor, shortens the fabrication period of the thin film transistor, and also improves the yield and reduces the production cost. Therefore, the thin film transistor in this embodiment has a simple process, high yield, and low production cost.
  • the embodiment provides a display substrate comprising the above-described thin film transistor, and other necessary functional layers and connecting lines well known to those skilled in the art.
  • the display substrate provided in this embodiment has the advantages of simple process, high yield, and low production cost.
  • the embodiment provides a display device, wherein the display device comprises the above display substrate.
  • the display device provided in this embodiment has the advantages of simple process, high yield, and low production cost.
  • the display device can be applied to liquid crystal televisions, high definition digital televisions, computers (desktops and notebooks), mobile phones, PDAs, GPS, car displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronics. Instruments, meters, public displays, and unreal displays.

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Abstract

一种薄膜晶体管及其制备方法、显示基板、显示装置。在所述制备方法中，通过一次构图工艺对保护层（5）与氧化物有源层（4）进行图形化来形成保护层（5）和氧化物有源层（4）的图形；在含氧气氛下进行退火，使得所述氧化物有源层（4）的材料通过所述氧化物有源层（4）与所述保护层（5）之间的接触面而扩散到所述保护层（5），以在所述保护层（5）中形成一过渡区域（8），并且所述保护层（5）的材料通过所述接触面而扩散到所述氧化物有源层（4），以在所述氧化物有源层（4）中形成一过渡区域（8），所述的过渡区域（8）用于降低薄膜晶体管的关态电流。

Description

薄膜晶体管及其制备方法、显示基板、显示装置 技术领域
本发明属于显示技术领域，具体涉及薄膜晶体管及其制备方法、显示基板、显示装置。
背景技术
近年来，随着平板显示技术的不断发展，大尺寸、高分辨率、3D液晶显示器以及有机电致发光显示(OLED)技术已经成为主要发展方向。传统的非晶硅薄膜晶体管已经难以满足相关技术要求，有源层为氧化物(如氧化铟镓锌(IGZO，In-Ga-Zn-O))的薄膜晶体管作为最有希望用于下一代平板显示器的薄膜晶体管，几乎满足上述所有的技术要求。如图1所示为氧化物(如氧化铟镓锌(IGZO))薄膜晶体管的结构示意图，包括衬底基板1、以及设置在该衬底基板1上的栅极2，栅极2上设有栅极绝缘层3，栅极绝缘层3上设有氧化铟镓锌(IGZO)有源层4，有源层4上设有刻蚀阻挡层5，以用于保护有源层4并且防止刻蚀液腐蚀有源层4的有源区，在刻蚀阻挡层5上设有源、漏电极6。
当采用氧化铟镓锌(IGZO)作为薄膜晶体管有源层的材料时，常采用如图1所示的底栅结构，并且采用由绝缘材料制备的刻蚀阻挡层5来保护氧化铟镓锌(IGZO)有源区不受源、漏电极6刻蚀液的腐蚀。由于刻蚀阻挡层5是采用绝缘材料制备的，需要在有源层4和源、漏电极6之间形成过孔，通过该过孔使有源层4和源、漏电极6电连接。但该制作过程增加了单独形成刻蚀阻挡层5的构图工艺步骤，导致氧化铟镓锌(IGZO)薄膜晶体管的制程复杂，制作周期延长，良品率降低，生产成本增高。
发明内容
本发明的目的是解决现有技术的薄膜晶体管及其制备方法、 显示基板、显示装置中由于刻蚀阻挡层需要单独构图工艺而造成的制程复杂、制作周期延长、良品率降低、生产成本高的问题，提供一种制程简单、周期短、良品率高、生产成本低的薄膜晶体管及其制备方法、显示基板、显示装置。
本发明提供一种薄膜晶体管的制备方法，包括以下步骤：在基板上形成氧化物有源层薄膜、保护层薄膜，所述保护层薄膜的材料为氧化锡系材料，并且采用一次构图工艺对氧化物有源层薄膜、保护层薄膜进行图形化，以形成氧化物有源层、保护层的图形；在保护层上形成源、漏电极薄膜，通过构图工艺对源、漏电极薄膜进行图形化，以形成源、漏电极的图形；以及在含氧气氛下进行退火，使得所述氧化物有源层的材料通过所述氧化物有源层与所述保护层之间的接触面而扩散到所述保护层，以在所述保护层中形成一过渡区域，并且所述保护层的材料通过所述接触面而扩散到所述氧化物有源层，以在所述氧化物有源层中形成一过渡区域，所述的过渡区域用于降低薄膜晶体管的关态电流。
所述保护层还包括远离氧化物有源层的非过渡区域，所述的非过渡区域是由含氧化锡系材料制备的。
可替代地，所述保护层由过渡区域构成。
所述氧化锡系材料可以为氧化铟锡锌、氧化铝锡锌、氧化锌锡、氧化镓锡、氧化铟镓锡、氧化铟锡中的任意一种。
所述氧化物有源层的材料可以为氧化铟镓锌。
所述过渡区域可以包括氧化铟镓锡锌材料。
所述在含氧气氛下进行退火的步骤中所述含氧气氛为1％-99％范围的氧气分压气氛或纯氧气氛。
所述在含氧气氛下进行退火的步骤中所述退火是在100-900℃范围的退火温度下进行的。
所述的保护层是在含氧气氛下沉积制备的，所述的含氧气氛为1％-99％范围的氧气分压气氛或纯氧气氛。
本发明还提供一种薄膜晶体管，包括：氧化物有源层、位于氧化物有源层之上的保护层、以及源、漏电极，所述保护层包括 氧化锡系材料，所述氧化物有源层在与所述保护层相接触的部分中包括一过渡区域，并且所述保护层在与所述氧化物有源层相接触的部分中包括一过渡区域，所述的过渡区域用于降低薄膜晶体管的关态电流。
所述保护层还包括远离氧化物有源层的非过渡区域，所述过渡区域包含氧化锡系材料与所述氧化物有源层的材料相互结合形成的材料，所述的非过渡区域是由含氧化锡系材料制备的。
可替代地，所述保护层由过渡区域构成，所述过渡区域包含氧化锡系材料与所述氧化物有源层的材料相互结合形成的材料。
所述保护层的一侧与氧化物有源层接触，所述保护层的另一侧与所述源、漏接触，所述氧化物有源层通过保护层分别与所述源、漏电极电连接。
所述氧化锡系材料可以为氧化铟锡锌、氧化铝锡锌、氧化锌锡、氧化镓锡、氧化铟镓锡、氧化铟锡中的任意一种。
所述氧化物有源层的材料可以为氧化铟镓锌。
所述保护层的厚度范围可以为1-100nm。
所述氧化物有源层的厚度范围可以为5-200nm。
所述氧化锡系材料与氧化物有源层的材料相互结合形成的过渡区域包括氧化铟镓锡锌材料。
本发明还提供一种显示基板，所述的显示基板包括上述的薄膜晶体管。
本发明还提供一种显示装置，所述的显示装置包括上述的显示基板。
在本发明的薄膜晶体管、显示基板、显示装置中，由于保护层采用对常规源、漏电极刻蚀液不敏感的氧化锡系材料，在制作源、漏电极时，位于氧化物有源层之上的氧化锡系保护层能保护氧化物有源层免受源、漏电极刻蚀液的影响。此外，相对于现有技术中采用的绝缘的刻蚀阻挡层，氧化锡系保护层为半导体材料，与氧化物有源层和源、漏电极有很好的电学匹配，因此在实现源、漏电极与氧化物有源层之间的电连接时无需制备过孔。而且，保 护层和氧化物有源层可采用一次构图工艺形成，与现有技术相比，省去了刻蚀阻挡层单独形成的光照制程，减少了一次构图工艺，使得产品的制程简单、制作周期短、良品率高、生产成本低。此外，在含氧气氛下进行退火，能够修复沉积源、漏电极薄膜时等离子对有源层的损伤，同时，在氧化物有源层和保护层两者相接触的各自部分中分别形成一过渡区域，其能够降低薄膜晶体管的关态电流。
附图说明
图1为现有技术中的氧化物薄膜晶体管的结构示意图。
图2为本发明的实施例1的氧化物薄膜晶体管的制备方法中形成栅极之后的结构示意图。
图3为本发明的实施例1的氧化物薄膜晶体管的制备方法中形成栅极绝缘层之后的结构示意图。
图4为本发明的实施例1的氧化物薄膜晶体管的制备方法中形成氧化物有源层及保护层之后的结构示意图。
图5为本发明的实施例1的氧化物薄膜晶体管的制备方法中形成源、漏电极并退火之后的结构示意图。
图6为本发明的实施例1中的氧化铟镓锌(IGZO)薄膜晶体管的未经退火的转移电流特性曲线(Ids-Vgs)。
图7为本发明的实施例1中的氧化铟镓锌(IGZO)薄膜晶体管的经过退火后的转移电流特性曲线(Ids-Vgs)。
图8为本发明的实施例2中的氧化物薄膜晶体管的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1
本实施例提供一种薄膜晶体管的制备方法，包括以下步骤： 在基板上形成氧化物有源层薄膜、保护层薄膜，所述保护层薄膜的材料为氧化锡系材料，并且采用一次构图工艺对氧化物有源层薄膜、保护层薄膜进行图形化，以形成氧化物有源层、保护层的图形；在保护层上形成源、漏电极薄膜，通过构图工艺对源、漏电极薄膜进行图形化，以形成源、漏电极的图形；以及在含氧气氛下进行退火，使得所述氧化物有源层的材料通过所述氧化物有源层与所述保护层之间的接触面而扩散到所述保护层，以在所述保护层中形成一过渡区域，并且所述保护层的材料通过所述接触面而扩散到所述氧化物有源层，以在所述氧化物有源层中形成一过渡区域，所述的过渡区域用于降低薄膜晶体管的关态电流。
本实施例的薄膜晶体管的制作方法中，由于保护层采用对常规源、漏电极刻蚀液不敏感的氧化锡系材料，在制作源、漏电极时，位于氧化物有源层之上的氧化锡系保护层能保护氧化物有源层免受源、漏电极刻蚀液的影响。相对于现有技术中采用的绝缘的刻蚀阻挡层，氧化锡系保护层为半导体材料，与氧化物有源层和源、漏电极有很好的电学匹配，因此在实现源、漏电极与氧化物有源层之间的电连接时无需制备过孔，并且保护层和氧化物有源层可采用一次构图工艺形成，与现有技术相比，省去了刻蚀阻挡层单独形成所需的构图工艺，减少了一次构图工艺，从而产品的制程简单、制作周期短、良品率高、生产成本低。此外，在含氧气氛下进行退火，能够修复沉积源、漏电极薄膜时等离子对有源层的损伤。而且，未经含氧气氛下的退火工艺而制作成的薄膜晶体管的关态电流非常高，薄膜晶体管的开关特性较差，而在含氧气氛下进行退火工艺时，氧化物有源层的材料和保护层的材料在两者之间接触面处发生扩散，在两者相接触的各自部分中分别形成一过渡区域，从而能够降低薄膜晶体管的关态电流。
所述保护层还可以包括远离氧化物有源层的非过渡区域，所述的非过渡区域是由含氧化锡系材料制备的。控制保护层的厚度和退火工艺条件，使得保护层的部分区域形成为过渡区域的结构，即，保护层的靠近有源层的部分为过渡区域，而远离有源层的部 分为非过渡区域。有源层的材料没有扩散至保护层的非过渡区域，保护层的非过渡区域由氧化锡系材料构成。
可替代地，所述保护层可以由过渡区域构成，也就是说，在本实施例的薄膜晶体管的制作方法中，可通过控制保护层的厚度和退火工艺条件，使得氧化物有源层的材料扩散至整个氧化锡系保护层，从而保护层完全转变为过渡区域。
所述氧化锡系材料可以为氧化铟锡锌、氧化铝锡锌、氧化锌锡、氧化镓锡、氧化铟镓锡、氧化铟锡中的任意一种。
所述氧化物有源层的材料可以为氧化铟镓锌。
所述在含氧气氛下进行退火的步骤中，所述含氧气氛为1％-99％范围的氧气分压气氛或纯氧气氛，在含氧气氛下进行退火有利于修复有源层损伤。
所述在含氧气氛下进行退火的步骤中，所述退火是在100-900℃范围的退火温度下进行的，在此温度下退火，使得保护层的材料通过保护层与氧化物有源层之间的接触面而扩散到氧化物有源层，从而在氧化物有源层中与保护层相接触的部分中形成一过渡区域，并且氧化物有源层的材料通过该接触面而扩散到保护层，从而在保护层中与氧化物有源层相接触的部分中形成一过渡区域，因而可降低薄膜晶体管的关态电流。
所述的保护层可以在含氧气氛下沉积制备，所述的含氧气氛为1％-99％范围的氧气分压气氛或纯氧气氛，在含氧气氛下沉积得到的保护层含氧量高，为富氧的材料层。在含氧气氛中退火，富氧的保护层中的部分氧运动到氧化物有源层，或者有源层内部的氧运动而与氧化物有源层中的金属键合，使有源层得到修复，从而改善薄膜晶体管的特性。
下面以底栅型并且氧化物有源层为IGZO的薄膜晶体管的制备方法为例进行说明，应当理解的是该方法对于顶栅型的薄膜晶体管也是适用的，该制备方法包括以下步骤1至步骤4。
在步骤1中，制作金属栅极。
如图2所示，首先对衬底基板1进行清洗，然后进行磁控溅 射而沉积栅极金属膜，并采用构图工艺(包括光刻胶涂布、掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部工艺)形成栅极2的图形。栅极2以及连接金属可采用Cr、Ti、Mo、W、Al、Cu等金属材料或合金材料及其它复合导电材料制作。上述的栅极金属膜可以是一层或多层结构，厚度范围为1-1000nm。本实施例中，例如，栅极金属膜的厚度为700nm。
在步骤2中，制作栅极绝缘层。
如图3所示，采用化学气相沉积(CVD)技术沉积栅极绝缘层3，并采用构图工艺形成栅极绝缘层3的图形。栅极绝缘层3可采用SiOx、SiNx、SiONx、AlOx等中的一种或多种绝缘材料制作。本实施例中，栅极绝缘层3采用SiOx。栅极绝缘层3可以是一层或多层结构，厚度范围为1-500nm。本实施例中，例如，栅极绝缘层的厚度为300nm。
在步骤3中，制作有源层及保护层。
如图4所示，采用磁控溅射技术首先沉积氧化铟镓锌(IGZO)有源层4，然后在含氧气氛下沉积纳米级厚度的保护层5，含氧气氛为氧气分压范围为1％-99％的气氛。本实施例中，例如，氧气分压为50％。在含氧气氛中沉积形成的保护层5具有较高的氧含量，从而，在后续的在含氧气氛中进行退火的工艺中，能使富氧的保护层5中的部分氧运动到有源层4，或者有源层4内部的氧运动而与有源层4内部的金属键合，从而使有源层4得到修复，从而改善薄膜晶体管的特性。保护层5的厚度范围为1-100nm，本实施例中，例如，保护层5的厚度为50nm，并且保护层5可以采用氧化锡系材料制备。氧化锡系材料对常规源、漏电极刻蚀液不敏感，在制作源、漏电极时，位于氧化物有源层之上的氧化锡系保护层能保护氧化物有源层免受源、漏电极刻蚀液的影响。所述氧化锡系材料可以为氧化铟锡锌(ITZO)、氧化铝锡锌(ATZO)、氧化锌锡(ZTO)、氧化镓锡(GTO)、氧化铟镓锡(IGTO)、氧化铟锡(ITO)中的任意一种。本实施例中，采用氧化铟锡锌(ITZO)材料来制备保护层5。
对于上述的氧化物有源层4及保护层5采用构图工艺，以形成图形化的氧化物有源层4和图形化的保护层5，这样，有源层4被保护层5覆盖，能避免在形成源、漏极时金属刻蚀液对氧化物有源层4(氧化铟镓锌)的腐蚀。此外，在本次构图工艺过程中，保护层同样能够阻止刻蚀液对位于保护层之下的氧化物有源层的损伤。
相对于现有技术中采用的绝缘的刻蚀阻挡层，ITZO保护层5为半导体材料层，其与氧化物有源层4和源、漏电极有很好的电学匹配，因此在源、漏电极与氧化物有源层4电连接时无需制备过孔。而且，保护层5和氧化物有源层4可采用一次构图工艺形成，与现有技术相比，省去了刻蚀阻挡层单独形成所需的光照制程，减少了一次构图工艺，使得产品的制程简单、制作周期短、良品率高、生产成本低。本实施例中具体介绍了以ITZO为保护层的薄膜晶体管的制作方法，应当理解的是，由于具体制作方法和技术效果基本相同，包括由其他氧化锡系材料形成的保护层的薄膜晶体管同样落入本发明的保护范围。
在步骤4中，制作源、漏极，并进行退火。
如图5所示，采用磁控溅射技术沉积源、漏电极金属膜，并且采用构图工艺，形成源、漏电极6的图形。源、漏电极6以及连接金属可采用Cr、Ti、Mo、W、Al、Cu等金属材料或合金材料及其它复合导电材料制备。源、漏电极6可以是一层或多层结构，厚度范围为1-1000nm。本实施例中，例如，源、漏电极6的厚度为800nm。然后，在含氧气气氛中进行退火，退火温度范围为100-900℃，含氧气氛为氧气分压为1％-99％的气氛。本实施例中，例如，退火温度范围为300-500℃，氧气分压为60％。含氧气氛中退火使得氧化物有源层得到补氧修复，提升了薄膜晶体管的性能。本实施例中还可以采用其它可以补氧修复有源层的气氛，在此不作限定。
由于采用磁控溅射技术沉积源、漏电极金属时，等离子对氧化物有源层4会造成损伤，如当氧化物有源层4为氧化铟镓锌 (IGZO)时，等离子会对IGZO材料中的O-In，O-Ga，O-Zn键造成损伤，例如，上述键断裂使氧产生扩散。在含氧气气氛中进行退火，能使富氧的保护层5中的部分氧运动到有源层4或者有源层4内部的氧运动而与有源层4内部的金属键合，使有源层4得到修复，从而改善薄膜晶体管的特性。同时，退火时较高的温度使氧化物有源层4(氧化铟镓锌)和保护层5(如氧化铟锡锌)内的物质发生相互扩散，并分别在氧化物有源层4与保护层5两者相接触的各自部分中形成过渡区域8，该过渡区域8包含由于扩散形成的氧化铟镓锡锌(InGaZnSnO)材料。图6示出了未经含氧气氛退火工艺得到的薄膜晶体管的转移特性曲线，从图6中可以看出，未经含氧气氛退火工艺得到的薄膜晶体管的关态电流很大，几乎与开态电流在同一个数量级，导致制备成的薄膜晶体管缺乏开关特性而不能正常使用。图7示出了经过在含氧气氛中进行退火而得到的薄膜晶体管的转移特性曲线，从图7中可以看出，本实施例的薄膜晶体管经在含氧气氛中退火，其关态电流较退火之前(参考图6)有明显的降低，因此在含氧气氛中进行退火形成的过渡区域能够降低薄膜晶体管的关态电流。
应当理解的是，上述的保护层5可以全部由过渡区域8构成，也就是说，可以控制保护层的厚度和退火工艺条件使得氧化物有源层材料扩散到整个氧化锡系保护层，从而保护层完全转变为过渡区域8。可替代地，控制保护层的厚度和退火工艺条件也可以使保护层5的部分区域形成为过渡区域8的结构，即靠近有源层4的部分为过渡区域8，远离有源层4的部分为非过渡区域，此时有源层4的材料没有扩散至保护层的非过渡区域，保护层的非过渡区域由氧化锡系材料构成。
此外，保护层5和源、漏电极6之间也会发生物质的相互扩散，能改善源、漏电极与有源层4的欧姆接触。
本实施例以氧化物有源层为IGZO、保护层为ITZO为例介绍了薄膜晶体管的制作方法。通过应用本实施例的制作方法，在采用其他氧化物有源层材料(如氮氧化锌等)、采用其他氧化锡系 保护层材料时，同样能够减少构图工艺，在含氧气氛中进行退火同样能够修复沉积源、漏电极薄膜时等离子对有源层的损伤，并且在氧化物有源层和保护层两者相接触的各自部分中分别形成一过渡区域，从而能够降低薄膜晶体管的关态电流。因此，采用其他氧化物有源层材料(如氮氧化锌等)和其他氧化锡系保护层材料的薄膜晶体管的制备方法同样落入本发明的保护范围之内。
实施例2
如图8所示，本实施例提供一种薄膜晶体管，包括：氧化物有源层4、位于氧化物有源层4之上的保护层5、以及源、漏电极6，所述保护层包括氧化锡系材料，所述氧化物有源层4的与所述保护层5接触的部分中包括一过渡区域8，并且所述保护层5的与所述氧化物有源层4接触的部分中包括一过渡区域8，所述的过渡区域8用于降低薄膜晶体管的关态电流。本实施例中的薄膜晶体管的具体制作过程可参照实施例1中的方法，在此不再赘述。
具体地，所述保护层5还包括远离氧化物有源层4的非过渡区域，所述过渡区域8包含氧化锡系材料与所述氧化物有源层的材料经过退火发生扩散而相互结合形成的材料，所述非过渡区域是由含氧化锡系材料制备的。
本实施以底栅型薄膜晶体管为例介绍，应当理解的是，对于顶栅型薄膜晶体管也是适用的。
所述保护层5可以由过渡区域8构成，也就是说全部的保护层5都是由过渡区域8构成。所述过渡区域8包含氧化锡系材料与所述氧化物有源层的材料经过退火发生扩散而相互结合形成的材料。
所述保护层5的一侧与氧化物有源层4接触，所述保护层5的另一侧与所述源、漏电极6接触。所述氧化物有源层4通过保护层5分别与所述源、漏电极6电连接。
所述氧化锡系材料可以为氧化铟锡锌(ITZO)、氧化铝锡锌(ATZO)、氧化锌锡(ZTO)、氧化镓锡(GTO)、氧化铟镓锡(IGTO)、氧化铟锡(ITO)中的任意一种。
所述氧化物有源层4的材料可以为氧化铟镓锌(IGZO)。
应当理解的是，其它元素的半导体或化合物半导体可以用于制备有源层，其它非晶态、多晶态、单晶态以及混合态半导体也可以用于制备有源层。
所述保护层5的厚度范围为1-100nm。
所述有源层4的厚度范围为5-200nm。
当所述氧化物有源层的材料为IGZO时，所述氧化锡系材料与氧化物有源层4的材料经过退火形成包含氧化铟镓锡锌的过渡区材料层，并且所形成的过渡区域能够降低薄膜晶体管的关态电流。
本实施例中的薄膜晶体管的过渡区域8为经过退火发生扩散的保护层5的材料和氧化物有源层4的材料相互结合形成的，与未经含氧气氛下的退火工艺得到的薄膜晶体管相比，本实施例中的薄膜晶体管具有较低的关态电流，薄膜晶体管的特性优异。
另外，由于保护层5是采用氧化锡系材料制备的，氧化锡系材料对于源、漏极刻蚀液有良好的阻隔作用，在制作薄膜晶体管过程中，保护层的设置使氧化物有源层4的性能不受源、漏极刻蚀液的影响，并且由氧化锡系材料制成的保护层5除了能保护氧化物有源层4免受源、漏极刻蚀液腐蚀外，还能阻止后续制备功能层时对氧化物有源层4的影响，例如，源、漏电极6溅射成膜对氧化物有源层4的影响。
另外，现有技术的刻蚀阻挡层5通常采用绝缘材料制备，从而需要在刻蚀阻挡层5上形成过孔，通过该过孔使有源层4和源、漏电极6电性连接，因此需要用于制作刻蚀阻挡层5的单独构图工艺。本实施例中的保护层5是采用氧化锡系材料制备的，具有半导体性质，因此，无须在保护层5上形成过孔，可以采用一次构图工艺对保护层5和氧化物有源层4进行图形化，从而减少了一次构图工艺，简化了薄膜晶体管的制程，缩短了薄膜晶体管制作周期，同时也提高了良品率，降低了生产成本。因此本实施例中的薄膜晶体管的制程简单，良品率高，生产成本低。
实施例3
本实施例提供一种显示基板，所述的显示基板包括上述的薄膜晶体管、以及本领域技术人员公知的其它必要的功能层和连接线。
本实施例提供的显示基板具有制程简单、良品率高、生产成本低的优点。
实施例4
本实施例提供一种显示装置，其特征在于，所述的显示装置包括上述的显示基板。本实施例提供的显示装置具有制程简单、良品率高、生产成本低的优点。
应当理解的是，显示装置可以应用于液晶电视、高清晰度数字电视、电脑(台式和笔记本)、手机、PDA、GPS、车载显示、投影显示、摄像机、数码相机、电子手表、计算器、电子仪器、仪表、公共显示和虚幻显示等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种薄膜晶体管的制备方法，其特征在于，包括步骤：
    在基板上形成氧化物有源层薄膜、保护层薄膜，所述保护层薄膜的材料为氧化锡系材料，并且采用一次构图工艺对氧化物有源层薄膜、保护层薄膜进行图形化，以形成氧化物有源层、保护层的图形；
    在保护层上形成源、漏电极薄膜，通过构图工艺对源、漏电极薄膜进行图形化，以形成源、漏电极的图形；以及
    在含氧气氛下进行退火，使得所述氧化物有源层的材料通过所述氧化物有源层与所述保护层之间的接触面而扩散到所述保护层，以在所述保护层中形成一过渡区域，并且所述保护层的材料通过所述接触面而扩散到所述氧化物有源层，以在所述氧化物有源层中形成一过渡区域，所述的过渡区域用于降低薄膜晶体管的关态电流。
  2. 如权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述保护层还包括远离氧化物有源层的非过渡区域，所述的非过渡区域是由含氧化锡系材料制备的。
  3. 如权利要求1所述的薄膜晶体管的制备方法，其特征在于，所述保护层由过渡区域构成。
  4. 如权利要求1至3中任一项所述的薄膜晶体管的制备方法，其特征在于，所述氧化锡系材料为氧化铟锡锌、氧化铝锡锌、氧化锌锡、氧化镓锡、氧化铟镓锡、氧化铟锡中的任意一种。
  5. 如权利要求4所述的薄膜晶体管的制备方法，其特征在于，所述氧化物有源层的材料为氧化铟镓锌。
  6. 如权利要求5所述的薄膜晶体管的制备方法，其特征在于， 所述过渡区域包括氧化铟镓锡锌材料。
  7. 如权利要求1至3中任一项所述的薄膜晶体管的制备方法，其特征在于，所述在含氧气氛下进行退火的步骤中所述含氧气氛为1％-99％范围的氧气分压气氛或纯氧气氛。
  8. 如权利要求1至3中任一项所述的薄膜晶体管的制备方法，其特征在于，所述在含氧气氛下进行退火的步骤中所述退火是在100-900℃范围的退火温度下进行的。
  9. 如权利要求1至3中任一项所述的薄膜晶体管的制备方法，其特征在于，所述的保护层是在含氧气氛下沉积制备的，所述的含氧气氛为1％-99％范围的氧气分压气氛或纯氧气氛。
  10. 一种薄膜晶体管，其特征在于，包括：氧化物有源层、位于氧化物有源层之上的保护层、以及源、漏电极，所述保护层包括氧化锡系材料，所述氧化物有源层的与所述保护层相接触的部分中包括一过渡区域，并且所述保护层的与所述氧化物有源层相接触的部分中包括一过渡区域，所述的过渡区域用于降低薄膜晶体管的关态电流。
  11. 如权利要求10所述的薄膜晶体管，其特征在于，所述保护层还包括远离氧化物有源层的非过渡区域，
    所述过渡区域包含氧化锡系材料与所述氧化物有源层的材料相互结合形成的材料，所述的非过渡区域是由含氧化锡系材料制备的。
  12. 如权利要求10所述的薄膜晶体管，其特征在于，所述保护层由过渡区域构成，所述过渡区域包含氧化锡系材料与所述氧化物有源层的材料相互结合形成的材料。
  13. 如权利要求10所述的薄膜晶体管，其特征在于，所述保护层的一侧与氧化物有源层接触，所述保护层的另一侧与所述源、漏接触，所述氧化物有源层通过保护层分别与所述源、漏电极电连接。
  14. 如权利要求11或12所述的薄膜晶体管，其特征在于，所述氧化锡系材料为氧化铟锡锌、氧化铝锡锌、氧化锌锡、氧化镓锡、氧化铟镓锡、氧化铟锡中的任意一种。
  15. 如权利要求14所述的薄膜晶体管，其特征在于，所述氧化物有源层的材料为氧化铟镓锌。
  16. 如权利要求15所述的薄膜晶体管，其特征在于，所述保护层的厚度范围为1-100nm。
  17. 如权利要求16所述的薄膜晶体管，其特征在于，所述氧化物有源层的厚度范围为5-200nm。
  18. 如权利要求15所述的薄膜晶体管，其特征在于，所述氧化锡系材料与氧化物有源层的材料相互结合形成的过渡区域包括氧化铟镓锡锌材料。
  19. 一种显示基板，其特征在于，所述的显示基板包括如权利要求10至18中任一项所述的薄膜晶体管。
  20. 一种显示装置，其特征在于，所述的显示装置包括如权利要求19所述的显示基板。
PCT/CN2014/086920 2014-04-28 2014-09-19 薄膜晶体管及其制备方法、显示基板、显示装置 WO2015165196A1 (zh)

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103985639B (zh) * 2014-04-28 2015-06-03 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板、显示装置
CN104916703B (zh) * 2015-05-07 2018-07-31 京东方科技集团股份有限公司 一种氧化物薄膜晶体管、阵列基板和显示装置
CN105572990B (zh) * 2015-12-21 2019-07-12 武汉华星光电技术有限公司 阵列基板及其制造方法、液晶显示面板
CN105655294B (zh) * 2016-01-14 2019-05-31 京东方科技集团股份有限公司 阵列基板的制造方法、阵列基板和显示装置
KR102653048B1 (ko) * 2018-04-20 2024-04-01 소니그룹주식회사 촬상 소자, 적층형 촬상 소자 및 고체 촬상 장치
CN116913974A (zh) * 2023-06-26 2023-10-20 河南省科学院材料研究所 一种高性能ZnSnO薄膜晶体管及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008062720A1 (en) * 2006-11-21 2008-05-29 Canon Kabushiki Kaisha Method for manufacturing thin film transistor which uses an oxide semiconductor
US20100219410A1 (en) * 2009-02-27 2010-09-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR100999798B1 (ko) * 2010-02-11 2010-12-08 엘지이노텍 주식회사 반도체 발광소자 및 그 제조방법
US20110157509A1 (en) * 2009-12-30 2011-06-30 Younghoon Kim Liquid crystal display device and manufacturing method of the same
CN103715264A (zh) * 2013-12-23 2014-04-09 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板及显示装置
CN103985639A (zh) * 2014-04-28 2014-08-13 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板、显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5584960B2 (ja) * 2008-07-03 2014-09-10 ソニー株式会社 薄膜トランジスタおよび表示装置
KR20120084940A (ko) * 2011-01-21 2012-07-31 서울대학교산학협력단 박막 트랜지스터 및 그 제조 방법
CN103403849B (zh) * 2011-02-28 2016-08-03 夏普株式会社 半导体装置及其制造方法以及显示装置
CN102655165B (zh) * 2011-03-28 2015-04-29 京东方科技集团股份有限公司 一种非晶氧化物薄膜晶体管及其制作方法、显示面板
CN103579115B (zh) * 2013-11-11 2015-11-25 京东方科技集团股份有限公司 互补式薄膜晶体管及其制备方法、阵列基板、显示装置
CN103715268B (zh) * 2013-12-27 2016-04-06 合肥京东方光电科技有限公司 氧化物薄膜晶体管及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008062720A1 (en) * 2006-11-21 2008-05-29 Canon Kabushiki Kaisha Method for manufacturing thin film transistor which uses an oxide semiconductor
US20100219410A1 (en) * 2009-02-27 2010-09-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20110157509A1 (en) * 2009-12-30 2011-06-30 Younghoon Kim Liquid crystal display device and manufacturing method of the same
KR100999798B1 (ko) * 2010-02-11 2010-12-08 엘지이노텍 주식회사 반도체 발광소자 및 그 제조방법
CN103715264A (zh) * 2013-12-23 2014-04-09 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板及显示装置
CN103985639A (zh) * 2014-04-28 2014-08-13 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板、显示装置

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