WO2018196087A1 - 一种阵列基板、显示装置及其制作方法 - Google Patents

一种阵列基板、显示装置及其制作方法 Download PDF

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WO2018196087A1
WO2018196087A1 PCT/CN2017/086232 CN2017086232W WO2018196087A1 WO 2018196087 A1 WO2018196087 A1 WO 2018196087A1 CN 2017086232 W CN2017086232 W CN 2017086232W WO 2018196087 A1 WO2018196087 A1 WO 2018196087A1
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layer
insulating layer
oxide
transistor
polysilicon
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PCT/CN2017/086232
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English (en)
French (fr)
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刘兆松
徐源竣
李松杉
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深圳市华星光电技术有限公司
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Priority to US15/536,924 priority Critical patent/US20190103420A1/en
Publication of WO2018196087A1 publication Critical patent/WO2018196087A1/zh

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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of planar display technologies, and in particular, to an array substrate, a display device, and a method of fabricating the same.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED), and an active-matrix organic light emitting diode (Active-matrix organic light emitting diode, AMOLED) has significant advantages over LCDs in terms of power consumption, color saturation, contrast, and flexible applications, and is widely used.
  • TFT Thin Film Transistor
  • LTPS low temperature poly-silicon
  • Oxide TFT oxide thin film transistor
  • the preparation process if the ILD film layer is improperly selected, the polycrystalline silicon cannot be sufficiently repaired in the hydrogenation process, eventually leading to leakage, or excessive hydrogen atoms permeating into the oxide semiconductor layer, resulting in reduced reliability. The problem.
  • the technical problem to be solved by the present invention is to provide an array substrate, a display device and a manufacturing method thereof.
  • the leakage problem of the low temperature polysilicon transistor is effectively reduced, and the reliability of the oxide transistor is improved.
  • a technical solution adopted by the present invention is to provide a display device including the above array substrate, wherein the array substrate includes a substrate substrate and a low temperature polysilicon transistor and oxidation over the substrate substrate
  • the transistor is provided with a display area and a non-display area around the display area, the low temperature polysilicon transistor is located in the non-display area, the oxide transistor is located in the display area, and the low temperature polysilicon transistor comprises a stacked polysilicon layer and a first insulation Floor And a third insulating layer, the first insulating layer comprises a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is between the polysilicon layer and the silicon oxide layer, and the third insulating layer is between the polysilicon layer and the first insulating layer
  • the oxide transistor includes a stacked oxide semiconductor layer, a second insulating layer, and a fourth insulating layer, the fourth insulating layer is over the oxide semiconductor layer, the second insulating layer is
  • an array substrate including: a substrate substrate and a low temperature polysilicon transistor and an oxide transistor over the substrate substrate, and the substrate is provided with a display area and a non-display area around the display area, the low temperature polysilicon transistor is located in the non-display area, the oxide transistor is located in the display area, and the low temperature polysilicon transistor comprises a stacked polysilicon layer and a first insulating layer, and the first insulating layer includes oxidation a silicon layer and a silicon nitride layer, wherein the silicon nitride layer is between the polysilicon layer and the silicon oxide layer; the oxide transistor comprises a stacked oxide semiconductor layer and a second insulating layer, and the second insulating layer does not comprise a silicon nitride layer .
  • another technical solution adopted by the present invention is to provide a method for preparing an array substrate, comprising: forming a low temperature polysilicon transistor and an oxide transistor on a substrate, respectively, and displaying a display on the substrate a region and a non-display region around the display region, the low temperature polysilicon transistor is located in the non-display region, and the oxide transistor is located in the display region; forming the low temperature polysilicon transistor over the substrate substrate comprises: sequentially forming a polysilicon layer on the substrate substrate and An insulating layer, the first insulating layer includes a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is adjacent to the polysilicon layer; forming an oxide transistor over the substrate substrate comprises: sequentially forming a second insulating layer on the substrate substrate The oxide semiconductor layer, the second insulating layer does not contain a silicon nitride layer.
  • the beneficial effects of the present invention are: forming a silicon oxide and silicon nitride structure on the polysilicon layer by laminating a polysilicon layer and a first insulating layer including a silicon oxide layer and a silicon nitride layer in a low temperature polysilicon transistor, and During the formation of the silicon nitride layer, a large amount of hydrogen bonds are generated, so that the polysilicon layer is sufficiently repaired in the hydrogenation process, the leakage problem of the low-temperature polysilicon transistor is effectively reduced, and the oxide semiconductor layer is stacked and disposed in the oxide transistor.
  • the second insulating layer, and the second insulating layer does not contain a silicon nitride layer, so that the oxide semiconductor layer is not affected by hydrogen bonding, thereby improving the reliability of the oxide transistor.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • step S11 in FIG. 3 is a schematic flow chart of step S11 in FIG. 3;
  • FIG. 5 is a schematic structural view of an embodiment of the array substrate of FIG. 4; FIG.
  • FIG. 6 is a schematic flow chart of step S12 in Figure 3;
  • FIG. 7 is a schematic structural view of an embodiment of the array substrate of FIG. 6;
  • FIG. 8 is a schematic flow chart of another embodiment of a method for fabricating an array substrate according to the present invention.
  • FIG. 9 is a schematic structural view of an embodiment of the array substrate of FIG. 8;
  • Figure 10 is a schematic view showing the structure of a display device of the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate according to the present invention.
  • the array substrate includes: a substrate substrate 10 and a low temperature polysilicon transistor 20 and an oxide transistor 30 over the substrate substrate 10.
  • the low temperature polysilicon transistor 20 includes a polysilicon layer 21 and a first insulating layer 22, and the first insulating layer 22 includes a silicon oxide layer 222 and a silicon nitride layer 221, wherein the silicon nitride layer 221 is located in the polysilicon layer 21 and silicon oxide. Between layers 222.
  • the oxide transistor 30 includes a stacked oxide semiconductor layer 31 and a second insulating layer 32, and the second insulating layer 32 does not contain a silicon nitride layer.
  • low temperature poly-silicon is combined with an oxide thin film transistor (Oxide TFT), which is prepared in the same device, thereby forming a low temperature polysilicon transistor on the substrate substrate 10. 20 and an oxide transistor 30.
  • the substrate 10 may be a glass substrate or a flexible substrate.
  • a silicon dioxide substrate, or a polyvinyl chloride (PV) or a polytetrafluoro ethylene (PFA) may be used.
  • PV polyvinyl chloride
  • PFA polytetrafluoro ethylene
  • PET polyethylene terephthalate
  • the polysilicon layer 21 is located on the base substrate 10, and may be a polysilicon material semiconductor layer, or may be an amorphous silicon material by a solid phase crystallization technique (SPC), and a heat treatment process is used to convert the amorphous silicon material into a polysilicon material.
  • the first insulating layer 22 may be composed of a single layer of silicon nitride (SiNx) or a plurality of layers of silicon nitride/silicon oxide (SiO 2 /SiNx).
  • the first insulating layer 22 may further include a silicon oxide layer 222 and a silicon nitride layer 221, wherein the silicon nitride layer 221 is adjacent to the polysilicon layer 21, and in the process of forming the silicon nitride layer 221, due to the addition of a large amount
  • the ammonia gas (NH 3 ) also generates a large amount of hydrogen bonds (H) while forming silicon nitride (SiNx).
  • the oxide semiconductor layer 31 may be at least one of indium oxide, zinc oxide, tin oxide, gallium oxide, or the like, and the second insulating layer 32 may be composed of silicon oxide (SiO 2 ).
  • a structure of silicon oxide and silicon nitride is formed on the polysilicon layer, and at the same time, a large amount of hydrogen bonds are generated in the process of forming the silicon nitride layer, so that the polysilicon layer is sufficiently repaired in the hydrogenation process, and the silicon layer is effectively reduced.
  • the leakage problem of the low-temperature polysilicon transistor is formed, and a silicon oxide layer containing no silicon nitride is formed in the vicinity of the oxide semiconductor layer, so that the oxide semiconductor layer is not affected by hydrogen bonding, thereby improving the reliability of the oxide transistor.
  • the second insulating layer 32 may be the same layer as the silicon oxide layer 222 in the first insulating layer 22, and finally form a structure of silicon oxide and silicon nitride on the polysilicon layer by two film formation methods, and oxidize. There is only a silicon oxide structure in the vicinity of the semiconductor layer.
  • FIG. 2 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • the array substrate further includes a third insulating layer 23 and a fourth insulating layer 33.
  • the third insulating layer 23 is located between the polysilicon layer 21 and the first insulating layer 22.
  • the fourth insulating layer 33 is located above the oxide semiconductor layer 31.
  • the low temperature polysilicon transistor 20 distinguished by a broken line further includes a first gate electrode 24, a first source electrode 25a, and a first drain electrode 25b.
  • the first gate 24 is adjacent to the polysilicon layer 21 and is located between the third insulating layer 23 and the first insulating layer 22.
  • the first source 25a and the first drain 25b are located above the fourth insulating layer 33.
  • first source electrode 25a and the first drain electrode 25b are respectively disposed through the first insulating layer 33, the second insulating layer 32, the first insulating layer 22, and the third insulating layer 23, and the first contact hole and the second The contact hole is electrically connected to the polysilicon layer 21 and forms a low-temperature polysilicon transistor of a top gate structure with the first gate 24.
  • the oxide transistor 30 distinguished by a broken line further includes a second gate electrode 34, a second source electrode 35a, and a second drain electrode 35b.
  • the second gate electrode 34 is adjacent to the oxide semiconductor layer 31 and located between the third insulating layer 23 and the second insulating layer 32.
  • the second source 35a and the second drain 35b are located above the fourth insulating layer 33. Further, a portion of the second source 35a and the second drain 35b are electrically connected to the oxide semiconductor layer 31 and the second gate through the third contact hole and the fourth contact hole provided in the fourth insulating layer 33, respectively. 34 forms an oxide transistor of a bottom gate structure.
  • the low-temperature polysilicon transistor is formed by automatically adjusting the top gate structure, and the oxide transistor is formed by using the bottom gate structure, so that the number of the photomask can be reduced.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention. among them, The method for fabricating the array substrate comprises the following steps:
  • S10 forming a low-temperature polysilicon transistor and an oxide transistor on the substrate, respectively, a display region and a non-display region around the display region are disposed on the substrate, the low-temperature polysilicon transistor is located in the non-display region, and the oxide transistor is located in the display region .
  • the base substrate may be a transparent material, and specifically may be a water-proof and oxygen-transparent organic material or glass. Commonly used are glass substrates, silica substrates, and some applications can use polyvinyl chloride (PV), polytetrafluoro ethylene (PFA), polyethylene terephthalate (Polytetrafluoroethylene). Polyethylene terephthalate, PET) substrates, and the like. In other embodiments, a buffer layer of a certain thickness may be deposited on the substrate before the low temperature polysilicon transistor and the oxide transistor are formed.
  • the deposition material may be a single layer or a plurality of layers of SiO 2 /SiNx for increasing the degree of adhesion between the polysilicon layer to be formed and the substrate, and is advantageous for reducing the heat conduction effect.
  • step S10 includes the following sub-steps:
  • S11 forming a low temperature polysilicon transistor over the substrate substrate comprises: sequentially forming a polysilicon layer and a first insulating layer on the substrate, the first insulating layer comprising a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is adjacent to the polysilicon layer .
  • Forming an oxide transistor over the base substrate includes sequentially forming a second insulating layer and an oxide semiconductor layer on the base substrate, and the second insulating layer does not include a silicon nitride layer.
  • the first insulating layer may be composed of a single layer of silicon nitride (SiNx) or a plurality of layers of silicon nitride/silicon oxide (SiO 2 /SiNx). Further, the first insulating layer may include a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is close to the polysilicon layer, and in the process of forming the silicon nitride layer, a large amount of ammonia gas (NH 3 ) is added to generate Silicon nitride (SiNx) also produces a large number of hydrogen bonds (H), providing the hydrogen required for hydrogenation of polysilicon.
  • the second insulating layer is composed of silicon oxide (SiO 2 ), which prevents the oxide transistor from being affected by H.
  • a structure of silicon oxide and silicon nitride is formed on the polysilicon layer, and a large amount of hydrogen bonds are generated in the process of forming the silicon nitride layer, so that the polysilicon layer is sufficiently repaired in the hydrogenation process, and the low temperature is effectively reduced.
  • the leakage problem of the polysilicon transistor forms a silicon oxide layer containing no silicon nitride on the oxide semiconductor layer, so that the oxide semiconductor layer is not affected by hydrogen bonding, thereby improving the reliability of the oxide transistor.
  • silicon oxide is deposited on the base substrate to form a second insulating layer, and the second insulating layer is the same layer as the silicon oxide layer in the first insulating layer.
  • silicon nitride is deposited on the polysilicon layer to form a first insulating layer, and silicon oxide is further deposited on the first insulating layer to form a second insulating layer. After two film formation methods, a structure of silicon oxide and silicon nitride is finally formed on the polysilicon layer, and only a silicon oxide structure is formed in the vicinity of the oxide semiconductor layer.
  • FIG. 4 is a schematic flowchart of step S11 in FIG. 3, and step S11 further includes the following sub-steps:
  • S111 depositing silicon oxide and/or silicon nitride on the polysilicon layer to form a third insulating layer.
  • S112 depositing a metal substance on the third insulating layer and forming a first gate and a second gate by patterning, the first gate is adjacent to the polysilicon layer, and the second gate is adjacent to the oxide semiconductor layer.
  • S113 forming a connection region corresponding to the source and the drain of the polysilicon layer by using the first gate in a self-aligned manner.
  • S114 depositing silicon nitride or a mixture of silicon oxide and silicon nitride on the first gate to form a first insulating layer.
  • the above sub-step S110 specifically includes: depositing a polysilicon layer on the base substrate 10, and patterning the polysilicon layer 21 to form a low-temperature polysilicon layer, wherein the patterning process may include photoresist coating and exposure. , development, etching and photoresist stripping processes.
  • an amorphous silicon layer (a-Si) may also be deposited, and the amorphous silicon layer (a-Si) is converted into a polysilicon layer by solid phase crystallization (SPC).
  • SPC solid phase crystallization
  • -Si) further forms a low temperature polysilicon layer, which is not limited herein.
  • the sub-step S111 includes: after the polysilicon layer 21 is formed and patterned, the deposition of a single-layer silicon oxide (SiO 2 ) film layer or a silicon nitride (SiNx) film layer, or silicon oxide (SiO 2 ).
  • a laminate of silicon nitride (SiNx) is formed to form a third insulating layer 23 overlying the polysilicon layer 21 and the substrate 20 for isolating the polysilicon layer 21 from other metal layers to avoid short circuits.
  • a buffer layer of a certain thickness may be deposited on the substrate 10 before the polysilicon layer 21 and the third insulating layer 23 are formed.
  • the deposition material may be a single layer or a plurality of layers of SiO 2 /SiNx for increasing the degree of adhesion between the polysilicon layer to be formed and the substrate, and is advantageous for reducing the heat conduction effect.
  • the sub-step S112 includes: depositing a layer of metal on the third insulating layer 23, forming a first gate 24 having a predetermined pattern by a process such as photoresist coating, exposure, development, etching, and photoresist stripping.
  • the second gate 34 wherein the first gate 24 is adjacent to the polysilicon layer 21, and the second gate 34 is adjacent to the oxide semiconductor layer.
  • the material of the first gate electrode 24 and the second gate electrode 34 may be any combination of metals such as aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), and titanium (Ti).
  • the sub-step S113 includes: forming the source and drain connection regions 21a and 21b of the polysilicon layer 21 by using the first gate 24 in a self-alignment manner, the connection region being used for the corresponding source Automatically connected to the drain.
  • step S113 may be performed after S111 and S112, or may be performed before S111 and S112, which is not limited herein. In order to avoid that the operation of dividing the connection region corresponding to the source and the drain affects other operations, it may be selected to perform S113 after S111 and S112.
  • the above sub-step S114 specifically includes depositing silicon nitride, or a mixture of silicon oxide and silicon nitride on the first gate 24 to form the first insulating layer 22, and performing pattern processing.
  • the first insulating layer 22 covers only the first gate electrode 24 and a portion of the third insulating layer 23 corresponding to the polysilicon layer 21.
  • a large amount of hydrogen bonds (H) are generated in the formation of silicon nitride (SiNx) due to the addition of a large amount of ammonia (NH 3 ), which provides hydrogen required for hydrogenation of polycrystalline silicon. .
  • first gate 24 and the second gate 34 may also be formed by other methods, such as by spraying or the like, which is not limited herein.
  • FIG. 6 is a schematic flowchart of step S12 in FIG. 3 , and step S12 further includes the following sub-steps:
  • S120 depositing silicon oxide on the second gate to form a second insulating layer.
  • S121 forming an oxide semiconductor layer by patterning on the second insulating layer.
  • S122 depositing silicon oxide on the oxide semiconductor layer to form a fourth insulating layer.
  • the above sub-step S120 specifically includes depositing silicon oxide on the second gate electrode 34 to form a second insulating layer 32.
  • the second insulating layer 32 covers the second gate 34, the third insulating layer and the first insulating layer for isolating the second gate 34 from other metal layers to avoid short circuit.
  • the second insulating layer 32 may be the same layer as the silicon oxide layer in the first insulating layer.
  • the sub-step S121 includes the following steps: forming the oxide semiconductor layer 31 by patterning on the second insulating layer 32.
  • the oxide used in the oxide semiconductor layer 31 is an oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).
  • the sub-step S122 includes: depositing an insulating material such as silicon oxide or resin on the oxide semiconductor layer 31 to form a fourth insulating layer 33, and covering the oxide semiconductor layer 31 and the second insulating layer 32 on the fourth insulating layer 33, It is used to isolate the oxide semiconductor layer 31 from other metal layers to avoid short circuits.
  • an insulating material such as silicon oxide or resin
  • FIG. 8 is a schematic flow chart of another embodiment of a method for fabricating an array substrate according to the present invention.
  • the method for fabricating an array substrate further includes the following steps:
  • S15 depositing a transparent metal layer on the first contact hole and the second contact hole, the third contact hole, and the fourth contact hole, respectively, to form a first source and a first drain, a second source, and a second drain.
  • holes are formed in the fourth insulating layer 33, the second insulating layer 32, the first insulating layer 22, and the third insulating layer 23 to form a connection region corresponding to the source and drain of the polysilicon layer 21.
  • a first contact hole and a second contact hole depositing a transparent metal to the first contact hole and the second contact hole, so that a part of the metal is electrically connected to the doped region of the polysilicon layer 21 in a self-aligned manner through the contact hole to form a first
  • the source 25a and the first drain 25b The first source 25a, the first drain 25b, and the first gate 24 form a low temperature polysilicon transistor of a top gate structure.
  • a third contact hole and a fourth contact hole are formed in the fourth insulating layer 33 to form the oxide semiconductor layer 31, and a transparent metal is deposited on the third contact hole and the fourth contact hole, so that part of the metal passes.
  • the contact holes are electrically connected to the oxide semiconductor layer 31 to form a second source 35a and a second drain 35b.
  • the second source 35a, the second drain 35b, and the second gate 34 form an oxide transistor of a bottom gate structure.
  • the first source 25a, the first drain 25b, the second source 35a, and the second drain 35b may be simultaneously formed by one patterning process, and the source drain metal material may be aluminum (Al) or molybdenum.
  • Metals such as (Mo), chromium (Cr), copper (Cu), and titanium (Ti).
  • the low-temperature polysilicon transistor is formed by automatically adjusting the top gate structure, and the oxide transistor is formed by using the bottom gate structure, so that the number of the photomask can be reduced.
  • a PV layer, a PLN layer, an OLED layer, a cathode, and the like are sequentially formed on the first source electrode 25a, the first drain electrode 25b, the second source electrode 35a, and the second drain electrode 35b to obtain a complete thin film transistor TFT substrate.
  • the present invention further includes a display device.
  • the display device 100 includes the array substrate 101 of any of the above structures, or the array substrate 101 prepared by any of the above methods. The method can be used to form the array substrate shown in FIG. 1 or 2, and details are not described herein again.
  • the display device may be an active-matrix organic light emitting diode (AMOLED) or a TFT LCD display device.
  • AMOLED active-matrix organic light emitting diode
  • the array substrate comprises a base substrate and a low temperature polysilicon transistor and an oxide transistor disposed above the substrate, the substrate is provided with a display area and a non-display area around the display area, and the low temperature polysilicon transistor is located in the non-display area, The oxide transistor is located within the display area.
  • the low temperature polysilicon transistor includes a stacked polysilicon layer and a first insulating layer, the first insulating layer including a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is adjacent to the polysilicon layer.
  • the oxide transistor includes a stacked oxide semiconductor layer and a second insulating layer, and the second insulating layer does not contain a silicon nitride layer.

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Abstract

一种阵列基板、显示装置及其制作方法。其中，阵列基板包括衬底基板（10）和位于衬底基板（10）上方的低温多晶硅晶体管（20）和氧化物晶体管（30）；低温多晶硅晶体管（20）包括层叠设置的多晶硅层（21）和第一绝缘层（22），第一绝缘层（22）包括氧化硅层（222）以及氮化硅层（221），其中氮化硅层（221）位于多晶硅层（21）和氧化硅层（222）之间；氧化物晶体管（30）包括层叠设置的氧化物半导体层（31）和第二绝缘层（32），第二绝缘层（32）不含氮化硅层。有效降低了低温多晶硅晶体管的漏电问题，同时提高氧化物晶体管的可靠性。

Description

一种阵列基板、显示装置及其制作方法 【技术领域】
本发明涉及平面显示技术领域，特别是涉及一种阵列基板、显示装置及其制作方法。
【背景技术】
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)，而主动矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)在能耗、色彩饱和度、对比度、柔性应用等方面相对于LCD有显著优势，被广泛使用。
本申请的发明人在长期的研发中发现，由于主动矩阵有机发光二极体AMOLED面板为电流驱动，需要薄膜晶体管(Thin Film Transistor，TFT)具有较高的流动性。现有技术中，将低温多晶硅技术(Low Temperature Poly-silicon，LTPS)与氧化物薄膜电晶体管(Oxide TFT)相结合，将其制备在同一器件中。然而，在制备过程中，如果ILD膜层选择不当，则无法使多晶硅在氢化过程中得到充分的修复，最终导致漏电的后果，或者有过多的氢原子渗入氧化物半导体层，导致可靠度降低的问题。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板、显示装置及其制作方法，通过上述方式，有效降低了低温多晶硅晶体管的漏电问题，同时提高氧化物晶体管的可靠性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示装置，该显示装置包括上述的阵列基板，其中，阵列基板包括衬底基板和位于衬底基板上方的低温多晶硅晶体管和氧化物晶体管，衬底上设置有显示区域和位于显示区域周围的非显示区域，低温多晶硅晶体管位于非显示区域内，氧化物晶体管位于显示区域内；低温多晶硅晶体管包括层叠设置的多晶硅层、第一绝缘层 和第三绝缘层，第一绝缘层包括氧化硅层以及氮化硅层，其中氮化硅层位于多晶硅层和氧化硅层之间，第三绝缘层，位于多晶硅层与第一绝缘层之间；氧化物晶体管包括层叠设置的氧化物半导体层、第二绝缘层和第四绝缘层，第四绝缘层，位于氧化物半导体层上方，第二绝缘层不含氮化硅层，第二绝缘层与第一绝缘层中的氧化硅层为同一层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括：衬底基板和位于衬底基板上方的低温多晶硅晶体管和氧化物晶体管，衬底上设置有显示区域和位于显示区域周围的非显示区域，低温多晶硅晶体管位于非显示区域内，氧化物晶体管位于显示区域内；低温多晶硅晶体管包括层叠设置的多晶硅层和第一绝缘层，第一绝缘层包括氧化硅层以及氮化硅层，其中氮化硅层位于多晶硅层和氧化硅层之间；氧化物晶体管包括层叠设置的氧化物半导体层和第二绝缘层，第二绝缘层不含氮化硅层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制备方法，该方法包括：在衬底基板上分别形成低温多晶硅晶体管和氧化物晶体管，衬底上设置有显示区域和位于显示区域周围的非显示区域，低温多晶硅晶体管位于非显示区域内，氧化物晶体管位于显示区域内；在衬底基板上方形成低温多晶硅晶体管包括：在衬底基板上依次形成多晶硅层和第一绝缘层，第一绝缘层包括氧化硅层以及氮化硅层，其中氮化硅层靠近多晶硅层；在衬底基板上方形成氧化物晶体管包括：在衬底基板上依次形成第二绝缘层和氧化物半导体层，第二绝缘层不含氮化硅层。
本发明的有益效果是：通过在低温多晶硅晶体管中层叠设置多晶硅层和包括氧化硅层及氮化硅层的第一绝缘层，以在多晶硅层上形成氧化硅加氮化硅的结构，并在氮化硅层形成的过程中产生大量的氢键，使得多晶硅层在氢化过程中得到充分的修复，有效降低了低温多晶硅晶体管的漏电问题，同时，在氧化物晶体管中层叠设置氧化物半导体层和第二绝缘层，且第二绝缘层不含氮化硅层，使得氧化物半导体层不受氢键的影响，进而提高了氧化物晶体管的可靠性。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是本发明阵列基板另一实施方式的结构示意图；
图3是本发明阵列基板制作方法一实施方式的流程示意图；
图4是图3中步骤S11的流程示意图；
图5是图4中阵列基板一实施方式的结构示意图；
图6是图3中步骤S12的流程示意图；
图7是图6中阵列基板一实施方式的结构示意图；
图8是本发明阵列基板制作方法另一实施方式的流程示意图；
图9是图8中阵列基板一实施方式的结构示意图；
图10是本发明显示装置的结构示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
请参阅图1，图1是本发明阵列基板一实施方式的结构示意图，该阵列基板包括：衬底基板10和位于衬底基板10上方的低温多晶硅晶体管20和氧化物晶体管30，衬底上设置有显示区域B和位于显示区域B周围的非显示区域A，低温多晶硅晶体管20位于非显示区域A内，氧化物晶体管30位于显示区域B内。其中，低温多晶硅晶体管20包括层叠设置的多晶硅层21和第一绝缘层22，第一绝缘层22包括氧化硅层222以及氮化硅层221，其中氮化硅层221位于多晶硅层21和氧化硅层222之间。氧化物晶体管30包括层叠设置的氧化物半导体层31和第二绝缘层32，第二绝缘层32不含氮化硅层。
本实施例中，将低温多晶硅技术(Low Temperature Poly-silicon，LTPS)与氧化物薄膜电晶体管(Oxide TFT)相结合，将其制备在同一器件中，进而在衬底基板10上形成低温多晶硅晶体管20和氧化物晶体管30。其中，基板10可以为玻璃基板或柔性基板，在一些应用中，也可以采用二氧化硅基板，或者聚氯乙烯(Polyvinyl chloride，PV)、可熔性聚四氟乙烯(Polytetrafluoro ethylene，PFA)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)基板等。多晶硅层21位于衬底基板10上，可以为多晶硅材质的半导体层，也可以为非晶硅材质通过固相结晶技术(Solid Phase Crystallization，SPC)，采用热处理工艺将非晶硅材质转变为多晶硅材质。第一绝缘层22可以由单层氮化硅(SiNx)或者多层氮化硅/氧化硅(SiO2/SiNx)组成。在本实施例中，第一绝缘层22可以进一步包括氧化硅层222以及氮化硅层221，其中氮化硅层221靠近多晶硅层21，在形成氮化硅层221的过程中，由于加入大量的氨气(NH3)， 在生成氮化硅(SiNx)的同时也会产生大量的氢键(H)。氧化物半导体层31可以为铟氧化物、锌氧化物、锡氧化物、镓氧化物等中的至少一种，第二绝缘层32可以由氧化硅(SiO2)组成。
通过上述方式，在多晶硅层上形成氧化硅加氮化硅的结构，同时，在氮化硅层形成的过程中产生大量的氢键，使得多晶硅层在氢化过程中得到充分的修复，有效降低了低温多晶硅晶体管的漏电问题，而在氧化物半导体层附近形成不含氮化硅的氧化硅层，使得氧化物半导体层不受氢键的影响，进而提高了氧化物晶体管的可靠性。
进一步地，第二绝缘层32可以与第一绝缘层22中的氧化硅层222为同一层，通过两次成膜的方式，最终在多晶硅层上形成氧化硅加氮化硅的结构，而氧化物半导体层附近只有氧化硅结构。
请参阅图2，图2是本发明阵列基板另一实施方式的结构示意图。如图2所示，阵列基板还包括第三绝缘层23及第四绝缘层33。其中，第三绝缘层23，位于多晶硅层21与第一绝缘层22之间。第四绝缘层33，位于氧化物半导体层31上方。
如图2所示，用虚线区分出来的低温多晶硅晶体管20还包括：第一栅极24、第一源极25a和第一漏极25b。第一栅极24，与多晶硅层21相邻，位于第三绝缘层23及第一绝缘层22之间。第一源极25a和第一漏极25b，位于第四绝缘层33上方。进一步地，部分第一源极25a和第一漏极25b分别通过第四绝缘层33、第二绝缘层32、第一绝缘层22及第三绝缘层23所设置的第一接触孔及第二接触孔，与多晶硅层21电连接，且与第一栅极24形成顶栅结构的低温多晶硅晶体管。
如图2所示，用虚线区分出来的氧化物晶体管30还包括：第二栅极34、第二源极35a和第二漏极35b。第二栅极34，与氧化物半导体层31相邻，位于第三绝缘层23及第二绝缘层32之间。第二源极35a和第二漏极35b，位于第四绝缘层33上方。进一步地，部分第二源极35a和第二漏极35b分别通过第四绝缘层33所设置的第三接触孔及第四接触孔，与氧化物半导体层31电连接，且与第二栅极34形成底栅结构的氧化物晶体管。
通过上述方式，采用自动调整顶栅结构形成低温多晶硅晶体管，而采用底栅结构形成氧化物晶体管，可以减少光罩的数量。
参考图3，图3是本发明阵列基板制作方法一实施方式的流程示意图。其中， 阵列基板的制作方法包括以下步骤：
S10：在衬底基板上分别形成低温多晶硅晶体管和氧化物晶体管，衬底上设置有显示区域和位于显示区域周围的非显示区域，低温多晶硅晶体管位于非显示区域内，氧化物晶体管位于显示区域内。
衬底基板可以为透明材质，具体可以为隔水隔氧透明有机材质或玻璃。常见的有玻璃基板、二氧化硅基板，也有一些应用中可采用聚氯乙烯(Polyvinyl chloride，PV)、可熔性聚四氟乙烯(Polytetrafluoro ethylene，PFA)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)基板等。在其他实施例中，形成低温多晶硅晶体管和氧化物晶体管之前，还可以在衬底基板上沉积一层一定厚度的缓冲层。沉积材料可以为单层或多层SiO2/SiNx，用于提高待形成的多晶硅层与基板之间的附着程度，有利于降低热传导效应。
如图3所示，步骤S10包括如下子步骤：
S11：在衬底基板上方形成低温多晶硅晶体管包括：在衬底基板上依次形成多晶硅层和第一绝缘层，第一绝缘层包括氧化硅层以及氮化硅层，其中氮化硅层靠近多晶硅层。
S12：在衬底基板上方形成氧化物晶体管包括：在衬底基板上依次形成第二绝缘层和氧化物半导体层，第二绝缘层不含氮化硅层。
在本实施例中，第一绝缘层可以由单层氮化硅(SiNx)或者多层氮化硅/氧化硅(SiO2/SiNx)组成。进一步地，第一绝缘层可以包括氧化硅层以及氮化硅层，其中氮化硅层靠近多晶硅层，在形成氮化硅层的过程中，由于加入大量的氨气(NH3)，在生成氮化硅(SiNx)的同时也会产生大量的氢键(H)，为多晶硅氢化提供所需要的氢。而第二绝缘层由氧化硅(SiO2)组成，防止氧化物晶体管受H影响。
通过上述方法，在多晶硅层上形成氧化硅加氮化硅的结构，并在氮化硅层形成的过程中产生大量的氢键，使得多晶硅层在氢化过程中得到充分的修复，有效降低了低温多晶硅晶体管的漏电问题，同时，在氧化物半导体层上形成不含氮化硅的氧化硅层，使得氧化物半导体层不受氢键的影响，进而提高了氧化物晶体管的可靠性。
进一步地，在衬底基板上沉积氧化硅以形成第二绝缘层，第二绝缘层与第一绝缘层中的氧化硅层为同一层。具体实施过程中，在多晶硅层上沉积氮化硅以形成第一绝缘层，并在第一绝缘层上继续沉积氧化硅以形成第二绝缘层，通 过两次成膜的方式，最终在多晶硅层上形成氧化硅加氮化硅的结构，而氧化物半导体层附近只有氧化硅结构。
如图4所示，图4是图3中步骤S11的流程示意图，步骤S11进一步包括如下子步骤：
S110：在衬底基板上采用图形化处理形成多晶硅层。
S111：在多晶硅层上沉积氧化硅和/或氮化硅以形成第三绝缘层。
S112：在第三绝缘层上沉积金属物质并采用图形化处理形成第一栅极及第二栅极，第一栅极与多晶硅层相邻，第二栅极与氧化物半导体层相邻。
S113：以自对准方式利用第一栅极形成所述多晶硅层与源极和漏极对应的连接区域。
S114：在第一栅极上沉积氮化硅、或氧化硅和氮化硅的混合物以形成第一绝缘层。
参考图5，上述子步骤S110具体包括：在衬底基板10上沉积一层多晶硅层，并对多晶硅层21进行构图工艺以形成低温多晶硅层，其中，构图工艺可以包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等工艺。在其他实施例中，也可以沉积一层非晶硅层(a-Si)，并采用固相结晶技术(Solid Phase Crystallization，SPC)将非晶硅层(a-Si)转化为多晶硅层(p-Si)进而形成低温多晶硅层，在此不做限定。
上述子步骤S111具体包括：做出多晶硅层21并进行图形化处理后，继续沉积单层的氧化硅(SiO2)膜层或氮化硅(SiNx)膜层，或者为氧化硅(SiO2)和氮化硅(SiNx)的叠层，以形成覆盖在多晶硅层21和基板20上的第三绝缘层23，用于将多晶硅层21与其他金属层隔离，避免短路。
在其他实施例中，形成多晶硅层21及第三绝缘层23之前还可以在衬底基板10上沉积一层一定厚度的缓冲层(图中未标识)。沉积材料可以为单层或多层SiO2/SiNx，用于提高待形成的多晶硅层与基板之间的附着程度，有利于降低热传导效应。
上述子步骤S112具体包括：在第三绝缘层23上沉积一层金属，经过光刻胶涂覆、曝光、显影、蚀刻以及光刻胶剥离等工艺形成具有预定图案的第一栅极24以及第二栅极34，其中，第一栅极24与多晶硅层21相邻，第二栅极34与氧化物半导体层相邻。第一栅极24和第二栅极34的材料可以是铝(Al)、钼(Mo)、铬(Cr)、铜(Cu)、钛(Ti)等金属的任意组合。
上述子步骤S113具体包括：以自对准方式(self-alignment)利用第一栅极24做出多晶硅层21的源极、漏极连接区域21a以及21b，该连接区域用于与对应的源极和漏极自动电连接。
可选的，步骤S113可以在S111和S112之后进行，也可以在S111和S112之前进行，在此不做限定。为了避免划分源极和漏极对应的连接区域的操作影响其他操作，可以选择在S111和S112之后进行S113。
上述子步骤S114具体包括：在第一栅极24上沉积氮化硅、或氧化硅和氮化硅的混合物以形成第一绝缘层22，并进行图形化处理。第一绝缘层22仅覆盖在第一栅极24以及多晶硅层21对应的部分第三绝缘层23上。在形成氮化硅层的过程中，由于加入大量的氨气(NH3)，在生成氮化硅(SiNx)的同时也会产生大量的氢键(H)，为多晶硅氢化提供所需要的氢。
在其他应用场景中，第一栅极24和第二栅极34也可以采用其他形成方法，例如通过喷涂等方式，此处不做限定。
如图6、图7所示，图6是图3中步骤S12的流程示意图，步骤S12进一步包括如下子步骤：
S120：在第二栅极上沉积氧化硅形成第二绝缘层。
S121：在第二绝缘层上采用图形化处理形成氧化物半导体层。
S122：在氧化物半导体层上沉积氧化硅形成第四绝缘层。
参考图7，上述子步骤S120具体包括：在第二栅极34上沉积氧化硅以形成第二绝缘层32。第二绝缘层32覆盖在第二栅极34、第三绝缘层以及第一绝缘层上，用于将第二栅极34与其他金属层隔离，避免短路。在其他应用场景中，第二绝缘层32可以与第一绝缘层中的氧化硅层为同一层。
上述子步骤S121具体包括：在第二绝缘层32上采用图形化处理形成氧化物半导体层31。在本实施例中，氧化物半导体层31所采用的氧化物为铟镓锌氧化物(IGZO)或铟锡锌氧化物(ITZO)等氧化物半导体材料。
上述子步骤S122具体包括：在氧化物半导体层31上沉积氧化硅或树脂等绝缘材料以形成第四绝缘层33，第四绝缘层33覆盖在氧化物半导体层31以及第二绝缘层32上，用于将氧化物半导体层31与其他金属层隔离，避免短路。
如图8所示，图8是本发明阵列基板制作方法另一实施方式的流程示意图，阵列基板的制作方法还包括以下步骤：
S13：在第四绝缘层、第二绝缘层、第一绝缘层及第三绝缘层上开洞形成通 往多晶硅层与源极和漏极对应的连接区域的第一接触孔和第二接触孔。
S14：在第四绝缘层上开洞形成通往氧化物半导体层的第三接触孔和第四接触孔。
S15：在第一接触孔和第二接触孔、第三接触孔和第四接触孔分别沉积透明金属层以形成第一源极和第一漏极、第二源极和第二漏极。
如图9所示，在第四绝缘层33、第二绝缘层32、第一绝缘层22及第三绝缘层23上开洞形成通往多晶硅层21与源极和漏极对应的连接区域的第一接触孔和第二接触孔，并向第一接触孔和第二接触孔沉积透明金属，使得部分金属通过触孔以自对准方式与多晶硅层21的渗杂区电连接，形成第一源极25a和第一漏极25b。第一源极25a、第一漏极25b以及第一栅极24形成顶栅结构的低温多晶硅晶体管。
同理，在第四绝缘层33上开洞形成通往氧化物半导体层31的第三接触孔和第四接触孔，并向第三接触孔和第四接触孔沉积透明金属，使得部分金属通过触孔与氧化物半导体层31电连接，形成第二源极35a和第二漏极35b。第二源极35a、第二漏极35b以及第二栅极34形成底栅结构的氧化物晶体管。在具体实施中，可以通过一次构图工艺同时形成第一源极25a、第一漏极25b、第二源极35a和第二漏极35b，该源漏极金属材料可以是铝(Al)、钼(Mo)、铬(Cr)、铜(Cu)、钛(Ti)等金属。
通过上述方法，采用自动调整顶栅结构形成低温多晶硅晶体管，而采用底栅结构形成氧化物晶体管，可以减少光罩的数量。
进一步地，在第一源极25a、第一漏极25b、第二源极35a和第二漏极35b上依次制作PV层、PLN层、OLED层以及阴极等，得到完整的薄膜晶体管TFT基板。
本发明还包括一种显示装置，如图10所示，该显示装置100包括上述任意结构的阵列基板101，或者由上述任意一方法所制备的阵列基板101，具体方法如上述各实施方式，上述方法可用于制作形成图1或2所示的阵列基板，在此处不再赘述。进一步地，显示装置可以为主动矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)或TFT LCD显示装置。其中，该阵列基板包括衬底基板和位于衬底基板上方的低温多晶硅晶体管和氧化物晶体管，衬底上设置有显示区域和位于显示区域周围的非显示区域，低温多晶硅晶体管位于非显示区域内，氧化物晶体管位于显示区域内。其中， 低温多晶硅晶体管包括层叠设置的多晶硅层和第一绝缘层，第一绝缘层包括氧化硅层以及氮化硅层，其中氮化硅层靠近多晶硅层。氧化物晶体管包括层叠设置的氧化物半导体层和第二绝缘层，第二绝缘层不含氮化硅层。在形成氮化硅层的过程中，由于加入大量的氨气，在生成氮化硅的同时也会产生大量的氢键，使得多晶硅层在氢化过程中得到充分的修复，有效降低了低温多晶硅晶体管的漏电问题，同时，在氧化物半导体层附近形成不含氮化硅的氧化硅层，使得氧化物半导体层不受氢键的影响，进而提高了氧化物晶体管的可靠性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种显示装置，其中，所述显示装置包括阵列基板，
    所述阵列基板包括衬底基板和位于所述衬底基板上方的低温多晶硅晶体管和氧化物晶体管，所述衬底上设置有显示区域和位于所述显示区域周围的非显示区域，所述低温多晶硅晶体管位于所述非显示区域内，所述氧化物晶体管位于所述显示区域内；
    所述低温多晶硅晶体管包括层叠设置的多晶硅层、第一绝缘层和第三绝缘层，所述第一绝缘层包括氧化硅层以及氮化硅层，其中所述氮化硅层位于所述多晶硅层和所述氧化硅层之间，所述第三绝缘层，位于所述多晶硅层与所述第一绝缘层之间；
    所述氧化物晶体管包括层叠设置的氧化物半导体层、第二绝缘层和第四绝缘层，所述第四绝缘层，位于所述氧化物半导体层上方，所述第二绝缘层不含氮化硅层，所述第二绝缘层与所述第一绝缘层中的所述氧化硅层为同一层。
  2. 根据权利要求1所述的显示装置，其中，
    所述低温多晶硅晶体管还包括：
    第一栅极，与所述多晶硅层相邻，位于所述第三绝缘层及所述第一绝缘层之间；
    第一源极和第一漏极，位于所述第四绝缘层上方；
    其中，部分所述第一源极和第一漏极分别通过所述第四绝缘层、第二绝缘层、第一绝缘层及第三绝缘层所设置的第一接触孔及第二接触孔，与所述多晶硅层电连接，且与所述第一栅极形成顶栅结构的低温多晶硅晶体管；
    所述氧化物晶体管还包括：
    第二栅极，与所述氧化物半导体层相邻，位于所述第三绝缘层及所述第二绝缘层之间；
    第二源极和第二漏极，位于所述第四绝缘层上方；
    其中，部分所述第二源极和第二漏极分别通过所述第四绝缘层所设置的第三接触孔及第四接触孔，与所述氧化物半导体层电连接，且与所述第二栅极形成底栅结构的氧化物晶体管。
  3. 根据权利要求1所述的显示装置，其中，所述阵列基板包括以下制作方法：
    在衬底基板上分别形成低温多晶硅晶体管和氧化物晶体管，所述衬底上设置有显示区域和位于所述显示区域周围的非显示区域，所述低温多晶硅晶体管位于所述非显示区域内，所述氧化物晶体管位于所述显示区域内；
    所述在衬底基板上方形成低温多晶硅晶体管包括：在所述衬底基板上依次形成多晶硅层和第一绝缘层，所述第一绝缘层包括氧化硅层以及氮化硅层，其中所述氮化硅层靠近所述多晶硅层；
    所述在衬底基板上方形成氧化物晶体管包括：在所述衬底基板上依次形成第二绝缘层和氧化物半导体层，所述第二绝缘层不含氮化硅层。
  4. 根据权利要求3所述的显示装置，其中，所述在所述衬底基板上依次形成第二绝缘层和氧化物半导体层，包括：
    在所述衬底基板上沉积氧化硅以形成第二绝缘层，所述第二绝缘层与所述第一绝缘层中的所述氧化硅层为同一层。
  5. 根据权利要求3所述的显示装置，其中，
    所述在所述衬底基板上依次形成多晶硅层和第一绝缘层，包括：
    在所述衬底基板上采用图形化处理形成多晶硅层；
    在所述多晶硅层上沉积氧化硅和/或氮化硅以形成第三绝缘层；
    在所述第三绝缘层上沉积金属物质并采用图形化处理形成第一栅极及第二栅极，所述第一栅极与所述多晶硅层相邻，所述第二栅极与所述氧化物半导体层相邻；
    以自对准方式利用所述第一栅极形成所述多晶硅层与源极和漏极对应的连接区域；
    在所述第一栅极上沉积氮化硅、或氧化硅和氮化硅的混合物以形成第一绝缘层；
    所述在所述衬底基板上依次形成第二绝缘层和氧化物半导体层，包括：
    在所述第二栅极上沉积氧化硅形成第二绝缘层；
    在所述第二绝缘层上采用图形化处理形成氧化物半导体层；
    在所述氧化物半导体层上沉积氧化硅形成第四绝缘层。
  6. 根据权利要求5所述的显示装置，其中，
    在所述第四绝缘层、第二绝缘层、第一绝缘层及第三绝缘层上开洞形成通往所述多晶硅层与源极和漏极对应的连接区域的第一接触孔和第二接触孔；
    在所述第四绝缘层上开洞形成通往所述氧化物半导体层的第三接触孔和第 四接触孔；
    在所述第一接触孔和第二接触孔、所述第三接触孔和第四接触孔分别沉积透明金属层以形成第一源极和第一漏极、第二源极和第二漏极。
  7. 根据权利要求1所述的显示装置，其中，所述显示装置为主动矩阵有机发光二极体AMOLED或TFT LCD显示装置。
  8. 一种阵列基板，其中，所述阵列基板包括衬底基板和位于所述衬底基板上方的低温多晶硅晶体管和氧化物晶体管，所述衬底上设置有显示区域和位于所述显示区域周围的非显示区域，所述低温多晶硅晶体管位于所述非显示区域内，所述氧化物晶体管位于所述显示区域内；
    所述低温多晶硅晶体管包括层叠设置的多晶硅层和第一绝缘层，所述第一绝缘层包括氧化硅层以及氮化硅层，其中所述氮化硅层位于所述多晶硅层和所述氧化硅层之间；
    所述氧化物晶体管包括层叠设置的氧化物半导体层和第二绝缘层，所述第二绝缘层不含氮化硅层。
  9. 根据权利要求8所述的阵列基板，其中，所述第二绝缘层与所述第一绝缘层中的所述氧化硅层为同一层。
  10. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    第三绝缘层，位于所述多晶硅层与所述第一绝缘层之间；
    第四绝缘层，位于所述氧化物半导体层上方。
  11. 根据权利要求10所述的阵列基板，其中，
    所述低温多晶硅晶体管还包括：
    第一栅极，与所述多晶硅层相邻，位于所述第三绝缘层及所述第一绝缘层之间；
    第一源极和第一漏极，位于所述第四绝缘层上方；
    其中，部分所述第一源极和第一漏极分别通过所述第四绝缘层、第二绝缘层、第一绝缘层及第三绝缘层所设置的第一接触孔及第二接触孔，与所述多晶硅层电连接，且与所述第一栅极形成顶栅结构的低温多晶硅晶体管；
    所述氧化物晶体管还包括：
    第二栅极，与所述氧化物半导体层相邻，位于所述第三绝缘层及所述第二绝缘层之间；
    第二源极和第二漏极，位于所述第四绝缘层上方；
    其中，部分所述第二源极和第二漏极分别通过所述第四绝缘层所设置的第三接触孔及第四接触孔，与所述氧化物半导体层电连接，且与所述第二栅极形成底栅结构的氧化物晶体管。
  12. 一种阵列基板的制备方法，其中，包括：
    在衬底基板上分别形成低温多晶硅晶体管和氧化物晶体管，所述衬底上设置有显示区域和位于所述显示区域周围的非显示区域，所述低温多晶硅晶体管位于所述非显示区域内，所述氧化物晶体管位于所述显示区域内；
    所述在衬底基板上方形成低温多晶硅晶体管包括：在所述衬底基板上依次形成多晶硅层和第一绝缘层，所述第一绝缘层包括氧化硅层以及氮化硅层，其中所述氮化硅层靠近所述多晶硅层；
    所述在衬底基板上方形成氧化物晶体管包括：在所述衬底基板上依次形成第二绝缘层和氧化物半导体层，所述第二绝缘层不含氮化硅层。
  13. 根据权利要求12所述的方法，其中，所述在所述衬底基板上依次形成第二绝缘层和氧化物半导体层，包括：
    在所述衬底基板上沉积氧化硅以形成第二绝缘层，所述第二绝缘层与所述第一绝缘层中的所述氧化硅层为同一层。
  14. 根据权利要求12所述的方法，其中，
    所述在所述衬底基板上依次形成多晶硅层和第一绝缘层，包括：
    在所述衬底基板上采用图形化处理形成多晶硅层；
    在所述多晶硅层上沉积氧化硅和/或氮化硅以形成第三绝缘层；
    在所述第三绝缘层上沉积金属物质并采用图形化处理形成第一栅极及第二栅极，所述第一栅极与所述多晶硅层相邻，所述第二栅极与所述氧化物半导体层相邻；
    以自对准方式利用所述第一栅极形成所述多晶硅层与源极和漏极对应的连接区域；
    在所述第一栅极上沉积氮化硅、或氧化硅和氮化硅的混合物以形成第一绝缘层；
    所述在所述衬底基板上依次形成第二绝缘层和氧化物半导体层，包括：
    在所述第二栅极上沉积氧化硅形成第二绝缘层；
    在所述第二绝缘层上采用图形化处理形成氧化物半导体层；
    在所述氧化物半导体层上沉积氧化硅形成第四绝缘层。
  15. 根据权利要求14所述的方法，其中，所述方法还包括：
    在所述第四绝缘层、第二绝缘层、第一绝缘层及第三绝缘层上开洞形成通往所述多晶硅层与源极和漏极对应的连接区域的第一接触孔和第二接触孔；
    在所述第四绝缘层上开洞形成通往所述氧化物半导体层的第三接触孔和第四接触孔；
    在所述第一接触孔和第二接触孔、所述第三接触孔和第四接触孔分别沉积透明金属层以形成第一源极和第一漏极、第二源极和第二漏极。
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