CN107275350B - 阵列基板及其制作方法和显示装置 - Google Patents
阵列基板及其制作方法和显示装置 Download PDFInfo
- Publication number
- CN107275350B CN107275350B CN201710591961.8A CN201710591961A CN107275350B CN 107275350 B CN107275350 B CN 107275350B CN 201710591961 A CN201710591961 A CN 201710591961A CN 107275350 B CN107275350 B CN 107275350B
- Authority
- CN
- China
- Prior art keywords
- layer
- transistor
- active layer
- metal
- interlayer dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 223
- 230000004888 barrier function Effects 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 230000000903 blocking effect Effects 0.000 claims abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 7
- 150000004706 metal oxides Chemical group 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 63
- 239000002184 metal Substances 0.000 claims description 63
- 238000005530 etching Methods 0.000 claims description 16
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 6
- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 claims description 5
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000010409 thin film Substances 0.000 abstract description 32
- 239000001257 hydrogen Substances 0.000 abstract description 15
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 13
- 238000010438 heat treatment Methods 0.000 abstract description 10
- 230000002411 adverse Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229920001621 AMOLED Polymers 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- -1 hydrogen ions Chemical class 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007715 excimer laser crystallization Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
本公开提供一种阵列基板及其制作方法和显示装置,该阵列基板包括:衬底基板;衬底基板的第一区域和第二区域分别设置有第一晶体管和第二晶体管,第一晶体管具有第一有源层,且第一有源层低温多晶硅,第二晶体管具有第二有源层,且第二有源层为金属氧化物半导体;其中第一有源层、层间介质层、第二有源层依次设置在衬底基板上,且在层间介质层和第二有源层之间设置有阻挡层。通过设置阻挡层,对低温多晶硅薄膜晶体管的层间介质层与氧化物薄膜晶体管的有源层起到绝缘和氢阻挡的作用,可以阻止在后续热处理工艺中低温多晶硅薄膜晶体管与氧化物薄膜晶体管之间的氢渗透,防止低温多晶硅薄膜晶体管和氧化物薄膜晶体管的晶体管特性受到不良影响。
Description
技术领域
本公开涉及显示技术领域,具体而言,涉及一种阵列基板及其制作方法和显示装置。
背景技术
目前,AMOLED(Active Matrix Organic Light Emitting Diode,有源矩阵有机发光二极体)技术是电子产品的发展趋势,因其具有更宽的视角、更高的刷新率和更薄的尺寸,在智能手机上得到广泛应用。
LTPO((Low Temperature Polycrystalline Oxide,低温多晶氧化物)技术结合了LTPS-TFT(Low Temperature Poly-silicon Thin Film Transistor,低温多晶硅薄膜晶体管)和Oxide-TFT(氧化物薄膜晶体管)这两种TFT各自的优势,在AMOLED产品的高PPI(Pixels Per Inch,像素密度)、低功耗、高画质等方面具备一定的技术优势。另外,由于Oxide-TFT具有较低的漏电流的优点,在LTPS+Oxide技术的传感器技术应用上也有一定的优点。
基于上述,LTPO工艺的开发具有较高的价值和意义,但是现有LTPO工艺中,需要在LTPS层之上形成Oxide层,而Oxide工艺中涉及多步热处理以及退火等工艺,这样会导致LTPS-TFT的ILD(Inter Layer Dielectric,层间介质)层中的氢会在后续热处理中进入Oxide中,影响Oxide-TFT的晶体管特性,Oxide层中的氢和氧可能会在后续热处理中进入LTPS中影响LTPS-TFT的晶体管特性。
因此,现有技术中的技术方案还存在有待改进之处。
需要说明的是,在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解,因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种阵列基板及其制作方法和显示装置,进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开的其他特性和优点将通过下面的详细描述变得清晰,或者部分地通过本公开的实践而习得。
根据本公开的一个方面,提供一种阵列基板,包括:
衬底基板;
所述衬底基板的第一区域和第二区域分别设置有第一晶体管和第二晶体管,所述第一晶体管具有第一有源层,且所述第一有源层为低温多晶硅,所述第二晶体管具有第二有源层,且所述第二有源层为金属氧化物半导体;
其中所述第一有源层、层间介质层、所述第二有源层依次设置在所述衬底基板上,且在所述层间介质层和所述第二有源层之间设置有阻挡层。
在本公开的一种示例性实施例中,所述阻挡层为部分刻蚀留下的保留金属经过氧化处理形成。
在本公开的一种示例性实施例中,所述保留金属的材料为钛,所述阻挡层的材料为氧化钛;或
所述保留金属的材料为铝,所述阻挡层的材料为氧化铝。
在本公开的一种示例性实施例中,所述第一晶体管为顶栅型结构,所述第二晶体管为底栅型结构。
在本公开的一种示例性实施例中,所述第一晶体管包括依次在所述衬底基板上形成的所述第一有源层、第一绝缘层、第一栅极以及所述层间介质层,所述第一晶体管的源极和漏极分别通过两个通孔与所述第一有源层的两端电连接;所述第二晶体管包括依次在所述阻挡层上形成的第二栅极、第二绝缘层、所述第二有源层和保护层,且所述第二晶体管的源极和漏极分别通过两个通孔与所述第二有源层的两端电连接。
根据本公开的第二方面,提供一种阵列基板的制作方法,包括:
在衬底基板的第一区域上通过多次构图工艺形成第一晶体管和阻挡层,所述第一晶体管具有第一有源层和层间介质层,且所述第一有源层为低温多晶硅;
在位于所述第二区域的所述阻挡层的上方通过多次构图工艺形成第二晶体管所述第二晶体管具有第二有源层,且所述第二有源层为金属氧化物半导体;
其中所述阻挡层形成于所述层间介质层和所述第二有源层之间,且所述阻挡层还延伸到所述衬底基板的第二区域。
在本公开的一种示例性实施例中,所述形成第一晶体管和阻挡层包括:
在所述衬底基板的所述第一区域以及所述第二区域上形成第一绝缘层和所述层间介质层,并在所述第一区域通过构图工艺形成所述第一有源层和第一栅极,其中所述层间介质层覆盖在所述第一栅极以及所述第一绝缘层上方;
在形成有所述层间介质层的衬底基板上形成源漏极金属层;
通过构图工艺在所述第一区域形成所述第一晶体管的源极和漏极,在所述第二区域形成第二栅极,在所述第一晶体管的源极和漏极以及所述第二栅极以外的区域对所述源漏极金属层进行部分刻蚀,得到保留金属;
对所述保留金属进行氧化处理,得到所述阻挡层。
在本公开的一种示例性实施例中,所述源漏极金属层的材料为钛-铝-钛合金,所述保留金属的材料为钛,所述阻挡层的材料为氧化钛;或
所述源漏极金属层的材料为铝-钛合金,所述保留金属为铝,所述阻挡层的材料为氧化铝。
根据本公开的第三方面,还提供一种显示装置,包括以上所述的阵列基板。
本公开的某些实施例的阵列基板,通过设置阻挡层,对低温多晶硅薄膜晶体管的层间介质层与氧化物薄膜晶体管的有源层起到绝缘和氢阻挡的作用,可以阻止在后续热处理工艺中低温多晶硅薄膜晶体管与氧化物薄膜晶体管之间的氢渗透,防止低温多晶硅薄膜晶体管和氧化物薄膜晶体管的晶体管特性受到不良影响。
应当理解的是,以上的一般描述和后文的细节描述仅是示例性和解释性的,并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分,示出了符合本公开的实施例,并与说明书一起用于解释本公开的原理。显而易见地,下面描述中的附图仅仅是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1示出本公开一示例性实施例中提供的一种阵列基板的示意图
图2示出本公开另一示例性实施例中提供的一种阵列基板的制作方法的流程图。
图3示出本公开另一示例性实施例中步骤S21的流程图。
图4示出本公开另一示例性实施例中在衬底基板上制作第一晶体管的工艺到源漏极金属层得到的结构剖面图。
图5示出本公开另一示例性实施例中在图4所示结构基础上形成阻挡层的结构剖面图。
图6示出本公开另一示例性实施例中在图5所示结构基础上形成第二绝缘层、有源层和保护层的结构剖面图。
图7示出本公开另一示例性实施例中在图6所示结构基础上形成过孔的结构剖面图。
图8示出本公开另一示例性实施例中在图7所示结构基础上形成源极和漏极的结构剖面图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而,示例实施方式能够以多种形式实施,且不应被理解为限于在此阐述的范例;相反,提供这些实施方式使得本公开将更加全面和完整,并将示例实施方式的构思全面地传达给本领域的技术人员。附图仅为本公开的示意性图解,并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分,因而将省略对它们的重复描述。
此外,所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中,提供许多具体细节从而给出对本公开的实施方式的充分理解。然而,本领域技术人员将意识到,可以实践本公开的技术方案而省略所述特定细节中的一个或更多,或者可以采用其它的方法、组元、装置、步骤等。在其它情况下,不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免喧宾夺主而使得本公开的各方面变得模糊。
附图中所示的一些方框图是功能实体,不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体,或在一个或多个硬件模块或集成电路中实现这些功能实体,或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
图1示出本公开示例性实施例中提供的一种阵列基板的示意图。
如图1所示,该阵列基板包括:衬底基板101以及设置在衬底基板101的第一区域A1的第一晶体管和设置在在衬底基板101的第二区域A2的第二晶体管,其中第一晶体管具有第一有源层,且第一有源层为低温多晶硅,即第一晶体管为低温多晶硅薄膜晶体管(后文简称为LTPS-TFT),第二晶体管具有第二有源层,且第二有源层为金属氧化物半导体,即第二晶体管为氧化物薄膜晶体管(后文简称Oxide-TFT)。
如图1所示,第一晶体管结构中包括:依次在衬底基板101上形成的第一有源层111、第一绝缘层112、第一栅极113以及层间介质层114,第一晶体管的源116和漏极117分别通过两个通孔与第一有源层111的两端电连接,其结构和加工工艺与现有LTPS-TFT无异,但是本实施例中的层间介质层114上方还设置有阻挡层115。
其中有源层111采用多晶硅(P-Si),其形成过程可以采用ELA(Excimer LaserAnnealing,准分子激光晶化)技术将高功率的激光束作用于待晶化非晶硅(a-Si)薄膜的表面,由于硅极强的紫外光吸收能力,在极短的时间内(50ns~150ns)可使非晶硅薄膜表面在瞬间达到1000℃以上的高温而变成熔融状态,激光脉冲停止后,融化的非晶硅冷却结晶变为多晶硅。其中第一绝缘层112为栅绝缘层,覆盖在第一有源层111上,可以为单层硅氧化物(SiOx)膜或者为包括硅氮化物(SiNx)和SiOx的双层膜。层间介质层114的材料为SiNx/SiO2,而且成膜后需要进行1~3分钟600℃的活化以及30分钟380~420℃的氢化处理,最终得到层间介质层114。
在本实施例中,阻挡层115为对源漏极金属层进行部分刻蚀留下的保留金属经过氧化处理形成,通常源漏极金属为合金材料,例如钛-铝-钛合金或铝-钛合金,这样在对源漏极金属进行刻蚀形成源极116和漏极117的过程中,对源极116和漏极117以外的区域进行部分刻蚀,得到保留金属(也就是第一层金属)为钛或铝,进一步对其进行氧化掺杂处理,得到的氧化钛或氧化铝就是阻挡层。
需要说明的是,在本公开其他实施例中,阻挡层还可以是其他通过氧等离子体氧化处理后能转变形成非导电性介质薄膜的金属,可以起到阻挡层间介质层中氢离进入第二晶体管中即可,此处不做具体限定。
如图1所示,在第二区域A2中利用源漏极金属可刻蚀形成第二晶体管的栅极,即在阻挡层115上形成的第二栅极121,而且在第二栅极121的周围也设置有阻挡层115,第二晶体管中还包括:第二绝缘层122、第二有源层123、保护层124以及第二晶体管的源极125和漏极126,第二晶体管的源极125和漏极126也分别通过两个通孔与第二有源层122的两端电连接,最终在第二晶体管的源极125和漏极126的上方还具有钝化层127。
其中第二绝缘层122为栅绝缘层,覆盖在第二栅极121上,材质可以为单层硅氧化物(SiOx)膜或者为包括硅氮化物(SiNx)和SiOx的双层膜。第二有源层123为氧化物薄膜,通过氧化物半导体材料成膜后经过构图工艺形成,其中氧化物半导体材料具体为含有金属铟、镓和锌等金属中至少一种的氧化物半导体。
还需要说明的是,本实施例中并未对第一区域和第二区域的界限的划分做详细介绍,并且这也不是本公开的设计重点,标注第一区域和第二区域仅仅是为了说明LTPS-TFT和Oxide-TFT是设置在不同区域的,LTPS-TFT由于开关迅速,通常用做开关晶体管,而Oxide-TFT由于半导体特性,通常用做驱动晶体管,也是由于其各自不同的特定及功能,需要将二者分别设置在对应的区域,比单纯的LTPS-TFT和Oxide-TFT的效果都要好,LTPS电子移动率过高导致的耗电量巨大,结合氧化物的低耗电量与LTPS的优点使得二者的优点极大化。
综上所述,本实施例提供的阵列基板通过设置阻挡层,对低温多晶硅薄膜晶体管的层间介质层与氧化物薄膜晶体管的有源层起到绝缘和氢阻挡的作用,可以阻止在后续热处理工艺中低温多晶硅薄膜晶体管与氧化物薄膜晶体管之间的氢渗透,防止低温多晶硅薄膜晶体管和氧化物薄膜晶体管的晶体管特性受到不良影响。另外,阻挡层还可以阻挡第二有源层中的氢和氧在后续热处理中对低温多晶硅薄膜晶体管的晶体管特性产生影响。
图2示出本公开另一实施例中提供的一种阵列基板的制作方法的流程图。
如图2所示,在步骤S21中,在衬底基板的第一区域上通过多次构图工艺形成第一晶体管和阻挡层。需要说明的是,本实施例中阻挡层是在形成第一晶体管的过程中进一步氧化处理形成的,因此阻挡层还延伸到衬底基板的第二区域。
图3示出本实施例中步骤S21的流程图。
如图3所示,在步骤S211中,在衬底基板的第一区域以及第二区域上形成第一绝缘层和层间介质层,并在第一区域通过构图工艺形成第一有源层和第一栅极,其中层间介质层覆盖在第一栅极以及第一绝缘层上方。
如图3所示,在步骤S212中,在形成有层间介质层的衬底基板上形成源漏极金属层。
如图3所示,在步骤S213中,通过构图工艺在第一区域形成第一晶体管的源极和漏极,在第二区域形成第二栅极,在第一晶体管的源极和漏极以及第二栅极以外的区域对源漏极金属层进行部分刻蚀,得到保留金属。
如图3所示,在步骤S214中,对保留金属进行氧化处理,得到阻挡层。
在本实施例中,阻挡层为对源漏极金属层进行部分刻蚀留下的保留金属经过氧化处理形成,通常源漏极金属为合金材料,例如钛-铝-钛合金或铝-钛合金,这样在对源漏极金属进行刻蚀形成第一晶体管的源极和漏极的过程中,对源极和漏极以外的区域进行部分刻蚀,得到保留金属(也就是第一层金属)为钛或铝,进一步对其进行氧化掺杂处理,得到的氧化钛或氧化铝就是阻挡层。
如图2所示,在步骤S22中,在位于第二区域的阻挡层的上方通过多次构图工艺形成第二晶体管。
在本实施例中,第一有源层为低温多晶硅,第二有源层为金属氧化物半导体,第二晶体管形成在第一晶体管之上,因此阻挡层形成于层间介质层和第二有源层之间。
以下结合图4~图8对本实施例中提供的阵列基板的制作方法进行介绍:
图4示出在衬底基板上制作第一晶体管的工艺到源漏极金属层得到的结构剖面图,由于第一晶体管在形成源极和漏极之前,与传统的LTPS-TFT制作工艺并无太大差别,此处不做详细描述。
如图4所示,在衬底基板101上通过多次构图工艺依次形成第一有源层111、第一绝缘层112、第一栅极113以及覆盖在第一栅极113上的层间介质层114,之后在形成第一有源层111、第一绝缘层112、第一栅极113以及层间介质层114的衬底基板101上沉积源漏极金属层102,由于源漏极金属层102为多层合金金属(以钛-铝-钛合金为例),需经过多次金属溅射工艺形成。
之后,在源漏极金属层102上涂覆光刻胶103,利用掩膜板进行光照形成光刻胶图案(如图4所示),再按照图4所示的光刻胶图案对下面的源漏极金属层103进行刻蚀,刻蚀后保留光刻胶图案覆盖下的第一晶体管的源极115和漏极116以及第二栅极121。还需要注意的是,本实施例在刻蚀的过程中采用EPD(End Point Detector,终点检测器)技术进行部分刻蚀,即在光刻胶图案未覆盖区域保留一定厚度的金属,即保留金属。其中EPD利用从刻蚀开始到结束为止特定的波长的光强度的变化,检测出刻蚀的最合适的终点,因此保证刻蚀过程中最底层的金属能够被保留下来。
以本实施例为例,保留的钛金属,之后再利用离子注入(Implanter)技术对保留金属进行氧气掺杂,将裸露在光刻胶外侧残留的薄层金属--钛进行氧化处理,得到氧化钛,也就是形成阻挡层115。的氧化钛具有近似绝缘体的性质,因此能够起到阻挡层间介质层中氢离进入第二晶体管中有源层的作用。
在本公开其他实施例中保留金属还可以是铝,相应的也对其进行氧气掺杂得到氧化铝,形成阻挡层115。
另外,利用离子注入技术进行金属氧化处理过程中,将活性的氧离子注入到金属中形成透明的绝缘层氧化物。具体的,根据离子种类,能量范围可控制范围为6~10Kev,电子束电流可控制范围为(6~9)±10%uA/cm,扫描次数为3~5次,以保证保留金属能够被充分氧化。
需要说明的是,上述参数会因设备不同而有细微变化,但是这并不是本实施例的方法所要保护的重点。
图5示出在图4所示结构基础上形成阻挡层的结构剖面图。
金属氧化处理完成后进行光刻胶剥离,继续形成第二绝缘层122、第二有源层123以及覆盖在第二有源层123上方的保护层124,得到LTPO背板,这个过程与传统工艺无异,此处不再详细描述。
图6示出在图5所示结构基础上形成第二绝缘层、第二有源层和保护层的结构剖面图。
之后,利用光刻工艺对第二绝缘层122和保护层124进行刻蚀,在对应第一晶体管的漏极117以及第二有源层123的两端形成三个过孔,即H1,H2和H3。
图7示出在图6所示结构基础上形成过孔的结构剖面图。
之后,在图7所示结构的基础上沉积第二金属层,并通过构图工艺形成第二晶体管的源极125和漏极126。
图8示出在图7所示结构基础上形成源极和漏极的结构剖面图。
需要说明的是,本实施例源极图示中源极和漏极的位置并不局限于本实施例图示所示,即源极和漏极的位置还可以互换,需要根据具体的电路设计来确定。
最后,在图8所示结构的基础上形成钝化层127,得到图1所示的阵列基板的结构,即在衬底基板上形成第一晶体管和第二晶体管的结构,而且第一晶体管的层间介质层与第二有源层之间有阻挡层进行绝缘和阻挡。
需要说明的是,本实施例中的一次构图工艺通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。
综上所述,本实施例提供的阵列基板的制作方法在衬底基板上通过对源漏极金属层进行部分刻蚀后进行氧化处理形成阻挡层,对低温多晶硅薄膜晶体管的层间介质层与氧化物薄膜晶体管的有源层起到绝缘和氢阻挡的作用,可以阻止在后续热处理工艺中低温多晶硅薄膜晶体管与氧化物薄膜晶体管之间的氢渗透,防止低温多晶硅薄膜晶体管和氧化物薄膜晶体管的晶体管特性受到不良影响。另外,阻挡层还可以阻挡第二有源层中的氢和氧在后续热处理中对低温多晶硅薄膜晶体管的晶体管特性产生影响。
基于上述,本公开实施例还提供了一种显示装置,其包括上述任意一种阵列基板。所述显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
相应的,该显示装置也具有与阵列基板相同的技术效果,此处不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后,将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化,这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的,本公开的真正范围和精神由所附的权利要求指出。
Claims (8)
1.一种阵列基板,其特征在于,包括:
衬底基板;
所述衬底基板的第一区域和第二区域分别设置有第一晶体管和第二晶体管,所述第一晶体管具有第一有源层,且所述第一有源层为低温多晶硅,所述第二晶体管具有第二有源层,且所述第二有源层为金属氧化物半导体;
其中所述第一有源层、层间介质层、所述第二有源层依次设置在所述衬底基板上,且在所述层间介质层和所述第二有源层之间设置有阻挡层,所述阻挡层为对源漏极金属层进行部分刻蚀留下的保留金属经过氧化处理形成。
3.根据权利要求1所述的阵列基板,其特征在于,所述保留金属的材料为钛,所述阻挡层的材料为氧化钛;或
所述保留金属的材料为铝,所述阻挡层的材料为氧化铝。
4.根据权利要求1所述的阵列基板,其特征在于,所述第一晶体管为顶栅型结构,所述第二晶体管为底栅型结构。
5.根据权利要求4所述的阵列基板,其特征在于,所述第一晶体管包括依次在所述衬底基板上形成的所述第一有源层、第一绝缘层、第一栅极以及所述层间介质层,所述第一晶体管的源极和漏极分别通过两个通孔与所述第一有源层的两端电连接;所述第二晶体管包括依次在所述阻挡层上形成的第二栅极、第二绝缘层、所述第二有源层和保护层,且所述第二晶体管的源极和漏极分别通过两个通孔与所述第二有源层的两端电连接。
6.一种阵列基板的制作方法,其特征在于,包括:
在衬底基板的第一区域上通过多次构图工艺形成第一晶体管和阻挡层,且所述阻挡层还延伸到所述衬底基板的第二区域,所述第一晶体管具有第一有源层和层间介质层,且所述第一有源层为低温多晶硅;
在位于所述第二区域的所述阻挡层的上方通过多次构图工艺形成第二晶体管,所述第二晶体管具有第二有源层,且所述第二有源层为金属氧化物半导体;
其中所述阻挡层形成于所述层间介质层和所述第二有源层之间;
所述形成第一晶体管和阻挡层包括:
在所述衬底基板的所述第一区域以及所述第二区域上形成第一绝缘层和所述层间介质层,并在所述第一区域通过构图工艺形成所述第一有源层和第一栅极,其中所述层间介质层覆盖在所述第一栅极以及所述第一绝缘层上方;
在形成有所述层间介质层的衬底基板上形成源漏极金属层;
通过构图工艺在所述第一区域形成所述第一晶体管的源极和漏极,在所述第二区域形成第二栅极,在所述第一晶体管的源极和漏极以及所述第二栅极以外的区域对所述源漏极金属层进行部分刻蚀,得到保留金属;
对所述保留金属进行氧化处理,得到所述阻挡层。
7.根据权利要求6所述的阵列基板的制作方法,其特征在于,所述源漏极金属层的材料为钛-铝-钛合金,所述保留金属为钛,所述阻挡层的材料为氧化钛;或
所述源漏极金属层的材料为铝-钛合金,所述保留金属为铝,所述阻挡层的材料为氧化铝。
8.一种显示装置,其特征在于,包括权利要求1-5中任一项所述的阵列基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710591961.8A CN107275350B (zh) | 2017-07-19 | 2017-07-19 | 阵列基板及其制作方法和显示装置 |
US15/968,835 US10580804B2 (en) | 2017-07-19 | 2018-05-02 | Array substrate, fabricating method therefor and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710591961.8A CN107275350B (zh) | 2017-07-19 | 2017-07-19 | 阵列基板及其制作方法和显示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107275350A CN107275350A (zh) | 2017-10-20 |
CN107275350B true CN107275350B (zh) | 2020-03-10 |
Family
ID=60077928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710591961.8A Active CN107275350B (zh) | 2017-07-19 | 2017-07-19 | 阵列基板及其制作方法和显示装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10580804B2 (zh) |
CN (1) | CN107275350B (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107393934B (zh) | 2017-08-14 | 2020-02-21 | 京东方科技集团股份有限公司 | 一种阵列基板、其制作方法及显示装置 |
CN107507841B (zh) * | 2017-09-22 | 2021-01-22 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法、显示装置 |
US10559696B2 (en) * | 2017-10-11 | 2020-02-11 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Hybrid CMOS device and manufacturing method thereof |
US11239221B2 (en) | 2018-11-02 | 2022-02-01 | Boe Technology Group Co., Ltd. | Array substrate and fabrication method thereof, and electronic apparatus |
CN109638034B (zh) * | 2018-11-06 | 2021-04-27 | 深圳市华星光电半导体显示技术有限公司 | 显示面板的制造方法 |
CN109509775A (zh) * | 2018-11-19 | 2019-03-22 | 云谷(固安)科技有限公司 | 一种有机电致发光显示面板及制作方法、显示装置 |
CN109659357B (zh) * | 2018-12-18 | 2020-11-24 | 武汉华星光电半导体显示技术有限公司 | 薄膜晶体管和显示面板 |
CN112640106A (zh) * | 2018-12-25 | 2021-04-09 | 深圳市柔宇科技股份有限公司 | 阵列基板及其制造方法及显示装置 |
CN109742089B (zh) * | 2019-01-02 | 2020-12-25 | 合肥京东方光电科技有限公司 | 显示基板、显示装置和显示基板的制造方法 |
CN111506886A (zh) * | 2019-01-31 | 2020-08-07 | 陕西坤同半导体科技有限公司 | 全屏触控指纹解锁的感应组件、移动终端以及方法 |
CN109887936B (zh) | 2019-03-25 | 2021-01-29 | 合肥京东方光电科技有限公司 | 阵列基板及其制作方法 |
CN110085606B (zh) * | 2019-05-23 | 2021-08-27 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法 |
CN110620119A (zh) * | 2019-08-26 | 2019-12-27 | 武汉华星光电技术有限公司 | 阵列基板及其制备方法 |
CN110634888A (zh) * | 2019-09-25 | 2019-12-31 | 武汉华星光电技术有限公司 | 阵列基板及其制备方法、显示装置 |
CN110707098B (zh) * | 2019-09-27 | 2022-08-23 | 上海天马微电子有限公司 | 阵列基板、显示面板、显示装置及阵列基板的制备方法 |
CN110649043B (zh) * | 2019-09-30 | 2021-11-19 | 厦门天马微电子有限公司 | 阵列基板、显示面板、显示装置及阵列基板的制备方法 |
CN111179742A (zh) * | 2020-02-12 | 2020-05-19 | 武汉华星光电技术有限公司 | 一种显示面板、栅极驱动电路及电子装置 |
CN111863837B (zh) * | 2020-07-13 | 2023-04-18 | 武汉华星光电半导体显示技术有限公司 | 阵列基板和显示面板 |
CN114788000A (zh) * | 2020-09-22 | 2022-07-22 | 京东方科技集团股份有限公司 | 显示基板、显示面板及显示装置 |
CN112259610B (zh) * | 2020-10-09 | 2024-03-22 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及显示面板 |
CN113345924B (zh) * | 2021-06-03 | 2024-06-11 | 京东方科技集团股份有限公司 | 显示面板及其制作方法和显示装置 |
EP4170718A3 (en) | 2021-09-03 | 2023-08-23 | LG Display Co., Ltd. | Display panel and electronic device including same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103715196A (zh) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN106876412A (zh) * | 2017-03-15 | 2017-06-20 | 厦门天马微电子有限公司 | 一种阵列基板以及制作方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9397124B2 (en) * | 2014-12-03 | 2016-07-19 | Apple Inc. | Organic light-emitting diode display with double gate transistors |
CN107026178B (zh) * | 2017-04-28 | 2019-03-15 | 深圳市华星光电技术有限公司 | 一种阵列基板、显示装置及其制作方法 |
-
2017
- 2017-07-19 CN CN201710591961.8A patent/CN107275350B/zh active Active
-
2018
- 2018-05-02 US US15/968,835 patent/US10580804B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103715196A (zh) * | 2013-12-27 | 2014-04-09 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN106876412A (zh) * | 2017-03-15 | 2017-06-20 | 厦门天马微电子有限公司 | 一种阵列基板以及制作方法 |
Also Published As
Publication number | Publication date |
---|---|
US20190027511A1 (en) | 2019-01-24 |
CN107275350A (zh) | 2017-10-20 |
US10580804B2 (en) | 2020-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107275350B (zh) | 阵列基板及其制作方法和显示装置 | |
US10312271B2 (en) | Array substrate, manufacturing method thereof and display device | |
EP3185305B1 (en) | Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof and display device | |
US9202896B2 (en) | TFT, method of manufacturing the TFT, and method of manufacturing organic light emitting display device including the TFT | |
US10101620B2 (en) | Manufacture method of low temperature poly-silicon array substrate | |
US8440483B2 (en) | Method of fabricating array substrate | |
US9620646B2 (en) | Array substrate, manufacturing method thereof and display device | |
US10224416B2 (en) | Method for manufacturing low-temperature poly-silicon thin film transistor, low-temperature poly-silicon thin film transistor and display device | |
KR20140113902A (ko) | 박막 트랜지스터와 그의 제조 방법, 및 표시 장치 | |
US9711356B2 (en) | Method for manufacturing thin-film transistor by implanting ions into channel region for lowering leakage current | |
WO2017028461A1 (zh) | 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置 | |
EP3252802B1 (en) | Thin film transistor manufacturing method and array substrate manufacturing method | |
KR100811997B1 (ko) | 박막트랜지스터 및 그 제조방법과 이를 포함한평판표시장치 | |
KR20050001937A (ko) | 액정표시패널 및 그 제조 방법 | |
KR20140148349A (ko) | 박막 트랜지스터와 능동형 유기 발광 다이오드 어셈블리 및 제조 방법 | |
US11456386B2 (en) | Thin film transistor, manufacturing method thereof, array substrate and electronic device | |
US7071040B2 (en) | Method of fabricating thin film transistor | |
US10957713B2 (en) | LTPS TFT substrate and manufacturing method thereof | |
KR20190076094A (ko) | 디스플레이 장치와, 이의 제조 방법 | |
JP4234363B2 (ja) | 薄膜トランジスタ装置及びその製造方法、並びにそれを備えた薄膜トランジスタ基板及び表示装置 | |
CN111129033B (zh) | 阵列基板及其制备方法 | |
US6703266B1 (en) | Method for fabricating thin film transistor array and driving circuit | |
US11699761B2 (en) | Thin film transistor and fabrication method thereof, array substrate and fabrication method thereof, and display panel | |
KR20120067108A (ko) | 어레이 기판 및 이의 제조방법 | |
CN114792694A (zh) | 薄膜晶体管阵列基板及其制备方法、显示面板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |