WO2018214771A1 - 一种oled阵列基板及其制备方法和oled显示装置 - Google Patents

一种oled阵列基板及其制备方法和oled显示装置 Download PDF

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Publication number
WO2018214771A1
WO2018214771A1 PCT/CN2018/086661 CN2018086661W WO2018214771A1 WO 2018214771 A1 WO2018214771 A1 WO 2018214771A1 CN 2018086661 W CN2018086661 W CN 2018086661W WO 2018214771 A1 WO2018214771 A1 WO 2018214771A1
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insulating layer
tube
array substrate
gate
active layer
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PCT/CN2018/086661
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English (en)
French (fr)
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王利忠
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京东方科技集团股份有限公司
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Priority to US16/323,678 priority Critical patent/US20190172850A1/en
Publication of WO2018214771A1 publication Critical patent/WO2018214771A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present invention relates to the field of mobile device technologies, and in particular, to an OLED array substrate, a method for fabricating the same, and an OLED display device.
  • OLED Organic Light-Emitting Diode
  • LTPS TFT Low Temperature Poly-silicon Thin Film Transistor
  • a switching transistor (Controling TFT) for controlling pixel display and a driving transistor (Driving TFT) for driving pixel display are usually disposed on the OLED array substrate.
  • the switching transistor In order to speed up the switching speed of the switching transistor, the switching transistor generally needs to have a low subthreshold swing (SS); in order to better display the different gray levels of the OLED display, the driving transistor requires a large subthreshold swing. (SS), otherwise, too fast voltage changes will cause incomplete grayscale display, affecting the display effect of OLED displays.
  • the present invention is directed to the above technical problems existing in the prior art, and provides an OLED array substrate, a method for fabricating the same, and an OLED display device.
  • the OLED array substrate can increase the capacitance between the gate of the switch tube and the active layer relative to the drive tube, thereby reducing the subthreshold swing of the switch tube relative to the drive tube, thereby improving the switching rate of the switch tube;
  • the capacitance between the gate of the driving tube and the active layer is reduced relative to the switching tube, thereby delaying the voltage change of the driving tube, so that the subthreshold swing of the driving tube is increased relative to the switching tube, thereby avoiding the driving tube
  • the inaccurate gray scale display of the OLED display device caused by the rapid voltage change enhances the display effect of the gray scale of the OLED display device.
  • the present invention provides an OLED array substrate including a switch tube for controlling pixel display and a drive tube for driving pixel display, the switch tube including a first insulation layer disposed between an active layer and a gate thereof;
  • the driving tube includes a second insulating layer disposed between an active layer and a gate thereof, the dielectric constant of the first insulating layer being higher than a dielectric constant of the second insulating layer.
  • the first insulating layer is made of a silicon nitride material
  • the second insulating layer is made of a silicon dioxide material.
  • the thickness of the first insulating layer ranges from 50 to 150 nm, and the thickness of the second insulating layer ranges from 120 to 200 nm.
  • the first insulating layer comprises an underlying film and a top film which are superposed on each other, the underlying film is in contact with the active layer, and the top film is in contact with the gate;
  • the underlayer film is made of a silicon dioxide material, and the top film is made of a silicon nitride material;
  • the second insulating layer is made of a silicon dioxide material.
  • the thickness of the underlayer film ranges from 30 to 50 nm, and the thickness of the top film ranges from 50 to 150 nm;
  • the thickness of the second insulating layer ranges from 120 to 200 nm.
  • the active layer of the switch tube and the active layer of the drive tube are both made of a low temperature polysilicon material.
  • the switch tube and the drive tube are top-gate transistors; or the switch tube and the drive tube are bottom-gate transistors.
  • the present invention also provides an OLED display device comprising the above OLED array substrate.
  • the present invention also provides a method for fabricating the above OLED array substrate, comprising forming a switching tube and a driving tube, the forming the switching tube comprising forming a first insulating layer between an active layer and a gate thereof; forming the driving tube comprises A second insulating layer is formed between the active layer and the gate, the dielectric constant of the first insulating layer being higher than the dielectric constant of the second insulating layer.
  • the active layer of the switch tube and the active layer of the drive tube are simultaneously formed using the same material, and the gate of the switch tube and the gate of the drive tube are The same material is formed at the same time.
  • the OLED array substrate provided by the present invention can make the dielectric constant of the first insulating layer higher than the dielectric constant of the second insulating layer, so that the gate between the switching tube and the active layer can be
  • the capacitance is increased relative to the driving tube, so that the subthreshold swing of the switching tube is lowered relative to the driving tube, thereby increasing the switching rate of the switching tube; and simultaneously reducing the capacitance between the gate of the driving tube and the active layer relative to the switching tube Small, thereby delaying the voltage change of the driving tube, so that the subthreshold swing of the driving tube is increased relative to the switching tube, thereby avoiding the incomplete display of the gray scale display of the OLED display device caused by the excessive voltage variation in the driving tube, and enhancing The display effect of the gray scale of the OLED display device.
  • the OLED display device provided by the present invention improves the reaction speed of the OLED display device by using the OLED array substrate, and improves the display effect of the OLED display device.
  • FIG. 1 is a cross-sectional view showing a partial structure of an OLED array substrate according to Embodiment 1 of the present invention
  • FIG. 2 is a cross-sectional view showing the structure of the preparation of step S101 in the method for preparing the OLED array substrate of FIG. 1;
  • step S102 is a cross-sectional view showing the structure of the preparation of step S102 in the method for fabricating the OLED array substrate of FIG. 1;
  • step S103 is a cross-sectional view showing the structure of the preparation of step S103 in the method for preparing the OLED array substrate of FIG. 1.
  • Switch tube 11. Active layer of switch tube; 12. Gate of switch tube; 13. First insulation layer; 14. Source of switch tube; 15. Drain of switch tube; 2.
  • the switch tube 1 includes a switch tube 1 for controlling pixel display and a drive tube 2 for driving pixel display.
  • the switch tube 1 includes an active layer 11 and a gate disposed thereon. a first insulating layer 13 between the poles 12; the driving tube 2 includes a second insulating layer 23 disposed between the active layer 21 and the gate 22 thereof, the first insulating layer 13 having a higher dielectric constant than the second insulating layer The dielectric constant of 23.
  • the capacitance between the gate electrode 12 of the switching transistor 1 and the active layer 11 can be increased relative to the driving tube 2, thereby The subthreshold swing of the switch tube 1 is lowered relative to the drive tube 2, thereby increasing the switching rate of the switch tube 1; at the same time, the capacitance between the gate 22 of the drive tube 2 and the active layer 21 can be reduced relative to the switch tube 1, Therefore, the voltage variation of the driving tube 2 is delayed, so that the subthreshold swing of the driving tube 2 is increased relative to the switching tube 1, thereby avoiding the incomplete display of the gray scale display of the OLED display device caused by the excessive voltage variation in the driving tube 2.
  • the display of the gray scale of the OLED display device is enhanced.
  • the first insulating layer 13 is made of silicon nitride material
  • the second insulating layer 23 is made of silicon dioxide.
  • the thickness of the first insulating layer 13 ranges from 50 to 150 nm, and the thickness of the second insulating layer 23 ranges from 120 to 200 nm.
  • the first insulating layer 13 of the above thickness and material can increase the capacitance between the gate 12 of the switching tube 1 and the active layer 11 relative to the driving tube 2, thereby lowering the subthreshold swing of the switching tube 1 relative to the driving tube 2. , thereby increasing the switching rate of the switching tube 1.
  • the second insulating layer 23 of the above thickness and material can reduce the capacitance between the gate 22 of the driving tube 2 and the active layer 21 relative to the switching tube 1, thereby delaying the voltage change of the driving tube 2, so that the driving tube 2 is The subthreshold swing is increased relative to the switch tube 1, thereby avoiding the incomplete display of the gray scale of the OLED display device caused by the excessive voltage variation in the drive tube 2, and enhancing the display effect of the gray scale of the OLED display device.
  • first insulating layer 13 and the second insulating layer 23 may also adopt other insulating materials, and the thickness thereof is determined according to the specific insulating layer material used, as long as the dielectric of the first insulating layer 13 can be ensured.
  • the constant is higher than the dielectric constant of the second insulating layer 23, which ultimately increases the switching rate of the switching transistor 1 and delays the voltage change of the driving tube 2, ensuring that the gray scale display of the OLED display device is complete.
  • the active layer 11 of the switch tube 1 and the active layer 21 of the drive tube 2 are both made of a low temperature polysilicon material.
  • the above-described dielectric constant setting of the first insulating layer 13 and the second insulating layer 23 is particularly effective for improving the switching tube 1 and the driving tube 2 of the active layer of the low-temperature polysilicon material.
  • the active layer 11 of the switch tube 1 and the active layer 21 of the drive tube 2 may also be made of an amorphous silicon material or an oxide semiconductor material.
  • the switching transistor 1 and the driving transistor 2 are top-gate transistors.
  • the switching tube and the driving tube may also be bottom-gate transistors, that is, the dielectric constants of the first insulating layer 13 of the switching tube 1 and the second insulating layer 23 of the driving tube 2 are also applicable to the OLED array substrate. Bottom-gate transistor.
  • the OLED array substrate further includes a glass substrate 3 and a buffer layer 4 disposed on the glass substrate 3.
  • the active layer 11 of the switch tube 1 and the active layer 21 of the drive tube 2 are disposed on the buffer layer 4;
  • the first insulating layer 13 is provided with the gate electrode 12 of the switch tube 1, and the second insulating layer 23 is provided with a drive tube a gate 22 of the switch 2;
  • a source 14 and a drain 15 of the switch transistor 1 are disposed above the gate 11 thereof, and a third insulating layer 5 is disposed between the source 14 and the drain 15 and the gate 11;
  • the source 24 and the drain 25 are disposed above the gate 21 thereof, and a third insulating layer 5 is disposed between the source 24 and the drain 25 and the gate 21.
  • the embodiment further provides a method for preparing the array substrate, as shown in FIG. 2 to FIG. 4, including forming the switch tube 1 and the drive tube 2, and forming the switch tube 1 includes A first insulating layer 13 is formed between the active layer 11 and the gate electrode 12; forming the driving tube 2 includes forming a second insulating layer 23 between the active layer 21 and the gate electrode 22, and the first insulating layer 13 is interposed.
  • the electric constant is higher than the dielectric constant of the second insulating layer 23.
  • forming the switch tube 1 and the drive tube 2 specifically includes:
  • Step S101 depositing a 50-150 nm silicon nitride (SiN) film layer and a 100-500 nm silicon dioxide (SiO 2 ) film layer as a buffer layer on the glass substrate 3 by plasma enhanced chemical vapor deposition (PECVD). Buffer layer) 4; then depositing a 30-100 nm amorphous silicon film layer (a-Si), the amorphous silicon film layer is formed into a polysilicon film layer (p-Si) by a laser quenching process (ELA); finally, simultaneously formed by a patterning process The pattern of the active layer 11 of the switch tube 1 and the pattern of the active layer 21 of the drive tube 2 (shown in FIG. 2).
  • PECVD plasma enhanced chemical vapor deposition
  • Step S102 depositing a silicon dioxide film layer (SiO 2 ) of 120 to 200 nm by plasma enhanced chemical vapor deposition (PECVD); then forming a pattern of the second insulating layer 21 of the driving tube 2 by a patterning process; then, passing the plasma A 50-150 nm silicon nitride film layer (SiN) is deposited by bulk enhanced chemical vapor deposition (PECVD); then a pattern of the first insulating layer 11 of the switching transistor 1 is formed by a patterning process (as shown in FIG. 3).
  • PECVD plasma enhanced chemical vapor deposition
  • Step S103 forming a subsequent film layer of the switching tube 1 and the driving tube 2 by a patterning process, that is, simultaneously forming the gate electrode 12 of the switching tube 1 and the gate electrode 22 of the driving tube 2 on the glass substrate 3 completing the step S102; Forming a third insulating layer 5 over the gate; finally, forming a source 14 and a drain 15 of the switching transistor 1 , a source 24 and a drain 25 of the driving transistor 2, and a OLED array substrate over the third insulating layer 5 Subsequent layers (such as pixel layers, etc.) (as shown in Figure 4).
  • the source 14 and the drain 15 of the switch 1 and the source 24 and the drain 25 of the drive tube 2 are formed of the same material and formed by a single patterning process, and the specific preparation process will not be described again.
  • the gate 12 of the switch tube 1 and the gate 22 of the drive tube 2 are formed of the same material and formed by one patterning process, and the specific preparation process will not be described again.
  • the third insulating layer 5 and the subsequent methods for preparing the respective film layers on the OLED array substrate adopt a conventional patterning process, and details are not described herein.
  • the embodiment provides an OLED array substrate.
  • the first insulating layer includes an underlying film and a top film which are overlapped with each other, and the underlying film is in contact with the active layer, and the top film is in contact with the gate.
  • the underlying film is made of a silicon dioxide material
  • the top film is made of a silicon nitride material
  • the second insulating layer is made of a silicon dioxide material.
  • the underlying film of the silicon dioxide material is in contact with the active layer, which can reduce the interface defects of the active layer and improve the interface effect of the active layer, thereby making the switching control performance of the switching tube more stable.
  • the thickness of the underlying film ranges from 30 to 50 nm
  • the thickness of the top film ranges from 50 to 150 nm
  • the thickness of the second insulating layer ranges from 120 to 200 nm.
  • the thickness and the first insulating layer of the material can also increase the capacitance between the gate and the active layer of the switching tube relative to the driving tube, thereby lowering the subthreshold swing of the switching tube relative to the driving tube, thereby improving the switching tube. Switching rate.
  • the thickness and the second insulating layer of the material can also reduce the capacitance between the gate and the active layer of the driving tube relative to the switching tube, thereby delaying the voltage change of the driving tube, so that the subthreshold swing of the driving tube is opposite to the switch.
  • the tube is enlarged, thereby avoiding the incomplete display of the gray scale of the OLED display device caused by the excessive voltage change in the driving tube, and enhancing the display effect of the gray scale of the OLED display device.
  • the OLED array substrate provided in Embodiment 1-2 can make the gate of the switch tube and the dielectric constant of the first insulating layer higher than the dielectric constant of the second insulating layer.
  • the capacitance between the active layers is increased relative to the driving tube, so that the subthreshold swing of the switching tube is lowered relative to the driving tube, thereby increasing the switching rate of the switching tube; and simultaneously between the gate of the driving tube and the active layer
  • the capacitance is reduced relative to the switch tube, thereby delaying the voltage change of the drive tube, so that the subthreshold swing of the drive tube is increased relative to the switch tube, thereby avoiding the gray scale of the OLED display device caused by the excessive voltage change in the drive tube.
  • the incomplete display enhances the display of the gray scale of the OLED display device.
  • This embodiment provides an OLED display device including the OLED array substrate in Embodiment 1 or 2.
  • the reaction speed of the OLED display device is improved, and the display effect of the OLED display device is improved.
  • the OLED display device provided by the present invention may be any product or component having an display function such as an OLED panel, an OLED TV, a display, a mobile phone, a navigator or the like.

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Abstract

本发明提供一种OLED阵列基板及其制备方法和OLED显示装置。该OLED阵列基板包括用于控制像素显示的开关管和用于驱动像素显示的驱动管，开关管包括设置在其有源层和栅极之间的第一绝缘层；驱动管包括设置在其有源层和栅极之间的第二绝缘层，第一绝缘层的介电常数高于第二绝缘层的介电常数。该OLED阵列基板能使开关管的栅极与有源层之间的电容相对驱动管增大，从而使开关管的亚阈值摆幅相对驱动管降低，进而提高了开关管的开关速率；同时能使驱动管的栅极与有源层之间的电容相对开关管减小，从而延缓了驱动管的电压变化，使驱动管的亚阈值摆幅相对开关管增大，进而增强了OLED显示器件的灰阶的显示效果。

Description

一种OLED阵列基板及其制备方法和OLED显示装置 技术领域
本发明涉及移动设备技术领域，具体地，涉及一种OLED阵列基板及其制备方法和OLED显示装置。
背景技术
随着显示技术的发展，有机发光二极管(Organic Light-Emitting Diode,OLED)显示技术具有自发光、广视角、高的对比度、较低耗电、极高反应速度等优点，成为大家研究的热点。
在平板显示技术领域，低温多晶硅薄膜晶体管显示器(Low Temperature Poly-silicon Thin Film Transistor，简称LTPS TFT)具有高的反应速度、高开口率、高亮度等优点，LTPS技术越来越受市场青睐。而且它还能被用于柔性显示以及被称为下一代显示技术的有机发光二极管显示器上。
OLED阵列基板上通常会设置用于控制像素显示的开关晶体管(Switching TFT)和用于驱动像素显示的驱动晶体管(Driving TFT)。其中为了加快开关晶体管的开关速度，开关晶体管一般需要具有较低的亚阈值摆幅(SS)；而为了更好地显示OLED显示器的不同灰阶，驱动晶体管则要求具有较大的亚阈值摆幅(SS)，否则的话，过快的电压变化会造成灰阶显示的不完全，影响OLED显示器的显示效果。
因此，如何使OLED阵列基板上的开关晶体管的亚阈值摆幅增大的同时还能使驱动晶体管的亚阈值摆幅降低已成为目前亟待解决的技术问题。
发明内容
本发明针对现有技术中存在的上述技术问题，提供一种 OLED阵列基板及其制备方法和OLED显示装置。该OLED阵列基板能使开关管的栅极与有源层之间的电容相对驱动管增大，从而使开关管的亚阈值摆幅相对驱动管降低，进而提高了开关管的开关速率；同时能使驱动管的栅极与有源层之间的电容相对开关管减小，从而延缓了驱动管的电压变化，使驱动管的亚阈值摆幅相对开关管增大，进而避免了驱动管中过快的电压变化所造成的OLED显示器件灰阶显示的不完全，增强了OLED显示器件的灰阶的显示效果。
本发明提供一种OLED阵列基板，包括用于控制像素显示的开关管和用于驱动像素显示的驱动管，所述开关管包括设置在其有源层和栅极之间的第一绝缘层；所述驱动管包括设置在其有源层和栅极之间的第二绝缘层，所述第一绝缘层的介电常数高于所述第二绝缘层的介电常数。
优选地，所述第一绝缘层采用氮化硅材料，所述第二绝缘层采用二氧化硅材料。
优选地，所述第一绝缘层的厚度范围为50～150nm，所述第二绝缘层的厚度范围为120～200nm。
优选地，所述第一绝缘层包括相互叠覆的底层膜和顶层膜，所述底层膜与所述有源层相接触，所述顶层膜与所述栅极相接触；
所述底层膜采用二氧化硅材料，所述顶层膜采用氮化硅材料；
所述第二绝缘层采用二氧化硅材料。
优选地，所述底层膜的厚度范围为30～50nm，所述顶层膜的厚度范围为50～150nm；
所述第二绝缘层的厚度范围为120～200nm。
优选地，所述开关管的有源层和所述驱动管的有源层均采用低温多晶硅材料。
优选地，所述开关管和所述驱动管均为顶栅型晶体管；或者，所述开关管和所述驱动管均为底栅型晶体管。
本发明还提供一种OLED显示装置，包括上述OLED阵列基板。
本发明还提供一种上述OLED阵列基板的制备方法，包括形成开关管和驱动管，形成所述开关管包括在其有源层和栅极之间形成第一绝缘层；形成所述驱动管包括在其有源层和栅极之间形成第二绝缘层，所述第一绝缘层的介电常数高于所述第二绝缘层的介电常数。
优选地，所述开关管的所述有源层和所述驱动管的所述有源层采用相同材料同时形成，所述开关管的所述栅极和所述驱动管的所述栅极采用相同材料同时形成。
本发明的有益效果：本发明所提供的OLED阵列基板，通过使第一绝缘层的介电常数高于第二绝缘层的介电常数，能使开关管的栅极与有源层之间的电容相对驱动管增大，从而使开关管的亚阈值摆幅相对驱动管降低，进而提高了开关管的开关速率；同时能使驱动管的栅极与有源层之间的电容相对开关管减小，从而延缓了驱动管的电压变化，使驱动管的亚阈值摆幅相对开关管增大，进而避免了驱动管中过快的电压变化所造成的OLED显示器件灰阶显示的不完全，增强了OLED显示器件的灰阶的显示效果。
本发明所提供的OLED显示装置，通过采用上述OLED阵列基板，提升了该OLED显示装置的反应速度，并提高了该OLED显示装置的显示效果。
附图说明
图1为本发明实施例1中OLED阵列基板的局部结构剖视示意图；
图2为图1中OLED阵列基板的制备方法中步骤S101的制备结构剖视示意图；
图3为图1中OLED阵列基板的制备方法中步骤S102的制备结构剖视示意图；
图4为图1中OLED阵列基板的制备方法中步骤S103的制备结构剖视示意图。
其中的附图标记说明：
1.开关管；11.开关管的有源层；12.开关管的栅极；13.第一绝缘层；14.开关管的源极；15.开关管的漏极；2.驱动管；21.驱动管的有源层；22.驱动管的栅极；23.第二绝缘层；24.驱动管的源极；25.驱动管的漏极；3.玻璃基底；4.缓冲层；5.第三绝缘层。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种OLED阵列基板及其制备方法和OLED显示装置作进一步详细描述。
实施例1：
本实施例提供一种OLED阵列基板，如图1所示，包括用于控制像素显示的开关管1和用于驱动像素显示的驱动管2，开关管1包括设置在其有源层11和栅极12之间的第一绝缘层13；驱动管2包括设置在其有源层21和栅极22之间的第二绝缘层23，第一绝缘层13的介电常数高于第二绝缘层23的介电常数。
通过使第一绝缘层13的介电常数高于第二绝缘层23的介电常数，能使开关管1的栅极12与有源层11之间的电容相对驱动管2增大，从而使开关管1的亚阈值摆幅相对驱动管2降低，进而提高了开关管1的开关速率；同时能使驱动管2的栅极22与有源层21之间的电容相对开关管1减小，从而延缓了驱动管2的电压变化，使驱动管2的亚阈值摆幅相对开关管1增大，进而避免了驱动管2中过快的电压变化所造成的OLED显示器件灰阶显示的不完全，增强了OLED显示器件的灰阶的显示效果。
优选的，本实施例中，第一绝缘层13采用氮化硅材料，第二绝缘层23采用二氧化硅材料。
其中，第一绝缘层13的厚度范围为50～150nm，第二绝缘层23的厚度范围为120～200nm。上述厚度和材料的第一绝缘层 13能使开关管1的栅极12与有源层11之间的电容相对驱动管2增大，从而使开关管1的亚阈值摆幅相对驱动管2降低，进而提高了开关管1的开关速率。上述厚度和材料的第二绝缘层23能使驱动管2的栅极22与有源层21之间的电容相对开关管1减小，从而延缓了驱动管2的电压变化，使驱动管2的亚阈值摆幅相对开关管1增大，进而避免了驱动管2中过快的电压变化所造成的OLED显示器件灰阶显示的不完全，增强了OLED显示器件的灰阶的显示效果。
需要说明的是，第一绝缘层13和第二绝缘层23也可以采用其他的绝缘材料，且其厚度设置根据具体所采用的绝缘层材料而定，只要能够确保第一绝缘层13的介电常数高于第二绝缘层23的介电常数，最终能使开关管1的开关速率提高，并使驱动管2的电压变化延缓，确保OLED显示器件的灰阶显示完全即可。
本实施例中，开关管1的有源层11和驱动管2的有源层21均采用低温多晶硅材料。第一绝缘层13和第二绝缘层23的上述介电常数设置对于低温多晶硅材料的有源层的开关管1和驱动管2的改善效果尤为明显。
需要说明的是，开关管1的有源层11和驱动管2的有源层21也可以采用非晶硅材料或者氧化物半导体材料。
本实施例中，开关管1和驱动管2均为顶栅型晶体管。另外，开关管和驱动管也可以均为底栅型晶体管，即上述开关管1的第一绝缘层13和驱动管2的第二绝缘层23的介电常数设置同样适用于OLED阵列基板上的底栅型晶体管。
另外，本实施例中，OLED阵列基板还包括玻璃基底3和设置在玻璃基底3上的缓冲层4。开关管1的有源层11和驱动管2的有源层21设置在缓冲层4上；第一绝缘层13上设置有开关管1的栅极12，第二绝缘层23上设置有驱动管2的栅极22；开关管1的源极14和漏极15设置于其栅极11上方，且源极14和漏极15与栅极11之间设置有第三绝缘层5；驱动管2的源极24和漏极25设置于其栅极21上方，且源极24和漏极25与栅极 21之间设置有第三绝缘层5。
基于本实施例中提供的上述OLED阵列基板，本实施例还提供一种该阵列基板的制备方法，如图2-图4所示，包括形成开关管1和驱动管2，形成开关管1包括在其有源层11和栅极12之间形成第一绝缘层13；形成驱动管2包括在其有源层21和栅极22之间形成第二绝缘层23，第一绝缘层13的介电常数高于第二绝缘层23的介电常数。
其中，形成开关管1和驱动管2具体包括：
步骤S101：在玻璃基底3上，通过等离子体增强化学气相沉积法(PECVD)沉积50-150nm氮化硅(SiN)膜层和100-500nm的二氧化硅(SiO 2)膜层作为缓冲层(Buffer层)4；然后沉积30-100nm的非晶硅膜层(a-Si)，非晶硅膜层通过激光淬火工艺(ELA)形成多晶硅膜层(p-Si)；最后通过构图工艺同时形成开关管1的有源层11的图形和驱动管2的有源层21的图形(如图2所示)。
步骤S102：通过等离子体增强化学气相沉积法(PECVD)沉积120～200nm的二氧化硅膜层(SiO 2)；然后通过构图工艺形成驱动管2的第二绝缘层21的图形；接着，通过等离子体增强化学气相沉积法(PECVD)沉积50-150nm的氮化硅膜层(SiN)；然后通过构图工艺形成开关管1的第一绝缘层11的图形(如图3所示)。
步骤S103：通过构图工艺形成开关管1和驱动管2的后续膜层，即在完成步骤S102的玻璃基底3上同时制备形成开关管1的栅极12和驱动管2的栅极22；然后在栅极上方制备形成第三绝缘层5；最后在第三绝缘层5上方制备形成开关管1的源极14和漏极15、驱动管2的源极24和漏极25以及OLED阵列基板上的后续各膜层(如像素层等)(如图4所示)。
其中，开关管1的源极14和漏极15及驱动管2的源极24和漏极25采用相同材料且通过一次构图工艺形成，具体制备过程不再赘述。另外，开关管1的栅极12和驱动管2的栅极22 采用相同材料且通过一次构图工艺形成，具体制备过程不再赘述。第三绝缘层5和OLED阵列基板上后续各膜层的制备方法均采用传统的构图工艺，具体不再赘述。
实施例2：
本实施例提供一种OLED阵列基板，与实施例1中不同的是，第一绝缘层包括相互叠覆的底层膜和顶层膜，底层膜与有源层相接触，顶层膜与栅极相接触；底层膜采用二氧化硅材料，顶层膜采用氮化硅材料；第二绝缘层采用二氧化硅材料。
如此设置，二氧化硅材料的底层膜与有源层接触，能够减小有源层的界面缺陷，提升有源层的界面效果，从而使开关管的开关控制性能更加稳定。
相应地，本实施例中，底层膜的厚度范围为30～50nm，顶层膜的厚度范围为50～150nm；第二绝缘层的厚度范围为120～200nm。
上述厚度和材料的第一绝缘层同样能使开关管的栅极与有源层之间的电容相对驱动管增大，从而使开关管的亚阈值摆幅相对驱动管降低，进而提高了开关管的开关速率。上述厚度和材料的第二绝缘层同样能使驱动管的栅极与有源层之间的电容相对开关管减小，从而延缓了驱动管的电压变化，使驱动管的亚阈值摆幅相对开关管增大，进而避免了驱动管中过快的电压变化所造成的OLED显示器件灰阶显示的不完全，增强了OLED显示器件的灰阶的显示效果。
本实施例中OLED阵列基板的其他结构及OLED阵列基板的制备方法均与实施例1中相同，此处不再赘述。
实施例1-2的有益效果：实施例1-2所提供的OLED阵列基板，通过使第一绝缘层的介电常数高于第二绝缘层的介电常数，能使开关管的栅极与有源层之间的电容相对驱动管增大，从而使开关管的亚阈值摆幅相对驱动管降低，进而提高了开关管的开关速率；同时能使驱动管的栅极与有源层之间的电容相对开关管减 小，从而延缓了驱动管的电压变化，使驱动管的亚阈值摆幅相对开关管增大，进而避免了驱动管中过快的电压变化所造成的OLED显示器件灰阶显示的不完全，增强了OLED显示器件的灰阶的显示效果。
实施例3：
本实施例提供一种OLED显示装置，包括实施例1或2中的OLED阵列基板。
通过采用实施例1或2中的阵列基板，提升了该OLED显示装置的反应速度，并提高了该OLED显示装置的显示效果。
本发明所提供的OLED显示装置可以为OLED面板、OLED电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种OLED阵列基板，包括用于控制像素显示的开关管和用于驱动像素显示的驱动管，所述开关管包括设置在其有源层和栅极之间的第一绝缘层；所述驱动管包括设置在其有源层和栅极之间的第二绝缘层，其特征在于，所述第一绝缘层的介电常数高于所述第二绝缘层的介电常数。
  2. 根据权利要求1所述的OLED阵列基板，其特征在于，所述第一绝缘层采用氮化硅材料，所述第二绝缘层采用二氧化硅材料。
  3. 根据权利要求2所述的OLED阵列基板，其特征在于，所述第一绝缘层的厚度范围为50～150nm，所述第二绝缘层的厚度范围为120～200nm。
  4. 根据权利要求1所述的OLED阵列基板，其特征在于，所述第一绝缘层包括相互叠覆的底层膜和顶层膜，所述底层膜与所述有源层相接触，所述顶层膜与所述栅极相接触；
    所述底层膜采用二氧化硅材料，所述顶层膜采用氮化硅材料；
    所述第二绝缘层采用二氧化硅材料。
  5. 根据权利要求4所述的OLED阵列基板，其特征在于，所述底层膜的厚度范围为30～50nm，所述顶层膜的厚度范围为50～150nm；
    所述第二绝缘层的厚度范围为120～200nm。
  6. 根据权利要求1所述的OLED阵列基板，其特征在于，所述开关管的有源层和所述驱动管的有源层均采用低温多晶硅材料。
  7. 根据权利要求1所述的OLED阵列基板，其特征在于，所述开关管和所述驱动管均为顶栅型晶体管；或者，所述开关管和所述驱动管均为底栅型晶体管。
  8. 一种OLED显示装置，其特征在于，包括权利要求1-7任意一项所述的OLED阵列基板。
  9. 一种如权利要求1-7任意一项所述的OLED阵列基板的制备方法，包括形成开关管和驱动管，形成所述开关管包括在其有源层和栅极之间形成第一绝缘层；形成所述驱动管包括在其有源层和栅极之间形成第二绝缘层，其特征在于，所述第一绝缘层的介电常数高于所述第二绝缘层的介电常数。
  10. 根据权利要求9所述的OLED阵列基板的制备方法，其特征在于，所述开关管的所述有源层和所述驱动管的所述有源层采用相同材料同时形成，所述开关管的所述栅极和所述驱动管的所述栅极采用相同材料同时形成。
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