WO2018040489A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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WO2018040489A1
WO2018040489A1 PCT/CN2017/071600 CN2017071600W WO2018040489A1 WO 2018040489 A1 WO2018040489 A1 WO 2018040489A1 CN 2017071600 W CN2017071600 W CN 2017071600W WO 2018040489 A1 WO2018040489 A1 WO 2018040489A1
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layer
active layer
gate
insulating layer
over
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PCT/CN2017/071600
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English (en)
French (fr)
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曾勉
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深圳市华星光电技术有限公司
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Priority to US15/500,125 priority Critical patent/US20180211984A1/en
Publication of WO2018040489A1 publication Critical patent/WO2018040489A1/zh

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    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G02F1/136245—Active matrix addressed cells having more than one switching element per pixel having complementary transistors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer

Definitions

  • the present invention relates to the field of liquid crystal displays, and in particular, to an array substrate and a method of fabricating the same.
  • LCD Liquid Crystal Display
  • LCD panel mobile phone
  • CMOS Complementary Metal Oxide Semiconductor
  • PMOS P-channel metal oxide semiconductor
  • N-channel metal oxide semiconductor Nigative channel Metal Oxide Semiconductor
  • CMOS circuit is the most basic circuit structure of an integrated circuit IC.
  • the CMOS transmission gate is formed by a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and an N-channel MOSFET in parallel, except as a switch for transmitting an analog signal. It can also be used as the basic unit circuit of various logic circuits.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • CMOS complementary metal-oxide-semiconductor
  • the complementary structure of CMOS utilizes the "complementary" feature. There is no threshold loss when transmitting high and low levels, that is, the input and output signals have good consistency; and the on-resistance of the CMOS transmission gate is low, and can be approximated as a constant.
  • the CMOS transmission gate has bidirectionality, and if it is applied in a GOA (Gate On Array) circuit, it can be used as a control switch for bidirectional scanning of the panel.
  • GOA Gate On Array
  • the active device formed thereon is basically an N-type amorphous silicon (a-Si) thin film transistor.
  • a-Si N-type amorphous silicon
  • TFT Thin Film Transistor
  • LTPS Low Temperature Poly-silicon
  • a-Si can be converted to Poly Si by ELA and other technologies, and P-type TFTs and N-types can be formed by using different types of doping at the channel.
  • TFT thereby forming a CMOS-like Complementary Thin Film Transistor (CTFT), but the process flow is complicated, and its system The backup cost is also relatively high.
  • CTFT Complementary Thin Film Transistor
  • the technical problem to be solved by the present invention is to provide an array substrate and a preparation method thereof, which are advantageous for simplifying the preparation process of the CTFT and improving the success rate of the preparation.
  • a first aspect of the present invention provides an array substrate
  • the present invention provides an array substrate comprising a transmission gate structure, the transmission gate structure comprising, in order from bottom to top, in order:
  • a first gate over the substrate, a first gate insulating layer over the first gate and completely covering the first gate, above the first gate insulating layer a first active layer opposite to the first gate, an insulating layer over the first active layer, over the insulating layer, through a via located in the insulating layer a source and drain layer electrically connected to the first active layer, a second active layer over the source and drain layers, over the second active layer and completely covering the second a second gate insulating layer of the active layer, a second gate opposite the second gate above the second gate insulating layer.
  • the first active layer is an N-type active layer
  • the second active layer is a P-type active layer.
  • the insulating layer comprises an etch barrier layer and/or a flat layer.
  • the insulating layer comprises an etch barrier layer and a planarization layer
  • the etch barrier layer is located above the first active layer
  • the planarization layer is located above the etch barrier layer.
  • the material of the etch barrier layer comprises a nitride of silicon and/or an oxide of silicon.
  • the transmission gate structure includes two upper and lower TFTs, the active layer of the TFT on the lower side is the first active layer, and the active layer of the TFT on the upper side is the second active layer.
  • the first active layer and the second active layer are respectively disposed on both sides of the source and drain layers, and the source and drain electrodes are shared.
  • the invention also provides a method for preparing an array substrate, comprising the following steps:
  • Step S1 acquiring a substrate
  • Step S2 forming a first gate on the substrate
  • Step S3 forming a first gate insulating layer completely covering the first metal layer on the first gate;
  • Step S4 forming a first active layer over the first gate insulating layer, the first active layer being opposite to the first gate;
  • Step S5 forming an insulating layer on the first active layer, and patterning the insulating layer to form a via hole;
  • Step S6 forming a source and drain layer over the insulating layer, the source and drain layers being electrically connected to the first active layer through the via holes;
  • Step S7 forming a second active layer on the source and drain layers
  • Step S8 forming a second gate insulating layer completely covering the second active layer over the second active layer;
  • Step S9 forming a second gate opposite to the second active layer over the second gate insulating layer.
  • the first active layer is an N-type active layer
  • the second active layer is a P-type active layer
  • the first active layer is made of a metal oxide material
  • the second The material of the active layer is a P-type organic semiconductor material.
  • the insulating layer comprises an etch barrier layer and/or a flat layer.
  • the step S5 includes:
  • Step S51 forming an etch stop layer covering the first active layer over the first active layer
  • Step S52 forming a flat layer covering the etch barrier layer over the etch barrier layer
  • Step S53 performing a patterning process on the etch stop layer and the flat layer to form via holes penetrating the flat layer and the etch stop layer.
  • the material of the etch barrier layer comprises a nitride of silicon and/or an oxide of silicon.
  • the transmission gate structure includes two upper and lower TFTs, the active layer of the TFT on the lower side is the first active layer, and the active layer of the TFT on the upper side is the second active layer.
  • the first active layer and the second active layer are respectively disposed on both sides of the source and drain layers, and the source and drain electrodes are shared.
  • FIG. 1 is a schematic structural diagram of a first array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a second array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a third array substrate according to an embodiment of the present invention.
  • the embodiment of the invention provides an array substrate, which optimizes the structure of the CTFT transmission gate device in the prior art, so that the integrated process can be fully fabricated on the array substrate and other substrates such as glass and PEN, thereby applying the same. It is more extensive and can reduce the production cost of its application products to a greater extent.
  • the CTFT is a transmission gate circuit structure, and is optimized by the present invention, which includes, from bottom to top, in order:
  • the insulating layer is an etch stop layer 5
  • a source-drain layer 7 electrically connected to the N-type active layer 4 is formed over the insulating layer via a via 6 located in the insulating layer
  • a P-type active layer 8 is disposed over the source-drain layer 7 at P a second gate insulating layer 9 over the active layer 8 and completely covering the P-type active layer 8, and a second gate opposite the second gate 10 over the second gate insulating layer 9.
  • each CTFT includes two upper and lower TFTs, and the active layer of the TFT on the lower side is an N-type active layer 4, and thus is an N-type TFT; the TFT located on the upper side
  • the active layer is a P-type active layer 8, and thus is a P-type TFT.
  • the N-type active layer 4 and the P-type active layer 8 are respectively disposed on both sides of the source/drain layer 7, and share source-drain electrodes.
  • the embodiment of the present invention further provides a corresponding preparation method, specifically It can include the following steps:
  • step S1 the base substrate 1 is obtained.
  • step S2 the first gate electrode 2 is formed on the base substrate 1.
  • Step S3 forming a first gate insulating layer 3 completely covering the first metal layer over the first gate 2.
  • Step S4 an N-type active layer 4 is formed on the first gate insulating layer 3, and the N-type active layer 4 is opposed to the first gate 2.
  • Step S5 forming an insulating layer on the N-type active layer 4, and patterning the insulating layer to form via holes 6.
  • Step S6 a source/drain layer 7 is formed over the insulating layer, and the source and drain layers 7 are electrically connected to the N-type active layer 4 through the via holes 6.
  • Step S7 a P-type active layer 8 is formed over the source and drain layers 7.
  • Step S8 forming a second gate insulating layer 9 completely covering the P-type active layer 8 over the P-type active layer 8.
  • Step S9 forming a second gate 10 opposite to the P-type active layer 8 over the second gate insulating layer 9.
  • the process of the P-type TFT is placed as far as possible after the NTFT process, and the structure of the top gate bottom contact is adopted. It is ensured that the characteristics of the organic semiconductor in the P-type TFT device are not affected by the process.
  • the insulating layer may be only one layer of the etch barrier layer 5 as shown in FIG. 1 or only a layer of the flat layer 11 as shown in FIG. 3, and may also be engraved as shown in FIG. A flat layer 11 is superposed on the etch barrier layer 5.
  • the embodiment of the present invention provides three specific array substrates and corresponding preparation methods, as follows:
  • FIG. 1 it is a structural diagram of a CTFT on a first type of array substrate, wherein the CTFT comprises a P-type TFT of a top gate bottom contact structure and an N-type TFT of an etch barrier layer 5, and the preparation method thereof is as follows: :
  • a gate metal layer is sputtered on the base substrate 1 (for example, using a material such as Mo/Al/Mo or Cu/Ti), and a first gate electrode 2 is formed after exposure, development, etching, stripping, and the like.
  • a gate electrode of the N-type oxide TFT As the gate electrode of the N-type oxide TFT.
  • the base substrate 1 in the embodiment of the present invention can be obtained by using materials such as glass or polyethylene naphthalate (PEN).
  • the first gate insulating layer 3 is then formed by a vapor deposition (CVD) or a coating method. Then, a layer of indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO for short) or other N-type metal oxide semiconductor material is formed, and the N-type active layer 4 is formed after exposure, development, etching, stripping, and the like. . Then, an etch stop layer 5 is formed thereon, and the material thereof is generally silicon nitride. (SiNx) or an oxide of silicon (SiOx), and a via 6 connected to the source/drain layer 7 is formed on the etch barrier layer 5 by a patterning process.
  • CVD vapor deposition
  • a coating method a layer of indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO for short) or other N-type metal oxide semiconductor material is formed, and the N-type active layer 4 is formed after exposure, development, etching, stripping, and the like. . The
  • a layer of source and drain electrode metal layers (for example, Mo/Al/Mo, Cu/Ti, etc.) is sputtered, and after exposure, development, etching, and stripping, the source/drain layer 7 is formed as an N-type TFT and Source-drain electrodes shared by P-type TFTs.
  • a P-type active layer 8 is prepared, that is, a P-type organic semiconductor material (for example, a material such as pentacene) is coated on the base substrate 1, and a pattern of the P-type active layer 8 is formed by a photolithography method;
  • the protective layer is formed by CVD or coating, and serves as a gate insulating layer of the P-type TFT, that is, the second gate insulating layer 9.
  • a top gate electrode structure of a P-type TFT that is, a second gate electrode 10 is formed over the second gate insulating layer 9 by photolithography or evaporation. So far, the CTFT transmission gate structure shown in FIG. 1 has been completed, and the description of the subsequent electrical connection preparation and the subsequent preparation of the package protective layer is omitted.
  • the insulating layer in the CTFT of the array substrate shown in FIG. 1 is only one layer structure of the etch barrier layer 5.
  • the CTFT also includes a P-type TFT of a top gate bottom contact structure and an N-type TFT of an etch barrier layer 5.
  • the structure of the CTFT shown in FIG. 2 is the improved structure of FIG. 1.
  • the etch stop layer 5 is formed, after the etch stop layer 5 is formed, The surface is coated with a flat layer 11, and the material of the flat layer 11 is generally an organic material, which has a flattening effect. Then, the etching stopper layer 5 and the flat layer 11 are patterned together to form a via hole 6 for the source drain layer 7 to contact the N-type active layer 4.
  • the insulating layer can also be prepared by using only one flat layer 11.
  • the CTFT of the array substrate also includes a P-type TFT of a top gate bottom contact structure and an N-type TFT of an etch barrier structure.
  • the structure of the CTFT shown in FIG. 3 is the improved structure of FIG. 2.
  • the planar layer 11 in FIG. 3 can serve as an etch barrier for protecting the N-type active layer 4, and can also be used as an improved P-type active layer 8 spin coating. Or a flattening layer of the coating effect. This can save a process of etching the barrier layer, save the preparation cost of the array substrate, and improve the preparation success rate and yield rate.
  • N-type active layer and the P-type active layer of the present application can be interchanged, and the technical solutions described in the respective embodiments are not affected.

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Abstract

一种阵列基板及其制备方法，该阵列基板包括一种传输门结构。传输门结构包括上下两个TFT，位于下侧的TFT的有源层为第一有源层（4），位于上侧的TFT的有源层为第二有源层（8），第一有源层（4）和第二有源层（8）分别设置在源漏极层（7）的两侧，共用源漏电极。这个结构有利于简化传输门结构的制备工艺，提高制备的成功率。

Description

一种阵列基板及其制备方法
本申请要求享有2016年8月31日提交的名称为“一种阵列基板及其制备方法”的中国专利申请CN201610799421.4的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示器领域，尤其涉及一种阵列基板及其制备方法。
背景技术
液晶显示面板(Liquid Crystal Display，简称LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶面板、移动电话、个人数字助理
互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)由P型沟道金属氧化物半导体(Positive channel Metal Oxide Semiconductor，简称PMOS)和N型沟道金属氧化物半导体(Negative channel Metal Oxide Semiconductor，简称NMOS)共同构成，而CMOS电路是作为驱动集成电路(Integrated Circuit)IC的最基本电路结构。
其中，CMOS传输门由一个P沟道金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)和一个N沟道MOSFET并联而成，除了作为传输模拟信号的开关之外，也可作为各种逻辑电路的基本单元电路。
CMOS的互补结构利用了“互补”的特性，传输高低电平时都没有阈值损耗，即输入与输出信号的一致性好；而且CMOS传输门的导通电阻较低，且基本上可近似为一常数；另外，由于其源极和漏极可以互换使用，因此，CMOS传输门具有双向性，若应用在GOA(Gate On Array)电路里面，则可以作为面板双向扫描的控制开关。
而目前显示面板中的衬底基板大部分为玻璃、聚萘二甲酸乙二醇酯(PEN)等，在其上面形成的主动元件基本上为N型的非晶硅(a-Si)薄膜晶体管(Thin Film Transistor，简称TFT)，而无P型的TFT结构。在低温多晶硅技术(Low Temperature Poly-silicon，简称LTPS)中，通过ELA等技术可将a-Si转变成Poly Si，并且通过在沟道处使用不同类型的掺杂可以形成P型TFT和N型TFT，从而形成类似CMOS的互补薄膜晶体管(Complementary Thin Film Transistor，简称CTFT)，但其工艺流程较为复杂，而且其制 备成本也比较高。
发明内容
本发明所要解决的技术问题在于提供一种阵列基板及其制备方法，有利于简化CTFT的制备工艺，提高制备的成功率。
为解决上述技术问题，本发明采用如下技术方案：
本发明第一方面提供了一种阵列基板，
本发明提供了一种阵列基板，其包括一种传输门结构，所述传输门结构由下至上依次包括：
位于衬底基板之上的第一栅极，位于所述第一栅极之上的且完全覆盖所述第一栅极的第一栅极绝缘层，位于所述第一栅极绝缘层之上的、与所述第一栅极相对的第一有源层，位于所述第一有源层之上的绝缘层，位于所述绝缘层之上的、通过位于所述绝缘层的过孔实现与所述第一有源层电连接的源漏极层，位于所述源漏极层之上的第二有源层，位于所述第二有源层之上的且完全覆盖所述第二有源层的第二栅极绝缘层，位于所述第二栅极绝缘层之上的、与所述第二栅极相对的第二栅极。
优选的，所述第一有源层为N型有源层，所述第二有源层为P型有源层。
优选的，所述绝缘层包括刻蚀阻挡层和/或平坦层。
优选的，当所述绝缘层包括刻蚀阻挡层和平坦层时，所述刻蚀阻挡层位于所述第一有源层之上，所述平坦层位于所述刻蚀阻挡层之上。
优选的，所述刻蚀阻挡层的材质包括硅的氮化物和/或硅的氧化物。
在本发明实施例提供的阵列基板中，传输门结构包括上下两个TFT，位于下侧的TFT的有源层为第一有源层，位于上侧的TFT的有源层为第二有源层，第一有源层和第二有源层分别设置在源漏极层的两侧，共用源漏电极。这个结构与现有技术相比更简单，并且有利于简化传输门结构的制备工艺，提高制备的成功率。
本发明还提供了一种阵列基板的制备方法，包括如下步骤：
步骤S1、获取衬底基板；
步骤S2、在所述衬底基板之上形成第一栅极；
步骤S3、在所述第一栅极之上形成完全覆盖所述第一金属层的第一栅极绝缘层；
步骤S4、在所述第一栅极绝缘层之上形成第一有源层，所述第一有源层与所述第一栅极相对；
步骤S5、在所述第一有源层之上形成绝缘层，对所述绝缘层进行构图工艺，形成过孔；
步骤S6、在所述绝缘层之上形成源漏极层，所述源漏极层通过所述过孔实现与所述第一有源层的电连接；
步骤S7、在所述源漏极层之上形成第二有源层；
步骤S8、在所述第二有源层之上形成完全覆盖所述第二有源层的第二栅极绝缘层；
步骤S9、在所述第二栅极绝缘层之上形成与所述第二有源层相对的第二栅极。
优选的，所述第一有源层为N型有源层，所述第二有源层为P型有源层；所述第一有源层的材质为金属氧化物材料，所述第二有源层的材质为P型有机半导体材料。
优选的，所述绝缘层包括刻蚀阻挡层和/或平坦层。
优选的，当所述绝缘层包括刻蚀阻挡层和平坦层时，所述步骤S5包括：
步骤S51、在所述第一有源层之上形成覆盖所述第一有源层的刻蚀阻挡层；
步骤S52、在所述刻蚀阻挡层之上形成覆盖所述刻蚀阻挡层的平坦层；
步骤S53、对所述刻蚀阻挡层和所述平坦层进行构图工艺，形成贯穿所述平坦层和所述刻蚀阻挡层的过孔。
优选的，所述刻蚀阻挡层的材质包括硅的氮化物和/或硅的氧化物。
在本发明实施例提供的阵列基板中，传输门结构包括上下两个TFT，位于下侧的TFT的有源层为第一有源层，位于上侧的TFT的有源层为第二有源层，第一有源层和第二有源层分别设置在源漏极层的两侧，共用源漏电极。这个结构与现有技术相比更简单，并且有利于简化传输门结构的制备工艺，提高制备的成功率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的第一种阵列基板的结构示意图；
图2为本发明实施例提供的第二种阵列基板的结构示意图；
图3为本发明实施例提供的第三种阵列基板的结构示意图。
附图标记说明：1—衬底基板；2—第一栅极；3—第一栅极绝缘层；4—N型有源层；5—刻蚀阻挡层；6—过孔；7—源漏极层；8—P型有源层；9—第二栅极绝缘层；10—第二栅极；11—平坦层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板，将现有技术中的CTFT传输门器件结构进行优化，使其能够充分利用现有制程集成制造在阵列基板及其他玻璃、PEN等基板上，从而使其应用更为广泛，并且可以更大程度上降低其应用产品的生产成本。
如图1所示，CTFT作为一种传输门电路结构，经过本发明的优化，其由下至上依次包括：
位于衬底基板1之上的第一栅极2，位于第一栅极2之上的且完全覆盖第一栅极2的第一栅极绝缘层3，位于第一栅极绝缘层3之上的、与第一栅极2相对的N型有源层4，位于N型有源层4之上的绝缘层(在图1所示的实施例中，绝缘层为刻蚀阻挡层5)，位于绝缘层之上的、通过位于绝缘层的过孔6实现与N型有源层4电连接的源漏极层7，位于源漏极层7之上的P型有源层8，位于P型有源层8之上的且完全覆盖P型有源层8的第二栅极绝缘层9，位于第二栅极绝缘层9之上的、与第二栅极10相对的第二栅极10。
显然，在本发明实施例提供的阵列基板中，每一个CTFT包括上下两个TFT，位于下侧的TFT的有源层为N型有源层4，因此为N型TFT；位于上侧的TFT的有源层为P型有源层8，因此为P型TFT。N型有源层4和P型有源层8分别设置在源漏极层7的两侧，共用源漏电极。这个结构与现有技术相比更简单，并且有利于简化CTFT的制备工艺，提高制备的成功率。
进一步的，为了制备上述的阵列基板，本发明实施例还提供了相应的制备方法，具体 可包括如下步骤：
步骤S1、获取衬底基板1。
步骤S2、在衬底基板1之上形成第一栅极2。
步骤S3、在第一栅极2之上形成完全覆盖第一金属层的第一栅极绝缘层3。
步骤S4、在第一栅极绝缘层3之上形成N型有源层4，N型有源层4与第一栅极2相对。
步骤S5、在N型有源层4之上形成绝缘层，对绝缘层进行构图工艺，形成过孔6。
步骤S6、在绝缘层之上形成源漏极层7，源漏极层7通过过孔6实现与N型有源层4的电连接。
步骤S7、在源漏极层7之上形成P型有源层8。
步骤S8、在P型有源层8之上形成完全覆盖P型有源层8的第二栅极绝缘层9。
步骤S9、在第二栅极绝缘层9之上形成与P型有源层8相对的第二栅极10。
考虑到有机材料的不稳定性，以及容易受到环境影响等因素，因此，本专利所述的结构中，尽量把P型TFT的制程放在NTFT制程之后，并采用顶栅底接触的结构，以保证P型TFT器件中的有机半导体的特性不受其制程的影响。
本发明实施例中，绝缘层可仅为如图1所示的一层刻蚀阻挡层5，也可仅为如图3所示的一层平坦层11，还可如图2所示在刻蚀阻挡层5的上方叠加一层平坦层11。
基于绝缘层的三种情况，本发明实施例提供了三种具体的阵列基板及对应的制备方法，具体如下：
如附图1所示，为第一种阵列基板上的CTFT的结构图，其中该CTFT包含顶栅底接触结构的P型TFT和刻蚀阻挡层5结构的N型TFT，其制备方法大致如下：
首先，在衬底基板1上溅射一层栅极金属层(例如利用Mo/Al/Mo、Cu/Ti等材料)，曝光、显影、刻蚀、剥离等步骤后形成第一栅极2，作为N型氧化物TFT的栅电极。本发明实施例中的衬底基板1可利用玻璃、聚萘二甲酸乙二醇酯(PEN)等材质制得。
然后用气相沉积(Chemical Vapor Deposition，简称CVD)或者涂布的方法形成第一栅极绝缘层3。接着，形成一层铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)或者其他N型金属氧化物半导体材料，并同样经过曝光、显影、刻蚀、剥离等步骤后形成N型有源层4。然后，再在其上面形成一层刻蚀阻挡层5，其材料一般可为硅的氮化物 (SiNx)或硅的氧化物(SiOx)，并通过构图工艺在刻蚀阻挡层5上形成与源漏极层7连接的过孔6。
接着，溅射一层源漏电极金属层(例如可为Mo/Al/Mo、Cu/Ti等材料)，经过曝光、显影、刻蚀、剥离后形成源漏极层7，作为N型TFT与P型TFT共用的源漏电极。
然后，制备P型有源层8，即在衬底基板1上涂布一层P型有机半导体材料(例如并五苯等材料)，并通过光刻方法形成P型有源层8的图案；再用CVD或者涂布的方法形成保护层，同时可作为P型TFT的栅极绝缘层，即第二栅极绝缘层9。
最后，用光刻或者蒸镀的方法在第二栅极绝缘层9上面制备成P型TFT的顶栅电极结构，即第二栅极10。至此，图1所示的CTFT传输门结构制备完成，其中省略了后续的电连接制备以及后续的封装保护层制备等描述。
显然，图1所示的阵列基板的CTFT中的绝缘层仅为刻蚀阻挡层5一层结构，对于绝缘层包括刻蚀阻挡层5和平坦层11的结构而言，如图2所示，该CTFT同样包含顶栅底接触结构的P型TFT和刻蚀阻挡层5结构的N型TFT。
图2所示的CTFT的结构为图1的改进结构，为了在P型有源层8旋涂或者涂布时，保证其基底表面的平整性，所以在刻蚀阻挡层5形成之后，再在其表面涂布一层平坦层11，平坦层11的材料一般为有机材料，具有平坦化的作用。然后再对刻蚀阻挡层5和平坦层11一起进行构图工艺，形成供源漏极层7接触N型有源层4的过孔6。
这样，即可保证在源漏极层7形成之后，再旋涂或涂布P型有源层8时，其下表面就是比较平坦的，并且还可以增加P型有源层8与其下表面的附着性，改善其界面性能，也即可优化后续制备的P型TFT的器件性能。
显然，绝缘层还可仅采用一层平坦层11制备，如图3所示，该阵列基板的CTFT同样包含顶栅底接触结构的P型TFT和刻蚀阻挡层结构的N型TFT。图3所示的CTFT的结构为图2的改进结构，图3中的平坦层11既可以作为保护N型有源层4的刻蚀阻挡层，又可以作为改善P型有源层8旋涂或者涂布效果的平坦化层。这样可以节省一道刻蚀阻挡层的制程，节约了阵列基板的制备成本，提高了制备成功率和良品率。
需要说明的是，本申请的N型有源层与P型有源层可进行位置互换，并且也不影响各个实施例记载的技术方案。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖 在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种阵列基板，包括一种传输门结构，所述传输门结构由下至上依次包括：
    位于衬底基板之上的第一栅极，位于所述第一栅极之上的且完全覆盖所述第一栅极的第一栅极绝缘层，位于所述第一栅极绝缘层之上的、与所述第一栅极相对的第一有源层，位于所述第一有源层之上的绝缘层，位于所述绝缘层之上的、通过位于所述绝缘层的过孔实现与所述第一有源层电连接的源漏极层，位于所述源漏极层之上的第二有源层，位于所述第二有源层之上的且完全覆盖所述第二有源层的第二栅极绝缘层，位于所述第二栅极绝缘层之上的、与所述第二栅极相对的第二栅极。
  2. 根据权利要求1所述的阵列基板，其中，所述第一有源层为N型有源层，所述第二有源层为P型有源层。
  3. 根据权利要求1所述的阵列基板，其中，
    所述绝缘层包括刻蚀阻挡层和/或平坦层。
  4. 根据权利要求3所述的阵列基板，其中，当所述绝缘层包括刻蚀阻挡层和平坦层时，所述刻蚀阻挡层位于所述第一有源层之上，所述平坦层位于所述刻蚀阻挡层之上。
  5. 根据权利要求3所述的阵列基板，其中，所述刻蚀阻挡层的材质包括硅的氮化物和/或硅的氧化物。
  6. 一种阵列基板的制备方法，包括如下步骤：
    步骤S1、获取衬底基板；
    步骤S2、在所述衬底基板之上形成第一栅极；
    步骤S3、在所述第一栅极之上形成完全覆盖所述第一金属层的第一栅极绝缘层；
    步骤S4、在所述第一栅极绝缘层之上形成第一有源层，所述第一有源层与所述第一栅极相对；
    步骤S5、在所述第一有源层之上形成绝缘层，对所述绝缘层进行构图工艺，形成过孔；
    步骤S6、在所述绝缘层之上形成源漏极层，所述源漏极层通过所述过孔实现与所述第一有源层的电连接；
    步骤S7、在所述源漏极层之上形成第二有源层；
    步骤S8、在所述第二有源层之上形成完全覆盖所述第二有源层的第二栅极绝缘层；
    步骤S9、在所述第二栅极绝缘层之上形成与所述第二有源层相对的第二栅极。
  7. 根据权利要求6所述的制备方法，其中，所述第一有源层为N型有源层，所述第二有源层为P型有源层；
    所述第一有源层的材质为金属氧化物材料，所述第二有源层的材质为P型有机半导体材料。
  8. 根据权利要求6所述的制备方法，其中，所述绝缘层包括刻蚀阻挡层和/或平坦层。
  9. 根据权利要求8所述的制备方法，其中，当所述绝缘层包括刻蚀阻挡层和平坦层时，所述步骤S5包括：
    步骤S51、在所述第一有源层之上形成覆盖所述第一有源层的刻蚀阻挡层；
    步骤S52、在所述刻蚀阻挡层之上形成覆盖所述刻蚀阻挡层的平坦层；
    步骤S53、对所述刻蚀阻挡层和所述平坦层进行构图工艺，形成贯穿所述平坦层和所述刻蚀阻挡层的过孔。
  10. 根据权利要求8所述的制备方法，其中，所述刻蚀阻挡层的材质包括硅的氮化物和/或硅的氧化物。
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