CN110148600A - 阵列基板及制备方法 - Google Patents

阵列基板及制备方法 Download PDF

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CN110148600A
CN110148600A CN201910368677.3A CN201910368677A CN110148600A CN 110148600 A CN110148600 A CN 110148600A CN 201910368677 A CN201910368677 A CN 201910368677A CN 110148600 A CN110148600 A CN 110148600A
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layer
array substrate
film transistor
transistor
metal oxide
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方俊雄
吴元均
吕伯彦
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of CN110148600A publication Critical patent/CN110148600A/zh
Priority to PCT/CN2019/102163 priority patent/WO2020224095A1/zh
Priority to US16/616,980 priority patent/US11355519B2/en
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Abstract

本发明提供一种阵列基板及制备方法，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。

Description

阵列基板及制备方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及制备方法。
背景技术
低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管是两种不同类型的薄膜晶体管，各有各的优点，例如低温多晶硅薄膜晶体管具有高载子迁移率,高稳定性,适合用于显示器的驱动电路，而金属氧化物半导体薄膜晶体管则具有较好的电性均匀性以及极低的关态漏电流,适合用于显示器的像素电路。
但是由于这两种薄膜晶体管对工作环境的要求不同，例如是否需要氢离子的不同等，不能长时间的工作于同一环境下，例如不能在同一显示面板中长时间稳定工作。
所以，现有技术存在不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题，需要改进。
发明内容
本发明提供一种阵列基板及制备方法，以缓解现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种阵列基板，其包括：
衬底；
形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
在本发明实施例提供的阵列基板中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
在本发明实施例提供的阵列基板中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
在本发明实施例提供的阵列基板中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
在本发明实施例提供的阵列基板中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层，所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
在本发明实施例提供的阵列基板中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
在本发明实施例提供的阵列基板中，所述缓冲层的材料为氧化硅。
在本发明实施例提供的阵列基板中，所述阵列基板还包括存储电容；
所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
在本发明实施例提供的阵列基板中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
本发明实施例还提供一种阵列基板制备方法，其包括；
提供衬底；
制备薄膜晶体管和氢离子薄膜；其中，所述薄膜晶体管包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，所述氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间、且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
本发明的有益效果为：本发明提供一种阵列基板及制备方法，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的阵列基板的结构示意图。
图2至图10为本发明实施例提供的阵列基板的制备示意图。
具体实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
在附图中，为了清楚表示器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
针对现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题，本发明实施例可以缓解。
在一种实施例中，如图1所示，本发明实施例提供的阵列基板10包括：
衬底M100；
形成于所述衬底M100上方的低温多晶硅薄膜晶体管200和金属氧化物半导体薄膜晶体管300；以及
氢离子薄膜400，形成于所述低温多晶硅薄膜晶体管200的有源层201和源漏极层203之间，且在所述金属氧化物半导体薄膜晶体管300的设置区域内形成开孔。
在低温多晶硅薄膜晶体管的制备工艺中,非晶硅并非完美的结晶,硅薄膜内部有许多硅空隙(Si vacancy)、晶界(grain boundary boundary)、缺排(dislocation)等缺陷,这些缺陷将严重影响薄膜晶体管的电气特性和稳定性，针对该缺陷，本发明实施例在多晶硅薄膜的上下方沉积含有大量的氢元素【H】的氢离子薄膜，如氮化硅(SiNx-H)薄膜,在后续的高温工艺中,氢元素将会扩散到多晶硅薄膜薄膜内与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性。
但是对于金属氧化物半导体薄膜晶体管而言,氢原子同样会扩散到金属氧化物薄膜内(例如铟镓锌氧化物等)，还原金属氧化物产生氧空穴,而氧空穴会影响金属氧化物半导体薄膜晶体管的导电性,导致金属氧化物电气特性偏移,针对此问题，本发明实施例中的氢离子薄膜在金属氧化物半导体薄膜晶体管的设置区域内形成开孔，金属氧化物半导体薄膜晶体管周围并无氮化硅等氢离子薄膜,可以确保金属氧化物主动层(即有源层)不会受到氢原子影响而改变金属氧化物半导体薄膜晶体管电气特性。
本实施例提供了一种阵列基板，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述阵列基板10包括位于所述低温多晶硅薄膜晶体管200的有源层201和栅极202之间的第一绝缘层500，所述第一绝缘层500包括层叠设置的第一氧化硅层M103和第一氮化硅层M104，所述第一氮化硅层M104图案化形成所述氢离子薄膜400中的第一氢离子薄膜。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述阵列基板10包括位于所述低温多晶硅薄膜晶体管200的栅极202和源漏极层203之间的第二绝缘层600，所述第二绝缘层600包括第二氧化硅层M108和第二氮化硅层M109，所述第二氮化硅层M109图案化形成所述氢离子薄膜400中的第二氢离子薄膜。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述第二氧化硅层M108设置于所述金属氧化物半导体薄膜晶体管300的栅极301和有源层302之间。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述阵列基板10包括形成于所述衬底上的缓冲层M101、以及位于所述低温多晶硅薄膜晶体管200的栅极202和所述第二绝缘层600之间的第三绝缘层M106，所述第一氧化硅层M103和所述第三绝缘层M106叠层设置于所述缓冲层M101和所述金属氧化物半导体薄膜晶体管300的栅极301之间。
在一种实施例中，所述第三绝缘层M106的材料为氧化硅，以降低材料复杂度。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述低温多晶硅薄膜晶体管200的有源层201设置在所述缓冲层上M101。
在一种实施例中，在本发明实施例提供的阵列基板中，所述缓冲层M101的材料为氧化硅，以降低材料复杂度。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述阵列基板10还包括存储电容700；
所述存储电容700的第一电极板701与所述低温多晶硅薄膜晶体管200的栅极202同层设置，所述存储电容700的第二电极板702与所述金属氧化物半导体薄膜晶体管300的栅极301同层设置。
在一种实施例中，如图1所示，在本发明实施例提供的阵列基板中，所述阵列基板10还包括保护层M112；所述第一氧化硅层M103和所述第一氮化硅层M104设置于所述缓冲层M101和所述存储电容700的第一电极板701之间，所述第三绝缘层M106设置于所述存储电容700的第一电极板701和第二电极板702之间，所述第二氧化硅层M108和所述第二氮化硅层M109设置于所述存储电容700的第二电极板702和所述保护层M112之间。
在一种实施例中，在本发明实施例提供的阵列基板中，所述保护层M112的材料为氧化硅，以降低材料复杂度。
在一种实施例中，多晶硅层M102图案化形成低温多晶硅薄膜晶体管200的有源层201。
在一种实施例中，第一金属层M105图案化形成低温多晶硅薄膜晶体管200的栅极202、以及存储电容700的第一电极板701。
在一种实施例中，第二金属层M107图案化形成存储电容700的第二电极板702、以及金属氧化物半导体薄膜晶体管300的栅极301。
在一种实施例中，第一金属层M105和第二金属层M107的材料为铜、或者钛铝钛合金等。
在一种实施例中，金属氧化物层M110图案化形成金属氧化物半导体薄膜晶体管300的有源层302。
在一种实施例中，源漏极层M111图案化形成低温多晶硅薄膜晶体管200的源漏极203、以及金属氧化物半导体薄膜晶体管300的源漏极303。
在一种实施例中，本发明还提供了一种显示装置，该显示装置包括显示面板，该显示面板的阵列基板包括：
衬底；
形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
在一种实施例中，在本发明实施例提供的显示装置中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
在一种实施例中，在本发明实施例提供的显示装置中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
在一种实施例中，在本发明实施例提供的显示装置中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
在一种实施例中，在本发明实施例提供的显示装置中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层，所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
在一种实施例中，在本发明实施例提供的显示装置中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
在一种实施例中，在本发明实施例提供的显示装置中，所述缓冲层的材料为氧化硅。
在一种实施例中，在本发明实施例提供的显示装置中，所述阵列基板还包括存储电容；
所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
在一种实施例中，在本发明实施例提供的显示装置中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
在一种实施例中，在本发明实施例提供的显示装置中，所述显示面板为液晶显示面板或者OLED显示面板。
为了制备得到上述实施例中的阵列基板，本发明实施例还提供了一种阵列基板制备方法，该阵列基板制备方法包括以下步骤：
步骤一、提供衬底，如玻璃板、透明柔性基材等；
步骤二、制备薄膜晶体管和氢离子薄膜；其中，所述薄膜晶体管包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，所述氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间、且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
本实施例提供了一种阵列基板制备方法，其得到的阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
在一种实施例中，本发明实施例提供的阵列基板制备方法包括以下步骤：
步骤A、在衬底M100上沉积氧化硅薄膜作为缓冲层M101，并在缓冲层M101上方沉积非晶硅薄膜，使用高温去除非晶硅薄膜内的氢原子，经过清洗制程清洁非晶硅薄膜表面,使用激光将非晶硅薄膜结晶为多晶硅层M102。采用黄光、蚀刻制程制作多晶硅硅岛201，去除光阻后,使用离子注入等制程调节薄膜晶体管的阈值电压；再次使用黄光制程定义出沟道区域与源极区域和漏极区域，利用离子注入等制程制作重掺杂的源极区域和漏极区域，去除光阻。
执行本步骤A之后，得到如图2所示的结构。
步骤B、在多晶硅硅岛201上方沉积栅极绝缘层(即上文中的第一绝缘层500)，栅极绝缘层由下往上依序包含第一氧化硅层M103以及第一氮化硅层M104两层薄膜。
执行本步骤B之后，得到如图3所示的结构。
步骤C、在栅极绝缘层上方沉积第一金属层M105，并使用黄光/蚀刻制程定义出所需要的第一金属层图案，包括栅极202和第一电极板701。在蚀刻第一金属层同时,调节干式蚀刻的工艺参数，将的第一金属层图案底下以外的第一氮化硅层M104蚀刻去除，去除光阻。
执行本步骤C之后，得到如图4所示的结构。
步骤D、在制作好的第一金属层图案上方沉积氧化硅层作为储存电容700两个电极板中间的介电夹层(即上文中的第三绝缘层M106)。
执行本步骤D之后，得到如图5所示的结构。
步骤E、在介电夹层上方沉积第二金属层M107，并使用黄光/蚀刻工艺定义出第二金属层图案，包括第二电极板702和栅极301，去除光阻。
执行本步骤E之后，得到如图6所示的结构。
步骤F、在第二金属层图案上方依序沉积第二氧化硅层M108以及第二氮化硅层M109两层介电层(即上文中的第二绝缘层600)，此介电层位于栅极202与源漏极金属层M111之间。
执行本步骤F之后，得到如图7所示的结构。
步骤G、使用灰阶光罩制作出图8的光阻图案，第一部分为连结多晶硅的过孔，此部份将过孔的光阻全部曝光/显影去除。第二部分为栅极301上方的光阻,此部份是灰阶光罩的区域,只将部分厚度的光阻去除。
执行本步骤G之后，得到如图8所示的结构。
步骤H、将图8制作好光阻的阵列基板进行干式蚀刻，将有源层201的过孔蚀刻开，同时也将金属氧化物半导体薄膜晶体管上方的第二氮化硅层M109蚀刻去除，去除光阻。
执行本步骤H之后，得到如图9所示的结构。
步骤I、在图9的结构上沉积金属氧化物薄膜(IGZO)层M110，并使用黄光/蚀刻制程定义出氧化物金属主动层的图案,去除光阻后在上方沉积源漏极金属层M111,并使用黄光/蚀刻制程定义出源漏极图案(包括源漏极203和源漏极303)，去除光阻后在源漏极图案上方沉积氧化硅层作为保护层M112。
执行本步骤I之后，得到如图10所示的结构。
如此薄膜晶体管器件结构已经完成，后续上方可以依据OLED或是LCD显示器的需求制作不同的结构在此不赘述。
根据上述实施例可知：
本发明实施例提供一种阵列基板及制备方法，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种阵列基板，其特征在于，包括：
衬底；
形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
2.如权利要求1所述的阵列基板，其特征在于，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
3.如权利要求2所述的阵列基板，其特征在于，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
4.如权利要求3所述的阵列基板，其特征在于，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
5.如权利要求3所述的阵列基板，其特征在于，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层；所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
6.如权利要求5所述的阵列基板，其特征在于，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
7.如权利要求5所述的阵列基板，其特征在于，所述缓冲层的材料为氧化硅。
8.如权利要求5所述的阵列基板，其特征在于，所述阵列基板还包括存储电容；
所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
9.如权利要求8所述的阵列基板，其特征在于，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
10.一种阵列基板制备方法，其特征在于，包括；
提供衬底；
制备薄膜晶体管和氢离子薄膜；其中，所述薄膜晶体管包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，所述氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间、且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
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