WO2016155215A1 - 阵列基板的制造方法及制造装置 - Google Patents

阵列基板的制造方法及制造装置 Download PDF

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WO2016155215A1
WO2016155215A1 PCT/CN2015/087920 CN2015087920W WO2016155215A1 WO 2016155215 A1 WO2016155215 A1 WO 2016155215A1 CN 2015087920 W CN2015087920 W CN 2015087920W WO 2016155215 A1 WO2016155215 A1 WO 2016155215A1
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gate
pattern
photoresist pattern
sub
gate photoresist
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PCT/CN2015/087920
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English (en)
French (fr)
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黄建邦
詹裕程
刘建宏
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京东方科技集团股份有限公司
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Priority to US14/905,733 priority Critical patent/US9893165B2/en
Publication of WO2016155215A1 publication Critical patent/WO2016155215A1/zh

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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of metal oxide semiconductor technology, and in particular, to a method and a device for manufacturing an array substrate.
  • the metal oxide semiconductor In the process of fabricating a metal oxide semiconductor array substrate, the metal oxide semiconductor generates a hot electron effect as the channel length decreases, causing a large leakage current, lowering the electrical properties of the metal oxide semiconductor, and affecting the metal oxide. The manufacturing effect of the semiconductor array substrate. Therefore, it is necessary to suppress the leakage current.
  • the leakage current is mainly suppressed by controlling the length of the lightly doped drain (English: Lightly Doped Drain; LDD).
  • the LDD is located in the active layer of the array substrate and is located below the gate.
  • the length of the LDD is determined by the gate line width.
  • the length of the LDD can be controlled by lengthening or shortening the exposure time of the LDD, or the gate line width can be controlled by extending or shortening the time of etching the gate, thereby controlling the length of the LDD, and finally achieving the purpose of suppressing leakage current. .
  • the etching gate needs to consider the calculation accuracy and stability of the gate line width. Meanwhile, when the gate line width is determined, the LDD length is also determined, so that the LDD can no longer be used. The length is modulated; on the other hand, the two processes of exposing the LDD and etching the gate cannot be performed simultaneously, and the conditional requirements for controlling the gate line width and the condition requirements for controlling the length of the LDD are mutually constrained, and it is necessary to sacrifice one of the condition requirements.
  • the embodiment of the present invention provides a method and a device for manufacturing an array substrate.
  • the technical solution is as follows:
  • a method of fabricating an array substrate comprising:
  • An active layer, a gate insulating layer, and a gate metal layer are sequentially formed on the substrate, the active
  • the layer includes a plurality of active layer sub-patterns
  • a gate pattern with a gate photoresist pattern on a substrate on which the gate metal layer is formed the gate pattern including a plurality of gate sub-patterns formed from the gate metal layer, the gate
  • the pole photoresist pattern includes a plurality of gate photoresist sub-patterns, a width of each of the gate photoresist patterns in the gate photoresist pattern being greater than a width of each of the gate patterns in the gate pattern;
  • the length of each of the LDDs is (ab)/2, where a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b Is the width of the gate sub-pattern in the gate pattern;
  • the changed gate photoresist pattern is stripped.
  • the step of changing a temperature of the gate photoresist pattern to change a width of a gate photoresist sub-pattern in the gate photoresist pattern comprises:
  • the gate photoresist pattern is subjected to heat treatment to lengthen the width of the gate photoresist pattern in the gate photoresist pattern.
  • the step of changing a temperature of the gate photoresist pattern to change a width of a gate photoresist sub-pattern in the gate photoresist pattern comprises:
  • the method before changing the temperature of the gate photoresist pattern to change the width of the gate photoresist sub-pattern in the gate photoresist pattern, the method further includes:
  • the step of changing a temperature of the gate photoresist pattern to change a width of a gate photoresist sub-pattern in the gate photoresist pattern comprises:
  • the method before changing the temperature of the gate photoresist pattern to change the width of the gate photoresist sub-pattern in the gate photoresist pattern, the method further includes:
  • the step of changing a temperature of the gate photoresist pattern to change a width of a gate photoresist sub-pattern in the gate photoresist pattern comprises:
  • the temperature of the gate photoresist pattern is changed to vary the width of the gate photoresist pattern in the gate photoresist pattern.
  • the step of forming a gate pattern with a gate photoresist pattern on a substrate on which the gate metal layer is formed includes:
  • a gate metal layer formed with the gate photoresist pattern is formed into the gate pattern by an etching process.
  • the method further includes:
  • a buffer layer is formed on the substrate.
  • the photoresist is any one of organic resin materials of the types DL-1000, DL-1000C, and DTFR-JCW702.
  • a device for manufacturing an array substrate includes:
  • a first forming unit configured to sequentially form an active layer, a gate insulating layer and a gate metal layer on the substrate, the active layer comprising a plurality of active layer sub-patterns;
  • a second forming unit configured to form a gate pattern with a gate photoresist pattern on the substrate on which the gate metal layer is formed, the gate pattern including a plurality of gates formed from the gate metal layer a pole pattern, the gate photoresist pattern comprising a plurality of gate photoresist sub-patterns, each gate photoresist pattern in the gate photoresist pattern having a width greater than each of the gate patterns The width of the gate sub-pattern;
  • a temperature processing unit configured to change a temperature of the gate photoresist pattern to change a width of a gate photoresist sub-pattern in the gate photoresist pattern
  • a third forming unit configured to form a lightly doped drain LDD on both sides of a predetermined region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed, the predetermined region For the projection sub-pattern of the active layer sub-pattern, the length of each of the LDDs is (ab)/2, where a is the gate lithography in the changed gate photoresist pattern The width of the glue pattern, b is the width of the gate sub-pattern in the gate pattern;
  • a stripping unit for stripping the changed gate photoresist pattern.
  • the temperature processing unit includes:
  • a heat treatment sub-unit for heating the gate photoresist pattern to make the width of the gate photoresist pattern in the gate photoresist pattern longer.
  • the temperature processing unit includes:
  • a cold processing sub-unit for performing a temperature lowering process on the gate photoresist pattern to shorten a width of a gate photoresist sub-pattern in the gate photoresist pattern.
  • the manufacturing apparatus of the array substrate further includes:
  • An acquiring unit configured to acquire a thermal expansion and contraction coefficient of the gate photoresist pattern
  • a first determining unit configured to determine a length of the LDD that needs to be obtained
  • a second determining unit configured to determine a photoresist processing temperature according to a thermal expansion and contraction coefficient of the gate photoresist pattern and a length of the LDD required to be obtained;
  • the temperature processing unit includes:
  • a first processing sub-unit for processing the gate photoresist pattern by using the photoresist processing temperature to change a width of a gate photoresist sub-pattern in the gate photoresist pattern.
  • the manufacturing apparatus of the array substrate further includes:
  • a third determining unit configured to determine a processing duration according to a thermal expansion and contraction coefficient of the gate photoresist pattern and a length of the LDD required to be obtained;
  • the temperature processing unit includes:
  • a second processing sub-unit configured to change a temperature of the gate photoresist pattern during the processing duration to change a width of the gate photoresist pattern.
  • the second forming unit comprises:
  • a first forming sub-unit for sequentially forming the gate photoresist pattern on a substrate on which the gate metal layer is formed by a coating process, an exposure process, and a developing process;
  • a second forming sub-unit for forming the gate metal pattern by forming a gate metal layer of the gate photoresist pattern by an etching process is a second forming sub-unit for forming the gate metal pattern by forming a gate metal layer of the gate photoresist pattern by an etching process.
  • the manufacturing apparatus of the array substrate further includes:
  • a fourth forming unit for forming a buffer layer on the substrate.
  • Embodiments of the present invention provide a method and a manufacturing apparatus for fabricating an array substrate, and forming a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, by changing a temperature of a gate photoresist pattern Varying the width of the gate photoresist sub-pattern in the gate photoresist pattern, and then on both sides of the predetermined region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed Forming an LDD that satisfies the length requirement, and controlling the length of the LDD, the method for controlling the length of the LDD compared to the manufacturing method of the existing array substrate does not need to satisfy both the condition of the gate line width and the condition of the LDD length. Increased control flexibility and feasibility for LDD length.
  • 1-1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention
  • 1-2 is a schematic diagram of a gate photoresist pattern width direction and a gate pattern width direction of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a flow chart of a method of fabricating an array substrate according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural view of forming a buffer layer on a substrate according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural view of forming an amorphous silicon film on a substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of forming an active layer photoresist on a substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of forming an active layer on a substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of forming a gate insulating layer on a substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural view of forming a gate metal layer on a substrate according to an embodiment of the present invention.
  • FIG. 9 is a flow chart of a method of forming a gate pattern with a gate photoresist pattern according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural view of forming a gate photoresist pattern on a substrate according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of forming a gate pattern on a substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a width variation of a gate photoresist sub-pattern in a gate photoresist pattern according to an embodiment of the present invention
  • FIG. 13 is a schematic structural diagram of a length change of a single-sided LDD according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a length distribution of an LDD according to an embodiment of the present invention.
  • 15 is a schematic structural diagram of an apparatus for manufacturing an array substrate according to an embodiment of the present invention.
  • 16 is a schematic structural diagram of a temperature processing unit according to an embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram of a temperature processing unit according to another embodiment of the present invention.
  • FIG. 18 is a schematic structural diagram of a second forming unit according to an embodiment of the present invention.
  • FIG. 19 is a schematic structural diagram of an apparatus for manufacturing an array substrate according to another embodiment of the present invention.
  • FIG. 20 is a schematic structural diagram of a temperature processing unit according to another embodiment of the present invention.
  • FIG. 21 is a schematic structural diagram of a temperature processing unit according to still another embodiment of the present invention.
  • the embodiment of the invention provides a method for manufacturing an array substrate. As shown in FIG. 1-1, the method may include:
  • Step 001 sequentially forming an active layer, a gate insulating layer and a gate metal layer on the substrate, the active layer comprising a plurality of active layer sub-patterns.
  • Step 002 forming a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, the gate pattern including a plurality of gate sub-patterns formed from the gate metal layer,
  • the gate photoresist pattern includes a plurality of gate photoresist sub-patterns, the gate lithography
  • the width of each of the gate photoresist sub-patterns in the glue pattern is greater than the width of each of the gate sub-patterns in the gate pattern.
  • Step 003 changing a temperature of the gate photoresist pattern to change a width of a gate photoresist sub-pattern in the gate photoresist pattern.
  • Step 004 forming a lightly doped drain LDD on both sides of a predetermined region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed, the predetermined region being a gate sub-pattern
  • the length of each LDD is (ab)/2, where a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, and b is the gate pattern The width of the gate sub-pattern in .
  • Step 005 peeling off the changed gate photoresist pattern.
  • the method for fabricating an array substrate forms a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, by changing the temperature of the gate photoresist pattern. Varying the width of the gate photoresist sub-pattern in the gate photoresist pattern, and then forming on both sides of a predetermined region of the active layer sub-pattern of the active layer of the substrate on which the changed gate photoresist pattern is formed The length of the LDD is controlled to meet the length requirement, and the length of the LDD is controlled. Compared with the method for controlling the LDD length of the existing array substrate manufacturing method, it is not necessary to simultaneously satisfy the condition of the gate line width and the condition of the LDD length, thereby improving The flexibility and feasibility of controlling the length of the LDD.
  • the width direction of the gate photoresist sub-pattern 301 in the gate photoresist pattern in step 002 is as shown in FIG. 1-2.
  • the width direction of the gate sub-pattern 3000 of the gate pattern The direction from the source 121 to the drain 122 on the array substrate, respectively parallel. 123 in Figure 1-2 is LDD.
  • the step 003 may include: heating the gate photoresist pattern to make the width of the gate photoresist pattern in the gate photoresist pattern longer.
  • Step 003 may further include: cooling the gate photoresist pattern to shorten the width of the gate photoresist pattern in the gate photoresist pattern.
  • the method may further include: acquiring a thermal expansion and contraction coefficient of the gate photoresist pattern; determining a length of the LDD to be obtained; according to a thermal expansion and contraction coefficient of the gate photoresist pattern and an LDD required to be obtained Length, determines the photoresist processing temperature.
  • step 003 can include: processing the gate photoresist pattern with a photoresist processing temperature to change a width of a gate photoresist sub-pattern in the gate photoresist pattern.
  • the method may further include: according to the heat of the gate photoresist pattern The expansion and contraction coefficient and the length of the LDD that needs to be obtained determine the processing time.
  • step 003 can include: changing a temperature of the gate photoresist pattern during the processing duration to change a width of a gate photoresist sub-pattern in the gate photoresist pattern.
  • the step 002 may specifically include: sequentially forming a gate photoresist pattern on the substrate on which the gate metal layer is formed by a coating process, an exposure process, and a developing process; and forming a gate metal formed with a gate photoresist pattern by an etching process The layer forms a gate pattern.
  • the method may further include: forming a buffer layer on the substrate.
  • the photoresist may be any of organic resin materials of the types DL-1000, DL-1000C, and DTFR-JCW702.
  • the method for fabricating an array substrate forms a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, by changing a gate photoresist pattern. a temperature that changes a width of a gate photoresist pattern in the gate photoresist pattern, and then on both sides of a predetermined region of the active layer sub-pattern of the active layer of the substrate on which the changed gate photoresist pattern is formed.
  • the method for controlling the length of the LDD compared to the manufacturing method of the existing array substrate does not need to satisfy both the condition of the gate line width and the condition of the LDD length. Increased control flexibility and feasibility for LDD length.
  • Another embodiment of the present invention provides another method for fabricating an array substrate, which is described by taking a low temperature polycrystalline silicon thin film transistor (LTPS TFT) as an example.
  • the LTPS TFT can be used for the LTPS TFT.
  • An active matrix organic light emitting diode (English: Active Matrix Organic Light Emitting Diode; AMOLED) display and a thin film transistor liquid crystal display (English: Thin Film Transistor Liquid Crystal Display; referred to as: TFT LCD) backplane.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • TFT LCD Thin Film Transistor Liquid Crystal Display
  • the method according to this embodiment may include:
  • Step 201 forming a buffer layer on the substrate.
  • a substrate 100 made of a transparent material such as glass is subjected to a cleaning treatment, and a buffer layer 101 is formed on the substrate 100 by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer 101 may be a single layer or a composite layer formed of silicon oxide or silicon nitride.
  • the thickness of the silicon oxide may be 50-100 nm, and the thickness of the silicon nitride may be 100-300 nm.
  • Step 202 sequentially forming an active layer, a gate insulating layer and a gate metal layer on the substrate.
  • an amorphous silicon is formed (English: amorphous-silicon; referred to as: A-si) film 102, the amorphous silicon film may have a thickness of 40-50 nm, and a schematic structural view of forming amorphous silicon film 102 is shown in FIG. 4. Then, the substrate is sent to a high-temperature furnace for treatment to achieve dehydrogenation (reducing the content of hydrogen in the amorphous silicon film), and the hydrogen content can be controlled within 2%.
  • A-si amorphous-silicon
  • the substrate is subjected to excimer laser annealing (ELA) treatment to convert the amorphous silicon film 102 into a polysilicon film 1020, and then an active layer photoresist is formed by exposure and development. As shown in Figure 5.
  • ELA excimer laser annealing
  • the polysilicon film 1020 is etched by etching, and the active layer photoresist 103 is stripped by a stripping liquid to form an active layer including a plurality of active layer sub-patterns 1021, as shown in FIG.
  • the gate insulating layer 200 is deposited by PECVD, and the structure of the gate insulating layer 200 is shown in FIG. Then, a gate metal layer 300 is formed on the gate insulating layer 200 by sputtering, as shown in FIG.
  • Step 203 forming a gate pattern with a gate photoresist pattern on the substrate on which the gate metal layer is formed.
  • step 203 may include:
  • Step 2031 forming a gate photoresist pattern on the substrate on which the gate metal layer is formed by a coating process, an exposure process, and a development process in sequence.
  • a gate photoresist pattern is sequentially formed by a coating process, an exposure process, and a development process, and the gate photoresist pattern includes a plurality of gate photoresist sub-patterns 301, such as Figure 10 shows.
  • Step 2032 forming a gate pattern by forming a gate metal layer with a gate photoresist pattern by an etching process.
  • the gate metal layer 300 in FIG. 10 is etched by an etching process to form a gate pattern including the multi-gate sub-pattern 3000, as shown in FIG.
  • Step 204 Obtain a thermal expansion and contraction coefficient of the gate photoresist pattern.
  • the thermal expansion and contraction coefficient of the gate photoresist pattern is obtained.
  • the method for obtaining the thermal expansion and contraction coefficient of the gate photoresist pattern is not limited in the embodiment of the present invention.
  • Step 205 Determine the length of the LDD that needs to be obtained.
  • the specific length of the final LDD is determined according to manufacturing requirements.
  • Step 206 according to the thermal expansion and contraction coefficient of the gate photoresist pattern and the required LDD
  • the length determines at least one of a photoresist processing temperature and a processing duration.
  • the relationship between the thermal expansion and contraction coefficient of the gate photoresist pattern, the length of the LDD to be obtained, the photoresist processing temperature, and the processing duration can be calculated according to the formula, or according to the existing The form is directly obtained, which is not limited by the embodiment of the present invention. It is assumed that the thermal expansion and contraction coefficient of the gate photoresist pattern, the correspondence between the length of the required LDD and the photoresist processing temperature, and the processing duration are in a table, as shown in Table 1, from Table 1.
  • the constituent material of the gate photoresist pattern is A
  • the thermal expansion and contraction coefficient is x1
  • the required LDD length is c1
  • the corresponding photoresist processing temperature is 150 ° C
  • the processing time is 15 minute.
  • the constituent material of the gate photoresist pattern may be a type of photoresist such as DL-1000, DL-1000C or DTFR-JCW702.
  • the sensitivity of the photoresist is high, and the gate lithography is changed.
  • the width of the gate photoresist pattern in the gate photoresist pattern can be changed faster, thereby facilitating the control of the length of the LDD and reducing the complexity of the entire process.
  • Step 207 changing the temperature of the gate photoresist pattern to change the width of the gate photoresist pattern in the gate photoresist pattern.
  • the photoresist processing temperature may be determined according to the thermal expansion and contraction coefficient of the gate photoresist pattern and the length of the LDD to be obtained.
  • Step 207 may include: processing the temperature processing gate with the photoresist. a pole photoresist pattern that varies the width of the gate photoresist pattern in the gate photoresist pattern; in another embodiment, the thermal expansion and contraction coefficient of the gate photoresist pattern and the length of the LDD required can be obtained
  • Determining the processing duration step 207 may include: changing the temperature of the gate photoresist pattern during the processing duration Degree, the width of the gate photoresist pattern in the gate photoresist pattern is changed; in still another embodiment, the light can be determined according to the thermal expansion and contraction coefficient of the gate photoresist pattern and the length of the LDD required.
  • the etch processing temperature and the processing duration the step 207 may include: processing the gate photoresist pattern by using the photoresist processing temperature to make the gate photoresist pattern in the gate photoresist
  • the gate photoresist pattern when the constituent material of the gate photoresist pattern is A, the gate photoresist pattern can be processed by the photoresist processing temperature (ie, 150 ° C) for 15 minutes to make the gate light in the gate photoresist pattern.
  • the photoresist processing temperature ie, 150 ° C
  • the width of the engraved glue pattern changes.
  • the width of the gate photoresist pattern of the gate photoresist pattern may need to be widened or narrowed, when the width of the gate photoresist pattern in the gate photoresist pattern needs to be widened.
  • the width of the gate photoresist pattern in the gate photoresist pattern can be widened by the principle of thermal expansion; when the width of the gate photoresist pattern needs to be narrowed, the gate photoresist pattern can be made by the principle of cold shrinkage.
  • the width of the gate photoresist pattern is narrowed. Therefore, the step 207 may include: heating the gate photoresist pattern to widen the width of the gate photoresist pattern in the gate photoresist pattern.
  • the temperature during the heat treatment may range from 150 to 200 ° C.
  • step 207 may include: cooling the gate photoresist pattern to narrow the width of the gate photoresist pattern in the gate photoresist pattern.
  • the temperature range during the temperature reduction treatment may be -30 to -40 °C. In one embodiment, it can be considered that when the photoresist processing temperature is less than -30 ° C, the gate photoresist pattern is cooled, and when the photoresist processing temperature is greater than 150 ° C, the gate photoresist pattern is performed.
  • Heat treatment. The heating time is about 10 to 20 minutes, and the cooling time can be about 10 to 20 minutes.
  • Figure 12 is a structural diagram showing the variation of the width of the gate photoresist sub-pattern 301 in the gate photoresist pattern by changing the temperature of the gate photoresist pattern.
  • FIG. 12 when the gate photoresist pattern is subjected to a temperature lowering process, the width of the gate photoresist sub-pattern 301 in the gate photoresist pattern is narrowed, and the gate light in the narrowed gate photoresist pattern is reduced.
  • the marking of the engraved sub-pattern is 302; when the gate photoresist pattern is heat-treated, the width of the gate photoresist sub-pattern 301 in the gate photoresist pattern is widened, and the gate photoresist pattern is widened.
  • the gate photoresist pattern is identified as 303.
  • the length of the one-sided LDD is c, when the gate photoresist in the gate photoresist pattern is The gate photoresist in the gate photoresist pattern when the pattern 301 is subjected to the temperature lowering process
  • the width of the sub-pattern 301 is narrowed, and the identification of the gate photoresist sub-pattern in the narrowed gate photoresist pattern is 302, and correspondingly, the length of the one-sided LDD becomes c1; when in the gate photoresist pattern
  • the width of the gate photoresist pattern 301 in the gate photoresist pattern is widened, and the identifier of the gate photoresist pattern in the gate photoresist pattern is widened.
  • the length of the one-sided LDD becomes c2.
  • the N+ doping in Fig. 13 refers to an N-type (electron type) high concentration doping.
  • 3000 in Fig. 13 is a gate sub-pattern in the gate pattern, and 200 is a gate insulating layer.
  • Step 208 forming an LDD on both sides of a preset region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed.
  • the predetermined area is a projection area of the gate sub-pattern in the gate pattern in the active layer sub-pattern, and each LDD has a length of (ab)/2, wherein a is a changed gate photoresist pattern
  • the width of the gate photoresist sub-pattern 302 or 303, b is the width of the gate sub-pattern 3000 of the gate pattern.
  • Step 209 stripping the changed gate photoresist pattern.
  • the stripping operation is performed, and the changed photoresist is peeled off.
  • the length distribution of the LDD is as shown in FIG. 14, c is the length of the one-sided LDD when the gate photoresist pattern is not processed, and c1 is the temperature drop.
  • the length of the one-sided LDD after processing the gate photoresist pattern, and c2 is the length of the one-sided LDD after heat processing the gate photoresist pattern.
  • 3000 in Fig. 14 is a gate sub-pattern in the gate pattern, and 200 is a gate insulating layer.
  • the internal dielectric layer, the internal dielectric photoresist, the source and drain layers, the source and drain layer photoresist, the flat layer and the pixel can be continuously formed.
  • the electrode layer and the like reference may be made to the prior art, and the embodiments of the present invention are not described herein again.
  • the identifiers not illustrated in the structural schematic diagram corresponding to each step in this embodiment may refer to the identifiers already described in the prior art schematic diagram.
  • 100 in FIG. 4 indicates the substrate 100 in FIG. 3
  • 101 in FIG. 4 indicates the buffer layer 101 in FIG.
  • the method for manufacturing the array substrate provided by the embodiment of the invention can not affect the gate line
  • the length of the LDD is controlled; the length of the LDD can be controlled according to the condition of the gate etching; when the line width is too large or too small after the gate is etched, according to the actual situation after the gate etching, The relative length of the LDD is controlled by changing the temperature of the gate photoresist pattern.
  • the method for fabricating an array substrate forms a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, by changing the temperature of the gate photoresist pattern. Varying the width of the gate photoresist sub-pattern in the gate photoresist pattern; then forming on both sides of the predetermined region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed.
  • the length of the LDD is controlled to meet the length requirement, and the length of the LDD is controlled. Compared with the method for controlling the LDD length of the existing array substrate manufacturing method, it is not necessary to simultaneously satisfy the condition of the gate line width and the condition of the LDD length, thereby improving The flexibility and feasibility of controlling the length of the LDD.
  • the manufacturing apparatus 1500 may include:
  • the first forming unit 1501 is configured to sequentially form an active layer, a gate insulating layer and a gate metal layer on the substrate, and the active layer includes a plurality of active layer sub-patterns.
  • a second forming unit 1502 configured to form a gate pattern with a gate photoresist pattern on the substrate formed with the gate metal layer, the gate pattern comprising a plurality of gate sub-patterns formed from the gate metal layer
  • the gate photoresist pattern includes a plurality of gate photoresist sub-patterns, a width of each of the gate photoresist patterns in the gate photoresist pattern being greater than each of the gate sub-patterns in the gate pattern width.
  • the temperature processing unit 1503 is configured to change the temperature of the gate photoresist pattern to change the width of the gate photoresist pattern in the gate photoresist pattern.
  • a third forming unit 1504 configured to form a lightly doped drain LDD on both sides of a predetermined region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed, the preset region For the projection area of the active layer sub-pattern of the gate sub-pattern, each LDD has a length of (ab)/2, where a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b is the width of the gate sub-pattern in the gate pattern.
  • the stripping unit 1505 is for stripping the changed gate photoresist pattern.
  • the apparatus for fabricating an array substrate forms a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, and changes a gate photoresist by a temperature processing unit.
  • the temperature of the pattern changes the width of the gate photoresist pattern in the gate photoresist pattern, and then the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed.
  • the LDDs satisfying the length requirements are formed on both sides of the area, so that the length of the LDD is controlled.
  • the LDD length control technology does not need to meet the condition of the gate line width and the LDD length. Therefore, the flexibility and feasibility of controlling the length of the LDD is improved.
  • the temperature processing unit 1503 may include:
  • the heat treatment sub-unit 15031 is configured to heat the gate photoresist pattern to lengthen the width of the gate photoresist pattern in the gate photoresist pattern.
  • the temperature processing unit 1503 may include:
  • the cold processing sub-unit 15032 is configured to perform a temperature lowering process on the gate photoresist pattern to shorten the width of the gate photoresist sub-pattern in the gate photoresist pattern.
  • the second forming unit 1502 may include:
  • the first forming sub-unit 15021 is configured to sequentially form a gate photoresist pattern on the substrate on which the gate metal layer is formed by a coating process, an exposure process, and a development process.
  • the second forming sub-unit 15022 is configured to form a gate metal pattern of the gate metal layer formed with the gate photoresist pattern by an etching process.
  • the apparatus for fabricating an array substrate forms a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, and changes a gate photoresist by a temperature processing unit.
  • the temperature of the pattern changes the width of the gate photoresist pattern in the gate photoresist pattern, and then the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed.
  • the LDDs satisfying the length requirements are formed on both sides of the area, so that the length of the LDD is controlled.
  • the LDD length control technology does not need to meet the condition of the gate line width and the LDD length. Therefore, the flexibility and feasibility of controlling the length of the LDD is improved.
  • Another embodiment of the present invention provides another manufacturing apparatus 1500 for an array substrate.
  • the manufacturing apparatus 1500 may include:
  • the first forming unit 1501 is configured to sequentially form an active layer, a gate insulating layer and a gate metal layer on the substrate, and the active layer includes a plurality of active layer sub-patterns.
  • a second forming unit 1502 configured to form a gate pattern with a gate photoresist pattern on the substrate formed with the gate metal layer, the gate pattern including a plurality of gates formed from the gate metal layer a sub-pattern, the gate photoresist pattern includes a plurality of gate photoresist sub-patterns, a width of each gate photoresist sub-pattern in the gate photoresist pattern being greater than each gate sub-pattern in the gate pattern The width.
  • the temperature processing unit 1503 is configured to change the temperature of the gate photoresist pattern to change the width of the gate photoresist pattern in the gate photoresist pattern.
  • a third forming unit 1504 configured to form a lightly doped drain LDD on both sides of a predetermined region of the active layer sub-pattern in the active layer of the substrate on which the changed gate photoresist pattern is formed, the preset region For the projection area of the active layer sub-pattern of the gate sub-pattern, each LDD has a length of (ab)/2, where a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b is the width of the gate sub-pattern in the gate pattern.
  • the stripping unit 1505 is for stripping the changed gate photoresist pattern.
  • the obtaining unit 1506 is configured to acquire a thermal expansion and contraction coefficient of the gate photoresist pattern.
  • the first determining unit 1507 is configured to determine the length of the LDD that needs to be obtained.
  • the second determining unit 1508 is configured to determine the photoresist processing temperature according to the thermal expansion and contraction coefficient of the gate photoresist pattern and the length of the LDD that needs to be obtained.
  • the fourth forming unit 1509 is configured to form a buffer layer on the substrate.
  • the third determining unit 1510 is configured to determine the processing duration according to the thermal expansion and contraction coefficient of the gate photoresist pattern and the length of the LDD that needs to be obtained.
  • the temperature processing unit 1503 corresponding to the second determining unit 1508 may include:
  • the first processing sub-unit 15033 is configured to process the gate photoresist pattern by using a photoresist processing temperature to change a width of a gate photoresist sub-pattern in the gate photoresist pattern.
  • the temperature processing unit 1503 corresponding to the third determining unit 1510 may include:
  • the second processing sub-unit 15034 is configured to change the temperature of the gate photoresist pattern during the processing duration to change the width of the gate photoresist sub-pattern in the gate photoresist pattern.
  • temperature processing unit and the second forming unit may also be described with reference to FIG. 16, FIG. 17, and FIG. 18, and details are not described herein again.
  • the apparatus for fabricating an array substrate forms a gate pattern with a gate photoresist pattern on a substrate on which a gate metal layer is formed, and changes a gate photoresist by a temperature processing unit.
  • the temperature of the pattern changes the width of the gate photoresist pattern in the gate photoresist pattern, and then the predetermined area of the active layer sub-pattern of the active layer of the substrate on which the changed gate photoresist pattern is formed
  • the LDDs satisfying the length requirements are formed on both sides, and the length of the LDD is controlled.
  • the control technique of the LDD length does not need to satisfy the condition of the gate line width and the condition of the LDD length. Therefore, the flexibility and feasibility of controlling the length of the LDD is improved.

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Abstract

一种阵列基板的制造方法及制造装置，制造方法包括：在基板(100)上依次形成有源层、栅极绝缘层(200)和栅极金属层(300)；在形成有栅极金属层(300)的基板(100)上形成带有栅极光刻胶图形的栅极图形；改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案(301)的宽度变化；在形成有变化后的栅极光刻胶图形的基板(100)的有源层中的有源层子图案(1021)的预设区域两侧形成LDD，预设区域为栅极图形中的栅极子图案(3000)在有源层子图案(1021)的投影区域，每个LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为栅极子图案(3000)的宽度；剥离变化后的栅极光刻胶图案。该制造方法减轻或缓解了对LDD长度的控制灵活度较低，且可行性较差的问题，实现了提高LDD长度的控制灵活度和可行性，用于制造阵列基板。

Description

阵列基板的制造方法及制造装置 技术领域
本发明涉及金属氧化物半导体技术领域，特别涉及一种阵列基板的制造方法及制造装置。
背景技术
在制造金属氧化物半导体阵列基板的过程中，金属氧化物半导体会随着沟道长度的减小而产生热电子效应，造成漏电流较大，降低金属氧化物半导体的电学性能，影响金属氧化物半导体阵列基板的制造效果。因此，需要对漏电流进行抑制。
现有技术中，主要是通过控制轻掺杂漏极(英文：Lightly Doped Drain；简称：LDD)的长度来对漏电流进行抑制。LDD位于阵列基板的有源层，且位于栅极的下方，LDD的长度由栅极线宽来确定。具体的，可以通过延长或缩短曝光LDD的时间来控制LDD的长度，或者可以通过延长或缩短刻蚀栅极的时间来控制栅极线宽，进而控制LDD的长度，最终达到抑制漏电流的目的。
但是在控制LDD的长度时，一方面，刻蚀栅极需要考虑栅极线宽的计算精度和稳定程度，同时，当栅极线宽确定了，LDD长度也被确定了，从而无法再对LDD长度进行调变；另一方面，曝光LDD和刻蚀栅极两个工艺无法同时进行，控制栅极线宽的条件要求和控制LDD长度的条件要求是相互制约的，需要牺牲一方的条件要求来满足另一方的条件要求，即在制作过程中无法同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，现有的阵列基板的制造方法对LDD长度的控制灵活度较低，且可行性较差。
发明内容
为了解决现有的阵列基板的制造方法对LDD长度的控制灵活度较低，且可行性较差的问题，本发明的实施例提供了一种阵列基板的制造方法及制造装置。所述技术方案如下：
第一方面，提供了一种阵列基板的制造方法，所述方法包括：
在基板上依次形成有源层、栅极绝缘层和栅极金属层，所述有源 层包括多个有源层子图案；
在形成有所述栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，所述栅极图形包括多个从所述栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，所述栅极光刻胶图形中的每个栅极光刻胶子图案的宽度大于所述栅极图形中的每个栅极子图案的宽度；
改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；
在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，所述预设区域为所述栅极子图案在所述有源层子图案的投影区域，每个所述LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为所述栅极图形中的栅极子图案的宽度；
剥离所述变化后的栅极光刻胶图形。
在一个实施例中，所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤，包括：
对所述栅极光刻胶图形进行加热处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变长。
在一个实施例中，所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
对所述栅极光刻胶图形进行降温处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变短。
在一个实施例中，在改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化之前，所述方法还包括：
获取所述栅极光刻胶图形的热胀冷缩系数；
确定需要得到的LDD的长度；
根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定光刻胶处理温度；
所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
采用所述光刻胶处理温度处理所述栅极光刻胶图形，使所述栅极 光刻胶图形中的栅极光刻胶子图案的宽度变化。
在一个实施例中，在改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化之前，所述方法还包括：
根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定处理时长；
所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
在所述处理时长中，改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
在一个实施例中，所述在形成有所述栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形的步骤包括：
依次通过涂敷工艺、曝光工艺、显影工艺在形成有所述栅极金属层的基板上形成所述栅极光刻胶图形；
通过刻蚀工艺将形成有所述栅极光刻胶图形的栅极金属层形成所述栅极图形。
在一个实施例中，在在基板上依次形成有源层、栅极绝缘层和栅极金属层之前，所述方法还包括：
在所述基板上形成缓冲层。
可选的，所述光刻胶为型号为DL-1000、DL-1000C和DTFR-JCW702的有机树脂材料中的任意一种。
第二方面，提供了一种阵列基板的制造装置，所述阵列基板的制造装置包括：
第一形成单元，用于在基板上依次形成有源层、栅极绝缘层和栅极金属层，所述有源层包括多个有源层子图案；
第二形成单元，用于在形成有所述栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，所述栅极图形包括多个从所述栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，所述栅极光刻胶图形中的每个栅极光刻胶子图案的宽度大于所述栅极图形中的每个栅极子图案的宽度；
温度处理单元，用于改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；
第三形成单元，用于在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，所述预设区域为所述栅极子图案在所述有源层子图案的投影区域，每个所述LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为所述栅极图形中的栅极子图案的宽度；
剥离单元，用于剥离所述变化后的栅极光刻胶图形。
在一个实施例中，所述温度处理单元，包括：
热处理子单元，用于对所述栅极光刻胶图形进行加热处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变长。
在一个实施例中，所述温度处理单元，包括：
冷处理子单元，用于对所述栅极光刻胶图形进行降温处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变短。
在一个实施例中，所述阵列基板的制造装置还包括：
获取单元，用于获取所述栅极光刻胶图形的热胀冷缩系数；
第一确定单元，用于确定需要得到的LDD的长度；
第二确定单元，用于根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定光刻胶处理温度；
所述温度处理单元，包括：
第一处理子单元，用于采用所述光刻胶处理温度处理所述栅极光刻胶图形，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
在一个实施例中，所述阵列基板的制造装置还包括：
第三确定单元，用于根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定处理时长；
所述温度处理单元，包括：
第二处理子单元，用于在所述处理时长中，改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形的宽度变化。
在一个实施例中，所述第二形成单元，包括：
第一形成子单元，用于依次通过涂敷工艺、曝光工艺、显影工艺在形成有所述栅极金属层的基板上形成所述栅极光刻胶图形；
第二形成子单元，用于通过刻蚀工艺将形成有所述栅极光刻胶图形的栅极金属层形成所述栅极图形。
在一个实施例中，所述阵列基板的制造装置还包括：
第四形成单元，用于在所述基板上形成缓冲层。
本发明的实施例提供了一种阵列基板的制造方法及制造装置，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，通过改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化，然后在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制方法，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-1是本发明实施例提供的阵列基板的制造方法的流程图；
图1-2是本发明实施例提供的阵列基板的栅极光刻胶图形宽度方向和栅极图形宽度方向的示意图；
图2是本发明的另一实施例提供的阵列基板的制造方法的流程图；
图3是本发明的另一实施例提供的在基板上形成缓冲层的结构示意图；
图4是本发明实施例提供的在基板上形成非晶硅薄膜的结构示意图；
图5是本发明实施例提供的在基板上形成有源层光刻胶的结构示意图；
图6是本发明实施例提供的在基板上形成有源层的结构示意图；
图7是本发明实施例提供的在基板上形成栅极绝缘层的结构示意图；
图8是本发明实施例提供的在基板上形成栅极金属层的结构示意图；
图9是本发明实施例提供的形成带有栅极光刻胶图形的栅极图形方法的流程图；
图10是本发明实施例提供的在基板上形成栅极光刻胶图形的结构示意图；
图11是本发明实施例提供的在基板上形成栅极图形的结构示意图；
图12是本发明实施例提供的栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的结构示意图；
图13是本发明实施例提供的单侧LDD的长度变化的结构示意图；
图14是本发明实施例提供的LDD的长度分布的结构示意图；
图15是本发明实施例提供的阵列基板的制造装置的结构示意图；
图16是本发明实施例提供的温度处理单元的结构示意图；
图17是本发明的另一实施例提供的温度处理单元的结构示意图；
图18是本发明实施例提供的第二形成单元的结构示意图；
图19是本发明的另一实施例提供的阵列基板的制造装置的结构示意图；
图20是本发明的另一实施例提供的温度处理单元的结构示意图；
图21是本发明的又一实施例提供的温度处理单元的结构示意图。
通过上述附图，已示出本发明的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本发明构思的范围，而是通过参考特定实施例为本领域技术人员说明本发明的概念。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明实施例提供了一种阵列基板的制造方法，如图1-1所示，该方法可以包括：
步骤001、在基板上依次形成有源层、栅极绝缘层和栅极金属层，所述有源层包括多个有源层子图案。
步骤002、在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，所述栅极图形包括多个从所述栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，该栅极光刻 胶图形中的每个栅极光刻胶子图案的宽度大于栅极图形中的每个栅极子图案的宽度。
步骤003、改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
步骤004、在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，该预设区域为栅极子图案在有源层子图案的投影区域，每个LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为栅极图形中的栅极子图案的宽度。
步骤005、剥离变化后的栅极光刻胶图形。
综上所述，利用本发明实施例提供的阵列基板的制造方法，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，通过改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化，然后在形成有变化后的栅极光刻胶图形的基板的有源层的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制方法，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
需要补充说明的是，如图1-2所示，步骤002中的栅极光刻胶图形中的栅极光刻胶子图案301的宽度方向
Figure PCTCN2015087920-appb-000001
栅极图形的栅极子图案3000的宽度方向
Figure PCTCN2015087920-appb-000002
分别与阵列基板上的源极121到漏极122的方向
Figure PCTCN2015087920-appb-000003
平行。图1-2中的123为LDD。
进一步的，步骤003可以包括：对栅极光刻胶图形进行加热处理，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变长。
步骤003还可以包括：对栅极光刻胶图形进行降温处理，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变短。
在步骤003之前，该方法还可以包括：获取栅极光刻胶图形的热胀冷缩系数；确定需要得到的LDD的长度；根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD的长度，确定光刻胶处理温度。
相应的，步骤003可以包括：采用光刻胶处理温度处理栅极光刻胶图形，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
在步骤003之前，该方法还可以包括：根据栅极光刻胶图形的热 胀冷缩系数和需要得到的LDD的长度，确定处理时长。
相应的，步骤003可以包括：在所述处理时长中，改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
步骤002具体可以包括：依次通过涂敷工艺、曝光工艺、显影工艺在形成有栅极金属层的基板上形成栅极光刻胶图形；通过刻蚀工艺将形成有栅极光刻胶图形的栅极金属层形成栅极图形。
在步骤001之前，该方法还可以包括：在基板上形成缓冲层。
在实施例中，光刻胶可以为型号为DL-1000、DL-1000C和DTFR-JCW702的有机树脂材料中的任意一种。
综上所述，本发明的该实施例提供的阵列基板的制造方法，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，通过改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化，然后在形成有变化后的栅极光刻胶图形的基板的有源层的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制方法，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
本发明另一实施例提供了另一种阵列基板的制造方法，以制造低温多晶硅薄膜晶体管(英文：Low temperature polycrystalline silicon thin film transistor；简称：LTPS TFT)为例进行说明，该LTPS TFT可以用于有源矩阵有机发光二极管(英文：Active Matrix Organic Light Emitting Diode；简称：AMOLED)显示器与薄膜晶体管液晶显示器(英文：Thin Film Transistor Liquid Crystal Display；简称：TFT LCD)的背板。如图2所示，根据该实施例的方法可以包括：
步骤201、在基板上形成缓冲层。
如图3所示，对由玻璃等透明材料构成的基板100进行清洗处理，利用等离子体增强化学气相沉积法(英文：Plasma Enhanced Chemical Vapor Deposition；简称：PECVD)在基板100上形成一缓冲层101。该缓冲层101可以是由氧化硅、氮化硅形成的单一层或复合层构成，氧化硅的厚度可以为50-100纳米，氮化硅厚度可以为100-300纳米。
步骤202、在基板上依次形成有源层、栅极绝缘层和栅极金属层。
在图3的基础上，形成一非晶硅(英文：amorphous-silicon；简称： a-si)薄膜102，该非晶硅薄膜厚度可以为40-50纳米，形成非晶硅薄膜102的结构示意图如图4所示。接着将该基板送往高温炉中进行处理，以达到脱氢(减少非晶硅薄膜中氢的含量)的目的，可将氢的含量控制在2％以内。
将上述基板进行准分子激光退火(英文：Excimer Laser Annealing；简称：ELA)处理，使非晶硅薄膜102转变为多晶硅薄膜1020，再通过曝光显影形成有源层光刻胶(Active Layer Photoresist)103，如图5所示。利用刻蚀的方法对多晶硅薄膜1020进行刻蚀，再利用剥离液对有源层光刻胶103进行剥离，形成包括多个有源层子图案1021的有源层，如图6所示。
接着再利用PECVD的方式沉淀形成栅极绝缘层200，形成的栅极绝缘层200的结构示意图如图7所示。然后再利用溅镀的方式在栅极绝缘层200上形成栅极金属层300，如图8所示。
步骤203、在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形。
该栅极光刻胶图形中的栅极光刻胶子图案的宽度大于栅极图形中的栅极子图案的宽度。具体的，如图9所示，步骤203可以包括：
步骤2031、依次通过涂敷工艺、曝光工艺、显影工艺在形成有栅极金属层的基板上形成栅极光刻胶图形。例如，在图8形成栅极金属层300的基板上，依次通过涂敷工艺、曝光工艺、显影工艺形成栅极光刻胶图形，栅极光刻胶图形包括多个栅极光刻胶子图案301，如图10所示。
步骤2032、通过刻蚀工艺将形成有栅极光刻胶图形的栅极金属层形成栅极图形。例如，通过刻蚀工艺将图10中的栅极金属层300进行刻蚀，形成包括多栅极子图案3000的栅极图形，如图11所示。
步骤204、获取栅极光刻胶图形的热胀冷缩系数。
根据实际应用中栅极光刻胶图形的构成，获取栅极光刻胶图形的热胀冷缩系数，本发明实施例对获取栅极光刻胶图形的热胀冷缩系数的方法不作限定。
步骤205、确定需要得到的LDD的长度。
根据制造要求，确定最终的LDD的具体长度。
步骤206、根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD 的长度，确定光刻胶处理温度和处理时长中的至少一个。
实际制造过程中，关于栅极光刻胶图形的热胀冷缩系数、需要得到的LDD的长度和光刻胶处理温度、处理时长之间的对应关系可以根据公式计算获得，也可以根据已有的表格直接获取，本发明实施例对此不作限定。假设栅极光刻胶图形的热胀冷缩系数、需要得到的LDD的长度和光刻胶处理温度、处理时长之间的对应关系是以一个表格存在的，如表1所示，从表1中可以看出，当栅极光刻胶图形的组成材料为A时，其热胀冷缩系数为x1，需要得到的LDD长度为c1，对应的光刻胶处理温度为150℃，且处理时长为15分钟。示例性的，栅极光刻胶图形的组成材料可以为型号是DL-1000、DL-1000C或者DTFR-JCW702等类型的光刻胶，该类光刻胶的敏感度较高，在改变栅极光刻胶图形的温度时，可以使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化得更快，从而有利于控制LDD的长度，降低整个工艺的复杂度。
表1
Figure PCTCN2015087920-appb-000004
步骤207、改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
在一个实施例中，可以根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD的长度，确定光刻胶处理温度，则步骤207可以包括：采用所述光刻胶处理温度处理栅极光刻胶图形，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；在另一实施例中，可以根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD的长度，确定处理时长，则步骤207可以包括：在所述处理时长中，改变栅极光刻胶图形的温 度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；在又一实施例中，可以根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD的长度，确定光刻胶处理温度和处理时长，则步骤207可以包括：在所述处理时长中，采用所述光刻胶处理温度处理栅极光刻胶图形，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
以表1为例，当栅极光刻胶图形的组成材料为A时，可以采用光刻胶处理温度(即150℃)处理栅极光刻胶图形15分钟，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
实际制造过程中，栅极光刻胶图形的栅极光刻胶子图案的宽度可能需要变宽，也可能需要变窄，当栅极光刻胶图形中的栅极光刻胶子图案的宽度需要变宽时，可以通过热胀原理使栅极光刻胶图形中的栅极光刻胶子图案的宽度变宽；当栅极光刻胶图形的宽度需要变窄时，可以通过冷缩原理使栅极光刻胶图形中的栅极光刻胶子图案的宽度变窄。因此，步骤207可以包括：对栅极光刻胶图形进行加热处理，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变宽。例如，加热处理时的温度范围可以为150～200℃或者，步骤207可以包括：对栅极光刻胶图形进行降温处理，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变窄。例如，降温处理时的温度范围可以为-30～-40℃。在一个实施例中，可以认为当光刻胶处理温度小于-30℃时，是对栅极光刻胶图形进行降温处理，当光刻胶处理温度大于150℃时，是对栅极光刻胶图形进行加热处理。加热的时长约为10到20分钟，降温的时长也可以约为10到20分钟。
图12为通过改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案301的宽度变化的结构示意图。如图12所示，当对栅极光刻胶图形进行降温处理时，栅极光刻胶图形中的栅极光刻胶子图案301的宽度变窄，变窄后的栅极光刻胶图形中的栅极光刻胶子图案的标识为302；当对栅极光刻胶图形进行加热处理时，栅极光刻胶图形中的栅极光刻胶子图案301的宽度变宽，变宽后的栅极光刻胶图形中的栅极光刻胶子图案的标识为303。
如图13所示，在栅极光刻胶图形中的栅极光刻胶子图案301未被处理的情况下，单侧LDD的长度为c，当对栅极光刻胶图形中的栅极光刻胶子图案301进行降温处理时，栅极光刻胶图形中的栅极光刻胶 子图案301的宽度变窄，变窄后的栅极光刻胶图形中的栅极光刻胶子图案的标识为302，相应的，单侧LDD的长度变为c1；当对栅极光刻胶图形中的栅极光刻胶子图案301进行加热处理时，栅极光刻胶图形中的栅极光刻胶子图案301宽度变宽，变宽后的栅极光刻胶图形中的栅极光刻胶子图案的标识为303，相应的，单侧LDD的长度就变为c2。其中，c1＜c＜c2。图13中的N+掺杂指的是N型(电子型)高浓度掺杂。图13中的3000为栅极图形中的栅极子图案，200为栅极绝缘层。
步骤208、在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成LDD。
该预设区域为栅极图形中的栅极子图案在有源层子图案的投影区域，每个LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案302或303的宽度，b为栅极图形的栅极子图案3000的宽度。当改变栅极光刻胶图形的温度，栅极光刻胶图形中的栅极光刻胶子图案的宽度发生变化后，开始进行LDD工艺，LDD的长度将依照栅极图形的栅极子图案3000上方的栅极光刻胶子图案301的宽度进行分布，且形成的单侧LDD的长度c与变化后的栅极光刻胶子图案的宽度a、栅极图形中栅极子图案的宽度b的关系为c＝(a-b)/2。
步骤209、剥离变化后的栅极光刻胶图形。
待掺杂完成后进行剥膜作业，剥离变化后的光刻胶，此时LDD的长度分布如图14所示，c为未处理栅极光刻胶图形时的单侧LDD的长度，c1为降温处理栅极光刻胶图形后的单侧LDD的长度，c2为加热处理栅极光刻胶图形后的单侧LDD的长度。图14中的3000为栅极图形中的栅极子图案，200为栅极绝缘层。
需要补充说明的是，实际制造过程中，剥离变化后的光刻胶之后，可以继续形成内部介质层，内部介质光刻胶，源漏极层，源漏极层光刻胶，平坦层及像素电极层等，形成过程可以参考现有技术，本发明实施例在此不再赘述。
需要说明的是，为描述的方便和简洁，该实施例中每个步骤对应的结构示意图中未说明的标识可以参考前面已有的结构示意图中已说明的标识。例如，图4中的100指示的是图3中的基板100，图4中的101指示的是图3中的缓冲层101。
本发明实施例提供的阵列基板的制造方法，可以在不影响栅极线 宽的情况下，控制LDD任意长度；可以根据栅极刻蚀的情况，控制LDD任意长度；当栅极刻蚀后出现线宽过大或过小时，则依照栅极刻蚀后的实际情况，通过改变栅极光刻胶图形的温度，控制LDD对应的相对长度。
综上所述，本发明实施例提供的阵列基板的制造方法，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，通过改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；然后在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制方法，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
本发明的另一实施例提供了一种阵列基板的制造装置1500，如图15所示，该制造装置1500可以包括：
第一形成单元1501，第二形成单元1502，温度处理单元1503，第三形成单元1504和剥离单元1505。
第一形成单元1501，用于在基板上依次形成有源层、栅极绝缘层和栅极金属层，有源层包括多个有源层子图案。
第二形成单元1502，用于在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，所述栅极图形包括多个从栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，该栅极光刻胶图形中的每个栅极光刻胶子图案的的宽度大于栅极图形中的每个栅极子图案的宽度。
温度处理单元1503，用于改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
第三形成单元1504，用于在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，该预设区域为栅极子图案在有源层子图案的投影区域，每个LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为栅极图形中的栅极子图案的宽度。
剥离单元1505，用于剥离变化后的栅极光刻胶图形。
综上所述，本发明实施例提供的阵列基板的制造装置，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，并通过温度处理单元改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化，然后在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制技术，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
进一步的，如图16所示，温度处理单元1503，可以包括：
热处理子单元15031，用于对栅极光刻胶图形进行加热处理，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变长。
如图17所示，温度处理单元1503，可以包括：
冷处理子单元15032，用于对栅极光刻胶图形进行降温处理，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变短。
如图18所示，第二形成单元1502，可以包括：
第一形成子单元15021，用于依次通过涂敷工艺、曝光工艺、显影工艺在形成有栅极金属层的基板上形成栅极光刻胶图形。
第二形成子单元15022，用于通过刻蚀工艺将形成有栅极光刻胶图形的栅极金属层形成栅极图形。
综上所述，本发明实施例提供的阵列基板的制造装置，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，并通过温度处理单元改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化，然后在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制技术，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
本发明的又一实施例提供了另一种阵列基板的制造装置1500，如图19所示，该制造装置1500可以包括：
第一形成单元1501，第二形成单元1502，温度处理单元1503，第三形成单元1504，剥离单元1505，获取单元1506，第一确定单元1507，第二确定单元1508和第四形成单元1509。
第一形成单元1501，用于在基板上依次形成有源层、栅极绝缘层和栅极金属层，有源层包括多个有源层子图案。
第二形成单元1502，用于在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，所述栅极图形包括多个从所述栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，该栅极光刻胶图形中的每个栅极光刻胶子图案的宽度大于栅极图形中的每个栅极子图案的宽度。
温度处理单元1503，用于改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
第三形成单元1504，用于在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，该预设区域为栅极子图案在有源层子图案的投影区域，每个LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为栅极图形中的栅极子图案的宽度。
剥离单元1505，用于剥离变化后的栅极光刻胶图形。
获取单元1506，用于获取栅极光刻胶图形的热胀冷缩系数。
第一确定单元1507，用于确定需要得到的LDD的长度。
第二确定单元1508，用于根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD的长度，确定光刻胶处理温度。
第四形成单元1509，用于在基板上形成缓冲层。
第三确定单元1510，用于根据栅极光刻胶图形的热胀冷缩系数和需要得到的LDD的长度，确定处理时长。
进一步的，如图20所示，第二确定单元1508对应的温度处理单元1503，可以包括：
第一处理子单元15033，用于采用光刻胶处理温度处理栅极光刻胶图形，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
如图21所示，第三确定单元1510对应的温度处理单元1503，可以包括：
第二处理子单元15034，用于在处理时长中，改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
需要补充说明的是，温度处理单元和第二形成单元还可以参考图16、图17和图18进行说明，在此不再赘述。
综上所述，本发明实施例提供的阵列基板的制造装置，在形成有栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，并通过温度处理单元改变栅极光刻胶图形的温度，使栅极光刻胶图形中的栅极光刻胶子图案的宽度变化，然后在形成有变化后的栅极光刻胶图形的基板的有源层的有源层子图案的预设区域两侧形成满足长度要求的LDD，使LDD的长度得到控制，相较于现有阵列基板的制造方法对LDD长度的控制技术，无需同时满足栅极线宽的条件要求和LDD长度的条件要求，因此，提高了对LDD长度的控制灵活度和可行性。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种阵列基板的制造方法，其中所述方法包括：
    在基板上依次形成有源层、栅极绝缘层和栅极金属层，所述有源层包括多个有源层子图案；
    在形成有所述栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形，所述栅极图形包括多个从所述栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，所述栅极光刻胶图形中的每个栅极光刻胶子图案的宽度大于所述栅极图形中的每个栅极子图案的宽度；
    改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；
    在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，所述预设区域为所述栅极子图案在所述有源层子图案的投影区域，每个所述LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为所述栅极图形中的栅极子图案的宽度；
    剥离所述变化后的栅极光刻胶图形。
  2. 根据权利要求1所述的方法，其中，
    所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
    对所述栅极光刻胶图形进行加热处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变长。
  3. 根据权利要求1所述的方法，其特征在于，
    所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
    对所述栅极光刻胶图形进行降温处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变短。
  4. 根据权利要求1至3任意一项权利要求所述的方法，其中在改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化之前，所述方法还包括：
    获取所述栅极光刻胶图形的热胀冷缩系数；
    确定需要得到的LDD的长度；
    根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定光刻胶处理温度；
    所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
    采用所述光刻胶处理温度处理所述栅极光刻胶图形，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
  5. 根据权利要求4所述的方法，其中在改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化之前，所述方法还包括：
    根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定处理时长；
    所述改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化的步骤包括：
    在所述处理时长中，改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
  6. 根据权利要求1所述的方法，其中所述在形成有所述栅极金属层的基板上形成带有栅极光刻胶图形的栅极图形的步骤包括：
    依次通过涂敷工艺、曝光工艺、显影工艺在形成有所述栅极金属层的基板上形成所述栅极光刻胶图形；
    通过刻蚀工艺将形成有所述栅极光刻胶图形的栅极金属层形成所述栅极图形。
  7. 根据权利要求1所述的方法，其中在在基板上依次形成有源层、栅极绝缘层和栅极金属层之前，所述方法还包括：
    在所述基板上形成缓冲层。
  8. 根据权利要求1所述的方法，其特征在于，
    所述光刻胶为型号为DL-1000、DL-1000C和DTFR-JCW702的有机树脂材料中的任意一种。
  9. 一种阵列基板的制造装置，所述阵列基板的制造装置包括：
    第一形成单元，用于在基板上依次形成有源层、栅极绝缘层和栅极金属层，所述有源层包括多个有源层子图案；
    第二形成单元，用于在形成有所述栅极金属层的基板上形成带有 栅极光刻胶图形的栅极图形，所述栅极图形包括多个从所述栅极金属层形成的栅极子图案，所述栅极光刻胶图形包括多个栅极光刻胶子图案，所述栅极光刻胶图形中的每个栅极光刻胶子图案的宽度大于所述栅极图形中的每个栅极子图案的宽度；
    温度处理单元，用于改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化；
    第三形成单元，用于在形成有变化后的栅极光刻胶图形的基板的有源层中的有源层子图案的预设区域两侧形成轻掺杂漏极LDD，所述预设区域为所述栅极子图案在所述有源层子图案的投影区域，每个所述LDD的长度为(a-b)/2，其中，a为变化后的栅极光刻胶图形中的栅极光刻胶子图案的宽度，b为所述栅极图形中的栅极子图案的宽度；
    剥离单元，用于剥离所述变化后的栅极光刻胶图形。
  10. 根据权利要求9所述的阵列基板的制造装置，其中所述温度处理单元，包括：
    热处理子单元，用于对所述栅极光刻胶图形进行加热处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变长。
  11. 根据权利要求9所述的阵列基板的制造装置，其特征在于，所述温度处理单元，包括：
    冷处理子单元，用于对所述栅极光刻胶图形进行降温处理，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变短。
  12. 根据权利要求9所述的阵列基板的制造装置，其中所述阵列基板的制造装置还包括：
    获取单元，用于获取所述栅极光刻胶图形的热胀冷缩系数；
    第一确定单元，用于确定需要得到的LDD的长度；
    第二确定单元，用于根据所述栅极光刻胶图形的热胀冷缩系数和所述需要得到的LDD的长度，确定光刻胶处理温度；
    所述温度处理单元，包括：
    第一处理子单元，用于采用所述光刻胶处理温度处理所述栅极光刻胶图形，使所述栅极光刻胶图形中的栅极光刻胶子图案的宽度变化。
  13. 根据权利要求12所述的阵列基板的制造装置，其中所述阵列基板的制造装置还包括：
    第三确定单元，用于根据所述栅极光刻胶图形的热胀冷缩系数和 所述需要得到的LDD的长度，确定处理时长；
    所述温度处理单元，包括：
    第二处理子单元，用于在所述处理时长中，改变所述栅极光刻胶图形的温度，使所述栅极光刻胶图形的宽度变化。
  14. 根据权利要求9所述的阵列基板的制造装置，其中所述第二形成单元，包括：
    第一形成子单元，用于依次通过涂敷工艺、曝光工艺、显影工艺在形成有所述栅极金属层的基板上形成所述栅极光刻胶图形；
    第二形成子单元，用于通过刻蚀工艺将形成有所述栅极光刻胶图形的栅极金属层形成所述栅极图形。
  15. 根据权利要求9所述的阵列基板的制造装置，其中所述阵列基板的制造装置还包括：
    第四形成单元，用于在所述基板上形成缓冲层。
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CN109712930B (zh) * 2018-11-27 2020-10-30 合肥鑫晟光电科技有限公司 显示基板及其制作方法、显示装置
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210377A1 (en) * 2006-03-07 2007-09-13 Eisuke Seo Semiconductor device and fabricating method thereof
CN101150092A (zh) * 2007-11-08 2008-03-26 友达光电股份有限公司 互补式金属氧化物半导体薄膜晶体管的制造方法
CN101840865A (zh) * 2010-05-12 2010-09-22 深圳丹邦投资集团有限公司 一种薄膜晶体管的制造方法及用该方法制造的晶体管
CN103021820A (zh) * 2011-09-20 2013-04-03 乐金显示有限公司 制造薄膜晶体管的方法和制造有机发光显示设备的方法
CN104716092A (zh) * 2015-04-02 2015-06-17 京东方科技集团股份有限公司 阵列基板的制造方法及制造装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020032580A (ko) * 1999-09-16 2002-05-03 모리시타 요이찌 박막트랜지스터 및 그 제조방법
US20020102785A1 (en) * 2001-01-26 2002-08-01 James Ho Method for forming shallow junctions by increasing width of photoresist and using implanting through poly film
KR100426381B1 (ko) * 2001-03-30 2004-04-08 주승기 결정질 실리콘 활성층을 포함하는 박막트랜지스터의 제조방법
KR101239889B1 (ko) * 2005-08-13 2013-03-06 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
CN101236904A (zh) * 2008-02-29 2008-08-06 上海广电光电子有限公司 具有轻掺杂漏极区的多晶硅薄膜晶体管的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210377A1 (en) * 2006-03-07 2007-09-13 Eisuke Seo Semiconductor device and fabricating method thereof
CN101150092A (zh) * 2007-11-08 2008-03-26 友达光电股份有限公司 互补式金属氧化物半导体薄膜晶体管的制造方法
CN101840865A (zh) * 2010-05-12 2010-09-22 深圳丹邦投资集团有限公司 一种薄膜晶体管的制造方法及用该方法制造的晶体管
CN103021820A (zh) * 2011-09-20 2013-04-03 乐金显示有限公司 制造薄膜晶体管的方法和制造有机发光显示设备的方法
CN104716092A (zh) * 2015-04-02 2015-06-17 京东方科技集团股份有限公司 阵列基板的制造方法及制造装置

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