CN107342260B - 一种低温多晶硅tft阵列基板制备方法及阵列基板 - Google Patents

一种低温多晶硅tft阵列基板制备方法及阵列基板 Download PDF

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CN107342260B
CN107342260B CN201710772525.0A CN201710772525A CN107342260B CN 107342260 B CN107342260 B CN 107342260B CN 201710772525 A CN201710772525 A CN 201710772525A CN 107342260 B CN107342260 B CN 107342260B
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CN107342260A (zh
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班圣光
曹占锋
姚琪
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BOE Technology Group Co Ltd
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Abstract

本发明涉及显示技术领域，公开一种低温多晶硅TFT阵列基板制备方法及阵列基板。制备方法包括在衬底基板上依次形成非晶硅膜层和多晶硅膜层；通过一次构图工艺对所述非晶硅膜层和所述多晶硅膜层进行图案化处理，使所述非晶硅膜层形成遮光层图形，并使所述多晶硅层形成有源层图形。与现有技术相比，本发明提供的低温多晶硅TFT阵列基板的制备方法省去了一次构图工艺，简化了低温多晶硅TFT阵列基板的制备工艺，提高了低温多晶硅TFT阵列基板的生产效率并降低了生产成本。

Description

一种低温多晶硅TFT阵列基板制备方法及阵列基板
技术领域
本发明涉及显示技术领域，特别涉及一种低温多晶硅TFT阵列基板制备方法及阵列基板。
背景技术
在目前的显示面板技术领域中，低温多晶硅(Low Temperature Poly-silicon；LTPS)技术已受到广泛的重视和应用。低温多晶硅具有高迁移率的特性，因此在显示面板中采用低温多晶硅制成的TFT(Thin Film Transistor；薄膜晶体管)器件，可提高显示面板的分辨率、反应速度、亮度和开口率，同时，利用低温多晶硅技术可将显示面板的外围驱动电路集成于基板上，还可起到节省显示面板的空间和降低生产成本的作用。
然而，在低温多晶硅TFT阵列基板的制备过程中，目前的低温多晶硅TFT半导体层的制备工艺复杂，与传统的基于非晶硅显示技术的阵列基板相比，非晶硅TFT阵列基板需采用4-5道构图工艺，而低温多晶硅TFT阵列基板需要采用9-11道构图工艺，其生产工艺较为复杂，导致低温多晶硅TFT阵列基板的生产效率降低且生产成本增加。
发明内容
本发明提供了一种低温多晶硅TFT阵列基板制备方法及阵列基板，用于解决现有技术中的低温多晶硅TFT阵列基板的生产工艺复杂而导致的生产效率降低和生产成本增加的问题。
为实现上述目的，本发明提供如下的技术方案：
一种低温多晶硅TFT阵列基板的制备方法，包括：
在衬底基板上依次形成非晶硅膜层和多晶硅膜层；
通过一次构图工艺对所述非晶硅膜层和所述多晶硅膜层进行图案化处理，使所述非晶硅膜层形成遮光层图形，并使所述多晶硅层形成有源层图形。
本发明提供的低温多晶硅TFT阵列基板的制备方法中，采用非晶硅材料膜层作为遮光层，可通过同一次构图工艺同时形成遮光层的图形和有源层的图形，而现有技术中采用金属材料膜层作为遮光层，需通过一次构图工艺单独形成遮光层图形之后，再通过另一次构图工艺形成有源层的图形。因此，与现有技术相比，本发明提供的低温多晶硅TFT阵列基板的制备方法省去了一次构图工艺，简化了低温多晶硅TFT阵列基板的制备工艺，提高了低温多晶硅TFT阵列基板的生产效率并降低了生产成本。
可选地，在所述衬底基板上形成多晶硅膜层之前，还包括：
在所述非晶硅膜层上形成防护层。
进一步地，所述防护层的材料为氧化铝。
进一步地，所述在所述非晶硅膜层上形成防护层，具体包括：
在所述非晶硅层上形成铝膜层；
对所述铝膜层进行氧化处理，使所述铝膜层形成所述防护层。
进一步地，所述对所述铝膜层进行氧化处理，具体包括：
在氧气或者空气中对所述铝膜层进行退火处理。
进一步地，所述防护层的厚度为100-1000埃米。
进一步地，所述在衬底基板上形成晶硅膜层，具体包括：
在所述防护层上形成有源层缓冲层。
进一步地，所述有源层缓冲层由氧化硅材料制成，且所述有源层缓冲层的厚度为1000-3000埃米。
可选地，在所述衬底基板上形成所述非晶硅膜层之前，还包括：
在所述衬底基板上形成遮光层缓冲层，所述遮光层缓冲层由氮化硅材料或氧化硅材料中的至少一种制成。
进一步地，所述遮光层的厚度为700-1200埃米。
本发明还提供了一种低温多晶硅TFT阵列基板，包括衬底基板和依次设置于所述衬底基板上的遮光层和有源层，其中，所述遮光层由非晶硅材料制成。
可选地，还包括设置于所述遮光层与所述有源层之间的防护层。
进一步地，所述防护层由氧化铝材料制成。
进一步地，所述防护层的厚度为100-1000埃米。
可选地，所述遮光层的厚度为700-1200埃米。
可选地，还包括设置于所述有源层与所述防护层之间的有源层缓冲层。
进一步地，所述有源层缓冲层由氧化硅材料制成。
本发明还提供了一种显示面板，包括如上述技术方案提供的低温多晶硅TFT阵列基板。
本发明还提供了一种显示装置，包括如上述技术方案提供的显示面板。
附图说明
图1是本发明实施例提供的低温多晶硅TFT阵列基板的工艺流程图；
图2是图1中步骤S100的工艺流程图；
图3是图2中步骤S130的工艺流程图；
图4是图2中步骤S150的工艺流程图；
图5是在衬底基板上形成遮光层缓冲层和非晶硅膜层之后的基板结构示意图；
图6是在非晶硅膜层上形成铝膜层之后的基板结构示意图；
图7是在非晶硅膜层上形成防护层之后的基板结构示意图；
图8是在防护层上形成有源层缓冲层和待晶化非晶硅膜层之后的基板结构示意图；
图9是在有源层缓冲层上形成多晶硅膜层之后的基板结构示意图；
图10是通过一次构图工艺形成遮光层和有源层图形之后的基板结构示意图；
图11是不同厚度的非晶硅膜层的透过率与波长的对应关系图。
附图标记：
10，衬底基板；20，遮光层缓冲层；30，非晶硅膜层；31，遮光层图形；
40，铝膜层；50，防护层；60，有源层缓冲层；70，待晶化非晶硅膜层；
80，多晶硅膜层；81，有源层图形。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种低温多晶硅TFT阵列基板的制备方法，用于解决现有技术中的低温多晶硅TFT阵列基板的生产工艺复杂而导致的生产效率降低和生产成本增加的问题。参见图1所示，该制备方法包括：
步骤S100，在衬底基板上依次形成非晶硅膜层和多晶硅膜层。
具体地，参见图2所示，步骤S100包括：
步骤S110，在衬底基板上形成遮光层缓冲层；具体实施中，衬底基板可为玻璃基板，遮光层缓冲层采用氧化硅材料和氮化硅材料中的至少一种制成，具体地，遮光层缓冲层可采用单层氧化硅材料制成，也可采用单层氮化硅材料制成，还可采用由单层氧化硅材料和单层氮化硅材料形成的双层结构。单层的氧化硅和氮化硅均可起到屏蔽衬底基板表面缺陷、阻隔衬底基板内的金属离子扩散的作用，在遮光层缓冲层采用单层氧化硅材料和单层氮化硅材料形成的双层结构时，可进一步提高对衬底基板内的金属离子的阻隔作用。具体实施中，遮光层缓冲层可采用PECVD(Plasma Enhanced Chemical Vapor Deposition；等离子体增强化学的气相沉积)方法形成于衬底基板上；遮光层缓冲层的厚度为1500-2500埃米，具体地，可为1500埃米、2000埃米或2500埃米；
步骤S120，在遮光层缓冲层上形成非晶硅膜层。具体实施中，非晶硅膜层同样可采用PECVD方法形成于遮光层缓冲层上，非晶硅膜层的厚度为700-1200埃米，具体地，可为700埃米、800埃米、900埃米、1000埃米、1100埃米或1200埃米；经过步骤S110和步骤S120之后形成的阵列基板的结构如图5所示，在衬底基板10上依次形成有遮光层缓冲层20和非晶硅膜层30；本实施例中提供的制备方法中，非晶硅膜层30用于在后续构图工艺中形成遮光层图形；
步骤S130，在非晶硅膜层上形成防护层；在采用非晶硅膜层作为遮光层时，在后续形成多晶硅膜层的工艺中，需要在非晶硅膜层上再形成一层用于形成多晶硅膜层的待晶化的非晶硅膜层，并采用ELA(Excimer Laser Annel；准分子激光退火)工艺对该待晶化非晶硅膜层进行晶化处理，但是在ELA工艺过程中，待晶化非晶硅膜层的热量会传递到其下方的非晶硅膜层，造成待晶化非晶硅膜层底部结晶不良，而且用于形成遮光层的非晶硅膜层中的氢离子的含量较高，会造成待晶化非晶硅膜层的结晶产生氢爆问题。现有技术中通常会在用于形成遮光层的非晶硅膜层上形成一层较厚的缓冲层，以阻挡热量和氢离子的传递，但是缓冲层厚度的增加会导致后续刻蚀工艺的难度增加，降低阵列基板的生产效率。本发明实施例提供的制备方法中，在非晶硅膜层上形成防护层，防护层由导热性能较差且致密性较高的材料制成，以阻挡ELA工艺过程中热量和氢离子的传递，并降低对后续刻蚀工艺的影响。具体地，防护层采用Al2O3材料制成，Al2O3具有较高的保温性能和致密性，在不增加用于形成遮光层的非晶硅膜层上的缓冲层的厚度的情况下，可阻挡ELA工艺过程中热量和氢离子的传递，提高待晶化非晶硅膜层的结晶效果，降低了后续刻蚀工艺的难度；具体实施中，与氧化铝性能相近的氧化镁也可作为防护层的材料。
具体地，参见图3所示，当防护层为Al2O3材料时，上述步骤S130具体包括：
步骤S131，在非晶硅膜层上形成铝膜层；参见图6所示，具体实施中，可采用溅射工艺在非晶硅膜层30上形成一层铝膜层40；
步骤S131，对铝膜层进行氧化处理，使铝膜层形成防护层；具体地，氧化处理为退火处理，具体实施中可将沉积有铝膜层的阵列基板产品放置于退火炉中，在氧气或空气中进行退火，使铝膜层氧化，形成一层Al2O3膜层，以得到所需的防护层；参见图7所示，铝膜层在氧化处理后形成防护层50，具体地，防护层的厚度为100-1000埃米，具体可为100埃米、200埃米、300埃米、400埃米、500埃米、600埃米、700埃米、800埃米、900埃米或1000埃米；
继续参见图2所示，在上述步骤S130之后，还包括：
步骤S140，在防护层上形成有源层缓冲层；由于防护层已经起到在ELA工艺中阻挡热量和氢离子传递的作用，因此有源层缓冲层的厚度不需再进行加厚。而在后续形成多晶硅膜层的工艺中，为了提高晶粒质量并减少多晶硅膜层与有源层缓冲层之间的层间缺陷，一种可选的实施方式中，有源层缓冲层采用氧化硅材料制成，氧化硅材料与多晶硅材料具有较高的晶格匹配性，因此在采用ELA工艺形成多晶硅膜层时，可提高多晶硅膜层的晶粒质量，并且减少多晶硅膜层与有源层缓冲层之间的层间缺陷。具体地，有源层缓冲层的厚度为1000-3000埃米，具体可为1000埃米、1500埃米、2000埃米、2500埃米或3000埃米。具体实施中，有源层缓冲层可采用PECVD方法沉积形成；
步骤S150，在有源层缓冲层上形成多晶硅层；多晶硅层用于在后续刻蚀工艺后形成有源层的图形，具体地，参见图4所示，步骤S150包括：
步骤S151，在有源层缓冲层上形成待晶化非晶硅膜层；具体地，待晶化非晶硅膜层可采用PECVD工艺沉积形成；参见图8所示，在防护层50上依次形成有源层缓冲层60和待晶化非晶硅膜层70；
步骤S152，对待晶化非晶硅膜层进行晶化处理，使待晶化非晶硅膜层形成多晶硅膜层；具体地，可采用ELA工艺对待晶化非晶硅膜层进行晶化处理，由于在之前的工艺中设置了防护层，因此可减少ELA工艺中非晶硅膜层与多晶硅膜层之间的热量传递和氢离子传递，降低在待晶化非晶硅膜层中的结晶产生不良的概率；参见图9所示，在晶化处理后，待晶化非晶硅膜层形成多晶硅膜层80；具体地，晶化处理后形成的多晶硅膜层80的厚度为400-600埃米，具体可为400埃米、500埃米或600埃米。
上述步骤S100中，在衬底基板上依次形成了非晶硅膜层和多晶硅膜层，非晶硅材料膜层在后续工艺中用于形成遮光层的图案，非晶硅膜层和多晶硅膜层可在同一次构图工艺中进行刻蚀，而现有技术中一般采用金属材料膜层作为遮光层，例如采用钼膜层作为遮光层，金属材料膜层与多晶硅膜层无法在同一次构图工艺中同时进行刻蚀，需通过一次构图工艺单独刻蚀金属材料膜层，再通过另一次构图工艺刻蚀多晶硅膜层，其制备工艺较为复杂。
继续参见图1所示，本发明实施例提供的制备方法还包括：
步骤S200，通过一次构图工艺对非晶硅膜层和多晶硅膜层进行图案化处理，使非晶硅膜层形成遮光层图形，并使多晶硅层形成有源层图形；具体参见图10所示，通过一次构图工艺，将非晶硅膜层和多晶硅膜层上的部分材料去除，使非晶硅膜层形成遮光层图形31，并使多晶硅层形成有源层图形81；具体实施中构图工艺可采用光刻工艺；具体地，遮光层的厚度为700-1200埃米，对不同厚度的非晶硅材料的透过率进行分析测试后，得到不同厚度的非晶硅材料的透过率与波长的对应关系如图11所示，由图11可知，非晶硅材料遮光层的厚度在700-1200埃米时，可得到较为理想的遮光性能。
由上述可知，本发明实施例提供的制备方法可通过同一次构图工艺同时形成遮光层的图形和有源层的图形，与现有技术相比，本发明提供的低温多晶硅TFT阵列基板的制备方法省去了一次构图工艺，简化了低温多晶硅TFT阵列基板的制备工艺，提高了低温多晶硅TFT阵列基板的生产效率，并降低了生产成本。
在通过上述步骤S100和S200形成遮光层和有源层的图形后，通过后续工艺形成栅极、源漏极、电极等图形，即可得到低温多晶硅TFT阵列基板产品。
基于同一发明构思，本发明实施例还提供了一种低温多晶硅TFT阵列基板，包括衬底基板和依次设置于衬底基板上的遮光层和有源层，其中，遮光层由非晶硅材料制成。具体地，遮光层的厚度为700-1200埃米，可实现较佳的遮光性能。
由于本发明实施例提供的低温多晶硅TFT阵列基板中的遮光层由非晶硅材料制成，则可通过同一次构图工艺同时形成遮光层的图形和有源层的图形，与现有技术相比，本发明实施例提供的低温多晶硅TFT阵列基板的制备工艺较为简单，其生产效率较高，且生产成本较低。具体实施参见上述制备方法的实施例，不再赘述。
为降低在形成有源层的工艺过程中由于热量和氢离子的传递造成的有源层产生结晶不良的概率，一种具体实施方式中，还包括设置于遮光层与有源层之间的防护层，防护层由氧化铝材料制成。氧化铝材料具有较好的隔热性能和致密性，可阻挡遮光层和有源层之间的热量和氢离子的传递，降低在形成有源层的工艺过程中成的有源层产生结晶不良的概率。具体地，防护层的厚度为100-1000埃米。
在本发明实施例提供的低温多晶硅TFT阵列基板的制备过程中，在形成多晶硅材料有源层的工艺中，为提高有源层的晶粒质量，一种具体实施方式中，该阵列基板还包括设置于有源层和防护层之间的有源层缓冲层，有源层缓冲层可起到屏蔽防护层上的缺陷并阻隔金属离子传递的作用，以提高有源层的晶粒质量。为进一步提高有源层的晶粒质量，有源层采用氧化硅材料制成，可提高有源层缓冲层与有源层之间的晶格匹配程度，改善有源层缓冲层与有源层之间的层间缺陷问题。
基于同一发明构思，本发明实施例还提供了一种显示面板，包括如上述实施例提供的低温多晶硅TFT阵列基板。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括如上述实施例提供的显示面板。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

1.一种低温多晶硅TFT阵列基板的制备方法，其特征在于，包括：
在衬底基板上依次形成非晶硅膜层和多晶硅膜层；
通过一次构图工艺对所述非晶硅膜层和所述多晶硅膜层进行图案化处理，使所述非晶硅膜层形成遮光层图形，并使所述多晶硅膜层形成有源层图形；
所述遮光层的厚度为700-1200埃米；
在所述衬底基板上形成多晶硅膜层之前，所述方法还包括：
在所述非晶硅膜层上形成防护层；
所述防护层的厚度为100-1000埃米；
所述防护层的材料为氧化镁。
2.根据权利要求1所述的低温多晶硅TFT阵列基板的制备方法，其特征在于，在所述非晶硅膜层上形成防护层之后，在衬底基板上形成多晶硅膜层之前，还包括：
在所述防护层上形成有源层缓冲层。
3.根据权利要求2所述的低温多晶硅TFT阵列基板的制备方法，其特征在于，所述有源层缓冲层由氧化硅材料制成，且所述有源层缓冲层的厚度为1000-3000埃米。
4.根据权利要求1所述的低温多晶硅TFT阵列基板的制备方法，其特征在于，在所述衬底基板上形成所述非晶硅膜层之前，还包括：
在所述衬底基板上形成遮光层缓冲层，所述遮光层缓冲层由氮化硅材料或氧化硅材料中的至少一种制成。
5.一种低温多晶硅TFT阵列基板，其特征在于，包括衬底基板和依次设置于所述衬底基板上的遮光层和有源层，其中，所述遮光层由非晶硅材料制成，所述遮光层与所述有源层通过同一次构图工艺同时形成；
所述低温多晶硅TFT阵列基板还包括设置于所述遮光层与所述有源层之间的防护层；
所述防护层的厚度为100-1000埃米；
所述防护层的材料为氧化镁；
所述遮光层的厚度为700-1200埃米。
6.根据权利要求5所述的低温多晶硅TFT阵列基板，其特征在于，还包括设置于所述有源层与所述防护层之间的有源层缓冲层。
7.根据权利要求6所述的低温多晶硅TFT阵列基板，其特征在于，所述有源层缓冲层由氧化硅材料制成。
8.一种显示面板，其特征在于，包括如权利要求5所述的低温多晶硅TFT阵列基板。
9.一种显示装置，其特征在于，包括如权利要求8所述的显示面板。
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