WO2020134937A1 - 薄膜晶体管的制作方法和显示面板 - Google Patents

薄膜晶体管的制作方法和显示面板 Download PDF

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WO2020134937A1
WO2020134937A1 PCT/CN2019/123232 CN2019123232W WO2020134937A1 WO 2020134937 A1 WO2020134937 A1 WO 2020134937A1 CN 2019123232 W CN2019123232 W CN 2019123232W WO 2020134937 A1 WO2020134937 A1 WO 2020134937A1
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layer
amorphous silicon
thin film
film transistor
forming
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PCT/CN2019/123232
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French (fr)
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葛邦同
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惠科股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present application relates to the field of display technology, in particular to a manufacturing method of a thin film transistor and a display panel.
  • Low-temperature polycrystalline silicon thin-film transistors Low-temperature Polycrystalline Silicon thin films transisitors, LTPS TFT
  • LTPS TFT Low-temperature Polycrystalline Silicon thin films transisitors
  • Solid-phase crystallization (SPC) and excimer laser annealing (Excimer laser annealing (ELA)) are commonly used methods for crystallizing amorphous silicon.
  • excimer laser annealing requires high cost and uneven grain distribution; solid phase crystallization requires long-term high-temperature heating, which will not only cause phase transformation of the glass substrate, but also reduce the production efficiency of the panel;
  • Metal-induced crystallization is another solid-phase crystallization technique, usually using metallic nickel. This method requires low temperature for crystallization, but the thin film transistors manufactured will have metal residue, resulting in large leakage current.
  • Ni bias-set metal induced lateral crystallization Ni-off-set Metal Seed-induced Lateralization, Ni-off-set MILC
  • cover layer SiNx, SiO2
  • the present application provides a method for manufacturing a thin film transistor and a display panel, which can effectively reduce residual metal, shorten crystallization annealing time, and can prepare a low-temperature polycrystalline silicon thin film transistor (LTPS, TFT, Low-Temperature, Poly-Si Thin Film Transistor) with stable high-quality performance.
  • LTPS low-temperature polycrystalline silicon thin film transistor
  • TFT Low-Temperature, Poly-Si Thin Film Transistor
  • the present application discloses a method for manufacturing a thin film transistor, including the steps of:
  • the amorphous silicon layer is transformed into a polysilicon layer under the induction of the metal seed layer and annealing treatment.
  • the present application also discloses a method for manufacturing a thin film transistor, including the steps of:
  • a second photomask process is used to form an etch barrier on the intrinsic amorphous silicon layer
  • a third photomask process is used to form an intrinsic amorphous silicon layer and a doped amorphous silicon layer, and the doped amorphous silicon layer corresponds to the etching barrier surface to form a channel;
  • a fourth mask process is used to form a protective layer covering the channel
  • a fifth photomask process is used to form the source and drain on the doped polysilicon layer
  • the annealing crystallization temperature range is between 400 and 600°C, and the annealing crystallization time range is between 0.5 and 2h.
  • the present application also discloses a display panel, which includes a plurality of scan lines, a plurality of data lines, a plurality of pixel electrodes, and a plurality of active switches.
  • the active switches are thin film transistors, and the thin film transistors include:
  • the source electrode of the thin film transistor is connected to the data line, the gate electrode is connected to the scan line, and the drain electrode is connected to the pixel electrode;
  • the polysilicon layer is made by the following method:
  • the amorphous silicon layer is transformed into the polysilicon layer under the induction of the metal seed layer and the annealing treatment.
  • the area of the amorphous silicon layer is greatly reduced, which can effectively shorten the crystallization annealing time.
  • This solution is also applicable to Low Temperature Poly-Silicon (LTPS) technology.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 3 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of this application.
  • FIG. 4 is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of this application.
  • FIG. 5 is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of this application.
  • FIG. 7 is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of this application.
  • FIG. 8 is a schematic diagram of a method for manufacturing a thin film transistor according to one embodiment of the present application.
  • FIG. 9 is a schematic diagram of a method for manufacturing a thin film transistor according to one embodiment of the present application.
  • FIG. 10 is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of this application.
  • FIG. 11 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • the term “including” and any variations thereof are intended to cover non-exclusive inclusions.
  • the present application discloses a display panel 500 including two first substrates 540 and second substrates 550 that are oppositely disposed, and a data line 520 is provided between the first substrate 540 and the second substrate 550
  • the first substrate 540 is an array substrate, including a plurality of scan lines 510, a plurality of data lines 520, a plurality of pixel electrodes 410, and a plurality of active switches.
  • the active switch is a thin film transistor 400
  • the thin film transistor 400 includes: a substrate 100; a gate metal layer 120, a gate insulating layer 130, a polysilicon layer 300, and a source formed on the polysilicon layer deposited on the substrate 100 in sequence Electrode 310 and drain 320; wherein, the source electrode 310 of the thin film transistor 400 is connected to a data line 520, the gate metal layer 120 is connected to a scanning line 510, and the drain 320 is connected to the pixel electrode 410;
  • the display panel further includes an amorphous silicon layer formed on the gate insulating layer, and a metal seed layer made of nickel disilicide material formed on the amorphous silicon layer; the amorphous silicon layer is formed on the metal seed layer
  • the polysilicon layer is transformed by annealing treatment under induction.
  • the step of transforming the amorphous silicon layer into the polycrystalline silicon layer under the induction effect of the metal seed layer and annealing treatment includes: inducing the amorphous silicon layer by lateral crystallization of the nickel bias metal seed layer and annealing treatment Into the polysilicon layer.
  • the thin film transistor 400 of the display panel 500 manufactured by the above method reduces the metal remaining in the amorphous silicon layer 150 and reduces the leakage current, and the grain growth is larger, which can improve the performance of the thin film transistor 400.
  • the amorphous silicon layer 150 in the present application that is, after patterning the amorphous silicon material layer through a photomask process, and then depositing the metal seed layer 200, the area of the amorphous silicon layer 150 is greatly reduced, which can effectively shorten the crystallization annealing time.
  • this application discloses a method for manufacturing a thin film transistor, including:
  • the patterned amorphous silicon thin film layer forms an amorphous silicon layer
  • NiSi2 nickel disilicide
  • the amorphous silicon layer is transformed into a polysilicon layer under the induction of the metal seed layer and the annealing treatment.
  • a metal seed layer is formed on the amorphous silicon layer.
  • the metal ions in the metal seed layer spread to the amorphous silicon layer to induce the amorphous silicon layer to crystallize to form polysilicon.
  • the metal atoms diffuse more during the heating and crystallization process, resulting in too many residual metal atoms in the thin film transistor, resulting in the thin film transistor Large leakage current.
  • the amorphous silicon layer includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer, the doped amorphous silicon layer 151 covers the surface of the intrinsic amorphous silicon layer, and the metal seed layer is disposed on the doped The surface of the heteroamorphous silicon layer.
  • NiSi2 and Si at the interface of the doped amorphous silicon layer (N+a-Si) have a higher free energy than Si at the NiSi2/c-Si interface, so it can be guaranteed that NiSi2/in the doped amorphous silicon layer (N The +a-Si) interface continues to advance to the side of the intrinsic amorphous silicon layer (a-Si), and is eventually converted to polysilicon. In this method, during the crystallization process, no unreacted metal will diffuse all the time, and the residual Ni impurity metal will be significantly reduced.
  • the step of forming a metal seed layer made of nickel disilicide (NiSi2) on the amorphous silicon layer includes:
  • NiSi2 is sputtered onto the surface of the amorphous silicon layer to form the metal seed layer.
  • magnetron sputtering is used to bombard the cathode target material, that is, the surface of the NiSi2 material, using the formed ion current under the action of a DC high-voltage electric field, so that the kinetic energy and momentum of the ions are transferred to the atoms on the solid surface.
  • the commonly used bombardment ions are the inert gas argon which is ionized by the action of a high-voltage electric field and forms an ion flow with certain functions.
  • Magnetron sputtering is easier to quickly deposit a uniform large-area thin film.
  • the sputtering method can also use radio frequency sputtering, binary sputtering and reactive sputtering.
  • the metal seed layer may also be formed by sol-gel, pulsed laser deposition (PLD), molecular beam epitaxy, and the like.
  • the steps of forming a metal seed layer made of nickel disilicide (NiSi2) on the amorphous silicon layer include:
  • the metal seed film is formed by treating the metal nickel film with an acidic solvent.
  • a metal nickel thin film is deposited on the amorphous silicon layer by a sputtering method.
  • the method of depositing the metal nickel thin film may use a magnetron sputtering method, which may be a direct current sputtering method or a radio frequency sputtering method.
  • the nickel metal will first react with the amorphous silicon layer, crystallize in advance, and then be removed with an acidic solvent to form the metal seed. This solution makes the crystallization time longer, produces larger crystal grains, the carrier mobility of the polysilicon layer formed by crystallization is higher, and the performance of the manufactured thin film transistor is better.
  • the thickness of the metal nickel thin film is in the range of 1-10 nm.
  • Acidic solvents include, but are not limited to, sulfuric acid, hydrochloric acid, nitric acid and other acidic substances.
  • the amorphous silicon thin film layer includes an intrinsic amorphous silicon thin film layer and a doped amorphous silicon thin film layer; the amorphous silicon layer includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer; an amorphous silicon layer is formed on the substrate
  • the methods include:
  • a first mask process is used to form a gate metal layer 120 on the surface of the substrate 100 (see FIG. 4);
  • a second photomask process is used to form an etch stop layer 140 on the intrinsic amorphous silicon thin film layer 153;
  • a doped amorphous silicon thin film layer 154 is formed on the surface of the etch barrier layer 140, the doped amorphous silicon thin film layer 154 covers the etch barrier layer 140, and the intrinsic non-intrinsic Crystal silicon thin film layer 153; (refer to FIG. 5);
  • the etch barrier layer 140 is located directly above the gate metal layer, the width is smaller than the gate metal layer, and the thickness is greater than the doped amorphous silicon layer 156; the doped amorphous silicon layer 156 corresponds to the surface of the etch barrier layer 140
  • the channel 160 is formed.
  • the etching barrier layer 140 ensures that the characteristics of the intrinsic amorphous silicon layer 152 are not affected by other processes, and stabilizes the characteristics of the thin film transistor 400.
  • the etch stop layer 140 does not exceed 5 nm, which improves the uniformity of the surface of the thin film transistor 400.
  • the gate metal layer 120 is one or more stack combinations of aluminum, molybdenum, titanium, and copper.
  • a buffer layer 110 may be first formed on the surface of the substrate 100, and then the gate metal layer 120 may be formed on the buffer layer 110; then, the gate may be formed by chemical deposition
  • the gate insulating layer 130 is deposited on the metal layer 120, specifically, by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the substrate 100 is made of glass, but of course it can also be made of transparent hard plastic.
  • the buffer layer 110, the gate insulating layer 130 and the etch stop layer 140 are a silicon oxide layer, a silicon nitride layer, or a composite layer in which silicon oxide and silicon nitride are superimposed.
  • the step of forming a metal seed layer 200 made of nickel disilicide (NiSi2) on the amorphous silicon layer 150 includes:
  • a fourth mask process is used to form a protective layer 180 covering the trench 160;
  • the metal seed layer 200 is formed by treating the metal nickel film 190 with an acidic solvent (refer to FIG. 8).
  • the intrinsic amorphous silicon layer 155 is converted into an intrinsic polysilicon layer 340 through the induction of the metal seed layer 200 and the annealing process, and the doped amorphous silicon layer 156 is converted into a doped polysilicon layer 350 (refer to FIG. 9 ).
  • the protective layer 180 to protect the channel 160, the metal seed will not be directly deposited on the conductive channel 160.
  • the polysilicon formed by the lateral diffusion method not only has less metal residue, but also has larger crystal grains. More specifically, the protective layer 180 is made of photoresist material.
  • the metal seed layer 200 may also be formed by sputtering nickel disilicide directly on the surface of the doped amorphous silicon layer 156.
  • the annealing crystallization temperature ranges from 400 to 600°C
  • the annealing crystallization time ranges from 0.5 to 2h.
  • the nickel disilicide layer is destroyed, and Ni atoms continue to migrate into the doped amorphous silicon layer 151 and the intrinsic amorphous silicon layer 152 to form nickel disilicide silicide, and so on until the doped amorphous
  • the silicon layer 151 and the intrinsic amorphous silicon layer 152 are all converted to a crystalline state. If the induction is performed before patterning the amorphous silicon thin film layer, it takes more than 20 hours. In this application, since the amorphous silicon thin film layer is patterned through the photomask process and then induced, the annealing time can be significantly shortened, which is about From 0.5h to 2h.
  • the metal does not directly cause silicon crystallization, but the silicide formed by the chemical reaction between the metal and silicon causes the silicon crystallization.
  • the silicide along The lateral propagation of silicon causes continuous crystallization of adjacent silicon regions.
  • the metal causing this MILC nickel and palladium or similar metals. Accordingly, in the MILC method, almost no metal component remains in the silicon layer, and therefore, the crystallized silicon layer does not affect the leakage current or other characteristics of the TFT containing the silicon layer.
  • the present application uses an asymmetric metal bias method, which has better electric field characteristics such as field effect mobility and leakage current than thin film transistors with a symmetric nickel bias structure. This is because the electrical characteristics of the channel region 160 of the thin film transistor with a symmetrical bias structure are adversely affected by the resident nickel silicide MILC boundary.
  • the amorphous silicon layer under the induction of the metal seed layer and after being transformed into a polysilicon layer by annealing, also includes a method for forming the source electrode and the drain electrode:
  • a fifth photomask process is used to form the source 310 and the drain 320 on the doped polysilicon layer 350;
  • An interlayer insulating layer 330 is formed on the source electrode 310 and the drain electrode 320 (see FIG. 10).
  • the source electrode 310 and the drain electrode 320 are arranged on both sides of the channel 160 and are in contact with the doped polysilicon layer 350.
  • the source electrode 310 and the drain electrode 320 are one or more stack combinations of aluminum, molybdenum, titanium, and copper.
  • the interlayer insulating layer 330 is a silicon oxide layer, a silicon nitride layer, or a composite layer in which silicon oxide and silicon nitride are superimposed.
  • the present application also discloses a method for manufacturing a thin film transistor, and the steps include:
  • a gate insulating layer and an intrinsic amorphous silicon thin film layer are sequentially stacked on the gate metal layer;
  • an etching barrier layer is formed on the intrinsic amorphous silicon layer by using a second photomask process
  • a third photomask process is used to form an intrinsic amorphous silicon layer and a doped amorphous silicon layer, and the doped amorphous silicon layer corresponds to the etching barrier surface to form a channel;
  • a fourth mask process is used to form a protective layer covering the channel
  • S118 Convert the intrinsic amorphous silicon layer into an intrinsic polysilicon layer through the induction effect and annealing treatment of the metal seed layer, and convert the doped amorphous silicon layer into a doped polysilicon layer;
  • a fifth photomask process is used to form source and drain electrodes on the doped polysilicon layer.
  • the annealing crystallization temperature range is between 400 and 600°C, and the annealing crystallization time range is between 0.5 and 2h.
  • the interlayer insulating layer is a silicon oxide layer, a silicon nitride layer, or a composite layer in which silicon oxide and silicon nitride are superimposed.
  • TFT-LCD Thin Film Transistor-Liquid Crystal
  • OLED Organic Light-Emitting Diode

Abstract

本申请公开一种薄膜晶体管的制作方法和显示面板，所述薄膜晶体管的制作方法包括步骤：提供衬底，在衬底上形成非晶硅薄膜层；图形化非晶硅薄膜层形成非晶硅层；在非晶硅层上形成二硅化镍(NiSi2)材质的金属种子层；所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层；形成源漏极层。

Description

薄膜晶体管的制作方法和显示面板
本申请要求于2018年12月25日提交中国专利局，申请号为CN201811587237.9，申请名称为“一种薄膜晶体管的制作方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管的制作方和显示面板。
背景技术
应当理解的是，这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
低温多晶硅薄膜晶体管(Low-temperature Polycrystalline Silicon thin film transisitors,LTPS TFT)因为其展现比较好的电学性能和可以被做成集成电路在平板显示领域得到很大应用。固相结晶(solid-phase crystallization，SPC)和准分子激光退火(Excimer laser annealing,ELA)是使非晶硅结晶常用的方法。但是，准分子激光退火则需要很高的成本和产生晶粒分布不均匀；固相结晶需要长时间的高温加热，这不仅会导致玻璃基板发生相变，而且会降低面板的生产效率；
金属诱导结晶是另一种固相结晶技术，通常使用金属镍，这种方法结晶需要的温度低，但是制造的薄膜晶体管中会残留金属，导致较大的漏电流。有一些研究去除薄膜晶体管中残留金属的技术，例如Ni偏置金属诱导横向结晶法(Ni off-set Metal Seed-induced Lateral Crystallization，Ni off-set MILC)、通过添加覆盖层(SiNx,SiO2),吸杂技术。然而这些技术复杂并且需要长时间高温退火，这会破坏薄膜晶体管，导致性能下降。
发明内容
本申请提供一种薄膜晶体管的制作方法和显示面板，有效降低残留的金属，缩短结晶退火时间，可制备高质量性能稳定的低温多晶硅薄膜晶体管(LTPS TFT,Low Temperature Poly-Si Thin Film Transistor)。
本申请公开一种薄膜晶体管的制作方法，包括步骤：
提供衬底；
在衬底上形成非晶硅薄膜层；
图形化非晶硅薄膜层形成非晶硅层；
在非晶硅层上形成二硅化镍材质的金属种子层；以及
所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层。
本申请还公开一种薄膜晶体管的制作方法，包括步骤：
采用第一道光罩制程在衬底表面形成栅极金属层；
在栅极金属层上依次堆叠形成栅极绝缘层、本征非晶硅薄膜层；
采用第二道光罩制程在本征非晶硅层上形成刻蚀阻挡层；
在刻蚀阻挡层上形成掺杂非晶硅薄膜层，所述掺杂非晶硅薄膜层覆盖所述刻蚀阻挡层，以及所述蚀阻挡层覆盖区域以外的所述本征非晶硅薄膜层；
采用第三道光罩制程形成本征非晶硅层和掺杂非晶硅层，所述掺杂非晶硅层对应刻蚀阻挡层表面形成沟道；
采用第四道光罩制程形成覆盖所述沟道的保护层；
在掺杂非晶硅层上形成二硅化镍材质的金属种子层；
通过所述金属种子层的诱导作用以及退火处理将本征非晶硅层转化为本征多晶硅层，将掺杂非晶硅层转化为掺杂多晶硅层；
采用第五道光罩制程在掺杂多晶硅层上形成源极和漏极；
在源极和漏极上形成层间绝缘层；以及
所述退火结晶温度范围在400至600℃之间，退火结晶的时间范围在0.5至2h之间。
本申请还公开一种显示面板，包括多条扫描线，多条数据线，多个像素电极和多个主动开关，所述主动开关为薄膜晶体管，所述薄膜晶体管包括：
衬底；
依次沉积在所述衬底上的栅极金属层、栅极绝缘层、非晶硅层、以及在非晶硅层上形成的源极和漏极；
所述薄膜晶体管的所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接；
所述多晶硅层采用以下方法制成：
在所述栅极绝缘层形成非晶硅层；
在所述非晶硅层上形成二硅化镍材质的金属种子层；以及
所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为所述多晶硅层。
相对于通过在非晶硅层形成金属种子层，直接使用金属诱导结晶的方法，由于结晶前未反应的金属层没有去除，所以加热结晶过程中，金属原子扩散更多，造成薄膜晶体管中残留金属原子过多，导致薄膜晶体管较大的漏电流。通过金属种子层诱导结晶方法，只有种子层中的金属原子扩散，可以有效减少非晶硅层残留的金属，降低漏电流，而且晶粒生长的更大，能够提高薄膜晶体管的性能。另外，本申请在形成非晶硅层后，即通过光罩制程图形化非晶 硅薄膜层以后再沉积金属种子层，非晶硅层的面积大幅缩减，能够有效缩短结晶退火时间。本方案同样适用于低温多晶硅技术(Low Temperature Poly-Silicon，LTPS)。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请其中一个实施例一种显示面板的结构示意图；
图2是本申请其中一个实施例一种显示面板的示意图；
图3本申请其中一个实施例一种薄膜晶体管的制作方法的流程图；
图4是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图5是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图6是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图7是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图8是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图9是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图10是本申请其中一个实施例一种薄膜晶体管的制作方法的示意图；
图11是本申请其中一个实施例一种薄膜晶体管的制作方法的流程图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面参考附图和较佳的实施例对本申请作进一步说明。
如图1至图2所示，本申请公开一种显示面板500包括两个相对设置的第一基板540和第二基板550，所述第一基板540和第二基板550中间设有数据线520；第一基板540为阵列基板，包括多条扫描线510、多条数据线520、多个像素电极410和多个主动开关。主动开关为薄膜晶体管400，薄膜晶体管400包括：衬底100；依次沉积在所述衬底100上的栅极金属层120、栅极绝缘层130、多晶硅层300、以及在多晶硅层上形成的源极310和漏极320；其中，薄膜晶体管400的源极310与一条数据线520连接，所述栅极金属层120与一条扫描线510连接，所述漏极320与像素电极410连接；所述显示面板还包括在所述栅极绝缘层形成的非晶硅层，以及在所述非晶硅层上形成二硅化镍材质的金属种子层；所述非晶硅层在所述金属种子层的诱导作用下并退火处理转化为所述多晶硅层。
具体的，所述非晶硅层在所述金属种子层的诱导作用下并退火处理转化为所述多晶硅层步骤包括：通过镍偏置金属种子层横向结晶诱导所述非晶硅层并退火处理转化为所述多晶硅层。
采用上述方法制造的显示面板500的薄膜晶体管400，减少非晶硅层150残留的金属，降低漏电流，而且晶粒生长的更大，能够提高薄膜晶体管400的性能。另外，本申请在形成非晶硅层150后，即通过光罩制程图形化非晶硅材料层以后再沉积金属种子层200，非晶硅层150的面积大幅缩减，能够有效缩短结晶退火时间。
如图3所示，本申请公开了一种薄膜晶体管的制造方法，包括：
S31、提供衬底；
S32、在衬底上形成非晶硅薄膜层；
S33、图形化非晶硅薄膜层形成非晶硅层；
S34、在非晶硅层上形成二硅化镍(NiSi2)材质的金属种子层200；
S35、所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层。
上述的薄膜晶体管的制作方法，通过在非晶硅层形成金属种子层，在退火结晶时，金属种子层中的金属离子扩展至非晶硅层，诱导非晶硅层结晶形成多晶硅。相比在退火结晶后，再去除未反应的金属，由于结晶前未反应的金属层没有去除，所以加热结晶过程中，金属原子扩散更多，造成薄膜晶体管中残留金属原子过多，导致薄膜晶体管较大的漏电流。
通过在非晶硅层形成金属种子层，通过金属种子层诱导结晶方法，只有种子层中的金属原子扩散，可以有效减少非晶硅层残留的金属，降低漏电流，而且晶粒生长的更大，能够提高薄膜晶体管的性能。另外，本申请在形成非晶硅层后，即通过光罩制程图形化非晶硅薄膜层以后再沉积金属种子层，非晶硅层的面积大幅缩减，能够有效缩短结晶退火时间。本方案同样适用于低温多晶硅技术(Low Temperature Poly-Silicon，LTPS)。
非晶硅层包括本征非晶硅层和掺杂非晶硅层，所述掺杂非晶硅层151覆盖在所述本征非晶硅层表面，所述金属种子层设置在所述掺杂非晶硅层表面。NiSi2与在掺杂非晶硅层(N+a-Si)界面处的Si相对NiSi2/c-Si界面处Si具有更高的自由能，所以可以保证NiSi2/在掺杂非晶硅层(N+a-Si)界面不断向本征非晶硅层(a-Si)一侧推进,最终都转化为多晶硅。此种方法，结晶过程中，不会有未反应金属一直扩散，残留的Ni杂质金属明显减少。
所述在非晶硅层上形成二硅化镍(NiSi2)材质的金属种子层的步骤包括：
将NiSi2溅射到非晶硅层表面，形成所述金属种子层。
具体来说，采用磁控溅射，在直流高压电场的作用下利用形成的离子流轰击阴极靶材料，即NiSi2材料表面，使离子的动能和动量转移给固体表面的原子，因化学键断裂而飞出，沉积在非晶硅层表面。通常采用的轰击离子是隋性气体氩受高压电场的作用而电离，并形成具有一定功能的离子流，磁控溅射更容易快速沉积均匀大面积薄膜。
当然，溅射方式还可以采用射频溅射、二元溅射和反应溅射。
除了采用溅射的方式，还可以溶胶-凝胶(sol-gel)，脉冲激光沉积(PLD)，分子束外延等方式形成所述金属种子层。
在非晶硅层上形成二硅化镍(NiSi2)材质的金属种子层的步骤包括：
在非晶硅层表面形成金属镍薄膜；
采用酸性溶剂处理金属镍薄膜形成所述金属种子层。
通过溅射方式在在非晶硅层上沉积金属镍薄膜，沉积金属镍薄膜的方法可以采用磁控溅射法，可以为直流溅射法或射频溅射法。金属镍会先与非晶硅层进行反应，提前结晶，然后再用酸性溶剂进行去除，形成所述金属种子。本方案使得结晶时间更长，产生的晶粒更大，结晶形成的多晶硅层的载流子迁移率更高，制成的薄膜晶体管性能更好。
更具体的，金属镍薄膜的厚度范围是1-10nm。酸性溶剂包括但不限于硫酸、盐酸、硝 酸等酸性物质。
非晶硅薄膜层包括本征非晶硅薄膜层和掺杂非晶硅薄膜层；非晶硅层包括本征非晶硅层和掺杂非晶硅层；在衬底上形成非晶硅层的方法包括：
采用第一道光罩制程在衬底100表面形成栅极金属层120(参考图4所示)；
在栅极金属层120上依次堆叠形成栅极绝缘层130、本征非晶硅薄膜层153；
采用第二道光罩制程在本征非晶硅薄膜层153上形成刻蚀阻挡层140；
在刻蚀阻挡层140表面形成掺杂非晶硅薄膜层154，掺杂非晶硅薄膜层154覆盖所述刻蚀阻挡层140，以及所述蚀阻挡层140覆盖区域以外的所述本征非晶硅薄膜层153；(参考图5所示)；
采用第三道光罩制程形成本征非晶硅层155和掺杂非晶硅层156(参考图6所示)；以及
所述刻蚀阻挡层140位于所述栅极金属层正上方，宽度小于栅极金属层的宽度，厚度大于掺杂非晶硅层156；掺杂非晶硅层156对应刻蚀阻挡层140表面形成沟道160。
刻蚀阻挡层140保证本征非晶硅层152的特性不受其他工艺的影响，稳定薄膜晶体管400的特性。
更具体的，所述刻蚀阻挡层140不超过5nm，改善薄膜晶体管400表面的均匀性。所述栅极金属层120为铝、钼、钛、铜中的一种或多种堆栈组合。为了提高栅极金属层120的附着力，可以先在衬底100表面先形成一层缓冲层110，然后在缓冲层110上再形成栅极金属层120；然后，可通过化学沉积方式在栅极金属层120上沉积栅极绝缘层130，具体的，通过等离子增强化学气相沉积(PECVD)。衬底100采用玻璃材质制成，当然也可以用透明硬质塑料制成。所述缓冲层110、栅极绝缘层130和刻蚀阻挡层140为氧化硅层、氮化硅层、或者氧化硅与氮化硅叠加的复合层。
所述在非晶硅层150上形成二硅化镍(NiSi2)材质的金属种子层200的步骤包括：
采用第四道光罩制程形成覆盖所述沟道160的保护层180；
在掺杂非晶硅层156表面形成金属镍薄膜190(参考图7所示)；
采用酸性溶剂处理金属镍薄膜190形成所述金属种子层200(参考图8所示)。
通过所述金属种子层200的诱导作用以及退火处理将本征非晶硅层155转化为本征多晶硅层340，将掺杂非晶硅层156转化为掺杂多晶硅层350(参考图9所示)。使用保护层180保护住沟道160，金属种子就不会直接在沉积在导电沟道160上面，利用横向扩散方法形成的多晶硅不仅金属残留少，而且晶粒也会较大。更具体的，保护层180采用光刻胶材质制作形成。
当然，本实施方式中，也可以通过直接在掺杂非晶硅层156表面溅射二硅化镍形成所述 金属种子层200。
在一实施例中，所述退火结晶温度范围在400至600℃之间，退火结晶的时间范围在0.5至2h之间。在高温诱导之下，二硅化镍层被破坏，Ni原子不断向掺杂非晶硅层151和本征非晶硅层152中迁移，再形成二硅化镍硅化物，如此反复直至掺杂非晶硅层151和本征非晶硅层152全部转化为结晶态。如果在图形化非晶硅薄膜层之前进行诱导，需要长达20个小时以上的时间，本申请由于通过光罩制程图形化非晶硅薄膜层以后再进行诱导，可以显著缩短退火时间，约为0.5h至2h即可。
更具体的，在金属诱发侧向结晶方法(MILC)中，金属并没有直接引起硅结晶，而是由金属与硅起化学反应生成的硅化物引起硅结晶，当结晶继续进行时，硅化物沿硅的侧向传播，引起邻近硅区的连续结晶。作为造成此MILC的金属，镍和钯或类似金属。相应地MILC方法中几乎没有金属成分残留在硅层中，因此，结晶的硅层不会影响含硅层的TFT的漏电流或其它特性。此外，金属诱发侧向结晶方法中，本申请采用不对称的金属偏置方法，相比有对称镍偏置结构的薄膜晶体管有较好的场效应迁移率和漏电流等电特性。这是由于有对称偏置结构的薄膜晶体管的沟道区160的电特性受到驻留的硅化镍MILC界线不好的影响。
所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层之后还包括源极和漏极的成型方法：
采用第五道光罩制程在掺杂多晶硅层350上形成源极310和漏极320；
在源极310和漏极320上形成层间绝缘层330(参考图10所示)。
源极310和漏极320分列在沟道160的两侧位置，与掺杂多晶硅层350接触。所述源极310和漏极320为铝、钼、钛、铜中的一种或多种堆栈组合。所述层间绝缘层330为氧化硅层、氮化硅层、或者氧化硅与氮化硅叠加的复合层。
作为本申请的另一实施例，参考图11所示，本申请还公开一种薄膜晶体管的制作方法，其步骤包括：
S111、采用第一道光罩制程在衬底表面形成栅极金属层；
S112、在栅极金属层上依次堆叠形成栅极绝缘层、本征非晶硅薄膜层；
S113、采用第二道光罩制程在本征非晶硅层上形成刻蚀阻挡层；
S114、在刻蚀阻挡层上形成掺杂非晶硅薄膜层；掺杂非晶硅薄膜层覆盖刻蚀阻挡层，以及蚀阻挡层覆盖区域以外的本征非晶硅薄膜层；
S115、采用第三道光罩制程形成本征非晶硅层和掺杂非晶硅层，所述掺杂非晶硅层对应刻蚀阻挡层表面形成沟道；
S116、采用第四道光罩制程形成覆盖所述沟道的保护层；
S117、在掺杂非晶硅层上形成二硅化镍材质的金属种子层；
S118、通过所述金属种子层的诱导作用以及退火处理将本征非晶硅层转化为本征多晶硅层，将掺杂非晶硅层转化为掺杂多晶硅层；
S119、采用第五道光罩制程在掺杂多晶硅层上形成源极和漏极；以及
S120、在源极和漏极上形成层间绝缘层。
所述退火结晶温度范围在400至600℃之间，退火结晶的时间范围在0.5至2h之间。
具体的，所述层间绝缘层为氧化硅层、氮化硅层、或者氧化硅与氮化硅叠加的复合层。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛应用于薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等平板显示器。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种薄膜晶体管的制造方法，包括步骤：
    提供衬底；
    在所述衬底上形成非晶硅薄膜层；
    图形化所述非晶硅薄膜层形成非晶硅层；
    在所述非晶硅层上形成二硅化镍材质的金属种子层；以及
    所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层。
  2. 如权利要求1所述的一种薄膜晶体管的制作方法，其中，所述在非晶硅层上形成二硅化镍材质的金属种子层的步骤包括：
    将所述二硅化镍溅射到所述非晶硅层表面，形成所述金属种子层。
  3. 如权利要求2所述的一种薄膜晶体管的制作方法，其中，所述将所述二硅化镍溅射到所述非晶硅层表面，形成所述金属种子层的步骤包括：将所述二硅化镍磁控溅射到所述非晶硅层表面。
  4. 如权利要求1所述的一种薄膜晶体管的制作方法，其中，所述在非晶硅层上形成二硅化镍材质的金属种子层的步骤包括：
    在所述非晶硅层表面形成金属镍薄膜；
    采用酸性溶剂处理所述金属镍薄膜形成所述金属种子层。
  5. 如权利要求4所述的一种薄膜晶体管的制作方法，其中，所述酸性溶剂包括硫酸、盐酸或硝酸。
  6. 如权利要求1所述的一种薄膜晶体管的制作方法，其中，所述非晶硅层包括本征非晶硅层和掺杂非晶硅层，所述掺杂非晶硅层覆盖在所述本征非晶硅层表面，所述金属种子层设置在所述掺杂非晶硅层表面。
  7. 如权利要求6所述的一种薄膜晶体管的制作方法，其中，所述在衬底上形成非晶硅层的方法包括：
    在所述衬底表面形成栅极金属层；
    在所述栅极金属层上依次堆叠形成栅极绝缘层、本征非晶硅薄膜层；
    在所述本征非晶硅薄膜层上形成刻蚀阻挡层；
    在所述刻蚀阻挡层表面形成掺杂非晶硅薄膜层，所述掺杂非晶硅薄膜层覆盖所述刻蚀阻挡层，以及所述蚀阻挡层覆盖区域以外的所述本征非晶硅薄膜层；
    图形化所述本征非晶硅薄膜层和掺杂非晶硅薄膜层形成本征非晶硅层和掺杂非晶硅层；以及
    所述刻蚀阻挡层位于所述栅极金属层正上方，宽度小于所述栅极金属层的宽度，厚度大于所述掺杂非晶硅层；所述掺杂非晶硅层对应所述刻蚀阻挡层表面形成沟道。
  8. 如权利要求7所述的一种薄膜晶体管的制作方法，其中，所述栅极绝缘层和所述刻蚀阻挡层均包括氧化硅层、氮化硅层、或者氧化硅与氮化硅叠加的复合层。
  9. 如权利要求7所述的一种薄膜晶体管的制作方法，其中，所述刻蚀阻挡层不超过5nm。
  10. 如权利要求7所述的一种薄膜晶体管的制作方法，其中，所述栅极金属层和所述衬底之间包括缓冲层。
  11. 如权利要求7所述的一种薄膜晶体管的制作方法，其中，所述栅极绝缘层通过化学沉积方式沉积在所述栅极金属层上。
  12. 如权利要求11所述的一种薄膜晶体管的制作方法，其中，化学沉积方式为等离子增强化学气相沉积。
  13. 如权利要求7所述的一种薄膜晶体管的制作方法，其中，在所述非晶硅层上形成二硅化镍材质的金属种子层的步骤包括：
    形成覆盖所述沟道的保护层；
    在所述掺杂非晶硅层上形成所述金属种子层。
  14. 如权利要求7所述的一种薄膜晶体管的制作方法，其中，所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层的步骤包括：
    通过退火结晶将本征非晶硅层转化为本征多晶硅层，将掺杂非晶硅层转化为掺杂多晶硅层；退火结晶温度范围在400至600℃之间，退火结晶的时间范围在0.5至2h之间。
  15. 如权利要求1所述的一种薄膜晶体管的制作方法，其中，所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为多晶硅层之后还包括源极和漏极的成型方法：
    在掺杂多晶硅层上形成源极和漏极；
    在源极和漏极上形成层间绝缘层。
  16. 一种薄膜晶体管的制作方法，包括：
    提供衬底；
    采用第一道光罩制程在衬底表面形成栅极金属层；
    在栅极金属层上依次堆叠形成栅极绝缘层、本征非晶硅薄膜层；
    采用第二道光罩制程在本征非晶硅层上形成刻蚀阻挡层；
    在刻蚀阻挡层上形成掺杂非晶硅薄膜层，所述掺杂非晶硅薄膜层覆盖所述刻蚀阻挡层，以及所述蚀阻挡层覆盖区域以外的所述本征非晶硅薄膜层；
    采用第三道光罩制程形成本征非晶硅层和掺杂非晶硅层，所述掺杂非晶硅层对应刻蚀阻挡层表面形成沟道；
    采用第四道光罩制程形成覆盖所述沟道的保护层；
    在掺杂非晶硅层上形成二硅化镍材质的金属种子层；
    通过所述金属种子层的诱导作用以及退火处理将本征非晶硅层转化为本征多晶硅层，将掺杂非晶硅层转化为掺杂多晶硅层；
    采用第五道光罩制程在掺杂多晶硅层上形成源极和漏极；
    在源极和漏极上形成层间绝缘层；以及
    所述退火结晶温度范围在400至600℃之间，退火结晶的时间范围在0.5至2h之间。
  17. 如权利要求15所述的一种薄膜晶体管的制作方法，其中，所述层间绝缘层为氧化硅层、氮化硅层、或者氧化硅与氮化硅叠加的复合层。
  18. 一种显示面板，包括多条扫描线，多条数据线，多个像素电极和多个主动开关，所述主动开关为薄膜晶体管，所述薄膜晶体管包括：
    衬底；
    依次沉积在所述衬底上的栅极金属层、栅极绝缘层、多晶硅层、以及在多晶硅层上形成的源极和漏极；
    所述薄膜晶体管的所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接；
    其中，所述多晶硅层采用以下方法制成：
    在所述栅极绝缘层形成非晶硅层；
    在所述非晶硅层上形成二硅化镍材质的金属种子层；以及
    所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为所述多晶硅层。
  19. 如权利要求18所述的一种显示面板，其中，所述非晶硅层在所述金属种子层的诱导作用下以及退火处理转化为所述多晶硅层步骤包括：通过镍偏置金属种子层横向结晶诱导所述非晶硅层以及退火处理转化为所述多晶硅层。
PCT/CN2019/123232 2018-12-25 2019-12-05 薄膜晶体管的制作方法和显示面板 WO2020134937A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1102908A (zh) * 1993-06-22 1995-05-24 株式会社半导体能源研究所 半导体器件及其制造方法
US20020015268A1 (en) * 2000-03-24 2002-02-07 Sining Mao Spin valve head using high-coercivity hard bias layer
CN1741257A (zh) * 1993-03-12 2006-03-01 株式会社半导体能源研究所 晶体管和半导体电路的制造方法
CN109727875A (zh) * 2018-12-25 2019-05-07 惠科股份有限公司 一种薄膜晶体管的制作方法和显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6713330B1 (en) * 1993-06-22 2004-03-30 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
TW272319B (zh) * 1993-12-20 1996-03-11 Sharp Kk
US6423196B1 (en) * 1997-11-19 2002-07-23 Tosoh Smd, Inc. Method of making Ni-Si magnetron sputtering targets and targets made thereby
KR100650343B1 (ko) * 2000-12-29 2006-11-27 엘지.필립스 엘시디 주식회사 박막 트랜지스터 및 그 제조방법
KR100539623B1 (ko) * 2003-06-25 2005-12-28 엘지.필립스 엘시디 주식회사 버텀 게이트형 폴리 실리콘 박막트랜지스터 소자의 제조방법
KR100928490B1 (ko) * 2003-06-28 2009-11-26 엘지디스플레이 주식회사 액정표시패널 및 그 제조 방법
KR101280827B1 (ko) * 2009-11-20 2013-07-02 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
CN101819999A (zh) * 2010-05-17 2010-09-01 广东中显科技有限公司 一种用于横向诱导晶化低温多晶硅薄膜的多层膜结构
CN107611141A (zh) * 2017-08-28 2018-01-19 深圳市华星光电技术有限公司 多晶硅基板、薄膜晶体管基板和制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1741257A (zh) * 1993-03-12 2006-03-01 株式会社半导体能源研究所 晶体管和半导体电路的制造方法
CN1102908A (zh) * 1993-06-22 1995-05-24 株式会社半导体能源研究所 半导体器件及其制造方法
US20020015268A1 (en) * 2000-03-24 2002-02-07 Sining Mao Spin valve head using high-coercivity hard bias layer
CN109727875A (zh) * 2018-12-25 2019-05-07 惠科股份有限公司 一种薄膜晶体管的制作方法和显示面板

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