CN107910378B - Ltps薄膜晶体管、阵列基板及其制作方法、显示装置 - Google Patents

Ltps薄膜晶体管、阵列基板及其制作方法、显示装置 Download PDF

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CN107910378B
CN107910378B CN201711121996.1A CN201711121996A CN107910378B CN 107910378 B CN107910378 B CN 107910378B CN 201711121996 A CN201711121996 A CN 201711121996A CN 107910378 B CN107910378 B CN 107910378B
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thin film
film transistor
ltps
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班圣光
曹占锋
姚琪
薛大鹏
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BOE Technology Group Co Ltd
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Abstract

本发明提供了一种LTPS薄膜晶体管、阵列基板及其制作方法、显示装置，属于显示技术领域。其中，LTPS薄膜晶体管的制作方法，包括：通过一次构图工艺在衬底基板上形成遮光图形和所述LTPS薄膜晶体管的有源层，所述有源层在所述衬底基板上的正投影落入所述遮光图形在所述衬底基板上的正投影中，所述遮光图形采用半导体材料制成。本发明的技术方案能够降低低温多晶硅阵列基板的制作成本，有效提升低温多晶硅阵列基板的产能。

Description

LTPS薄膜晶体管、阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，特别是指一种LTPS薄膜晶体管、阵列基板及其制作方法、显示装置。
背景技术
随着显示技术的发展，LTPS(Low Temperature Poly-silicon，低温多晶硅)背板技术由于其高的迁移率带来的高的开口率、可以实现GOA(Gate Drive on Array，栅极集成驱动)等原因，使得基于该技术的显示面板相比于基于a-Si(非晶硅)技术的显示面板具有更加优良的显示效果，正在受到越来越大的重视，也是现在小尺寸LCD(Liquid CrystalDisplay，液晶显示器)的一个重要分支。但是现有的LTPS阵列基板具有工艺复杂，成本较高的问题，相比于传统a-Si阵列基板需要4～5道Mask工艺来制作，LTPS阵列基板需要9道以上的Mask工艺来制作，使得LTPS阵列基板的生产成本较高，并且制约了LTPS阵列基板的产能。
发明内容
本发明要解决的技术问题是提供一种LTPS薄膜晶体管、阵列基板及其制作方法、显示装置，能够降低低温多晶硅阵列基板的制作成本，有效提升低温多晶硅阵列基板的产能。
为解决上述技术问题，本发明的实施例提供技术方案如下：
一方面，提供一种LTPS薄膜晶体管的制作方法，包括：
通过一次构图工艺在衬底基板上形成遮光图形和所述LTPS薄膜晶体管的有源层，所述有源层在所述衬底基板上的正投影落入所述遮光图形在所述衬底基板上的正投影中，所述遮光图形采用半导体材料制成。
进一步地，所述遮光图形采用的半导体材料的导电系数大于非晶硅的导电系数。
进一步地，利用重掺杂非晶硅制成所述遮光图形。
进一步地，所述制作方法具体包括：
在所述衬底基板上形成第一缓冲层；
在所述第一缓冲层上形成重掺杂非晶硅层；
在所述重掺杂非晶硅层上形成第二缓冲层；
在所述第二缓冲层上形成多晶硅层；
在所述多晶硅层上涂覆光刻胶，进行曝光后形成光刻胶去除区域和光刻胶保留区域，去除光刻胶去除区域的重掺杂非晶硅层、第二缓冲层和所述多晶硅层，形成所述遮光图形和所述有源层；
剥离光刻胶保留区域的光刻胶。
进一步地，所述在所述第一缓冲层上形成重掺杂非晶硅层包括：
通过等离子体增强化学气相沉积PECVD在所述第一缓冲层上形成所述重掺杂非晶硅层。
本发明实施例还提供了一种LTPS薄膜晶体管，采用如上所述的制作方法制作得到。
进一步地，在所述遮光图形采用重掺杂非晶硅制成时，所述遮光图形的厚度为
Figure BDA0001467553560000021
本发明实施例还提供了一种LTPS阵列基板的制作方法，采用如上所述的制作方法在衬底基板上制作LTPS薄膜晶体管。
本发明实施例还提供了一种LTPS阵列基板，包括位于衬底基板上的如上所述的LTPS薄膜晶体管。
本发明实施例还提供了一种显示装置，包括如上所述的LTPS阵列基板。
本发明的实施例具有以下有益效果：
上述方案中，遮光图形采用半导体材料制成，因此可以通过一次构图工艺同时形成遮光图形和LTPS薄膜晶体管的有源层，而不用通过两次构图工艺来分别形成遮光图形和有源层，降低了LTPS薄膜晶体管和LTPS阵列基板的构图次数，从而能够降低LTPS阵列基板的制作成本，有效提升LTPS阵列基板的产能。
附图说明
图1-图3为本发明实施例遮光图形采用非晶硅层的示意图；
图4为本发明实施例遮光图形采用重掺杂非晶硅层的示意图。
附图标记
1 衬底基板
2 第一缓冲层
3 非晶硅层
4 第二缓冲层
5 多晶硅层
6 栅绝缘层
7 栅金属层
8 重掺杂非晶硅层
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
现有技术中，一般采用金属Mo作为遮光图形，避免LTPS薄膜晶体管的有源层受到光照影响LTPS薄膜晶体管的器件特性，由于Mo为导体，因此，不能与有源层通过一次构图工艺来制作，需要对Mo进行构图形成遮光图形之后再进行缓冲层以及低温多晶硅材料的沉积，然后再对低温多晶硅材料进行构图形成有源层的图形，这样LTPS阵列基板需要至少9道的Mask工艺来制作，使得LTPS阵列基板的生产成本较高，并且制约了LTPS阵列基板的产能。
本发明的实施例针对现有技术中LTPS阵列基板所需的构图次数较多，生产成本较高的问题，提供一种LTPS薄膜晶体管、阵列基板及其制作方法、显示装置，能够降低低温多晶硅阵列基板的制作成本，有效提升低温多晶硅阵列基板的产能。
本发明实施例提供一种LTPS薄膜晶体管的制作方法，包括：
通过一次构图工艺在衬底基板上形成遮光图形和所述LTPS薄膜晶体管的有源层，所述有源层在所述衬底基板上的正投影落入所述遮光图形在所述衬底基板上的正投影中，所述遮光图形采用半导体材料制成。
本实施例中，遮光图形采用半导体材料制成，因此可以通过一次构图工艺同时形成遮光图形和LTPS薄膜晶体管的有源层，而不用通过两次构图工艺来分别形成遮光图形和有源层，降低了LTPS薄膜晶体管和LTPS阵列基板的构图次数，从而能够降低LTPS阵列基板的制作成本，有效提升LTPS阵列基板的产能。
其中，半导体材料可以采用非晶硅(a-Si)。如图1所示，本发明实施例LTPS薄膜晶体管包括依次位于衬底基板1上的第一缓冲层2、非晶硅层3、第二缓冲层4和多晶硅层5。其中，第一缓冲层2可以采用氮化硅或氧化硅，第二缓冲层4可以采用氧化硅，非晶硅层3用来形成遮光图形，多晶硅层5用来形成LTPS薄膜晶体管的有源层。
但是，采用非晶硅层3作为遮光图形可能会对LTPS薄膜晶体管的沟道产生一定的影响。如图2所示，LTPS薄膜晶体管还包括位于多晶硅层5上的栅绝缘层6和位于栅绝缘层6上的栅金属层7，其中，栅绝缘层6可以采用氮化硅或氧化硅制成，栅金属层7用以制作LTPS薄膜晶体管的栅电极。
如图2所示，在LTPS薄膜晶体管工作时，对栅电极施加电压，栅电极加电压以后，会在有源层即多晶硅层5的上表面感应出负电荷，使得LTPS薄膜晶体管沟道导通，进行工作，此时在多晶硅层5的下表面会有正电荷的积累，由于现有膜层结构的第二缓冲层4的厚度比较小，因此多晶硅层5下表面感应出的正电荷会对非晶硅层3有一定的影响，在非晶硅层3的上表面感应出负电荷。
因为非晶硅层3制作的遮光图形呈孤岛状，因此非晶硅层3上表面的负电荷无法被消除掉，如图3所示，在栅电极上施加的电压消除以后，非晶硅层3上表面的负电荷的存在会影响LTPS薄膜晶体管的有源层的电荷分配，影响LTPS薄膜晶体管沟道的正常工作，引起LTPS薄膜晶体管的阈值电压Vth漂移，发生Vth的负偏。
为了避免LTPS薄膜晶体管的阈值电压Vth漂移，本实施例中，可以利用导电系数大于非晶硅的导电系数的半导体材料制成遮光图形。在半导体材料的导电性能较强时，可以弱化原有遮光图形的半导体性质，减弱栅电极上加电压时对于半导体的遮光图形的影响，因此可以减弱遮光图形对于有源层的影响，使得LTPS薄膜晶体管的Vth的漂移现象也会有一定的减弱。
具体地，可以利用重掺杂非晶硅制成所述遮光图形。即如图4所示，将图1中的非晶硅层3替换为重掺杂非晶硅层(n+a-Si)8，也就是在非晶硅材料的沉积过程中加入更多的p离子，这样可以增加a-Si中的载流子浓度，将其进行导体化，以弱化原有a-Si的半导体性质，减弱栅电极上施加的电压对于其的影响，因此可以减弱遮光图形对有源层的影响，从而减弱或消除LTPS薄膜晶体管的Vth漂移的问题。
具体地，本实施例的LTPS薄膜晶体管的制作方法包括以下步骤：
步骤1、提供一衬底基板1，在衬底基板1上形成第一缓冲层2；
其中，衬底基板1可为玻璃基板或石英基板。具体地，可以采用等离子体增强化学气相沉积(PECVD)方法在衬底基板1上沉积第一缓冲层2，第一缓冲层2可以选用氧化物、氮化物或者氧氮化合物。
步骤2、在第一缓冲层2上形成重掺杂非晶硅层8；
本实施例中，采用PECVD方法在第一缓冲层2上沉积重掺杂非晶硅层8，其中，PECVD的工艺参数具体可以如下：沉积温度为250℃，沉积功率为300W,沉积基板的工作距离为1000mil,沉积压强为1230mtorr，反应气体为SiH4(气体流量为190sccm),H2(气体流量为1250sccm),PH3(气体流量为250sccm),其中。通过该方法可以得到导电性能较好的重掺杂非晶硅层8，以减弱遮光图形的半导体特性，使得LTPS薄膜晶体管的Vth的漂移现象有一定程度的减弱，进而保证LTPS薄膜晶体管的性能。
通过PECVD方法得到的重掺杂非晶硅层8的膜层内部是均匀的p离子，p离子在重掺杂非晶硅层8的表面和内部的浓度不存在差异。而如果通过掺杂的方法制备重掺杂非晶硅层8的话，即在非晶硅层中进行p离子的掺杂，由于Doping(掺杂)本身的特性，掺杂的p离子只会大多数存在于非晶硅层的表面，而在非晶硅层的内部存在较少的p离子，所以Doping的方法并不能够有效改善LTPS薄膜晶体管的Vth的漂移现象。
如表1所示，通过PECVD方法和通过掺杂方法得到的两种含有p离子的非晶硅层内部的载流子浓度以及方块电阻存在较大的差异：
表1
实现手段 PECVD Doping
电子浓度/cm<sup>3</sup> 3*10<sup>17</sup> 1*10<sup>15</sup>
方块电阻/Ω/口 400左右 20000左右
由上表可知，以掺杂浓度来衡量的话，通过PECVD方法得到的n+a-Si的电子浓度比通过Doping方法得到的n+a-Si的电子浓度高了2个数量级；从最终的电阻效果来看，通过PECVD方法得到的n+a-Si的电阻小于1000，导电性能较好，而通过Doping方法得到的n+a-Si则电阻较大，导电性能较差，不能有效改善LTPS薄膜晶体管的Vth的漂移现象。
步骤3、在重掺杂非晶硅层8上形成第二缓冲层4；
具体地，可以采用等离子体增强化学气相沉积方法在重掺杂非晶硅层8上沉积第二缓冲层4，第二缓冲层4可以选用氧化物、氮化物或者氧氮化合物。
步骤4、在第二缓冲层4上形成多晶硅层5，并通过构图工艺形成遮光图形和LTPS薄膜晶体管的有源层。
具体地，可以在多晶硅层5上涂覆光刻胶，进行曝光后形成光刻胶去除区域和光刻胶保留区域，之后去除光刻胶去除区域的重掺杂非晶硅层8、第二缓冲层4和多晶硅层5，形成遮光图形和LTPS薄膜晶体管的有源层，然后剥离光刻胶保留区域的光刻胶。
之后可以通过现有制作工艺制备LTPS薄膜晶体管的栅绝缘层、栅电极、层间绝缘层、源电极和漏电极以形成LTPS薄膜晶体管，在此不再进行赘述。
本发明实施例还提供了一种LTPS薄膜晶体管，采用如上所述的制作方法制作得到。
本实施例中，LTPS薄膜晶体管的遮光图形采用半导体材料制成，因此可以通过一次构图工艺同时形成遮光图形和LTPS薄膜晶体管的有源层，而不用通过两次构图工艺来分别形成遮光图形和有源层，降低了LTPS薄膜晶体管和LTPS阵列基板的构图次数，从而能够降低LTPS阵列基板的制作成本，有效提升LTPS阵列基板的产能。
优选地，遮光图形采用重掺杂非晶硅制成，这样可以减弱遮光图形的半导体特性，减弱LTPS薄膜晶体管的栅电极上施加的电压对于遮光图形的影响，因此可以减弱遮光图形对LTPS薄膜晶体管的有源层的影响，从而减弱或消除LTPS薄膜晶体管的Vth漂移的问题，进而保证LTPS薄膜晶体管的性能。
经过实验可以验证，将LTPS薄膜晶体管的遮光图形的材料由a-Si改为n+a-Si后，LTPS薄膜晶体管的Vth漂移情况有较大的改善。
进一步地，在所述遮光图形采用重掺杂非晶硅制成时，所述遮光图形的厚度为
Figure BDA0001467553560000071
在遮光图形达到此厚度时，既可以起到遮光的作用又可以不会使得LTPS薄膜晶体管的厚度过大。
本发明实施例还提供了一种LTPS阵列基板的制作方法，采用如上所述的制作方法在衬底基板上制作LTPS薄膜晶体管。
本实施例中，LTPS薄膜晶体管的遮光图形采用半导体材料制成，因此可以通过一次构图工艺同时形成遮光图形和LTPS薄膜晶体管的有源层，而不用通过两次构图工艺来分别形成遮光图形和有源层，降低了LTPS薄膜晶体管和LTPS阵列基板的构图次数，从而能够降低LTPS阵列基板的制作成本，有效提升LTPS阵列基板的产能。
优选地，LTPS阵列基板的遮光图形采用重掺杂非晶硅制成，这样可以减弱遮光图形的半导体特性，减弱LTPS薄膜晶体管的栅电极上施加的电压对于遮光图形的影响，因此可以减弱遮光图形对LTPS薄膜晶体管的有源层的影响，从而减弱或消除LTPS薄膜晶体管的Vth漂移的问题，进而保证LTPS薄膜晶体管的性能。
本发明实施例还提供了一种LTPS阵列基板，包括位于衬底基板上的如上所述的LTPS薄膜晶体管。
本实施例中，LTPS薄膜晶体管的遮光图形采用半导体材料制成，因此可以通过一次构图工艺同时形成遮光图形和LTPS薄膜晶体管的有源层，而不用通过两次构图工艺来分别形成遮光图形和有源层，降低了LTPS薄膜晶体管和LTPS阵列基板的构图次数，从而能够降低LTPS阵列基板的制作成本，有效提升LTPS阵列基板的产能。
优选地，LTPS阵列基板的遮光图形采用重掺杂非晶硅制成，这样可以减弱遮光图形的半导体特性，减弱LTPS薄膜晶体管的栅电极上施加的电压对于遮光图形的影响，因此可以减弱遮光图形对LTPS薄膜晶体管的有源层的影响，从而减弱或消除LTPS薄膜晶体管的Vth漂移的问题，进而保证LTPS薄膜晶体管的性能。
本发明实施例还提供了一种显示装置，包括如上所述的LTPS阵列基板。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
在本发明各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本发明的保护范围之内。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下″时，该元件可以“直接″位于另一元件“上″或“下″，或者可以存在中间元件。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (8)

1.一种LTPS薄膜晶体管的制作方法，其特征在于，包括：
通过一次构图工艺在衬底基板上形成遮光图形和所述LTPS薄膜晶体管的有源层，所述有源层在所述衬底基板上的正投影落入所述遮光图形在所述衬底基板上的正投影中，所述遮光图形采用半导体材料制成；
通过等离子体增强化学气相沉积PECVD利用重掺杂非晶硅制成所述遮光图形，所述重掺杂非晶硅中的p离子分布均匀，p离子在所述重掺杂非晶硅层的表面和内部的浓度不存在差异，所述遮光图形的方块电阻小于1000Ω/口。
2.根据权利要求1所述的LTPS薄膜晶体管的制作方法，其特征在于，所述制作方法具体包括：
在所述衬底基板上形成第一缓冲层；
在所述第一缓冲层上形成重掺杂非晶硅层；
在所述重掺杂非晶硅层上形成第二缓冲层；
在所述第二缓冲层上形成多晶硅层；
在所述多晶硅层上涂覆光刻胶，进行曝光后形成光刻胶去除区域和光刻胶保留区域，去除光刻胶去除区域的重掺杂非晶硅层、第二缓冲层和所述多晶硅层，形成所述遮光图形和所述有源层；
剥离光刻胶保留区域的光刻胶。
3.根据权利要求2所述的LTPS薄膜晶体管的制作方法，其特征在于，所述在所述第一缓冲层上形成重掺杂非晶硅层包括：
通过等离子体增强化学气相沉积PECVD在所述第一缓冲层上形成所述重掺杂非晶硅层。
4.一种LTPS薄膜晶体管，其特征在于，采用如权利要求1-3中任一项所述的制作方法制作得到。
5.根据权利要求4所述的LTPS薄膜晶体管，其特征在于，在所述遮光图形采用重掺杂非晶硅制成时，所述遮光图形的厚度为
Figure FDF0000010724500000011
6.一种LTPS阵列基板的制作方法，其特征在于，采用如权利要求1-3中任一项所述的制作方法在衬底基板上制作LTPS薄膜晶体管。
7.一种LTPS阵列基板，其特征在于，包括位于衬底基板上的如权利要求4或5所述的LTPS薄膜晶体管。
8.一种显示装置，其特征在于，包括如权利要求7所述的LTPS阵列基板。
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US10741692B2 (en) 2020-08-11

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