WO2020187237A1 - 薄膜晶体管及其制备方法和显示装置 - Google Patents

薄膜晶体管及其制备方法和显示装置 Download PDF

Info

Publication number
WO2020187237A1
WO2020187237A1 PCT/CN2020/079924 CN2020079924W WO2020187237A1 WO 2020187237 A1 WO2020187237 A1 WO 2020187237A1 CN 2020079924 W CN2020079924 W CN 2020079924W WO 2020187237 A1 WO2020187237 A1 WO 2020187237A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate
thin film
film transistor
active layer
Prior art date
Application number
PCT/CN2020/079924
Other languages
English (en)
French (fr)
Inventor
任艳伟
石天雷
唐乌力吉白尔
徐敬义
于亚楠
孙超超
刘敏
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/054,711 priority Critical patent/US20210066504A1/en
Publication of WO2020187237A1 publication Critical patent/WO2020187237A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a thin film transistor, a preparation method thereof, and a display device.
  • the gate of the thin film transistor is formed on a glass substrate
  • other film layers of the thin film transistor are directly formed on the glass substrate in sequence.
  • the gate formed on the glass substrate is an upwardly convex structure relative to the glass substrate itself, so that it is sequentially formed on the raised structure (ie, the gate)
  • the other film layers of the thin film transistor may also be deformed and convex, which will cause the carrier migration in the active layer of the thin film transistor to be blocked when the thin film transistor is working, thereby greatly reducing the thin film transistor performance.
  • the present disclosure provides a new method for manufacturing thin film transistors.
  • a thin film transistor provided by the present disclosure includes a substrate, a gate, a gate insulating layer, an active layer, and a source-drain layer which are sequentially arranged on the substrate; the source-drain layer is correspondingly located on the second layer of the active layer.
  • the material of the flat layer includes acrylic and transparent resin.
  • the thickness of the gate insulating layer includes
  • the material of the active layer includes low temperature polysilicon.
  • the present disclosure also provides a method for manufacturing a thin film transistor, including: sequentially forming a gate, a gate insulating layer, an active layer, and a source-drain layer on a substrate, the source-drain layer being formed on the first active layer The source contact area and the first drain contact area; wherein, after the gate is formed, a flat layer is also formed, the flat layer and the gate are in the same layer and are in close contact, and the flat layer The surface is flush with the upper surface of the grid.
  • the step of forming a gate and a flat layer includes: forming a gate pattern on a substrate through a patterning process; depositing a flat layer material on the substrate on which the gate is formed; The flat layer material is exposed, developed, and cured to form a flat layer pattern, and the flat layer pattern is dry-etched to leak the upper surface of the gate.
  • the dry etching makes the upper surface of the flat layer It is flush with the upper surface of the grid.
  • the dry etching includes deslagging and ashing treatment.
  • the step of forming the gate insulating layer includes: depositing a gate insulating layer material on the substrate on which the gate and the planarization layer are formed, and the thickness of the gate insulating layer is to
  • the step of forming the active layer includes:
  • the material of the active layer includes low temperature polysilicon.
  • the step of forming the source and drain layers includes: forming a photoresist layer above the active layer after the first ion implantation has been performed through a patterning process, and the photoresist layer partially covers The active layer allows the active to leak out of the first source contact area and the first drain contact area, and performs a second time on the first source contact area and the first drain contact area of the active layer Ion implantation; and reducing the width of the photoresist pattern by exposure and dry etching to leak out the second source contact area and the second drain contact area of the active layer, and to the second source of the active layer Performing a third ion implantation on the electrode contact area and the second drain contact area; and removing the photoresist layer by etching, on the first source contact area and the first drain contact area of the active layer
  • the source and drain layers are formed on corresponding positions.
  • the material of the flat layer includes acrylic and transparent resin.
  • the present disclosure also provides a display device including the above-mentioned thin film transistor.
  • FIG. 1 is a schematic diagram of the structure of a thin film transistor according to some embodiments of the disclosure.
  • FIGS. 2 to 4 are process cross-sectional views of a method for manufacturing a thin film transistor according to some embodiments of the disclosure
  • FIG. 5 is a flowchart of process steps of a method for manufacturing a thin film transistor according to some embodiments of the disclosure.
  • the thin film transistor is a bottom-gate thin film transistor as an example for description.
  • the thin film transistors of this embodiment are not limited to bottom-gate thin film transistors, which are not limited here.
  • This embodiment provides a thin film transistor including: a substrate 10, a gate electrode 1, a gate insulating layer 3, an active layer 4, and a first source contact area 5 electrically connected to the active layer 4 sequentially disposed on the substrate 10.
  • the connected source 9 and the drain 11 electrically connected to the first drain contact region 6 of the active layer 4; in particular, in this embodiment, a flat layer 2 is provided between the substrate 10 and the gate insulating layer 3 , The flat layer 2 and the gate 1 are in the same layer and are in close contact, and the upper surface of the flat layer 2 is flush with the upper surface of the gate 1.
  • the planarization layer 2 of this embodiment is in close contact with the gate 1 and the upper surface of the planarization layer 2 is flush with the upper surface of the gate 1, the upper surface of the gate insulating layer 3 disposed above the layer where the gate 1 is located is A plane parallel to the substrate 10, so that the upper and lower surfaces of the active layer 4 formed on the gate insulating layer 3 are relatively flat. In this way, it can be avoided in the prior art that the convex gate 1 is directly formed.
  • other film layers of the thin film transistor are sequentially formed, which causes the active layer 4 to undergo bump deformation; further, it also solves the problem that the active layer 4 is caused by the bumps of the thin film transistor. During operation, the migration of carriers in the active layer 4 is hindered, which affects the performance of the thin film transistor.
  • the gate 1 is arranged corresponding to the active layer 4, that is, the gate 1 is on the substrate 101.
  • the projection at least partially covers the orthographic projection of the active layer 4 on the substrate 10.
  • the gate 1 itself is an opaque structure
  • the thin film transistor of this embodiment when used to prepare a liquid crystal display, the backlight in the liquid crystal display
  • the light emitted by the source cannot be irradiated to the active layer 4 through the gate 1, so as to prevent the light from irradiating to the active layer 4, which causes the photoelectric effect of the active layer 4 and the leakage of electricity; at the same time, this structure No additional masking process is required to form the light shielding layer for shielding the active layer 4, thereby simplifying the manufacturing process of the thin film transistor of this embodiment and reducing the production cost.
  • the thickness of the gate insulating layer 3 includes
  • the thicker gate insulating layer 3 not only separates the active layer 4 of the thin film transistor from the gate 1, but also ensures that the gate There is a certain distance between the electrode 1 and the source 9 and the drain 11, so as to avoid the signal interference between the source 9, the drain 11 and the gate 1 of the thin film transistor, so as to ensure that the thin film transistor of this embodiment is included.
  • the display device has a better display effect.
  • the material of the flat layer 2 includes acrylic and transparent resin.
  • acrylic and transparent resin materials are a good leveling agent, which can make the flat layer 2 prepared by the leveling process have a flat, smooth and uniform surface. In this way, it is further ensured that the flat layer 2 and the gate 1 form a flat surface.
  • the material of the flat layer 2 in this embodiment is not limited to the aforementioned acrylic and transparent resin, and is not limited here.
  • the active layer material of the thin film transistor includes low temperature polysilicon, that is, the thin film transistor in this embodiment is a low temperature polysilicon thin film transistor.
  • the thin film transistors of this embodiment are not limited to the aforementioned low-temperature polysilicon thin film transistors, and will not be repeated here.
  • This embodiment provides a method for preparing a thin film transistor, wherein the thin film transistor in Embodiment 1 can be prepared by the method of this embodiment.
  • the preparation method includes the steps of sequentially forming the gate 1, the gate insulating layer 3, the active layer 4, the source 9 and the drain 11 on the substrate 10; the source 9 and the drain 11 are formed correspondingly The first source contact region 5 and the first drain contact region 6 of the active layer 4, in particular, the preparation method of the embodiment further includes the step of forming a flat layer 2 between the substrate 10 and the gate insulating layer 3 Wherein, the formed flat layer 2 and the gate 1 are in the same layer and are in close contact, and the upper surface of the flat layer 2 and the upper surface of the gate 1 are flush.
  • the patterning process may include only a photolithography process, or, a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • the photolithography process refers to Including film formation, exposure, development and other processes, the use of photoresist, mask, exposure machine and other processes to form patterns.
  • the corresponding patterning process can be selected according to the structure formed in the present disclosure.
  • the process flow chart of the manufacturing method of the thin film transistor is shown in FIGS. 2 to 4, and the method includes the following steps S1 to S5:
  • Step S1 On the substrate 10, the gate electrode 1 is formed by a patterning process.
  • the substrate 10 is made of transparent materials such as glass, and has been cleaned in advance.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • APCVD atmospheric pressure Atmospheric Pressure Chemical Vapor Deposition
  • ECR-CVD Electron Cyclotron Resonance Chemical Vapor Deposition
  • the material of the gate metal film includes metals and metal alloys, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium or copper and other conductive materials.
  • Step S2 through the patterning process on the substrate 10 after step S1, a pattern including the flat layer 2 is formed; wherein the flat layer 2 and the gate 1 are in the same layer and are in close contact, and the upper surface of the flat layer 2 and the gate 1 The upper surface is flush.
  • a flat layer material is deposited on the substrate 10, and the flat layer material is exposed, developed, and cured to form a flat layer pattern, and the flat layer pattern is dry-etched to The upper surface of the gate 1 leaks out, and the upper surface of the flat layer 2 is flush with the upper surface of the gate 1 by the dry etching.
  • the dry etching further includes a deslagging (Descum) ashing process to further ensure the flattening of the upper surface of the planarization layer 2 and the upper surface of the gate 1, and ensure that the upper surface of the gate 1 The surface leaks outside.
  • deslagging Descum
  • the material of the flat layer 2 includes acrylic or transparent resin.
  • the material of the flat layer 2 in this embodiment is not limited to the aforementioned acrylic and transparent resin, and is not limited here.
  • Step S3 forming a gate insulating layer 3 on the substrate 10 after step S2.
  • the gate insulating layer 3 can be formed by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
  • the material of the gate insulating layer 3 includes silicon oxide, silicon nitride or a composite material of the two. Of course, it is not limited to these two materials.
  • the thickness of the gate insulating layer 3 includes
  • the thicker gate insulating layer 3 not only separates the active layer 4 of the thin film transistor from the gate 1, but also ensures that the gate There is a certain distance between the electrode 1 and the source 9 and the drain 11, so as to avoid the signal interference between the source 9, the drain 11 and the gate 1 of the thin film transistor, so as to ensure that the thin film transistor of this embodiment is included.
  • the display device has a better display effect.
  • Step S4 on the substrate 10 after the step S3 is completed, a pattern including the active layer 4 is formed through a patterning process.
  • the active layer material is deposited on the gate insulating layer, the active layer pattern is formed through a patterning process, and the first ion implantation is performed on the active layer.
  • an amorphous silicon film (a-Si) can be formed.
  • the deposition methods include plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition.
  • the amorphous silicon film is crystallized.
  • the crystallization method includes the use of excimer laser crystallization method, metal induced crystallization method or solid phase crystallization method to convert the amorphous silicon film into a polysilicon film (p-Si), Among them, the excimer laser crystallization method and the metal-induced crystallization method are two low-temperature polysilicon methods, which are more commonly used methods for converting amorphous silicon into polysilicon.
  • the method of converting amorphous silicon into polysilicon in the present disclosure is not limited to the method using low-temperature polysilicon, as long as the active layer 4 can be converted into a desired polysilicon film.
  • a pattern including the active layer 4 is formed. That is, a layer of photoresist is formed on the polysilicon film, the photoresist is exposed and developed, and then the polysilicon film is dry-etched to form a pattern including the active layer 4. After that, the active layer 4 (p-Si) is doped for the first time by ion implantation.
  • the ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method or a solid diffusion implantation method. That is, in this embodiment, the low-temperature polysilicon material undergoes multiple steps such as crystallization, doping, and ion implantation to finally form the active layer 4 with good semiconductor properties.
  • Step S5 On the substrate 10 after step S4, a pattern including the source electrode 9 and the drain electrode 11 of the thin film transistor is formed by a patterning process.
  • a photoresist layer 12 is formed above the active layer 4 after the first ion implantation has been performed, and the photoresist layer 12 partially covers The active layer 4 makes the active layer 4 leak out the first source contact area 5 and the first drain contact area 6.
  • the first source contact region 5 and the first drain contact region 6 of the active layer 4 are subjected to a second ion implantation, that is, P-type doping or N-type doping is performed to determine the channel of the thin film transistor TFT Area conductivity type.
  • the width of the photoresist layer 12 is further reduced by exposure and dry etching to leak the second source contact area 7 and the second drain contact area 8 of the active layer 4.
  • the thin film transistor of the present disclosure adopts a bottom gate structure process, and controls the width of the photoresist (PR) through exposure and dry etching to form the required doped area, which can accurately control the ion implantation amount, and the doping method is simple Easy.
  • the second source contact region 7 and the second drain contact region 8 of the active layer 4 are subjected to a third ion implantation, that is, LDD doping is performed.
  • LDD is doped with a lower concentration to enhance the active
  • the layer 4 is in ohmic contact with the source 9 and the drain 11 to prevent the component from generating hot carrier effects, and to ensure that the active layer 4 forms a good ohmic contact with the source 5 and the drain 6.
  • the photoresist layer 12 is removed by etching, and the source electrode 9 and the source electrode 9 and the corresponding position on the first source electrode contact region 5 and the first drain contact region 6 of the active layer 4 are formed.
  • Drain 11 the source 9 and the drain 11 may be formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.
  • a source and drain metal film is formed, and a photoresist is formed on the source and drain metal film, and then a pattern including the source electrode 5 and the drain electrode 6 of the thin film transistor is formed through exposure, development, and etching processes.
  • the source and drain metal film materials include metals and metal alloys, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium or copper and other conductive materials.
  • step S2 that is, in other embodiments, the flat layer 2 is formed without a patterning process, but a leveling process.
  • a pattern including a flat layer 2 is formed on the substrate 10 after step S1 is completed by a leveling process; wherein the flat layer 2 and the gate 1 are in the same layer and are in close contact, and the upper surface of the flat layer 2 and the gate 1 The upper surface of 1 is flush.
  • the material of the flat layer 2 includes acrylic or transparent resin.
  • acrylic and transparent resin materials are a good leveling agent, which can make the flat layer 2 prepared by the leveling process have a flat, smooth and uniform surface. In this way, it is further ensured that the flat layer 2 and the upper surface of the gate 1 form a flat surface.
  • the method of manufacturing the thin film transistor of this embodiment includes the step of forming a flat layer 2, the flat layer 2 and the gate 1 are in the same layer and are in close contact, and the upper surface of the flat layer 2 is flush with the upper surface of the gate 1 Therefore, the upper surface of the gate insulating layer 3 disposed above the layer where the gate 1 is located is a plane parallel to the substrate 10, so that the upper and lower surfaces of the active layer 4 formed on the gate insulating layer 3 are relatively flat.
  • the embodiment of the present disclosure also provides a display device including the thin film transistor in the above embodiment. Since the display device of this embodiment includes the above thin film transistor, the display device of this embodiment has a better display effect.
  • the display device can be a liquid crystal display device or an electroluminescent display device, such as liquid crystal panels, electronic paper, OLED panels, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, etc., which have display functions. Products or parts.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制备方法和显示装置，该薄膜晶体管包括：基底（10），依次设置在所述基底（10）上的栅极（1）、栅绝缘层（3）、有源层（4）以及源漏极层；所述源漏极层相应的位于所述有源层（4）第一源极接触区（5）和第一漏极接触区（6）上；其中，在所述栅绝缘层（3）和所述基底（10）之间还设置有平坦层（2），所述平坦层（2）与所述栅极（1）处于同一层且紧密接触，且所述平坦层（2）的上表面与所述栅极（1）的上表面平齐。

Description

薄膜晶体管及其制备方法和显示装置
相关申请的交叉引用
本申请要求于2019年3月20日提交的中国专利申请No.201910214175.5的优先权，在此将其以引用方式整体并入本文。
技术领域
本公开属于显示技术领域，具体涉及一种薄膜晶体管及其制备方法和显示装置。
背景技术
在传统的底栅型薄膜晶体管的制备工艺中，薄膜晶体管的栅极形成在玻璃基底上之后，直接在该玻璃基底上依次形成薄膜晶体管的其它膜层。此时，很容易理解的是，形成在玻璃基底上的栅极相对于玻璃基底本身而言，是一个向上凸起的结构，这样一来，依次形成在该凸起结构(即栅极)上的薄膜晶体管的其它膜层(例如：薄膜晶体管的有源层)也有可能发生变形凸起，从而导致薄膜晶体管在进行工作时，有源层中的载流子迁移受阻，进而大大降低薄膜晶体管的性能。
为解决上述问题，本公开提供了一种新的薄膜晶体管的制备方法。
发明内容
本公开提供的一种薄膜晶体管，包括：基底，依次设置在所述基底上的栅极、栅绝缘层、有源层以及源漏极层；所述源漏极层相应的位于有源层第一源极接触区和第一漏极接触区上；其中，在所述栅绝缘层和所述基底之间还设置有平坦层，所述平坦层与所述栅极处于同一层且紧密接触，且所述平坦层的上表面与所述栅极的上表面平齐。
在一些实施例中，所述平坦层的材料包括丙烯酸、透明树 脂。
在一些实施例中，所述栅绝缘层的厚度包括
Figure PCTCN2020079924-appb-000001
在一些实施例中，所述有源层的材料包括低温多晶硅。
本公开还提供一种薄膜晶体管的制备方法，包括：在基底上依次形成栅极、栅绝缘层、有源层以及源漏极层，所述源漏极层相应的形成于有源层第一源极接触区和第一漏极接触区上；其中，在形成所述栅极之后还形成平坦层，所述平坦层与所述栅极处于同一层且紧密接触，且所述平坦层的上表面和所述栅极的上表面平齐。
在一些实施例中，所述形成栅极和平坦层的步骤，包括：在基底上，通过构图工艺形成栅极图案；在形成有所述栅极的基底上沉积平坦层材料，并对所述平坦层材料进行曝光、显影、固化工艺形成平坦层图案，并对所述平坦层图案进行干法刻蚀以漏出栅极的上表面，通过所述干法刻蚀使得所述平坦层的上表面与所述栅极的上表面平齐。
在一些实施例中，所述干法刻蚀包括除渣灰化处理。
在一些实施例中，所述形成栅绝缘层的步骤包括：在形成有所述栅极和平坦层的基底上沉积栅绝缘层材料，所述栅绝缘层的厚度为
Figure PCTCN2020079924-appb-000002
至
Figure PCTCN2020079924-appb-000003
在一些实施例中，所述形成有源层的步骤包括：
在栅绝缘层上沉积有源层材料，并通过构图工艺形成有源层图案；以及对所述有源层进行第一次离子注入。
在一些实施例中，所述有源层的材料包括低温多晶硅。
在一些实施例中，所述形成源漏极层的步骤包括：通过构图工艺，对已经进行第一次离子注入之后的有源层的上方形成光刻胶层，所述光刻胶层部分覆盖所述有源层，使得所述有源漏出第一源极接触区和第一漏极接触区，对所述有源层的第一源极接触区和第一漏极接触区进行第二次离子注入；以及通过曝光和干刻减小所述光刻胶图案的宽度，以漏出有源层的第二源极接触区和第二漏极接触区，对所述有源层的第二源极接触区和第 二漏极接触区进行第三次离子注入；以及通过刻蚀去除所述光刻胶层，在所述有源层的第一源极接触区和第一漏极接触区上相应位置上形成所述源漏极层。
在一些实施例中，所述平坦层的材料包括丙烯酸、透明树脂。
本公开还提供一种显示装置，所述显示装置包括上述的薄膜晶体管。
附图说明
图1为本公开的一些实施例的薄膜晶体管的结构示意图；
图2至图4为本公开的一些实施例的薄膜晶体管的制备方法的工艺截面图；
图5为本公开的一些实施例的薄膜晶体管的制备方法的工艺步骤流程图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
其中，为便于清楚地理解本实施例的意图，在本实施例中，以薄膜晶体管为底栅型薄膜晶体管为例进行说明。当然，本实施例的薄膜晶体管并不局限于底栅型薄膜晶体管，在此不做限定。
本实施例提供一种薄膜晶体管，包括：基底10，依次设置在基底10上的栅极1、栅绝缘层3、有源层4，以及与有源层4的第一源极接触区5电连接的源极9、与有源层4的第一漏极接触区6电连接的漏极11；特别的是，在本实施例中，基底10与栅绝缘层3之间设置有平坦层2，平坦层2与栅极1处于同一层且紧密接触，且平坦层2的上表面与栅极1的上表面平齐。
由于本实施例的平坦层2与栅极1紧密接触，且平坦层2的上表面与栅极1的上表面平齐，故设置在栅极1所在层上方的栅绝缘层3的上表面是一与基底10平行的平面，从而使得形成在栅绝缘层3上的有源层4上下表面均较为平整，这样一来，即可避免现有技术中，直接在形成有栅极1这一凸起结构的基底10上， 依次形成薄膜晶体管的其他膜层，所导致的有源层4发生凸起变形的情况；进一步地，还解决了有源层4发生凸起所导致的、薄膜晶体管在进行工作时，有源层4中的载流子迁移受阻，影响薄膜晶体管的性能的问题。
另外，在此应当注意的是，由图1还可以看出：在本实施例的薄膜晶体管中，栅极1是与有源层4对应设置的，也即栅极1在基底101上的正投影至少部分覆盖有源层4在基底10上的正投影，此时，由于栅极1本身为不透光结构，故当本实施例的薄膜晶体管用于制备液晶显示器时，液晶显示器中的背光源所发出的光线无法通过栅极1照射至有源层4，从而避免光线照射至有源层4，所导致的有源层4发生光电效应，出现漏电的情况；与此同时，该种结构设置无需额外进行掩膜工艺，以形成用以遮挡有源层4的遮光层，从而简化了本实施例的薄膜晶体管的制备工艺，降低生产成本。
在一些实施例中，栅绝缘层3的厚度包括
Figure PCTCN2020079924-appb-000004
在此需要说明的是，之所以这样设置是因为，在本实施例中，较厚的栅绝缘层3的作用不仅是将薄膜晶体管的有源层4与栅极1隔开，同时还保证栅极1与源极9、漏极11之间存在一定距离，从而避免薄膜晶体管的源极9、漏极11与栅极1之间的信号发生干扰，以此来确保包括本实施例的薄膜晶体管的显示装置具有较佳的显示效果。
其中，在一些实施例中，平坦层2的材料包括丙烯酸、透明树脂。之所以采用这些材料来制备平坦层2是因为，丙烯酸和透明树脂材料是一种良好的流平剂，其能够使得通过流平工艺制备所得的平坦层2具有一个平整、光滑、均匀的表面，以此来进一步确保平坦层2与栅极1构成一个平整的表面。当然，本实施例的平坦层2的材料并不局限于前述的丙烯酸、透明树脂，在此不做限定。
其中，在一些实施例中，薄膜晶体管的有源层材料包括低温多晶硅，也即本实施例中的薄膜晶体管为低温多晶硅薄膜晶体管。当然，本实施例的薄膜晶体管并不局限于前述的低温多晶硅薄膜 晶体管，在此不再一一赘述。
本实施例提供一种薄膜晶体管的制备方法，其中，实施例1中的薄膜晶体管可采用本实施例的制备方法进行制备。具体的，该制备方法包括在基底10上依次形成栅极1、栅绝缘层3、有源层4以及源极9和漏极11的步骤；所述源极9和漏极11相应的形成在有源层4的第一源极接触区5和第一漏极接触区6，特别的是，在实施例的制备方法中还包括在基底10和栅绝缘层3之间形成平坦层2的步骤；其中，所形成的平坦层2与栅极1处于同一层且紧密接触，且该平坦层2的上表面和栅极1的上表面平齐。
为了更清楚本实施例中的薄膜晶体管的制备方法，本实施例中给出以下几种具体制备工艺步骤，具体如下：
在本公开中，构图工艺，可只包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公开中所形成的结构选择相应的构图工艺。
在一些实施例中，薄膜晶体管的制备方法的工艺流程图如图2至图4所示，所述方法包括如下步骤S1至S5：
步骤S1、在基底10上，通过构图工艺形成包括栅极1。
具体的，基底10采用玻璃等透明材料制成、且经过预先清洗。具体的，在基底10上采用溅射方式、热蒸发方式、等离子体增强化学气相沉积(Plasma Enhanced Vapor Deposition：简称PECVD)方式、低压化学气相沉积(Low Pressure Chemical Vapor Deposition：简称LPCVD)方式、大气压化学气相沉积(Atmospheric Pressure Chemical Vapor Deposition：简称APCVD)方式或电子回旋谐振化学气相沉积(Electron Cyclotron Resonance Chemical Vapor Deposition:简称ECR-CVD)方式形成栅金属薄膜，并在栅金属薄膜上形成光刻胶，之后通过曝光、显影、刻蚀工艺形成包括薄膜晶体管的栅极1的图形。
其中，栅金属薄膜的材料包括金属、金属合金，如：钼、钼铌合金、铝、铝钕合金、钛或铜等导电材料形成。
步骤S2、在完成步骤S1的基底10上通过构图工艺，形成包括平坦层2的图形；其中，平坦层2与栅极1处于同一层且紧密接触，且平坦层2的上表面与栅极1的上表面平齐。
具体的，如图2所示，在基底10上沉积平坦层材料，并对所述平坦层材料进行曝光、显影、固化工艺形成平坦层图案，并对所述平坦层图案进行干法刻蚀以漏出栅极1的上表面，通过所述干法刻蚀使得所述平坦层2的上表面与所述栅极1的上表面平齐。
应当说明的是，所述干法刻蚀还进一步包括除渣(Descum)灰化处理，进一步保证平坦层2的上表面与所述栅极1的上表面的平坦化，并保证栅极1上表面漏在外面。
其中，平坦层2的材料包括：丙烯酸或者透明树脂。当然，本实施例的平坦层2的材料并不局限于前述的丙烯酸、透明树脂，在此不做限定。
步骤S3、在完成步骤S2的基底10上，形成栅绝缘层3。
具体的，在该步骤中可以采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式形成栅绝缘层3。
其中，栅绝缘层3的材料包括氧化硅、氮化硅或者二者的复合材料。当然，也不局限于这两种材料。
其中，栅绝缘层3的厚度包括
Figure PCTCN2020079924-appb-000005
在此需要说明的是，之所以这样设置是因为，在本实施例中，较厚的栅绝缘层3的作用不仅是将薄膜晶体管的有源层4与栅极1隔开，同时还保证栅极1与源极9、漏极11之间存在一定距离，从而避免薄膜晶体管的源极9、漏极11与栅极1之间的信号发生干扰，以此来确保包括本实施例的薄膜晶体管的显示装置具有较佳的显示效果。
步骤S4、在完成步骤S3的基底10上，通过构图工艺形成包括有源层4图案。
具体的，在该步骤中，在栅绝缘层上沉积有源层材料，并通 过构图工艺形成有源层图案，以及对所述有源层进行第一次离子注入。
首先可以形成非晶硅膜(a-Si)，沉积方式包括等离子体增强化学气相沉积方式、低压化学气相沉积方式。接着，对非晶硅膜进行晶化，晶化方式包括采用准分子激光晶化方式、金属诱导晶化方式或固相晶化方式，将非晶硅膜转变为多晶硅膜(p-Si)，其中，准分子激光晶化方式、金属诱导晶化方式为两种低温多晶硅的方法，是较为常用的把非晶硅转变为多晶硅的方法。然而，本公开将非晶硅转变为多晶硅的方法，并不限制于采用低温多晶硅的方法，只要能够将有源层4转变为所需的多晶硅薄膜就可以。之后，形成包括有源层4的图形。即在多晶硅膜上形成一层光刻胶，对光刻胶进行曝光和显影，然后对多晶硅膜进行干法刻蚀，以形成包括有源层4的图形。之后，采用离子注入法，将有源层4(p-Si)进行第一次掺杂。其中，离子注入法包括具有质量分析仪的离子注入方式、不具有质量分析仪的离子云式注入方式、等离子注入方式或固态扩散式注入方式。即本实施例中，由低温多晶硅材料经晶化、掺杂、离子注入等多个步骤，最终形成具有良好半导体性质的有源层4。
步骤S5、在完成步骤S4的基底10上，通过构图工艺形成包括薄膜晶体管的源极9和漏极11的图案。
具体的，在该步骤中，如图3所示，通过构图工艺，对已经进行第一次离子注入之后的有源层4的上方形成光刻胶层12，所述光刻胶层12部分覆盖所述有源层4，使得所述有源层4漏出第一源极接触区5和第一漏极接触区6。
然后，对有源层4的第一源极接触区5和第一漏极接触区6进行第二次离子注入，即进行P型掺杂或者N型掺杂，以决定薄膜晶体管TFT的沟道区导电类型。
进一步的，通过曝光和干刻进一步减小所述光刻胶层12的宽度，以漏出有源层4的第二源极接触区7和第二漏极接触区8。
需要说明的是，本公开的薄膜晶体管采用底栅结构工艺，通过曝光和干刻控制光刻胶(PR)的宽度，形成所需的掺杂区，可精 确控制离子注入量，掺杂方式简单易行。
对所述有源层4的第二源极接触区7和第二漏极接触区8进行第三次离子注入，即进行LDD掺杂，LDD是采用较低浓度的掺杂，以增强有源层4与源极9和漏极11的欧姆接触，以防止组件产生热载子效应，并保证有源层4与源极5、漏极6形成良好的欧姆接触。
进一步的，通过刻蚀去除所述光刻胶层12，在所述有源层4的第一源极接触区5和第一漏极接触区6上的相应位置上形成所述源极9和漏极11。具体的，形成所述源极9和漏极11可以采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成源漏金属薄膜，并在源漏金属薄膜上形成光刻胶，之后通过曝光、显影、刻蚀工艺形成包括薄膜晶体管的源极5和漏极6的图形。其中，源漏金属薄膜的材料包括金属、金属合金，如：钼、钼铌合金、铝、铝钕合金、钛或铜等导电材料形成。
至此完成薄膜晶体管的制备。
在另一些实施例与上述实施例的区别仅在于步骤S2，也即在另一些实施例中形成平坦层2不采用构图工艺，而是采用流平工艺。具体的，在完成步骤S1的基底10上通过流平工艺，形成包括平坦层2的图形；其中，平坦层2与栅极1处于同一层且紧密接触，且平坦层2的上表面与栅极1的上表面平齐。
具体地，平坦层2的材料包括：丙烯酸或者透明树脂。之所以采用这些材料来制备平坦层2是因为，丙烯酸和透明树脂材料是一种良好的流平剂，其能够使得通过流平工艺制备所得的平坦层2具有一个平整、光滑、均匀的表面，以此来进一步确保平坦层2与栅极1的上表面构成一个平整的表面。
采用流平工艺制作平坦层并形成薄膜晶体管的其余步骤与上述实施例的步骤相同，在此不再重复描述。
由于本实施例的薄膜晶体管的制备方法中包括形成平坦层2的步骤，且平坦层2与栅极1处于同一层且紧密接触，且平坦层2的上表面与栅极1的上表面平齐，故设置在栅极1所在层上方的栅绝缘层3的上表面是一与基底10平行的平面，从而使得形成在栅绝缘层3上的有源层4上下表面均较为平整，这样一来，即可避免现有技术中，直接在形成有栅极1这一凸起结构的基底10上，依次形成薄膜晶体管的其他膜层，所导致的有源层4发生凸起变形的情况；进一步地，还解决了有源层4发生凸起所导致的、薄膜晶体管在进行工作时，有源层4中的载流子迁移受阻，影响薄膜晶体管的性能的问题。
本公开的实施例还提供一种显示装置，包括上述实施例中的薄膜晶体管，由于本实施例的显示装置包括前述的薄膜晶体管，故本实施例的显示装置具有较佳的显示效果。
其中，显示装置可以为液晶显示装置或者电致发光显示装置，例如液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (13)

  1. 一种薄膜晶体管，包括：
    基底，
    依次设置在所述基底上的栅极、栅绝缘层、有源层以及源漏极层；所述源漏极层相应的位于所述有源层第一源极接触区和第一漏极接触区上；
    其中，在所述栅绝缘层和所述基底之间还设置有平坦层，所述平坦层与所述栅极处于同一层且紧密接触，且所述平坦层的上表面与所述栅极的上表面平齐。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述平坦层的材料包括丙烯酸、透明树脂。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述栅绝缘层的厚度为
    Figure PCTCN2020079924-appb-100001
    至
    Figure PCTCN2020079924-appb-100002
  4. 根据权利要求1所述的薄膜晶体管，其中，所述有源层的材料包括低温多晶硅。
  5. 一种薄膜晶体管的制备方法，包括：
    在基底上依次形成栅极、栅绝缘层、有源层以及源漏极层，所述源漏极层相应的形成于有源层第一源极接触区和第一漏极接触区上；
    其中，在形成所述栅极之后还形成平坦层，所述平坦层与所述栅极处于同一层且紧密接触，且所述平坦层的上表面和所述栅极的上表面平齐。
  6. 根据权利要求5所述的薄膜晶体管的制备方法，其中，所述形成栅极和平坦层的步骤，包括：
    在基底上，通过构图工艺形成栅极图案；
    在形成有所述栅极的基底上沉积平坦层材料，并对所述平坦层材料进行曝光、显影、固化工艺形成平坦层图案，并对所述平坦层图案进行干法刻蚀以漏出栅极的上表面，通过所述干法刻蚀使得所述平坦层的上表面与所述栅极的上表面平齐。
  7. 根据权利要求6所述的薄膜晶体管的制备方法，其中，所述干法刻蚀包括除渣灰化处理。
  8. 根据权利要求6所述的薄膜晶体管的制备方法，其中，所述形成栅绝缘层的步骤包括：
    在形成有所述栅极和平坦层的基底上沉积栅绝缘层材料，所述栅绝缘层的厚度为
    Figure PCTCN2020079924-appb-100003
    至
    Figure PCTCN2020079924-appb-100004
  9. 根据权利要求6所述的薄膜晶体管的制备方法，其中，所述形成有源层的步骤包括：
    在栅绝缘层上沉积有源层材料，并通过构图工艺形成有源层图案；以及
    对所述有源层进行第一次离子注入。
  10. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述有源层的材料包括低温多晶硅。
  11. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述形成源漏极层的步骤包括：
    通过构图工艺，对已经进行第一次离子注入之后的有源层的上方形成光刻胶层，所述光刻胶层部分覆盖所述有源层，使得所述有源层漏出第一源极接触区和第一漏极接触区，对所述有源层的第一源极接触区和第一漏极接触区进行第二次离子注入；以及
    通过曝光和干刻减小所述光刻胶层的宽度，以漏出有源层的第二源极接触区和第二漏极接触区，对所述有源层的第二源极接触区和第二低浓度漏极接触区进行第三次离子注入；以及
    通过刻蚀去除所述光刻胶层，在所述有源层的第一源极接触区和第一漏极接触区上的相应位置上形成所述源漏极层。
  12. 根据权利要求5所述的薄膜晶体管的制备方法，其中，所述平坦层的材料包括丙烯酸、透明树脂。
  13. 一种显示装置，其中，包括权利要求1-4中任一所述的薄膜晶体管。
PCT/CN2020/079924 2019-03-20 2020-03-18 薄膜晶体管及其制备方法和显示装置 WO2020187237A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/054,711 US20210066504A1 (en) 2019-03-20 2020-03-18 Thin film transistor and manufacturing method thereof and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910214175.5 2019-03-20
CN201910214175.5A CN109873037A (zh) 2019-03-20 2019-03-20 薄膜晶体管及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2020187237A1 true WO2020187237A1 (zh) 2020-09-24

Family

ID=66920865

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/079924 WO2020187237A1 (zh) 2019-03-20 2020-03-18 薄膜晶体管及其制备方法和显示装置

Country Status (3)

Country Link
US (1) US20210066504A1 (zh)
CN (1) CN109873037A (zh)
WO (1) WO2020187237A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530810A (zh) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 一种开关元件的制备方法、阵列基板的制备方法和显示面板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109873037A (zh) * 2019-03-20 2019-06-11 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823102A (ja) * 1994-07-08 1996-01-23 Matsushita Electric Ind Co Ltd 電子部品及びその製造方法
CN1489790A (zh) * 2001-02-19 2004-04-14 �Ҵ���˾ 薄膜晶体管结构及其制造方法和使用它的显示器件
CN101506985A (zh) * 2006-09-22 2009-08-12 国产大学法人东北大学 半导体装置和半导体装置的制造方法
CN101644865A (zh) * 2008-08-06 2010-02-10 株式会社日立显示器 显示装置
US20170309653A1 (en) * 2015-03-04 2017-10-26 Shenzhen China Star Optoelectronics Technology Co. Ltd. Tft backplate structure comprising transistors having gate isolation layers of different thicknesses and manufacture method thereof
CN107863352A (zh) * 2016-08-31 2018-03-30 株式会社半导体能源研究所 半导体装置
CN109873037A (zh) * 2019-03-20 2019-06-11 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100873702B1 (ko) * 2007-04-05 2008-12-12 삼성모바일디스플레이주식회사 평판 디스플레이용 박막 트랜지스터 및 그 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823102A (ja) * 1994-07-08 1996-01-23 Matsushita Electric Ind Co Ltd 電子部品及びその製造方法
CN1489790A (zh) * 2001-02-19 2004-04-14 �Ҵ���˾ 薄膜晶体管结构及其制造方法和使用它的显示器件
CN101506985A (zh) * 2006-09-22 2009-08-12 国产大学法人东北大学 半导体装置和半导体装置的制造方法
CN101644865A (zh) * 2008-08-06 2010-02-10 株式会社日立显示器 显示装置
US20170309653A1 (en) * 2015-03-04 2017-10-26 Shenzhen China Star Optoelectronics Technology Co. Ltd. Tft backplate structure comprising transistors having gate isolation layers of different thicknesses and manufacture method thereof
CN107863352A (zh) * 2016-08-31 2018-03-30 株式会社半导体能源研究所 半导体装置
CN109873037A (zh) * 2019-03-20 2019-06-11 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112530810A (zh) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 一种开关元件的制备方法、阵列基板的制备方法和显示面板
CN112530810B (zh) * 2020-11-24 2023-06-16 北海惠科光电技术有限公司 一种开关元件的制备方法、阵列基板的制备方法和显示面板

Also Published As

Publication number Publication date
US20210066504A1 (en) 2021-03-04
CN109873037A (zh) 2019-06-11

Similar Documents

Publication Publication Date Title
US10312271B2 (en) Array substrate, manufacturing method thereof and display device
JP6956008B2 (ja) 薄膜トランジスタ、表示基板及び表示基板を有する表示パネル、並びにそれらの製造方法
WO2016074373A1 (zh) 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
US10818797B2 (en) Thin film transistor and method of fabricating the same, array substrate and display device
WO2017092142A1 (zh) 低温多晶硅tft基板的制作方法
US20160276376A1 (en) Array substrate, method for fabricating the same, and display device
WO2016173322A1 (zh) 一种阵列基板及其制作方法、及显示装置
CN105702623B (zh) Tft阵列基板的制作方法
WO2017028461A1 (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
WO2018176784A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
WO2018188319A1 (zh) 低温多晶硅薄膜晶体管及其制造方法、显示基板
WO2018214732A1 (zh) 阵列基板及其制备方法、显示装置
WO2016206206A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2018126636A1 (zh) 薄膜晶体管、阵列基板和显示装置的制造方法
TW201622158A (zh) 薄膜電晶體以及其製作方法
WO2018149218A1 (zh) 薄膜晶体管及其制备方法、阵列基板及电子设备
WO2017092172A1 (zh) Tft基板的制作方法
WO2020187237A1 (zh) 薄膜晶体管及其制备方法和显示装置
WO2020062426A1 (zh) 阵列基板及其制备方法和显示器件
CN107275340A (zh) 薄膜晶体管制备方法、阵列基板、其制备方法及显示装置
US7176074B1 (en) Manufacturing method of thin film transistor array substrate
WO2017028499A1 (zh) 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
US20160329352A1 (en) Array substrate and fabrication method thereof, and display device
US20160284737A1 (en) Display substrate, its manufacturing method, and display device
WO2016011755A1 (zh) 薄膜晶体管及其制备方法、显示基板和显示设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20773312

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20773312

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20773312

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04/05/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20773312

Country of ref document: EP

Kind code of ref document: A1