WO2018149218A1 - 薄膜晶体管及其制备方法、阵列基板及电子设备 - Google Patents

薄膜晶体管及其制备方法、阵列基板及电子设备 Download PDF

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WO2018149218A1
WO2018149218A1 PCT/CN2017/115620 CN2017115620W WO2018149218A1 WO 2018149218 A1 WO2018149218 A1 WO 2018149218A1 CN 2017115620 W CN2017115620 W CN 2017115620W WO 2018149218 A1 WO2018149218 A1 WO 2018149218A1
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layer
thin film
film transistor
source
gate
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PCT/CN2017/115620
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English (en)
French (fr)
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何晓龙
李东升
班圣光
黄睿
米东灿
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京东方科技集团股份有限公司
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Priority to US16/078,160 priority Critical patent/US11264507B2/en
Publication of WO2018149218A1 publication Critical patent/WO2018149218A1/zh

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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a thin film transistor, an array substrate including the same, an electronic device including the array substrate, and a method of fabricating the thin film transistor.
  • LTPS low temperature polysilicon technology
  • top-gate LTPS TFTs usually require processes such as LS (light-shielding layer), source/drain doping (S/D doping), and lightly doped drain (Ldd doping). The process is complicated and the cost is high.
  • the bottom gate LTPS TFT does not require an LS layer and a doping process, but the damage and ohmic contact problems of the active layer by the back channel etching are difficult to solve at the same time.
  • the embodiments of the present disclosure aim to solve at least one of the technical problems in the related art to some extent.
  • a thin film transistor in one aspect of the disclosure, includes: a gate; a gate insulating layer; an active layer; a source/drain electrode, wherein the material of the active layer is polysilicon, and the source and drain electrodes are disposed near a surface of the gate There is a protective structure.
  • the thin film transistor is a bottom gate type thin film transistor.
  • the material of the protective structure is an oxide semiconductor.
  • the oxide semiconductor comprises indium gallium zinc oxide, indium zinc oxide And at least one of zinc oxide.
  • the thin film transistor further includes an ohmic contact structure disposed between the protection structure and the source and drain electrodes.
  • the material of the ohmic contact structure is N-type doped amorphous silicon.
  • an array substrate is provided.
  • the array substrate comprises the thin film transistor described above.
  • the array substrate has all the features and advantages of the thin film transistor described above, and will not be further described herein.
  • an electronic device comprising the array substrate described above.
  • the electronic device has all the features and advantages of the array substrate described above, and will not be further described herein.
  • a method of fabricating a thin film transistor includes: forming a gate and a gate insulating layer on a substrate; forming an active layer; forming a protective layer and an electrode in sequence on a side of the active layer and the gate insulating layer away from the substrate a layer; a source-drain electrode and a protective structure are sequentially formed by a patterning process.
  • forming a protective layer and an electrode layer in sequence on a side of the active layer and the gate insulating layer away from the substrate includes, on a side of the active layer and the gate insulating layer away from the substrate
  • the protective layer, the ohmic contact layer, and the electrode layer are sequentially formed.
  • sequentially forming the source and drain electrodes and the protection structure by a patterning process includes sequentially forming the source and drain electrodes, the ohmic contact structure, and the protection structure by a patterning process.
  • the source-drain electrodes, the ohmic contact structure, and the protection structure are sequentially formed by a patterning process, including: performing wet etching on the electrode layer to form the source-drain electrodes; and performing dry processing on the ohmic contact layer Etching to form the ohmic contact structure; wet etching the protective layer to form the protective structure.
  • FIG. 1 shows a schematic structural view of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 2 shows a schematic structural view of a thin film transistor according to another embodiment of the present disclosure.
  • 3A and 3B are schematic diagrams showing the structure of a thin film transistor according to still another embodiment of the present disclosure.
  • FIG. 4 shows a schematic flow diagram of a method of fabricating a thin film transistor in accordance with one embodiment of the present disclosure.
  • FIG. 5 shows a method of fabricating a thin film transistor according to another embodiment of the present disclosure. Schematic diagram of the process.
  • FIG. 6 shows a schematic flow chart of a method of fabricating a thin film transistor according to still another embodiment of the present disclosure.
  • 7A, 7B, 7C, 7D, and 7E show schematic flow diagrams of a method of fabricating a thin film transistor in accordance with still another embodiment of the present disclosure.
  • 8A, 8B, 8C, 8D, 8E, 8F, and 8G show schematic flow diagrams of a method of fabricating a thin film transistor in accordance with still another embodiment of the present disclosure.
  • Embodiments of the present disclosure are described in detail below.
  • the embodiments described below are illustrative only and are not to be construed as limiting the disclosure. Where specific techniques or conditions are not indicated in the examples, they are carried out according to the techniques or conditions described in the literature in the art or in accordance with the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are conventional products that can be obtained commercially.
  • the present disclosure provides a thin film transistor.
  • the thin film transistor includes a gate electrode 10, a gate insulating layer 20, an active layer 30, and source and drain electrodes 40.
  • the material of the active layer 30 is polysilicon, and a protective structure 50 is disposed on a surface of the source/drain electrode 40 adjacent to the gate 10.
  • the inventors have found that by providing a protective structure on the surface of the source and drain electrodes close to the gate, and the protective structure can be obtained by a wet etching process, damage to the active layer during the etching process can be avoided, and there is no The channel region of the source layer is eroded, and the protective structure can reduce the contact resistance, thereby greatly improving the electrical performance of the thin film transistor.
  • the specific structure of the thin film transistor is not particularly limited and may be a structure of a conventional thin film transistor in the art, for example, including but not limited to a bottom gate thin film transistor or a top gate thin film transistor.
  • the thin film transistor is a bottom gate type thin film transistor.
  • the bottom gate type thin film transistor has a large advantage in process and cost because the doping process and the light shielding layer process can be omitted.
  • the material forming the protective structure is not particularly limited as long as the active layer can be protected from being damaged during the etching process and can be removed by a wet etching process.
  • the material of the protective structure is an oxide semiconductor formation. Thereby, the effect of preventing the active layer from being damaged is better, and can be effectively removed by wet etching without causing erosion of the active layer.
  • the specific kind of the oxide semiconductor is also not particularly limited, and those skilled in the art can flexibly select as needed.
  • oxide semiconductors that may be employed include, but are not limited to, at least one of indium gallium zinc oxide, indium zinc oxide, and zinc oxide. Thereby, it has a better protective effect and is easily removed by wet etching.
  • the thin film transistor further includes an ohmic contact structure 60 disposed between the protective structure 50 and the source and drain electrode 40.
  • the inventors have found that by providing an ohmic contact structure, the contact resistance can be further reduced, the turn-on current Ion can be increased, and the drain current Ioff can be reduced.
  • the gate is under negative pressure, the electrons in the active layer are depleted, mainly through hot carriers (holes), and the ohmic contact layer is formed, and the formed PN junction can effectively prevent hole leakage. Current greatly reduces leakage current.
  • the specific material for forming the ohmic contact structure is not particularly limited as long as the contact resistance can be effectively exerted, the turn-on current can be increased, and the leakage current can be reduced.
  • the material forming the ohmic contact structure is N-type heavily doped amorphous silicon (n+a-Si). As a result, the contact resistance is low, the turn-on current is high, and the leakage current is greatly reduced.
  • the thin film transistor described above may also have other structures possessed by conventional thin film transistors in the art.
  • the thin film transistor described above may further include a substrate 100 to provide support for the thin film transistor, according to an embodiment of the present disclosure.
  • the present disclosure provides an array substrate.
  • the array substrate includes the thin film transistor described above.
  • the array substrate has all the features and advantages of the thin film transistor described above, and will not be further described herein.
  • the array substrate of the present disclosure further has other necessary structures and components of a conventional array substrate, such as gate lines, data lines, and necessary circuit structures, etc. A narrative.
  • the present disclosure provides an electronic device.
  • the electronic device includes the array substrate described above.
  • the electronic device has all the features and advantages of the array substrate described above, and will not be further described herein.
  • the specific kind of the electronic device is not particularly limited, and may be any electronic device provided with an array substrate.
  • the Electronic devices include, but are not limited to, mobile phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators, and the like, any products or components having display functions.
  • the electronic device includes other necessary structures and components of conventional electronic devices.
  • the electronic device further includes an array substrate, a color filter substrate, a liquid crystal filled between the array substrate and the color filter substrate, a backlight module, and the like.
  • the present disclosure provides a method of fabricating the thin film transistor described above. According to an embodiment of the present disclosure, referring to FIG. 4, the method may include the following steps:
  • S100 forming a gate and a gate insulating layer on the substrate.
  • any method for forming a gate and a gate insulating layer known in the art may be used, for example, including but not limited to forming a gate and a gate insulating layer by physical vapor deposition or chemical vapor deposition. It may be a method of vacuum sputtering, deposition, or the like. It can be understood by those skilled in the art that in this step, the gate and the gate insulating layer may be formed directly at a predetermined position, or the entire layer structure may be formed on the substrate in advance, and then patterned by etching or the like. In addition, this step may also include steps such as doping.
  • the material of the substrate, the gate, and the gate insulating layer is not particularly limited, and the substrate, the gate, and the gate insulating layer may be formed using materials conventional in the art.
  • the substrate includes, but is not limited to, a glass substrate, the gate may be a metal gate, or the like, and the material forming the gate insulating layer may be a polymer, an oxide, or the like.
  • a layer structure covering the gate insulating layer may be formed first, and then an active layer satisfying the requirements is formed by patterning or the like.
  • the method of forming the active layer may be physical vapor deposition or chemical vapor deposition, and specifically may be vacuum sputtering, deposition, or the like.
  • the material forming the active layer may be polysilicon.
  • the thin film transistor has good electrical properties.
  • an amorphous silicon layer may be formed on the upper surface of the gate insulating layer in advance, and then the amorphous silicon layer is converted into a polysilicon layer by an excimer laser crystallization process, and then the active layer is obtained by patterning.
  • S300 forming a protective layer and an electrode layer in sequence on a side of the active layer and the gate insulating layer away from the substrate.
  • the protective layer and the electrode layer may be formed by physical vapor deposition or chemical vapor deposition.
  • the material forming the protective layer may be an oxide semiconductor. Specifically, it includes, but is not limited to, at least one of indium gallium zinc oxide, indium zinc oxide, and zinc oxide. Thereby, it has a better protective effect and is easily removed by wet etching.
  • the material forming the electrode layer may be any material in the art that can form a source-drain electrode, and those skilled in the art can select as needed.
  • the protective layer and the electrode layer may be formed by physical vapor deposition or chemical vapor deposition, for example, including but not limited to, vacuum sputtering, deposition, or the like.
  • S400 Forming source and drain electrodes and a protection structure are sequentially formed by a patterning process.
  • the electrode layer and the protective layer are etched by wet etching, which does not damage the active layer, and effectively improves the electrical performance of the thin film transistor.
  • the thin film transistor described above can be obtained quickly and efficiently by this method, and since a protective structure is formed on the surface of the source/drain electrode near the gate, it can be obtained by a wet etching process, thereby effectively avoiding The active layer is damaged during the dry etching process, and the active layer is not eroded.
  • the protective structure can reduce the contact resistance and greatly improve the electrical performance of the thin film transistor.
  • the material of the active layer is polysilicon.
  • step S300 the protective layer, the ohmic contact layer, and the electrode layer are sequentially formed on a side of the active layer and the gate insulating layer away from the substrate;
  • step S400 the source/drain electrode, the ohmic contact structure, and the protection structure are sequentially formed by a patterning process.
  • the inventors have found that by providing an ohmic contact structure, the contact resistance can be further reduced, the turn-on current can be increased, and the leakage current can be reduced.
  • the gate is under negative pressure, the electrons in the active layer are depleted, mainly through hot carriers (holes), and the ohmic contact layer is formed, and the formed PN junction can effectively prevent hole leakage. Current greatly reduces leakage current.
  • the material forming the ohmic contact layer may be N-type doped amorphous silicon, whereby the contact resistance is low, the turn-on current is high, and the leak current is greatly reduced.
  • the source-drain electrode, the ohmic contact structure, and the protection structure are sequentially formed by a patterning process, including: S410: wet etching the electrode layer to form the source-drain electrode; S420 : dry etching the ohmic contact layer to form a An ohmic contact structure; S430: wet etching the protective layer to form the protective structure.
  • the electrode layer may be etched by wet etching, and then the ohmic contact layer is etched by dry etching, and then the protective layer is etched by wet etching.
  • the active layer can be effectively prevented from being damaged in the dry etching, and the protective layer can be patterned by wet etching. It does not erode the active layer, which greatly improves the electrical performance of the thin film transistor.
  • a method of fabricating the thin film transistor described above includes:
  • a gate 10 is formed on the substrate 100 as shown in FIG. 7A;
  • the polysilicon layer 32 is patterned to form the active layer 30, wherein the positive projection area of the active layer 30 on the gate 10 is smaller than the area of the gate 10, as shown in FIG. 7C;
  • a protective layer 52 and an electrode layer 42 are sequentially formed on the upper surfaces of the active layer 30 and the gate insulating layer 20, as shown in FIG. 7D;
  • the protective layer 52 and the electrode layer 42 are wet-etched to form the protective structure 50 and the source-drain electrodes 40, as shown in Fig. 7E, to obtain a thin film transistor.
  • a method of fabricating a thin film transistor includes:
  • a gate 10 is formed on the substrate 100 as shown in FIG. 8A;
  • a gate insulating layer 20 and an amorphous silicon layer are sequentially formed on the upper surface of the substrate 100 and the gate electrode 10, and an amorphous silicon layer is subjected to an excimer laser crystallization treatment to form a polysilicon layer 32, as shown in FIG. 8B;
  • the polysilicon layer 32 is patterned to form the active layer 30, wherein the orthographic projection area of the active layer 30 on the gate 10 is smaller than the area of the gate 10, as shown in FIG. 8C;
  • a protective layer 52, an ohmic contact layer 62 and an electrode layer 42 are sequentially formed on the upper surfaces of the active layer 30 and the gate insulating layer 20, as shown in FIG. 8D;
  • the electrode layer 42 is etched by wet etching to form the source and drain electrodes 40, as shown in FIG. 8E;
  • the ohmic contact layer 62 is etched by dry etching to form an ohmic contact structure 60, as shown in FIG. 8F;
  • the protective layer 52 is etched by wet etching to form a protective structure 50, as shown in FIG. 8G, to obtain a thin film transistor.

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Abstract

一种薄膜晶体管及其制备方法、阵列基板及电子设备，该薄膜晶体管包括：栅极（10）；栅绝缘层（20）；有源层（30）；源漏电极（40），其中在所述源漏电极（40）靠近所述栅极（10）的表面设置有保护结构（50）。通过在源漏电极（40）靠近所述栅极（10）的表面设置保护结构（50），可以避免在刻蚀过程对有源层(30)的损伤，不会对有源层(30)的沟道区发生侵蚀，从而可以大大提升薄膜晶体管的电气性能。

Description

薄膜晶体管及其制备方法、阵列基板及电子设备
相关申请的交叉引用
本申请主张于2017年2月16日提交的中国专利申请No.201710084366.5的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，并且具体地涉及薄膜晶体管、含有该薄膜晶体管的阵列基板，含有该阵列基板的电子设备，以及制备该薄膜晶体管的方法。
背景技术
随着液晶显示技术的发展，对TFT(薄膜晶体管)半导体层的电子迁移率要求越来越高，低温多晶硅技术(LTPS)应运而生。LTPS显示技术显著提高了像素写入速度，从而可以设置更细的线宽、更小的TFT开关，更高的开口率。
传统的顶栅LTPS TFT通常需要制备LS(遮光层)、源/漏极掺杂(S/D doping)、轻掺杂漏区(Ldd doping)等工艺，工艺复杂，成本较高。底栅LTPS TFT无需LS层和掺杂工艺，但是背沟道刻蚀对有源层的损伤和欧姆接触问题较难同时解决。
因而，目前的薄膜晶体管工艺仍有待改进。
发明内容
本公开实施例旨在至少在一定程度上解决相关技术中的技术问题之一。
在本公开的一个方面，提供了一种薄膜晶体管。根据一实施例，该薄膜晶体管包括：栅极；栅绝缘层；有源层；源漏电极，其中所述有源层的材料为多晶硅，在所述源漏电极靠近所述栅极的表面设置有保护结构。
根据一实施例，该薄膜晶体管为底栅型薄膜晶体管。
根据一实施例，所述保护结构的材料为氧化物半导体。
根据一实施例，所述氧化物半导体包括铟镓锌氧化物、氧化铟锌 和氧化锌中的至少一种。
根据一实施例，该薄膜晶体管进一步包括欧姆接触结构，所述欧姆接触结构设置在所述保护结构和所述源漏电极之间。
根据一实施例，所述欧姆接触结构的材料为N型掺杂的非晶硅。
在本公开的另一方面，提供了一种阵列基板。根据一实施例，该阵列基板包括前面所述的薄膜晶体管。该阵列基板具有前面所述的薄膜晶体管的全部特征和优点，在此不再一一赘述。
在本公开的再一方面，提供了一种电子设备。根据一实施例，该电子设备包括前面所述的阵列基板。该电子设备具有前面所述的阵列基板的全部特征和优点，在此不再一一赘述。
在本公开的又一方面，提供了一种制备薄膜晶体管的方法。根据一实施例，该方法包括：在衬底上形成栅极和栅绝缘层；形成有源层；在所述有源层和栅绝缘层远离所述衬底的一侧依次形成保护层和电极层；通过构图工艺依次形成源漏电极和保护结构。
根据一实施例，在所述有源层和栅绝缘层远离所述衬底的一侧依次形成保护层和电极层包括，在所述有源层和栅绝缘层远离所述衬底的一侧依次形成所述保护层、欧姆接触层和所述电极层。
根据一实施例，通过构图工艺依次形成源漏电极和保护结构包括，通过构图工艺依次形成所述源漏电极、欧姆接触结构和所述保护结构。
根据一实施例，通过构图工艺依次形成源漏电极、欧姆接触结构和保护结构，包括：对所述电极层进行湿法刻蚀，形成所述源漏电极；对所述欧姆接触层进行干法刻蚀，形成所述欧姆接触结构；对所述保护层进行湿法刻蚀，形成所述保护结构。
附图说明
图1显示了根据本公开一个实施例的薄膜晶体管的结构示意图。
图2显示了根据本公开另一个实施例的薄膜晶体管的结构示意图。
图3A和图3B显示了根据本公开又一个实施例的薄膜晶体管的结构示意图。
图4显示了根据本公开一个实施例的制备薄膜晶体管的方法的流程示意图。
图5显示了根据本公开另一个实施例的制备薄膜晶体管的方法的 流程示意图。
图6显示根据本公开又一个实施例的制备薄膜晶体管的方法的流程示意图。
图7A、7B、7C、7D和7E显示了根据本公开又一个实施例的制备薄膜晶体管的方法的流程示意图。
图8A、8B、8C、8D、8E、8F和8G显示了根据本公开再一个实施例的制备薄膜晶体管的方法的流程示意图。
具体实施方式
下面详细描述本公开的实施例。下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规产品。
在本公开的一个方面，本公开提供了一种薄膜晶体管。根据本公开的实施例，参照图1，该薄膜晶体管包括栅极10、栅绝缘层20、有源层30和源漏电极40。有源层30的材料为多晶硅，在所述源漏电极40靠近所述栅极10的表面设置有保护结构50。发明人发现，通过在源漏电极靠近所述栅极的表面设置保护结构，且保护结构可以通过湿法刻蚀处理获得，可以避免在刻蚀工艺过程对有源层的损伤，不会对有源层的沟道区发生侵蚀，同时该保护结构可以降低接触电阻，从而可以大大提升薄膜晶体管的电气性能。
根据本公开的实施例，该薄膜晶体管的具体结构没有特别限制，可以为本领域常规薄膜晶体管的结构，例如，包括但不限于底栅型薄膜晶体管或顶栅型薄膜晶体管。在本公开的一些优选实施例中，参照图1，该薄膜晶体管为底栅型薄膜晶体管。底栅型薄膜晶体管由于可以省去掺杂工艺和遮光层工艺，在工艺和成本上具有较大优势。
根据本公开的实施例，形成所述保护结构的材料不受特别限制，只要能够保护有源层不在刻蚀工艺过程中被损伤、且可通过湿法刻蚀工艺去除即可。在本公开的一些实施例中，所述保护结构的材料为氧化物半导体形成。由此，防止有源层不被损伤的效果较佳，且可以有效通过湿法刻蚀去除，不对有源层造成侵蚀。
根据本公开的实施例，所述氧化物半导体的具体种类也没有特别限制，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，可以采用的氧化物半导体包括但不限于铟镓锌氧化物、氧化铟锌和氧化锌中的至少一种。由此，具有较好的保护效果，且易于通过湿法刻蚀去除。
根据本公开的实施例，参照图2，该薄膜晶体管进一步包括欧姆接触结构60，所述欧姆接触结构60设置在所述保护结构50和所述源漏电极40之间。发明人发现，通过设置欧姆接触结构，可以进一步降低接触电阻，提升开启电流Ion，同时降低漏电流Ioff。特别的，当栅极加负压时，有源层中电子耗尽，主要通过热载流子(空穴)发生导电，而欧姆接触层的存在，形成的P-N结，可以有效阻止空穴漏电流，大大降低漏电流。
根据本公开的实施例，形成欧姆接触结构的具体材料没有特别限制，只要能够有效发挥降低接触电阻，提升开启电流，同时降低漏电流的作用即可。在本公开的一些实施例中，形成欧姆接触结构的材料为N型重掺杂的非晶硅(n+a-Si)。由此，接触电阻较低，开启电流较高，且漏电流大大降低。
本领域技术人员可以理解，上述的薄膜晶体管还可以具有本领域常规薄膜晶体管具备的其他结构。例如，根据本公开的实施例，参照图3A和图3B，上述的薄膜晶体管还可以包括衬底100，以对薄膜晶体管提供支撑作用。
在本公开的另一方面，本公开提供了一种阵列基板。根据本公开的实施例，该阵列基板包括前面所述的薄膜晶体管。该阵列基板具有前面所述的薄膜晶体管的全部特征和优点，在此不再一一赘述。
本领域技术人员可以理解，除了上述薄膜晶体管外，本公开所述的阵列基板还具备常规阵列基板的其他必要结构和部件，例如栅线、数据线及必要的电路结构等，在此不再一一赘述。
在本公开的再一方面，本公开提供了一种电子设备。根据本公开的实施例，该电子设备包括前面所述的阵列基板。该电子设备具有前面所述的阵列基板的全部特征和优点，在此不再一一赘述。
根据本公开的实施例，该电子设备的具体种类不受特别限制，可以为任何设置有阵列基板的电子设备。在本公开的一些实施例中，该 电子设备包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件等。
本领域技术人员可以理解，除了前面所述的阵列基板，该电子设备还包括常规电子设备的其他必要结构和部件。例如，以显示面板为例，该电子设备还包括阵列基板、彩膜基板、填充于阵列基板和彩膜基板之间的液晶、背光模组等。
在本公开的又一方面，本公开提供了一种制备前面所述的薄膜晶体管的方法。根据本公开的实施例，参照图4，该方法可以包括以下步骤：
S100：在衬底上形成栅极和栅绝缘层。
具体的，该步骤中，可以采用本领域任何已知的形成栅极和栅绝缘层的方法进行，例如，包括但不限于通过物理气相沉积或化学气相沉积方法形成栅极和栅绝缘层，具体可以为真空溅射、淀积等方法。本领域技术人员可以理解，该步骤中，可以直接在预定位置形成栅极和栅绝缘层，也可以预先在衬底上形成整面的层结构，然后通过刻蚀等工艺进行图形化。另外，该步骤也可以包括掺杂等步骤。
根据本公开的实施例，衬底、栅极和栅绝缘层的材质不受特别限制，可以采用本领域常规的材料形成衬底、栅极和栅绝缘层。例如，衬底包括但不限于为玻璃衬底，栅极可以为金属栅极等，形成栅绝缘层的材料可以为聚合物、氧化物等。
S200：形成有源层。
具体的，该步骤中，可以先形成覆盖栅绝缘层的层结构，然后通过图案化等操作形成满足要求的有源层。形成有源层的方法可以为物理气相沉积或化学气相沉积，具体可以为真空溅射、淀积等方法。
根据本公开的实施例，形成有源层的材料可以为多晶硅。由此，薄膜晶体管具有良好的电气性能。具体的，可以预先在栅绝缘层的上表面形成非晶硅层，然后通过准分子激光晶化工艺，将非晶硅层转化为多晶硅层，然后通过图案化获得有源层。
S300：在所述有源层和栅绝缘层远离所述衬底的一侧依次形成保护层和电极层。
根据本公开的实施例，可以通过物理气相沉积或化学气相沉积方法形成保护层和电极层。形成该保护层的材料可以为氧化物半导体， 具体的，包括但不限于铟镓锌氧化物、氧化铟锌和氧化锌中的至少一种。由此，具有较好的保护效果，且易于通过湿法刻蚀去除。形成电极层的材料可以为本领域任何可以形成源漏电极的材料，本领域技术人员可以根据需要进行选择。
根据本公开的实施例，该步骤中，可以通过物理气相沉积或化学气相沉积，例如，包括但不限于真空溅射、淀积等方法形成该保护层和电极层。
S400：通过构图工艺依次形成源漏电极和保护结构。
根据本公开的实施例，该步骤中，采用湿法刻蚀对电极层和保护层进行刻蚀处理，不会对有源层产生损伤，有效提升薄膜晶体管的电气性能。
发明人发现，通过该方法可以快速有效的制备获得前面所述的薄膜晶体管，且由于在源漏电极靠近栅极的表面形成保护结构，其可以通过湿法刻蚀工艺处理获得，从而可以有效避免干法刻蚀过程中对有源层造成损伤，不会对有源层造成侵蚀，同时该保护结构可以降低接触电阻，大大提高了薄膜晶体管的电气性能。
根据本公开的实施例，有源层的材料为多晶硅。由此，有源层不会在湿法刻蚀步骤中造成损伤，干法刻蚀步骤中也可以通过保护层得到理想的保护，薄膜晶体管的电气性能得到显著提升。
根据本公开的实施例，参照图5，步骤S300中，在所述有源层和栅绝缘层远离所述衬底的一侧依次形成所述保护层、欧姆接触层和所述电极层；步骤S400中，通过构图工艺依次形成所述源漏电极、欧姆接触结构和所述保护结构。发明人发现，通过设置欧姆接触结构，可以进一步降低接触电阻，提升开启电流，同时降低漏电流。特别的，当栅极加负压时，有源层中电子耗尽，主要通过热载流子(空穴)发生导电，而欧姆接触层的存在，形成的P-N结，可以有效阻止空穴漏电流，大大降低漏电流。
根据本公开的实施例，形成欧姆接触层的材料可以为N型掺杂的非晶硅，由此，接触电阻较低，开启电流较高，且漏电流大大降低。
根据本公开的实施例，参照图6，通过构图工艺依次形成源漏电极、欧姆接触结构和保护结构，包括：S410：对所述电极层进行湿法刻蚀，形成所述源漏电极；S420：对所述欧姆接触层进行干法刻蚀，形成所 述欧姆接触结构；S430：对所述保护层进行湿法刻蚀，形成所述保护结构。
具体的，首先可以通过湿法刻蚀对电极层进行刻蚀处理，然后通过干法刻蚀对欧姆接触层进行刻蚀处理，接着，再通过湿法刻蚀对保护层进行刻蚀处理，该通过干法刻蚀对欧姆接触层进行刻蚀处理过程中，由于保护层的存在，可以有效避免有源层在干法刻蚀中造成损伤，且保护层可以通过湿法刻蚀进行图案化，不会侵蚀有源层，进而大大提高了薄膜晶体管的电气性能。
在本公开的一个具体示例中，参照图7A-7E，制备前面所述的薄膜晶体管的方法包括：
在衬底100上形成栅极10，如图7A所示；
在衬底100和栅极10的上表面依次形成栅绝缘层20和非晶硅层，并对非晶硅层进行准分子激光晶化处理，以形成多晶硅层32，如图7B所示；
对多晶硅层32进行图案化处理，以形成有源层30，其中有源层30在栅极10上的正投影面积小于栅极10的面积，如图7C所示；
在有源层30和栅绝缘层20的上表面依次形成保护层52和电极层42，如图7D所示；
对保护层52和电极层42进行湿法刻蚀，以形成保护结构50和源漏电极40，如图7E所示，即得薄膜晶体管。
根据本公开的一个具体示例，参照图8A-图8G，制备薄膜晶体管的方法包括：
在衬底100上形成栅极10，如图8A所示；
在衬底100和栅极10的上表面依次形成栅绝缘层20和非晶硅层，并对非晶硅层进行准分子激光晶化处理，以形成多晶硅层32，如图8B所示；
对多晶硅层32进行图案化处理，以形成有源层30，其中有源层30在栅极10上的正投影面积小于栅极10的面积，如图8C所示；
在有源层30和栅绝缘层20的上表面依次形成保护层52、欧姆接触层62和电极层42，如图8D所示；
利用湿法刻蚀对电极层42进行刻蚀，以形成源漏电极40，如图8E所示；
利用干法刻蚀对欧姆接触层62进行刻蚀，以形成欧姆接触结构60，如图8F所示；
利用湿法刻蚀对保护层52进行刻蚀，以形成保护结构50，如图8G所示，即得薄膜晶体管。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (12)

  1. 一种薄膜晶体管，包括栅极、栅绝缘层、有源层以及源漏电极，
    其中所述有源层的材料为多晶硅，在所述源漏电极靠近所述栅极的表面设置有保护结构。
  2. 根据权利要求1所述的薄膜晶体管，其中所述薄膜晶体管为底栅型薄膜晶体管。
  3. 根据权利要求1所述的薄膜晶体管，其中所述保护结构的材料为氧化物半导体。
  4. 根据权利要求3所述的薄膜晶体管，其中所述氧化物半导体包括铟镓锌氧化物、氧化铟锌和氧化锌中的至少一种。
  5. 根据权利要求1-4任一项所述的薄膜晶体管，还包括欧姆接触结构，所述欧姆接触结构设置在所述保护结构和所述源漏电极之间。
  6. 根据权利要求5所述的薄膜晶体管，其中所述欧姆接触结构的材料为N型掺杂的非晶硅。
  7. 一种阵列基板，包括权利要求1-6中任一项所述的薄膜晶体管。
  8. 一种电子设备，包括权利要求7所述的阵列基板。
  9. 一种制备薄膜晶体管的方法，包括步骤：
    在衬底上形成栅极和栅绝缘层；
    形成有源层，其中所述有源层的材料为多晶硅；
    在所述有源层和栅绝缘层远离所述衬底的一侧依次形成保护层和电极层；以及
    通过构图工艺依次形成源漏电极和保护结构。
  10. 根据权利要求9所述的方法，其中在所述有源层和栅绝缘层远离所述衬底的一侧依次形成保护层和电极层包括：在所述有源层和栅绝缘层远离所述衬底的一侧依次形成所述保护层、欧姆接触层和所述电极层。
  11. 根据权利要求10所述的方法，其中通过构图工艺依次形成源漏电极和保护结构包括，通过对所述保护层、所述欧姆接触层和所述电极层进行构图工艺，依次形成所述源漏电极、欧姆接触结构和所述保护结构
  12. 根据权利要求11所述的方法，其中形成所述源漏电极、所述 欧姆接触结构和所述保护结构的步骤包括：
    对所述电极层进行湿法刻蚀，形成所述源漏电极；
    对所述欧姆接触层进行干法刻蚀，形成所述欧姆接触结构；以及
    对所述保护层进行湿法刻蚀，形成所述保护结构。
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