WO2018171368A1 - 多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法 - Google Patents
多晶硅薄膜及其制作方法、薄膜晶体管及其制作方法 Download PDFInfo
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- WO2018171368A1 WO2018171368A1 PCT/CN2018/076760 CN2018076760W WO2018171368A1 WO 2018171368 A1 WO2018171368 A1 WO 2018171368A1 CN 2018076760 W CN2018076760 W CN 2018076760W WO 2018171368 A1 WO2018171368 A1 WO 2018171368A1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 162
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 153
- 239000010409 thin film Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 189
- 239000002184 metal Substances 0.000 claims abstract description 189
- 239000000758 substrate Substances 0.000 claims abstract description 151
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 120
- 238000000034 method Methods 0.000 claims abstract description 81
- 230000008569 process Effects 0.000 claims abstract description 45
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 230000003197 catalytic effect Effects 0.000 claims abstract description 18
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- 238000000137 annealing Methods 0.000 claims description 27
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- 238000005530 etching Methods 0.000 description 4
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- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 238000002360 preparation method Methods 0.000 description 2
- 229910001415 sodium ion Inorganic materials 0.000 description 2
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- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 229910001413 alkali metal ion Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
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Definitions
- the present disclosure relates to the field of display, and in particular to a polysilicon film and a method of fabricating the same, a thin film transistor, and a method
- Poly-silicon has attracted much attention in the thin film transistor manufacturing industry, especially in the application of thin film transistor-driven displays, because of its superior electrical properties over amorphous silicon and lower cost advantages than single crystal silicon.
- polycrystalline silicon thin films are generally fabricated by Excimer Laser Anneal (ELA) technology, but this method has disadvantages such as expensive preparation equipment, poor uniformity of the formed polysilicon film layer, complicated manufacturing process, etc., resulting in an increase in production cost, and When a completed polycrystalline silicon film is applied to a thin film transistor, problems such as low performance of the thin film transistor are caused.
- ELA Excimer Laser Anneal
- the method for fabricating a polysilicon film provided by the embodiment of the present disclosure, the polysilicon film is applied to a thin film transistor; wherein the manufacturing method comprises:
- the manufacturing method after the forming the buffer layer, before the forming the amorphous silicon film layer, the manufacturing method further includes:
- a metal diffusion layer on a side of the buffer layer facing away from the substrate substrate; wherein the metal diffusion layer is diffused from a metal atom of the metal layer to the buffer layer facing away from the liner One side of the base substrate is formed;
- the catalyzing effect of the metal atom on the amorphous silicon film layer, converting the amorphous silicon film layer into a polysilicon film layer specifically comprising:
- the amorphous silicon film layer is converted into a polysilicon film layer by catalytic action of the metal diffusion layer by a second annealing process.
- the forming the amorphous silicon film layer specifically includes:
- the orthographic projection of the underlying substrate overlaps with the orthographic projection of the pattern of the amorphous silicon film layer on the underlying substrate.
- the forming the metal layer specifically includes:
- the catalytic effect of the metal atom on the amorphous silicon film layer converts the amorphous silicon film layer into a polysilicon film layer.
- the metal atom on the amorphous silicon film layer converts the amorphous silicon film layer into a polysilicon film layer.
- a third annealing process is performed to diffuse metal atoms of the metal layer to the amorphous silicon film layer, and convert the amorphous silicon film layer into a polysilicon film layer by catalytic action of the metal atoms diffused thereto.
- the manufacturing method after the converting the amorphous silicon film layer into the polysilicon film layer, the manufacturing method further includes:
- the surface of the polysilicon film layer facing away from the buffer layer is treated to remove a portion of the film of the polysilicon film layer facing away from the buffer layer.
- the manufacturing method before the forming the metal layer, the manufacturing method further includes:
- a barrier layer is formed on the base substrate.
- an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, including:
- a patterned polysilicon film is formed on a substrate
- a source and drain insulating layer having a first via and a second via on a side of the gate facing away from the substrate; wherein an orthographic projection of a pattern of the polysilicon film layer on the substrate Covering an orthographic projection of the first via and the second via in the substrate; an orthographic projection of the first via and the second via in the substrate and the gate The pattern of the poles does not overlap in the orthographic projection of the substrate;
- embodiments of the present disclosure further provide a polysilicon film, including:
- a metal layer disposed on one side of the substrate
- a polysilicon film layer disposed on a side of the buffer layer facing away from the substrate substrate; wherein the polysilicon film layer is fabricated by the method for fabricating the polysilicon film according to any one of claims 1-7.
- embodiments of the present disclosure further provide a thin film transistor, including:
- polysilicon film disposed on a side of the substrate; wherein the polysilicon film is a polysilicon film provided by the embodiments of the present disclosure;
- a source/drain insulating layer disposed on a side of the gate electrode facing away from the substrate substrate and having a first via hole and a second via hole; wherein the pattern of the polysilicon film layer is orthographically projected on the substrate substrate Covering an orthographic projection of the first via and the second via in the substrate; an orthographic projection of the first via and the second via in the substrate and the gate The pattern of the poles does not overlap in the orthographic projection of the substrate;
- a source and a drain disposed on a side of the source and drain insulating layer facing away from the substrate; wherein the source is connected to the polysilicon film layer through the first via, and the drain passes The second via is connected to the polysilicon film layer.
- FIG. 1 is a flow chart of a method for fabricating a polysilicon film according to an embodiment of the present disclosure
- FIG. 2 is a schematic structural view of forming a barrier layer on a substrate according to an embodiment of the present disclosure
- FIG. 3 is a schematic structural view of forming a metal layer on a barrier layer according to an embodiment of the present disclosure
- FIG. 4 is a schematic structural view of forming a buffer layer on an amorphous silicon film layer according to an embodiment of the present disclosure
- FIG. 5 is a schematic structural diagram of forming a metal diffusion layer on a buffer layer according to an embodiment of the present disclosure
- FIG. 6 is a schematic structural view of forming an amorphous silicon film on a metal diffusion layer according to an embodiment of the present disclosure
- FIG. 7 is a schematic structural diagram of forming a patterned amorphous silicon film layer according to an embodiment of the present disclosure.
- FIG. 8 is a schematic structural diagram of converting an amorphous silicon film layer into a polysilicon film layer according to an embodiment of the present disclosure
- FIG. 9 is a schematic structural diagram of a portion of a film on a side of a polysilicon film layer facing away from a buffer layer according to an embodiment of the present disclosure
- FIG. 10 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
- the material generally used for the active layer of the thin film transistor is mainly silicon, and includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, and the like.
- Polycrystalline silicon has gained much attention in the thin film transistor manufacturing industry because it has superior electrical properties over amorphous silicon and lower cost advantages than single crystal silicon.
- metal-induced amorphous silicon crystallization (MIC) technology can produce high-performance polysilicon film at low temperature, which has obvious advantages compared with other low-temperature polysilicon technologies.
- the method of fabricating a polycrystalline silicon film by using MIC technology is generally to first form an amorphous silicon film, and then deposit a metal isolation layer and a metal layer on the amorphous silicon film in order to allow metal atoms of the metal layer to diffuse through the metal isolation layer to The amorphous silicon film is then annealed to form an amorphous silicon film containing metal atoms to convert the amorphous silicon film containing metal atoms into a polysilicon film during the annealing process.
- the metal atom in the metal layer is generally used as a catalyst to convert the amorphous silicon film layer into a polysilicon film layer under the catalytic action of metal atoms. Since a metal isolation layer is further formed between the metal layer and the amorphous silicon film layer, in order to enable the metal atom of the metal layer to catalyze the amorphous silicon film layer, the metal layer needs to be heated to some extent. The metal atoms in the metal layer can be diffused so that the diffused metal atoms are in contact with the amorphous silicon film layer.
- the embodiments of the present disclosure provide a method for fabricating a polysilicon film that can be applied to a thin film transistor, which not only does not require additional fabrication of a metal isolation layer, but also eliminates a metal isolation layer and a metal layer removal process, thereby reducing production costs. Simplify the process steps.
- a method for fabricating a polysilicon film applied in a thin film transistor may include the following steps:
- a metal layer is formed on one side of the base substrate.
- a metal layer having a thickness of one nanometer to several hundred nanometers may be formed on a substrate by a process such as sputtering or plasma enhanced chemical vapor deposition (PECVD).
- the prepared metal layer may have a thickness of 10 nm, 50 nm or 100 nm.
- the material of the metal may include any one of Ni, Au, Cu, Pd, Co, and Ag.
- the base substrate in the embodiment of the present disclosure may specifically be a glass substrate.
- the substrate of the other material may be used as the substrate, which is not limited herein.
- the manufacturing method may further include: forming a barrier layer on the base substrate.
- a barrier layer having a thickness of several tens of nanometers to several hundreds of nanometers may be prepared on a base substrate by a process such as PECVD or Low Pressure Chemical Vapor Deposition (LPCVD).
- the prepared barrier layer may have a thickness of 10 nm, 50 nm or 100 nm.
- the material of the barrier layer may include a compound of silicon and nitrogen.
- the material of the barrier layer may specifically include SiNx.
- a buffer layer having a thickness of several tens of nanometers to several hundreds of nanometers may be prepared on the metal layer by a process such as PECVD or LPCVD.
- the prepared buffer layer may have a thickness of 10 nm, 50 nm or 100 nm.
- the buffer layer is generally a buffer layer commonly used in thin film transistors, and in the embodiment of the present disclosure, the buffer layer is not only used as a buffer layer commonly used in thin film transistors, but also can be used when metal atoms in a metal layer are diffused.
- the amount of metal atoms diffused to the upper amorphous silicon film layer is controlled, that is, a buffer layer is provided between the amorphous silicon film layer and the metal layer, and the metal atoms in the metal layer can be prevented from excessively diffusing to the amorphous silicon. Further, in the film layer, it is possible to prevent the formed thin film transistor from having a large leakage current due to the inclusion of a large number of metal atoms.
- the material of the specific buffer layer may include a compound of silicon and oxygen, for example, specifically, SiOx.
- an amorphous silicon film layer having a thickness of 10 nm to 100 nm may be deposited on the buffer layer by a process such as PECVD or LPCVD.
- the prepared amorphous silicon film layer may be 50 nm.
- the polysilicon film layer to which the amorphous silicon film layer is converted is generally used as an active layer in a thin film transistor.
- the method for fabricating a polysilicon film for use in a thin film transistor after sequentially forming a metal layer, a buffer layer, and an amorphous silicon film layer on a substrate, the metal atoms in the metal layer can be diffused by Contact with the amorphous silicon film layer, so that the amorphous silicon film layer can be converted into a polysilicon film layer under the catalytic action of metal atoms. Since the buffer layer existing in the fabricated thin film transistor is used in place of the metal isolation layer in the related art when the amorphous silicon film layer is converted into the polysilicon film layer, it is not necessary to separately form the metal isolation layer. Also, since the buffer layer and the metal layer are prepared before the formation of the amorphous silicon film layer, the process of removing the metal layer and the buffer layer can also be omitted. In turn, the production cost can be reduced and the process steps can be simplified.
- the metal atom is generally used as a catalyst to convert the amorphous silicon film layer into a polysilicon film layer under the catalytic action of metal atoms.
- the metal atom In order to form a buffer layer between the metal layer and the amorphous silicon film layer, in order to enable the metal atom of the metal layer to catalyze the amorphous silicon film layer, it is necessary to heat the metal layer to a certain extent.
- the metal atoms in the metal layer can be diffused and brought into contact with the amorphous silicon film layer.
- the amorphous silicon film layer can be converted into a polysilicon film layer through different process steps. The following is a specific example.
- the manufacturing method of the embodiment of the present disclosure forms an amorphous silicon film layer on the buffer layer after forming the buffer layer.
- the method further includes: forming, by the first annealing process, a metal diffusion layer on a side of the buffer layer facing away from the substrate, wherein the metal diffusion layer is formed by diffusion of metal atoms of the metal layer to a side of the buffer layer facing away from the substrate .
- the conversion of the amorphous silicon film layer into the polysilicon film layer by the catalytic action of the metal atom on the amorphous silicon film layer may specifically include: using a second annealing process to pass the catalytic effect of the amorphous silicon film layer through the metal diffusion layer Converted to a polysilicon film layer.
- defects on the surface of the film are relatively large in the interior, and since metal atoms generally diffuse into a region having many defects, metal atoms diffuse toward the surface of the buffer layer to form a metal diffusion layer.
- the metal diffusion layer is formed on the buffer layer by the first annealing process
- an amorphous silicon film layer is formed on the side of the metal diffusion layer facing away from the substrate, and the amorphous silicon film layer is formed on the metal by the second annealing process.
- the metal atoms in the diffusion layer are converted into a polysilicon film layer by the catalytic action.
- the first annealing process may be an annealing process under a condition that the temperature is lower than 600 ° C and the duration is the first preset duration
- the second annealing process may be at a temperature lower than 600 ° C and the duration is the second preset duration.
- the annealing process under the conditions.
- the first preset duration and the second preset duration need to be determined according to the actual application environment, which is not limited herein.
- the one-step annealing process can also be realized, that is, after the buffer layer is formed on the metal layer, the amorphous silicon is directly formed on the buffer layer.
- the film layer can diffuse metal atoms in the metal layer into the amorphous silicon film layer through a long annealing process, that is, using a third annealing process, and diffuse the amorphous silicon film layer into the film layer.
- the metal atom is converted into a polysilicon film by the catalytic action of the metal atom.
- the third annealing process may be an annealing process under the condition that the temperature is lower than 600 ° C and the duration is the third predetermined duration. Moreover, the third preset duration is greater than the first preset duration and is also greater than the second preset duration, that is, the duration of the third annealing process is longer than the first annealing process and the second annealing process. In the actual application, the third preset duration needs to be determined according to the actual application environment, which is not limited herein.
- the polysilicon film layer when the polysilicon film layer is formed, can be directly formed into a patterned polysilicon film layer, that is, the polysilicon film layer is directly provided with a pattern of an active layer.
- a polysilicon film is formed only in a channel region of a thin film transistor, and an amorphous silicon film layer is converted into a polysilicon film layer by a double annealing process, and a patterned polysilicon film layer may be formed after the first annealing process.
- amorphous silicon film Forming an amorphous silicon film on a side of the metal diffusion layer facing away from the substrate; afterwards, using a dry etching process, the amorphous silicon film is patterned into an amorphous silicon film layer, that is, the amorphous silicon film layer is directly formed A pattern having an active layer.
- a suitable over-etch ratio may be selected while removing the metal diffusion layer in other regions than the first region, wherein the first region corresponds to the thin film transistor
- the channel region, other than the first region corresponds to a non-channel region of the thin film transistor.
- the metal atoms in the metal layer diffuse above the buffer layer, they may also diffuse to the corresponding regions of the non-channel region, and when the amorphous silicon thin film layer is patterned, the metal diffusion layer is simultaneously removed except the first region.
- the thin film of other regions can reduce the influence of the metal atoms of the metal layer on the thin film transistor formed by the polysilicon film due to diffusion into the non-channel region. That is, the influence of the metal atoms of the metal layer on the thin film transistor formed by the polysilicon film due to diffusion into the non-channel region can be reduced without increasing the number of fabrication steps.
- the overetch ratio may be further etched down in the case of removing the amorphous silicon film layer of the non-channel region to remove the metal diffusion layer in the corresponding non-channel region under the amorphous silicon film layer.
- the etching time may be appropriately extended to 40 min to etch away the metal diffusion layer corresponding to the non-channel region.
- the above is only exemplified by 30 min and 40 min, and the disclosure is not limited thereto.
- a mixed gas of a fluorine-based gas and a chlorine-based gas may be used for etching.
- the metal layer is formed in the embodiment of the present disclosure, and specifically may include: on one side of the substrate Forming a patterned metal layer; wherein the orthographic projection of the pattern of the metal layer on the substrate substrate overlaps with the orthographic projection of the pattern of the amorphous silicon film layer on the substrate substrate. This can leave only the metal layer in the region corresponding to the channel region to diffuse the metal atoms in the metal layer in the region.
- the metal atoms diffused from the metal layer may be concentrated on the surface of the polysilicon film layer facing away from the buffer layer, so that the surface of the polysilicon film layer facing away from the buffer layer may be processed to remove the polysilicon film layer.
- a part of the film facing away from the buffer layer can further reduce the problem of high leakage current of the thin film transistor formed of the polysilicon film.
- the manufacturing method may further include: processing the surface of the polysilicon film layer facing away from the buffer layer, and removing the polysilicon film layer away from the buffer layer. Part of the film on the side.
- the surface of the polysilicon film layer facing away from the buffer layer may be etched by a dry etching process to remove a portion of the surface film layer enriched in metal atoms in the polysilicon film layer.
- a dry etching process to remove a portion of the surface film layer enriched in metal atoms in the polysilicon film layer.
- an ICP (Inductively Coupled Plasma) device can be used, in a CF 4 and O 2 or Cl 2 and O 2 atmosphere, and the source power is the first preset power.
- the surface of the polysilicon film layer is etched under the condition that the lower electrode bias power (Bias Power) is the second preset power.
- the first preset power is high power according to the requirements of the actual manufacturing method.
- the second predetermined power may be made low power or zero power.
- the method for preparing the polysilicon film in the thin film transistor provided by the embodiment of the present disclosure is specifically described below with reference to FIG. 2 to FIG. It can include the following steps:
- a 50 nm thick SiNx film layer is deposited as a barrier layer 2 on the base substrate 1 by a plasma chemical vapor deposition process.
- the base substrate 1 may be a glass substrate, and the SiNx film layer may be used to block alkali metal ions in the glass substrate, for example, Na ions or K ions.
- a schematic view of the barrier layer 2 formed on the base substrate 1 is shown in FIG.
- a 50 nm thick patterned Ni metal layer 3 is formed on the barrier layer 2 by a sputtering process and using a mask conforming to the pattern of the polysilicon film layer formed later.
- the pattern of the polysilicon film layer formed later corresponds to the channel region in the thin film transistor.
- the orthographic projection of the pattern of the Ni metal layer 3 on the underlying substrate overlaps with the orthographic projection of the pattern of the polysilicon film layer on the underlying substrate.
- a 50 nm thick SiOx film is deposited on the Ni metal layer 3 as a buffer layer 4 by a plasma chemical vapor deposition process, and the SiOx film is used to control the amount of metal entering the polysilicon film.
- a schematic view of the buffer layer 4 formed on the Ni metal layer 3 is shown in FIG.
- Step 4 annealing is performed under the condition that the temperature is 500 ° C and the duration is the first predetermined period of time, and the metal atoms in the Ni metal layer 3 are diffused to the upper surface of the SiOx buffer layer 4, and the surface of the buffer layer 4 is formed by diffusion.
- a metal diffusion layer 5 composed of metal atoms.
- a schematic view of the metal diffusion layer 5 formed on the buffer layer 4 is shown in FIG.
- step five a 50 nm thick amorphous silicon film 60 is deposited on the metal diffusion layer 5 by plasma chemical vapor deposition.
- a schematic view of the amorphous silicon film 60 formed on the metal diffusion layer 5 is shown in FIG.
- Step 6 forming a patterned photoresist layer (not shown) on the amorphous silicon film 60, and using a dry etching process, under the shielding of the patterned photoresist layer, in the fluorine gas and
- the amorphous silicon film 60 is etched in an atmosphere of a mixed gas of chlorine gas to form a patterned amorphous silicon film layer 6, which is converted into a polysilicon film layer after being subjected to crystallization treatment. It can be used as an active layer of a thin film transistor.
- the overetch ratio can be appropriately increased, and when the patterned amorphous silicon film layer 6 is formed, the metal diffusion layer 5 in the corresponding region of the non-channel region is simultaneously removed.
- a schematic view after forming the patterned amorphous silicon film layer 6 is shown in FIG.
- step 7 the annealing is performed under the condition that the temperature is 500 ° C and the duration is the second predetermined period of time, so that the amorphous silicon film layer 6 is converted into the polysilicon film layer 7 under the catalytic action of the metal atoms of the metal diffusion layer.
- the polysilicon film layer 7 may include a first film layer 7a containing more metal atoms on the side facing away from the buffer layer 4 and a second film containing less or no metal atoms in the error tolerance range.
- Layer 7b A schematic diagram after converting the amorphous silicon film layer 6 into the polysilicon film 7 is shown in FIG.
- Step 8 dry etching the surface of the polysilicon film layer 7 by using the ICP device in a mixed gas atmosphere of CF 4 and O 2 with Source Power as the first preset power and Bias Power as the second preset power.
- the etching treatment is performed to remove a portion of the film of the surface of the polysilicon film layer 7 facing away from the buffer layer 4, that is, the first film layer 7a, while leaving the second film layer 7b.
- a schematic view after removing the first film layer 7a is shown in FIG.
- an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, comprising forming a patterned polysilicon film on a substrate by using a method for fabricating a polysilicon film in a thin film transistor provided by an embodiment of the present disclosure.
- the principle of the method for fabricating the thin film transistor is similar to the method for fabricating the polysilicon film. Therefore, the implementation of the method for fabricating the thin film transistor can be referred to the implementation of the method for fabricating the polysilicon film, and the repeated description is omitted here.
- the manufacturing method of the thin film transistor further includes a manufacturing step of forming another film layer.
- the manufacturing step of the thin film transistor may further include the following steps:
- Step 1 A gate insulating layer 8 and a patterned gate electrode 9 are sequentially formed on the side of the polysilicon film layer 7 facing away from the substrate 1 .
- the pattern of the polysilicon film layer 7 is orthographically projected on the substrate substrate 1 to cover the orthographic projection of the pattern of the gate electrode 9 on the substrate substrate 1.
- a gate insulating layer 8 is formed on the polysilicon film layer 7, and a gate electrode 9 is formed on the gate insulating layer 8.
- the polysilicon film layer 7 herein may refer to a polysilicon film layer after removing a portion of the film from the surface on the side of the buffer layer 4.
- Step 2 forming a source/drain insulating layer 10 having a first via 13 and a second via 14 on a side of the gate 9 facing away from the substrate 1.
- the orthographic projection of the pattern of the polysilicon film layer 7 on the substrate substrate 1 covers the front projection of the first via hole 13 and the second via hole 14 in the substrate substrate 1; 1 the first via hole 13 and the second via hole 14
- the orthographic projection of the substrate 1 and the pattern of the gate 9 do not overlap the orthographic projection of the substrate 1.
- Step 3 forming a source 11 and a drain 12 on a side of the source/drain insulating layer 10 facing away from the substrate 1; wherein the source 11 is in contact with the polysilicon layer 7 through the first via 13, and the drain 12 The second via hole 14 is in contact with the polysilicon film layer 7.
- an embodiment of the present disclosure further provides a polysilicon film applied to a thin film transistor, and referring to FIG. 9, may include: a metal layer 3 disposed on one side of the substrate substrate 1; and disposed on the metal layer 3 away from the liner a buffer layer 4 on one side of the base substrate 1; a polysilicon film layer 7 disposed on a side of the buffer layer 4 facing away from the substrate substrate (the polysilicon film layer 7 may be referred to as a second film after removing a surface portion of the film facing away from the buffer layer side) The layer 7b), wherein the polysilicon film layer 7 is fabricated by the method for fabricating the above polysilicon film provided by the embodiments of the present disclosure.
- the principle of solving the problem of the polysilicon film is similar to the method for fabricating the polysilicon film. Therefore, the implementation of the polysilicon film can be referred to the implementation of the method for fabricating the polysilicon film, and the repeated description is omitted here.
- the embodiment of the present disclosure further provides a thin film transistor.
- the principle of solving the problem is similar to the method for fabricating the thin film transistor. Therefore, the implementation of the thin film transistor can be implemented by referring to the implementation of the method for fabricating the thin film transistor. I will not go into details here.
- the thin film transistor provided by the embodiment of the present disclosure may specifically include: a polysilicon film 7 disposed on one side of the substrate 1; wherein the polysilicon film 7 is a polysilicon film provided by the embodiment of the present disclosure.
- a gate insulating layer 8 on the side of the polysilicon film layer 7 facing away from the substrate 1 and a patterned gate electrode 9 are sequentially disposed; wherein the pattern of the polysilicon film layer 7 covers the gate electrode 9 in the orthographic projection of the substrate substrate 1 An orthographic projection of the pattern on the base substrate 1.
- the polysilicon film layer 7 may refer to the second film layer 7b after the partial film (i.e., the first film layer 7a) facing away from the surface of the buffer layer is removed.
- a source/drain insulating layer 10 disposed on a side of the gate electrode 9 facing away from the substrate substrate 1 and having a first via hole 13 and a second via hole 14; wherein the pattern of the polysilicon film layer 7 is covered by the orthographic projection of the substrate substrate 1
- the orthographic projections do not overlap.
- a source 11 and a drain 12 disposed on a side of the source/drain insulating layer 10 facing away from the substrate 1; wherein the source 11 is connected to the polysilicon layer 7 through the first via 13, and the drain 12 passes through the second pass.
- the hole 14 is connected to the polysilicon film layer 7.
- the present disclosure allows metal atoms in the metal layer to be contacted with the amorphous silicon film layer by diffusion after sequentially forming a metal layer, a buffer layer, and an amorphous silicon film layer on the substrate.
- the crystalline silicon film layer can be converted into a polysilicon film layer under the catalytic action of metal atoms. Since the buffer layer existing in the fabricated thin film transistor is used in place of the metal isolation layer in the related art when the amorphous silicon film layer is converted into the polysilicon film layer, it is not necessary to separately form the metal isolation layer. Also, since the buffer layer and the metal layer are prepared before the formation of the amorphous silicon film layer, the process of removing the metal layer and the buffer layer can also be omitted. In turn, the production cost can be reduced and the process steps can be simplified.
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Abstract
Description
Claims (10)
- 一种多晶硅薄膜的制作方法,所述多晶硅薄膜应用于薄膜晶体管中;其中,所述制作方法包括:在衬底基板一侧形成金属层;在所述金属层背离所述衬底基板的一侧形成缓冲层;在所述缓冲层背离所述衬底基板的一侧形成非晶硅膜层;通过金属原子对所述非晶硅膜层的催化作用,将所述非晶硅膜层转化为多晶硅膜层;其中,所述金属原子为所述金属层扩散的并与所述非晶硅膜层接触的金属原子。
- 如权利要求1所述的制作方法,其中,在所述形成缓冲层之后,在所述形成非晶硅膜层之前,所述制作方法还包括:采用第一退火工艺,在所述缓冲层背离所述衬底基板的一侧形成金属扩散层;其中,所述金属扩散层由所述金属层的金属原子扩散到所述缓冲层背离所述衬底基板的一侧形成;所述通过金属原子对所述非晶硅膜层的催化作用,将所述非晶硅膜层转化为多晶硅膜层,具体包括:采用第二退火工艺,使所述非晶硅膜层通过所述金属扩散层的催化作用转化为多晶硅膜层。
- 如权利要求2所述的制作方法,其中,所述形成非晶硅膜层,具体包括:在所述金属扩散层背离所述衬底基板一侧形成非晶硅薄膜;采用干法刻蚀工艺,使所述非晶硅薄膜形成图案化的非晶硅膜层,并去除除第一区域以外的其余区域中的金属扩散层;其中,所述第一区域在所述衬底基板的正投影与所述非晶硅膜层的图案在所述衬底基板的正投影重叠。
- 如权利要求3所述的制作方法,其中,所述形成金属层,具体包括:在所述衬底基板的一侧形成图案化的金属层;其中,所述金属层的图案 在所述衬底基板的正投影与所述非晶硅膜层的图案在所述衬底基板的正投影重叠。
- 如权利要求1所述的制作方法,其中,所述通过金属原子对所述非晶硅膜层的催化作用,将所述非晶硅膜层转化为多晶硅膜层,具体包括:采用第三退火工艺,使所述金属层的金属原子扩散到所述非晶硅膜层,并使所述非晶硅膜层通过扩散到的金属原子的催化作用转化为多晶硅膜层。
- 如权利要求1所述的制作方法,其中,在所述将所述非晶硅膜层转化为多晶硅膜层之后,所述制作方法还包括:对所述多晶硅膜层背离所述缓冲层一侧的表面进行处理,去除所述多晶硅膜层背离所述缓冲层一侧的部分薄膜。
- 如权利要求1所述的制作方法,其中,在所述形成金属层之前,所述制作方法还包括:在所述衬底基板上形成阻挡层。
- 一种薄膜晶体管的制作方法,其中,包括:采用如权利要求1-7任一项所述的多晶硅薄膜的制作方法,在衬底基板上形成图案化的多晶硅薄膜;在所述多晶硅膜层背离所述衬底基板的一侧依次形成栅极绝缘层与图案化的栅极;其中,所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述栅极的图案在所述衬底基板的正投影;在所述栅极背离所述衬底基板的一侧形成具有第一过孔和第二过孔的源漏极绝缘层;其中,所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述第一过孔和所述第二过孔在所述衬底基板的正投影;所述第一过孔和所述第二过孔在所述衬底基板的正投影与所述栅极的图案在所述衬底基板的正投影无交叠;在所述源漏极绝缘层背离所述衬底基板的一侧形成源极和漏极;其中,所述源极通过所述第一过孔与所述多晶硅膜层连接,所述漏极通过所述第二过孔与所述多晶硅膜层连接。
- 一种多晶硅薄膜,其中,包括:设置在衬底基板一侧的金属层;设置在所述金属层背离所述衬底基板一侧的缓冲层;设置在所述缓冲层背离所述衬底基板一侧的多晶硅膜层;其中,所述多晶硅膜层采用如权利要求1-7任一项所述的多晶硅薄膜的制作方法制作而成。
- 一种薄膜晶体管,其中,包括:设置在衬底基板一侧的多晶硅薄膜;其中,所述多晶硅薄膜为如权利要求9所述的多晶硅薄膜;依次设置在所述多晶硅薄膜背离所述衬底基板一侧的栅极绝缘层和图案化的栅极;其中,所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述栅极的图案在所述衬底基板的正投影;设置在所述栅极背离所述衬底基板一侧且具有第一过孔和第二过孔的源漏极绝缘层;其中,所述多晶硅膜层的图案在所述衬底基板的正投影覆盖所述第一过孔和所述第二过孔在所述衬底基板的正投影;所述第一过孔和所述第二过孔在所述衬底基板的正投影与所述栅极的图案在所述衬底基板的正投影无交叠;设置在所述源漏极绝缘层背离所述衬底基板一侧的源极和漏极;其中,所述源极通过所述第一过孔与所述多晶硅膜层连接,所述漏极通过所述第二过孔与所述多晶硅膜层连接。
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