CN108550590A - 主动元件基板及其制法 - Google Patents
主动元件基板及其制法 Download PDFInfo
- Publication number
- CN108550590A CN108550590A CN201810612190.0A CN201810612190A CN108550590A CN 108550590 A CN108550590 A CN 108550590A CN 201810612190 A CN201810612190 A CN 201810612190A CN 108550590 A CN108550590 A CN 108550590A
- Authority
- CN
- China
- Prior art keywords
- layer
- grid
- insulating layer
- active device
- device substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 88
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 19
- 230000000873 masking effect Effects 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 41
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 10
- 238000000059 patterning Methods 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 238000005224 laser annealing Methods 0.000 description 5
- 239000011787 zinc oxide Substances 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002003 electron diffraction Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 150000002927 oxygen compounds Chemical class 0.000 description 4
- DNAUJKZXPLKYLD-UHFFFAOYSA-N alumane;molybdenum Chemical group [AlH3].[Mo].[Mo] DNAUJKZXPLKYLD-UHFFFAOYSA-N 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000037230 mobility Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical group [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- FAHBNUUHRFUEAI-UHFFFAOYSA-M hydroxidooxidoaluminium Chemical compound O[Al]=O FAHBNUUHRFUEAI-UHFFFAOYSA-M 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- -1 aluminium tin-oxide Chemical compound 0.000 description 1
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明公开一种主动元件基板及其制法,该主动元件基板包括基板、第一主动元件以及第二主动元件。第一主动元件包括第一栅极、结晶金属氧化物层、第一绝缘层、第一源极与第一漏极。结晶金属氧化物层位于第一栅极上。结晶金属氧化物层与第一栅极之间夹有第一绝缘层。以穿透式电子显微镜的选区绕射模式观察从结晶金属氧化物的上表面至结晶金属氧化物层的下表面的范围,可以观察到结晶相的绕射图案。第二主动元件包括第二栅极、硅半导体层、第二源极与第二漏极。
Description
技术领域
本发明涉及一种主动元件(有源元件)基板,且特别是涉及一种包括结晶金属氧化物层的主动元件基板及其制法。
背景技术
目前,背通道蚀刻型(Back-Channel Etch)的金属氧化物薄膜晶体管逐渐被许多公司所重视。背通道蚀刻型的金属氧化物薄膜晶体管具有光刻次数少、器件小型化、制造成本低等优点,有利于制造更高开口率的显示面板。
在背通道蚀刻型金属氧化物薄膜晶体管的制作工艺中,金属形成于金属氧化物半导体通道层上,接着图案化金属以形成互相分离的源极与漏极。然而,在图案化金属时,金属氧化物半导体通道层相当容易因为暴露于蚀刻剂下而受到损伤,使得产品良率下降。有鉴于此,目前亟需一种能够解决前述问题的方法。
发明内容
本发明提供一种主动元件基板,在源极与漏极的图案化制作工艺中,可以减少蚀刻液对金属氧化物造成的损害。
本发明提供一种主动元件基板的制造方法,在形成源极与漏极的制作工艺中,可以减少蚀刻液对金属氧化物造成的损害。
本发明的一种主动元件基板,包括基板、第一主动元件以及第二主动元件。第一主动元件包括第一栅极、结晶金属氧化物层、第一绝缘层、第一源极与第一漏极。结晶金属氧化物层位于第一栅极上,且与第一栅极之间夹有第一绝缘层。以穿透式电子显微镜的选区绕射模式观察从结晶金属氧化物的上表面至结晶金属氧化物层的下表面的范围,可以观察到结晶相的绕射图案。第一源极及第一漏极电连接结晶金属氧化物层。第二主动元件包括第二栅极、硅半导体层、第二源极与第二漏极。硅半导体层,与第二栅极重叠。第二源极及第二漏极,与该硅半导体层电连接。
本发明的一种主动元件基板的制造方法,包括:形成第一栅极于基板上;形成第一绝缘层于第一栅极上;形成非结晶金属氧化物层于第一栅极上;形成第二绝缘层于非结晶金属氧化物层上;形成非结晶硅层于第二绝缘层上,且非结晶金属氧化物层位于非结晶硅层与第一栅极之间;进行快速热退火制作工艺,以将非结晶金属氧化物层转变成结晶金属氧化物层;以及形成第一源极与第一漏极,与结晶金属氧化物层电连接。
基于上述,本发明的至少一实施例中,主动元件基板金属氧化物层包括结晶相,可以减少在形成源极与漏极的制作工艺中,蚀刻液对金属氧化物造成的损害。此外,本发明的非结晶金属氧化物层不需经过准分子激光退火(excimer laser annealing,ELA)就可以转变成结晶金属氧化物层,可以缩减制造主动元件基板所需要的成本及工时。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附的附图作详细说明如下。
附图说明
图1A~图1D是本发明的一实施例的一种主动元件基板的制造流程的剖面示意图;
图2是本发明的一实施例的一种主动元件基板的制造流程的剖面示意图;
图3A~图3D是本发明的一实施例的一种主动元件基板的制造流程的剖面示意图;
图4是本发明的一实施例的一种结晶金属氧化物层的绕射图案的示意图;
图5是本发明的一实施例的一种结晶金属氧化物层的绕射图案的示意图;
图6是本发明的一实施例的一种结晶金属氧化物层的绕射图案的示意图;
图7A是本发明的一实施例的一种结晶金属氧化物层的穿透式电子显微镜照片图;
图7B~图7D是本发明的一实施例的一种结晶金属氧化物层的纳米束电子绕射(nano-beam electron diffraction,NBED)照片图。
符号说明
1、2、3:主动元件基板
100:基板
110:第一绝缘层
120、120’:第二绝缘层
130:非结晶硅层
130’:硅半导体层
140:第三绝缘层
CMO:结晶金属氧化物层
D1:第一漏极
D2:第二漏极
G1:第一栅极
G2:第二栅极
H1、H2、H3、H4:开口
M1:第一导电材料层
M2:第二导电材料层
M3:第三导电材料层
MO:非结晶金属氧化物层
R1:第一区
R2:第二区
S1:第一源极
S2:第二源极
SM:遮蔽金属层
T1:第一主动元件
T2:第二主动元件
X、Y、Z:区域
具体实施方式
图1A~图1D是依照本发明的一实施例的一种主动元件基板1的制造流程的剖面示意图。
请先参考图1A,在基板100上依序形成图案化的第一导电材料层M1、第一绝缘层110、非结晶金属氧化物层MO、第二绝缘层120以及非结晶硅层130。
图案化的第一导电材料层M1例如包括第一栅极G1与第二栅极G2,第一栅极G1与第二栅极G2分别位于基板100上的第一区R1与第二区R2。在一些实施例中,主动元件基板1为像素阵列基板,基板100上的第一区R1与第二区R2分别为显示区与周边区,但本发明不以此为限。
在一些实施例中,第一栅极G1与第二栅极G2包括金属,例如包括钛金、钼、铜、铝、银或其他金属或前述金属的组合。在一些实施例中,第一栅极G1与第二栅极G2包括多层结构,例如是钛-铝-钛结构或是钼-铝-钼结构,但本发明不以此为限。在一些实施例中,第一栅极G1与第二栅极G2较佳为钛或钛与铝的组合。在一些实施例中,第一栅极G1与第二栅极G2的厚度较佳为0.1微米至1微米,但本发明不以此为限。在一些实施例中,形成第一栅极G1与第二栅极G2的方法包括物理气相沉积(Physical vapor deposition,PVD)或其他类似的制作工艺。在一些实施例中,第一栅极G1与第二栅极G2同时形成。
形成第一绝缘层110于第一栅极G1上。在一些实施例中,第一绝缘层110覆盖第一栅极G1、第二栅极G2以及部分基板100。第一绝缘层110例如包括氧化硅。第一绝缘层110的厚度较佳为50纳米~300纳米,例如为100纳米、150纳米、200纳米或250纳米。在此厚度范围内,第一绝缘层110可以获得较佳的保温以及传热效果。在一些实施例中,形成第一绝缘层110的方法包括化学气相沉积(Chemical Vapor Deposition,CVD)或其他类似的制作工艺。
形成非结晶金属氧化物层MO于第一区R1中的第一栅极G1上,非结晶金属氧化物层MO至少覆盖第一栅极G1的部分顶面。在一些实施例中,非结晶金属氧化物层MO还覆盖了第一栅极G1的部分侧面。在一些实施例中,非结晶金属氧化物层MO还形成于第二区R2中的第二栅极G2上。非结晶金属氧化物层MO的金属元素例如包括元素铟、元素镓、元素锌或上述金属元素的组合。非结晶金属氧化物层MO例如是在常温下以溅镀的方式形成,但本发明不以此为限。在一些实施例中,非结晶金属氧化物层MO的厚度为40纳米~100纳米,例如为50纳米、60纳米、70纳米、80纳米或90纳米。
形成第二绝缘层120于非结晶金属氧化物层MO上,非结晶金属氧化物层MO位于第一绝缘层110与第二绝缘层120之间。在一些实施例中,第二绝缘层120覆盖第一栅极G1、第二栅极G2以及部分基板100。第二绝缘层120例如包括氧化硅。第二绝缘层120的厚度较佳为50纳米~250纳米,例如为100纳米、150纳米或200纳米。在此厚度范围内,第二绝缘层120可以获得较佳的保温以及传热效果。在一些实施例中,形成第二绝缘层120的方法包括化学气相沉积(Chemical Vapor Deposition,CVD)或其他类似的制作工艺。
形成非结晶硅层130于第二绝缘层120上,非结晶金属氧化物层MO位于非结晶硅层130与第一栅极G1之间。非结晶硅层130的厚度为10纳米~230纳米,较佳为40纳米~60纳米,例如为50纳米。在一些实施例中,形成非结晶硅层130的方法包括化学气相沉积(Chemical Vapor Deposition,CVD)或其他类似的制作工艺。
请参考图1B,进行一快速热退火制作工艺RTP,以将非结晶金属氧化物层MO转变成结晶金属氧化物层CMO。在一些实施例中,快速热退火制作工艺RTP的最高温度为400度~700度,例如是625度、650度或675度,且持续时间为30秒~6分钟。
现有技术在快速热退火制作工艺之后会再进行准分子激光退火(Excimer laserannealing,ELA)提供热量,才能使半导体(例如非结晶金属氧化物或非结晶硅)结晶化,但本发明直接于快速热退火制作工艺就能将非结晶金属氧化物层MO转变成结晶金属氧化物层CMO,节省了制造主动元件基板的成本以及工时。在一些实施例中,结晶金属氧化物层CMO包括了结晶轴不互相平行的多个结晶,但本发明不以此为限。以穿透式电子显微镜的选区绕射模式观察从结晶金属氧化物CMO的上表面U至结晶金属氧化物层CMO的下表面B的范围,可以观察到结晶相的绕射图案。在一些实施例中,结晶金属氧化物CMO包括铟镓锌氧化物,若以铟镓锌氧化物做为薄膜晶体管的通道层使用,则可以形成较薄的栅绝缘层,且具有载流子迁移率较高的优点。
请参考图1C,移除位于第一区R1的部分非结晶硅层130,剩余的非结晶硅层130包括硅半导体层130’。硅半导体层130’至少覆盖部分第二栅极G2。在本实施例中,部分第二绝缘层120也会被移除,部分第一绝缘层110以及剩于的第二绝缘层120’位于硅半导体层130’与第二栅极G2之间,且第二绝缘层120’与该第二栅极G2之间具有部分第一绝缘层110。
在基板100上形成第二导电材料层M2,第二导电材料层M2例如覆盖结晶金属氧化物层CMO、硅半导体层130’、第一绝缘层110以及第二绝缘层120’。第二导电材料层M2例如包括钛金、钼、铜、铝、银或其他金属或前述金属的组合。在一些实施例中,第二导电材料层M2包括多层结构,例如是钛-铝-钛结构或是钼-铝-钼结构,但本发明不以此为限。在一些实施例中,第二导电材料层M2较佳为钼或钼与铝的组合,但本发明不以此为限。在一些实施例中,形成第二导电材料层M2的方法包括物理气相沉积(Physical vapor deposition,PVD)或其他类似的制作工艺。
在一些实施例中,形成第二导电材料层M2之前,会先于结晶金属氧化物层CMO上形成一层蚀刻停止层,以在后续图案化第二导电材料层M2时能保护结晶金属氧化物层CMO。
请参考图1D,对第二导电材料层M2进行图案化制作工艺,以形成第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。第一源极S1与第一漏极D1电连接结晶金属氧化物层CMO。第二源极S2与第二漏极D2电连接硅半导体层130’。
图案化第二导电材料层M2的方法例如包括利用湿式蚀刻法于第二导电材料层M2中形成开口H1以及开口H2。开口H1将第一源极S1与第一漏极D1分隔开来,开口H2将第二源极S2与第二漏极D2分隔开来。在一些实施例中,结晶金属氧化物层CMO相较于非结晶金属氧化物层MO具有更佳的抗酸蚀能力,因此,可以降低图案化第二导电材料层M2时蚀刻液对结晶金属氧化物层CMO所造成的损害。在一些实施例中,图案化第二导电材料层M2会使用草酸、铝酸、氢氟酸或其他类似的蚀刻液。在一些实施例中,第二导电材料层M2使用具有较低阻值以及制造较低成本的钼-铝-钼多层结构,图案化第二导电材料层M2时可以使用铝酸蚀刻液以进一步降低制造成本。在本实施例中,利用湿式蚀刻法图案化第二导电材料层M2具有生产速度快以及低成本的优点。
至此,本实施例中的主动元件基板1已经大致完成,主动元件基板1包括基板100、第一主动元件T1以及第二主动元件T2。第一主动元件T1包括第一栅极G1、结晶金属氧化物层CMO、第一绝缘层110、第一源极S1与第一漏极D1。结晶金属氧化物层CMO位于第一栅极G1上,且与第一栅极G1之间夹有第一绝缘层110。第一源极S1及第一漏极D1电连接结晶金属氧化物层CMO。第二主动元件T2包括第二栅极G2、硅半导体层130’、第二源极S2与第二漏极D2。部分第一绝缘层110与第二绝缘层120’夹在第二栅极G2与硅半导体层130’之间。
在本实施例中,第一主动元件T1的第一漏极D1电连接至像素电极,且第二主动元件T2例如为栅极驱动电路在阵列基板上(Gate on Array,GOA)中的栅极驱动元件。第一主动元件T1的结晶金属氧化物层CMO具有较低的漏电流,且第二主动元件T2的硅半导体层130’包括非晶硅,因此,本实施例的主动元件基板1同时具有省电以及制造成本较低等优点,且以包括非晶硅的第二主动元件T2来作为栅极驱动电路在阵列基板上中的栅极驱动元件可以有更高元件可靠度。此外,本实施例中的第一主动元件T1为背通道蚀刻型薄膜晶体管,因此,主动元件基板1具有较高的开口率。
图2是依照本发明的一实施例的一种主动元件基板2的制造流程的剖面示意图。在此必须说明的是,图2的实施例沿用图1A~图1D的实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,在此不赘述。
请参考图2,在本实施例中,第二栅极G2不属于图案化的第一导电材料层M1,图案化的第一导电材料层M1例如包括第一栅极G1与遮蔽金属层SM。硅半导体层130’至少覆盖部分遮蔽金属层SM,部分第一绝缘层110与第二绝缘层120’位于硅半导体层130’与遮蔽金属层SM之间,且第二绝缘层120’与遮蔽金属层SM之间具有部分第一绝缘层110。
形成第三绝缘层140以覆盖第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。第三绝缘层140包括暴露出第二源极S2的开口H3以及暴露出第二漏极D2的开口H4。
在第三绝缘层140上形成图案化的第三导电材料层M3,第三导电材料层M3例如包括第二栅极G2、源极接触结构SC以及漏极接触结构DC。第二栅极G2、源极接触结构SC以及漏极接触结构DC属于同一膜层。源极接触结构SC穿过开口H3以电连接第二源极S2。漏极接触结构DC穿过开口H4以电连接第二漏极D2。第二栅极G2位于硅半导体层130’上方。在本实施例中,第二主动元件T2包括顶部栅极结构,硅半导体层130’位于遮蔽金属层SM与第二栅极G2之间,但本发明不以此为限。
在一些实施例中,第三导电材料层M3的材料包括透明导电材料,例如是铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟镓锌氧化物或其他金属氧化物或上述两种以上氧化物的叠层。由于第三导电材料层M3包括透明导电材料,当主动元件基板是用于显示装置时,可以具有较高的开口率。
在一些实施例中,遮蔽金属层SM能作为栅极使用,且硅半导体层130’位于第二栅极G2与遮蔽金属层SM之间,以形成双栅极结构。由于遮蔽金属层SM以及第一栅极G1为同一道图案化制作工艺中所定义出来的,因此,不用额外的图案化制作工艺就可以得到双栅极结构。双栅极结构可以增强硅半导体层130’的载流子迁移率(carrier mobility),因此第二主动元件T2中的硅半导体层130’即使为非晶硅,也可以有足够的载流子迁移率。此外,具有双栅极结构的主动元件可以有较高的元件电流。在一些实施例中,遮蔽金属层SM能作为栅极使用,且第三导电材料层M3不包括第二栅极G2。
图3A~图3D是依照本发明的一实施例的一种主动元件基板3的制造流程的剖面示意图。在此必须说明的是,图3A~图3C的实施例沿用图2的实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,在此不赘述。
图3A之前的步骤类似于图1A与图1B,在此不赘述。在本实施例中,第二栅极G2不属于图案化的第一导电材料层M1,图案化的第一导电材料层M1例如包括第一栅极G1与遮蔽金属层SM。
请参考图3A,移除部分非结晶硅层130(绘于图1B)以及第二绝缘层120(绘于图1B),以形成硅半导体层130’与第二绝缘层120’。硅半导体层130’至少覆盖部分遮蔽金属层SM,部分第一绝缘层110与第二绝缘层120’位于硅半导体层130’与遮蔽金属层SM之间,且第二绝缘层120’与遮蔽金属层SM之间具有部分第一绝缘层110。
在一些实施例中,移除部分非结晶硅层130之前或之后,会对非结晶硅层130进行准分子激光退火(Excimer laser annealing,ELA),以形成包括结晶硅的硅半导体层130’。硅半导体层130’至少覆盖部分遮蔽金属层SM。
请参考图3B,在基板100上形成第二导电材料层M2,第二导电材料层M2例如覆盖结晶金属氧化物层CMO、硅半导体层130’、第一绝缘层110以及第二绝缘层120’。
请参考图3C,对第二导电材料层M2进行图案化制作工艺,以形成第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。第一源极S1与第一漏极D1电连接结晶金属氧化物层CMO。第二源极S2与第二漏极D2电连接硅半导体层130’。图案化第二导电材料层M2的方法例如包括利用湿式蚀刻法于第二导电材料层M2中形成开口H1以及开口H2。开口H1将第一源极S1与第一漏极D1分隔开来,开口H2将第二源极S2与第二漏极D2分隔开来。
请参考图3D,形成第三绝缘层140以覆盖第一源极S1、第一漏极D1、第二源极S2以及第二漏极D2。第三绝缘层140包括暴露出第二源极S2的开口H3以及暴露出第二漏极D2的开口H4。
在第三绝缘层140上形成图案化的第三导电材料层M3,第三导电材料层M3例如包括第二栅极G2、源极接触结构SC以及漏极接触结构DC。第二栅极G2、源极接触结构SC以及漏极接触结构DC属于同一膜层。源极接触结构SC穿过开口H3以电连接第二源极S2。漏极接触结构DC穿过开口H4以电连接第二漏极D2。在本实施例中,第二主动元件T2包括顶部栅极结构,硅半导体层130’位于遮蔽金属层SM与第二栅极G2之间,但本发明不以此为限。在一些实施例中,遮蔽金属层SM能作为栅极使用,且硅半导体层130’位于第二栅极G2与遮蔽金属层SM之间,以形成双栅极结构。在一些实施例中,遮蔽金属层SM能作为栅极使用,且第三导电材料层M3不包括第二栅极G2。
在本实施例中,第一主动元件T1的第一漏极D1电连接至像素电极,且第二主动元件T2例如为栅极驱动电路在阵列基板上(Gate on Array,GOA)中的栅极驱动元件。第一主动元件T1的结晶金属氧化物层CMO具有较低的漏电流,且第二主动元件T2的硅半导体层130’包括多晶硅,因此,本实施例的主动元件基板3同时具有省电以及窄边框等优点。此外,本实施例中的第一主动元件T1为背通道蚀刻型薄膜晶体管,因此,主动元件基板3具有较高的开口率。
图4是依照本发明的一实施例的一种结晶金属氧化物层的绕射图案。图5是依照本发明的一实施例的一种结晶金属氧化物层的绕射图案。图6是依照本发明的一实施例的一种结晶金属氧化物层的绕射图案。
图4~图6可以是同一实施例中的结晶金属氧化物层在不同位置处的绕射图案,也可以是不同实施例中的结晶金属氧化物层的绕射图案。
请参考图4~图6,以穿透式电子显微镜的选区绕射模式观察从上述一些实施例的结晶金属氧化物CMO的上表面U至结晶金属氧化物层CMO的下表面B的范围,可以观察到结晶相的绕射图案,例如是从结晶金属氧化物层CMO剖面拍摄的绕射图案。在图4~图6可以于绕射图案中的看到多个明显的绕射点,而这些绕射点大致上排列出同心圆的样子。在本实施例中,结晶金属氧化物CMO包括多晶的金属氧化物,如铟镓锌氧化物。
图7A是依照本发明的一实施例的一种结晶金属氧化物层的穿透式电子显微镜照片。图7B~图7D是依照本发明的一实施例的一种结晶金属氧化物层的纳米束电子绕射(nano-beam electron diffraction,NBED)照片。图7B~图7D大致上分别对应图7A中的区域X、区域Y以及区域Z。
从图7A~图7D可以看出,结晶金属氧化物层于靠近上表面的区域X、靠近中间的区域Y以及靠近下表面的区域Z中,都可以发现结晶的金属氧化物。在本实施例中,前述金属氧化物为铟镓锌氧化物。
本发明一实施例中的第一主动元件的第一漏极电连接至像素电极,且第二主动元件例如为周边电路的驱动元件。第一主动元件的结晶金属氧化物层具有较低的漏电流,且第二主动元件的硅半导体层包括非晶硅,因此,主动元件基板同时具有省电以及制造成本低等优点。
本发明一实施例中的第一主动元件的第一漏极电连接至像素电极,且第二主动元件例如为周边电路的驱动元件。第一主动元件的结晶金属氧化物层具有较低的漏电流,且第二主动元件的硅半导体层包括多晶硅,因此,主动元件基板同时具有省电以及窄边框等优点。
本发明一实施例中的第一主动元件为背通道蚀刻型薄膜晶体管,因此,主动元件基板具有较高的开口率。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (16)
1.一种主动元件基板,其特征在于,包括:
第一主动元件,位于一基板上,且该第一主动元件包括:
第一栅极;
结晶金属氧化物层,位于该第一栅极上,且与该第一栅极之间夹有第一绝缘层,其中以穿透式电子显微镜的选区绕射模式观察从该结晶金属氧化物的上表面至该结晶金属氧化物层的下表面的范围,可以观察到结晶相的绕射图案;以及
第一源极及第一漏极,与该结晶金属氧化物层电连接;
第二主动元件,位于该基板上,且该第二主动元件包括:
第二栅极;
硅半导体层,与该第二栅极重叠;以及
第二源极及第二漏极,与该硅半导体层电连接。
2.如权利要求1所述的主动元件基板,其中该第一栅极的材料包括钛或钛与铝的组合。
3.如权利要求1所述的主动元件基板,还包括:
第二绝缘层,位于该第二栅极与该硅半导体层之间,且该第二绝缘层与该第二栅极之间具有部分该第一绝缘层。
4.如权利要求3所述的主动元件基板,其中该第一绝缘层以及该第二绝缘层的材料包括氧化硅。
5.如权利要求3所述的主动元件基板,其中该第一绝缘层的厚度为50纳米至300纳米,且该第二绝缘层的厚度为50纳米至300纳米。
6.如权利要求3所述的主动元件基板,还包括:
源极接触结构,电连接该第二源极;
漏极接触结构,电连接该第二漏极;
遮蔽金属层,其中该硅半导体层位于该遮蔽金属层与该第二栅极之间,且该第二栅极、该源极接触结构以及该漏极接触结构属于同一膜层。
7.一种主动元件基板的制造方法,其特征在于,包括:
形成一第一栅极于一基板上;
形成一第一绝缘层于该第一栅极上;
形成一非结晶金属氧化物层于该第一栅极上;
形成一第二绝缘层于该非结晶金属氧化物层上;
形成一非结晶硅层于该第二绝缘层上,且该非结晶金属氧化物层位于该非结晶硅层与该第一栅极之间;
进行一快速热退火制作工艺,以将该非结晶金属氧化物层转变成一结晶金属氧化物层;以及
形成一第一源极与一第一漏极,与该结晶金属氧化物层电连接。
8.如权利要求7所述的主动元件基板的制造方法,其中该快速热退火制作工艺的最高温度为400度~700度,且持续时间为30秒~6分钟。
9.如权利要求7所述的主动元件基板的制造方法,还包括:
形成一第二栅极于该基板上;
形成一硅半导体层,该硅半导体层至少覆盖部分该第二栅极;以及
形成一第二源极与一第二漏极,与该硅半导体层电连接。
10.如权利要求9所述的主动元件基板的制造方法,其中形成该硅半导体层的方法包括:
移除部分该非结晶硅层,剩余的该非结晶硅层包括该硅半导体层。
11.如权利要求9所述的主动元件基板的制造方法,其中形成该硅半导体层的方法包括:
以激光将该非结晶硅层转变为多晶硅层;
移除部分该多晶硅层,剩余的该多晶硅层包括该硅半导体层。
12.如权利要求9所述的主动元件基板的制造方法,其中该第一栅极与该第二栅极同时形成。
13.如权利要求9所述的主动元件基板的制造方法,其中该硅半导体层与该第二栅极之间夹有该第一绝缘层以及该第二绝缘层。
14.如权利要求7所述的主动元件基板的制造方法,其中该第一绝缘层以及该第二绝缘层的材料包括氧化硅。
15.如权利要求7所述的主动元件基板的制造方法,其中该第一绝缘层的厚度为50纳米至300纳米,且该第二绝缘层的厚度为50纳米至300纳米。
16.如权利要求7所述的主动元件基板的制造方法,其中该第一栅极的材料包括钛或钛与铝的组合。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107113414A TWI662330B (zh) | 2018-04-19 | 2018-04-19 | 主動元件基板及其製法 |
TW107113414 | 2018-04-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108550590A true CN108550590A (zh) | 2018-09-18 |
CN108550590B CN108550590B (zh) | 2021-02-09 |
Family
ID=63493665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810612190.0A Active CN108550590B (zh) | 2018-04-19 | 2018-06-14 | 主动元件基板及其制法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10840380B2 (zh) |
CN (1) | CN108550590B (zh) |
TW (1) | TWI662330B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI651765B (zh) * | 2018-03-29 | 2019-02-21 | 友達光電股份有限公司 | 結晶金屬氧化物層的製造方法、主動元件基板的製造方法及主動元件基板 |
TWI662330B (zh) * | 2018-04-19 | 2019-06-11 | 友達光電股份有限公司 | 主動元件基板及其製法 |
CN108766972B (zh) * | 2018-05-11 | 2021-10-22 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、显示基板 |
TWI699753B (zh) * | 2019-05-21 | 2020-07-21 | 友達光電股份有限公司 | 主動元件基板及其驅動方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201251026A (en) * | 2011-06-02 | 2012-12-16 | Au Optronics Corp | Hybrid thin film transistor and manufacturing method thereof and display panel |
CN104538352A (zh) * | 2014-12-31 | 2015-04-22 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示装置 |
CN106783627A (zh) * | 2016-12-13 | 2017-05-31 | 友达光电股份有限公司 | 金属氧化物半导体层的结晶方法、半导体结构、主动阵列基板、及氧化铟镓锌晶体 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005260168A (ja) * | 2004-03-15 | 2005-09-22 | Sharp Corp | トランジスタを備えた装置およびその製造方法 |
JP2010123758A (ja) | 2008-11-19 | 2010-06-03 | Nec Corp | 薄膜デバイス及びその製造方法 |
WO2013115051A1 (ja) | 2012-01-31 | 2013-08-08 | シャープ株式会社 | 半導体装置およびその製造方法 |
KR102639256B1 (ko) | 2012-12-28 | 2024-02-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치, 및 반도체 장치의 제작 방법 |
TWI593024B (zh) | 2015-07-24 | 2017-07-21 | 友達光電股份有限公司 | 薄膜電晶體的製造方法 |
TWI542715B (zh) | 2015-09-21 | 2016-07-21 | 友達光電股份有限公司 | 一種結晶氧化銦鎵鋅半導體層及薄膜電晶體的製造方法 |
TWI611463B (zh) | 2016-06-29 | 2018-01-11 | 友達光電股份有限公司 | 金屬氧化物半導體層的結晶方法及半導體結構 |
TWI662330B (zh) * | 2018-04-19 | 2019-06-11 | 友達光電股份有限公司 | 主動元件基板及其製法 |
-
2018
- 2018-04-19 TW TW107113414A patent/TWI662330B/zh active
- 2018-06-14 CN CN201810612190.0A patent/CN108550590B/zh active Active
-
2019
- 2019-04-19 US US16/388,887 patent/US10840380B2/en active Active
-
2020
- 2020-09-30 US US17/037,698 patent/US11362216B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201251026A (en) * | 2011-06-02 | 2012-12-16 | Au Optronics Corp | Hybrid thin film transistor and manufacturing method thereof and display panel |
CN104538352A (zh) * | 2014-12-31 | 2015-04-22 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示装置 |
CN106783627A (zh) * | 2016-12-13 | 2017-05-31 | 友达光电股份有限公司 | 金属氧化物半导体层的结晶方法、半导体结构、主动阵列基板、及氧化铟镓锌晶体 |
Also Published As
Publication number | Publication date |
---|---|
TW201944134A (zh) | 2019-11-16 |
US11362216B2 (en) | 2022-06-14 |
US20210013344A1 (en) | 2021-01-14 |
US10840380B2 (en) | 2020-11-17 |
US20190326440A1 (en) | 2019-10-24 |
TWI662330B (zh) | 2019-06-11 |
CN108550590B (zh) | 2021-02-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108550590A (zh) | 主动元件基板及其制法 | |
TWI385760B (zh) | 製造陣列基板的方法 | |
JP5171258B2 (ja) | Tft基板及びtft基板の製造方法 | |
JP5780902B2 (ja) | 半導体薄膜、薄膜トランジスタ及びその製造方法 | |
KR20100027377A (ko) | 박막 트랜지스터 기판 및 이의 제조 방법 | |
TW201244084A (en) | Oxide semiconductor layer and semiconductor device | |
JP2008219008A (ja) | 薄膜トランジスタ及びその製造方法 | |
US20130095606A1 (en) | Fabrication Method for ZnO Thin Film Transistors Using Etch-stop Layer | |
US20080210934A1 (en) | Semiconductor Device Using Titanium Dioxide as Active Layer and Method for Producing Semiconductor Device | |
CN107342260B (zh) | 一种低温多晶硅tft阵列基板制备方法及阵列基板 | |
WO2014127575A1 (zh) | 阵列基板的制备方法 | |
CN110246900A (zh) | 半导体装置及其制造方法 | |
JP2019091794A (ja) | 半導体装置 | |
EP3261127B1 (en) | Thin-film transistor and manufacturing method therefor, array substrate and display device | |
US10714631B2 (en) | Semiconductor structure and methods for crystallizing metal oxide semiconductor layer | |
JP2020004860A (ja) | 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法 | |
US20190088786A1 (en) | Low temperature poly-silicon thin film transistor, manufacturing method thereof, and array substrate | |
CN106057679A (zh) | 氧化物半导体薄膜晶体管的制作方法 | |
KR100474385B1 (ko) | 비정질실리콘박막을결정화하는방법과이를이용한다결정실리콘박막트랜지스터제조방법 | |
WO2017107238A1 (zh) | 阵列基板及其制造方法、液晶显示面板 | |
KR101346612B1 (ko) | 박막 트랜지스터 및 이의 제조 방법 | |
JPH11274505A (ja) | 薄膜トランジスタ構造およびその製造方法 | |
US20210210622A1 (en) | Thin film transistor and manufacturing method thereof, array substrate, display device and sensor | |
JPH02189935A (ja) | 薄膜トランジスタの製造方法 | |
JPH09307115A (ja) | 薄膜トランジスタ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |