WO2015172543A1 - 多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法 - Google Patents

多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法 Download PDF

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WO2015172543A1
WO2015172543A1 PCT/CN2014/091542 CN2014091542W WO2015172543A1 WO 2015172543 A1 WO2015172543 A1 WO 2015172543A1 CN 2014091542 W CN2014091542 W CN 2014091542W WO 2015172543 A1 WO2015172543 A1 WO 2015172543A1
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amorphous silicon
polysilicon
thin film
film
silicon film
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French (fr)
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刘政
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Definitions

  • Embodiments of the present invention relate to a method of fabricating a polysilicon film, a method of fabricating a low temperature polysilicon thin film transistor, and a method of fabricating an array substrate.
  • the Low Temperature Poly-Silicon-Thin Film Transistor (LTPS-TFT) display has the advantages of high resolution, fast response, high brightness, high aperture ratio, and high LTPS.
  • the electronic mobility rate; in addition, the peripheral driving circuit can be simultaneously fabricated on the glass substrate to achieve the purpose of system integration, space saving and cost of driving the IC, and can reduce the product defect rate.
  • the low temperature polysilicon thin film transistor includes an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode disposed on a base substrate; the active layer includes a source region, a drain region, and a source region and a channel region between the drain regions, and the like.
  • the active layer is generally obtained by performing an ion implantation process on the polysilicon layer.
  • the polysilicon layer is generally formed by forming an amorphous silicon film on the substrate, and then converting the amorphous silicon into polysilicon by using an excimer laser annealing method, and then The polysilicon film is formed into a polysilicon layer of a specific pattern by a patterning process.
  • Embodiments of the present invention provide a method of fabricating a polysilicon film, a polysilicon thin film transistor, and an array substrate.
  • a method for preparing a polysilicon film comprising: forming an amorphous silicon film on a substrate; performing a nickel salt solution treatment on the surface of the amorphous silicon film to make the nickel The salt solution is uniformly applied to the surface of the amorphous silicon film; and the amorphous silicon film is treated by an excimer laser annealing method to crystallize the amorphous silicon film into a polysilicon film.
  • a method of fabricating a polysilicon thin film transistor comprising: forming an active layer on a base substrate, a gate insulating layer over the active layer, a gate electrode, a source electrode, and a drain
  • the active layer includes a source region, a drain region, and the source a channel region between the polar region and the drain region; wherein the polysilicon layer is formed by patterning the polysilicon film, and the active layer passes through the pair of the polysilicon layer and the source A region and a region corresponding to the drain region are formed by a doping process.
  • a method of fabricating an array substrate includes: forming a thin film transistor and a pixel electrode; wherein the thin film transistor is formed by the above-described method of fabricating a polysilicon thin film transistor.
  • FIG. 1 is a schematic flow chart of a method for fabricating a polysilicon thin film transistor according to an embodiment of the invention
  • 2-7 are schematic diagrams showing processes of fabricating a polysilicon thin film transistor according to an embodiment of the present invention.
  • FIG. 8 is a first schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a second structural diagram of an array substrate according to an embodiment of the invention.
  • excimer laser as a gas laser has relatively poor stability, and the uniformity of polycrystalline silicon grains prepared by simply using an excimer laser can also be obtained. Poor, resulting in poor electrical uniformity of the thin film transistor.
  • the usual excimer laser crystallization process melts and recrystallizes amorphous silicon in a short period of time, the grain size is small and the crystal quality is not high, which limits the improvement of the electrical properties of the thin film transistor device.
  • the embodiment of the invention provides a method for preparing a polysilicon film, comprising: forming an amorphous silicon film on a substrate; performing a nickel salt solution treatment on the surface of the amorphous silicon film to uniformly coat the nickel salt solution On the surface of the amorphous silicon film; and treating the amorphous silicon film by an excimer laser annealing method to crystallize the amorphous silicon film into a polysilicon film.
  • the amorphous silicon thin film is processed by an excimer laser annealing method, and the amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by using a process of excimer laser irradiation treatment in a time of about 50 to 150 ns.
  • the surface of the amorphous silicon film instantaneously reaches a high temperature of 1000 ° C or higher and becomes molten. Then, the amorphous silicon in a molten state is annealed to be crystallized to form a polycrystalline silicon film.
  • the treatment method can ensure that the temperature of the glass substrate is about 400 ° C or below, because the laser pulse first excites the hot electron-hole pair in the amorphous silicon film, and then the electron-hole pair is non- Radiation recombination transfers energy to the lattice atoms, enabling instantaneous heating of the amorphous silicon film. Since the instantaneous energy of the laser pulse is absorbed by the amorphous silicon film and converted into phase change energy, no excessive heat energy is transmitted to the glass substrate, which can avoid the temperature rise of the glass substrate during the general furnace annealing. The problem of deformation.
  • nickel remains on the amorphous silicon film.
  • the surface therefore, undergoes excimer laser annealing, and nickel reacts with silicon to form a nickel-silicon bond to form a nickel-silicon mixture. Since the free energy of the silicon crystallized state is lower than that of the amorphous state, the thermal equilibrium process of the nickel-silicon bond rupture and recombination promotes the local crystal lattice recombination of amorphous silicon to polysilicon.
  • Nickel silicide (SiN 2 ) formed of nickel and silicon is easily formed at 350 ° C, and its lattice constant is only 0.4% different from the lattice constant of silicon. It is very suitable as a seed crystal for crystallization of amorphous silicon. Promote the conversion of amorphous silicon to polycrystalline silicon. On the other hand, due to the relatively uniform nucleation center (seed crystal), the polycrystalline silicon crystal can be more uniform. Moreover, due to the catalytic action of nickel, under the same temperature and time conditions, the crystallite size of the catalytic growth is larger, so that the crystal quality is higher.
  • the embodiment of the invention provides a method for preparing a polysilicon film, comprising: forming an amorphous silicon film on a substrate; performing a nickel salt solution treatment on the surface of the amorphous silicon film to uniformly coat the nickel salt solution On the surface of the amorphous silicon film; and treating the amorphous silicon film by an excimer laser annealing method to crystallize the amorphous silicon film into a polysilicon film. Due to Before the amorphous silicon film is treated by excimer laser annealing, the surface of the amorphous silicon film is treated with a nickel salt solution, and nickel remains on the surface of the amorphous silicon film and is subjected to excimer laser annealing treatment.
  • Nickel silicide formed by nickel and silicon as a seed crystal of amorphous silicon can promote the conversion of amorphous silicon to polycrystalline silicon, and make the polycrystalline silicon crystal more uniform, the crystal grain size is larger, and the crystal quality is higher.
  • electrical properties of the thin film transistor can be improved.
  • the nickel salt solution may be uniformly applied to the surface of the amorphous silicon film by immersion or sputtering.
  • the nickel salt solution in the embodiment of the present invention only needs to use a solution containing a trace amount of nickel, for example, a solution having a nickel concentration of 1 to 1000 ⁇ g/mg.
  • the amorphous silicon film is subjected to a nickel salt solution treatment, the amorphous silicon film is subjected to a dehydrogenation process before the amorphous silicon film is processed by an excimer laser annealing method.
  • the treatment is such that the hydrogen content in the amorphous silicon film is 3% or less.
  • the dehydrogenation temperature may be from 400 to 600 ° C, and the treatment time may be from 20 to 120 minutes.
  • the hydrogen content in the amorphous silicon film is controlled to be less than 3% during the preparation process, this step may be omitted, and may be specifically performed according to actual conditions.
  • An embodiment of the present invention further provides a method for fabricating a polysilicon thin film transistor, comprising: forming an active layer on a base substrate, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode above the active layer;
  • the active layer includes a source region, a drain region, and a channel region between the source region and the drain region.
  • the polysilicon layer is formed by patterning the polysilicon film obtained above, and the active layer is formed by doping a region of the polysilicon layer corresponding to the source region and the drain region.
  • the surface of the amorphous silicon film is treated with a nickel salt solution before the amorphous silicon film is treated by an excimer laser annealing method, nickel remains on the surface of the amorphous silicon film, so that the excimer is passed through Laser annealing treatment, nickel silicide formed by nickel and silicon as a seed crystal of amorphous silicon, can promote the conversion of amorphous silicon to polycrystalline silicon, and make the polycrystalline silicon crystal more uniform, the crystal grain size is larger, the crystal quality is high, and the film is made.
  • the electrical performance of the transistor is improved.
  • the thickness of the polysilicon layer is
  • the polysilicon layer is formed by patterning a polysilicon film, for example, by the following steps:
  • the dry etching may be performed by plasma etching, reactive ion etching, inductively coupled plasma etching, or the like.
  • the etching gas may be selected from fluorine-containing and chlorine-containing gases such as carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), sulfur hexafluoride (SF 6 ), and difluoromethylene chloride (CCl 2 F 2 ). Or a mixture of these gases and oxygen (O 2 ).
  • the photoresist is completely removed by a stripping process.
  • the polysilicon layer is formed by dry etching because the dry etching can very well control the sidewall profile of the formed polysilicon layer, that is, the sidewalls of the polysilicon layer can be controlled.
  • the substrate can be vertically aligned, so that the performance of the finally formed active layer is better, and the influence on the performance of the thin film transistor is avoided.
  • a harmful substance such as an alkali metal ion may be contained in the glass substrate, which may affect the performance of the polysilicon layer, and therefore, a buffer layer may be formed on the surface of the substrate before the polysilicon film is formed.
  • an embodiment of the present invention provides an example to describe in detail the method of fabricating the polysilicon thin film transistor and the structures formed. As shown in FIG. 1, the method includes the following steps:
  • a buffer layer 20 is formed on the base substrate 10.
  • the buffer layer 20 is formed by a method such as ECR-CVD or sputtering to block diffusion of impurities contained in the glass into the active layer, thereby preventing influence on characteristics such as threshold voltage and leakage current of the thin film transistor element.
  • the buffer layer 20 can be a single layer of silicon oxide, silicon nitride, or a combination of the two.
  • the thickness of the buffer layer 20 can be For example
  • the deposition temperature is controlled at 600 ° C or lower.
  • the glass substrate in the embodiment of the present invention can use the alkali-free glass as the substrate. .
  • the amorphous silicon film 301 can be formed by PECVD, LPCVD, or sputtering.
  • the deposition temperature is controlled to be 600 ° C or less.
  • the thickness of the amorphous silicon film 301 can be For example
  • the amorphous silicon film is immersed or sprayed with a nickel salt solution, and the nickel salt solution is uniformly applied to the surface of the amorphous silicon film.
  • the amorphous silicon film is immersed or sputtered with a nickel salt solution having a nickel concentration of 1 to 1000 ⁇ g/mg.
  • the substrate is placed in an annealing furnace for a certain period of time to reduce the hydrogen content in the amorphous silicon.
  • the hydrogen content in amorphous silicon is usually controlled to be less than 3% to avoid the problem of hydrogen explosion in the subsequent laser annealing process.
  • the dehydrogenation treatment temperature may be 400 to 600 ° C, and the treatment time may be 20 to 120 minutes.
  • the amorphous silicon film 301 is processed by an excimer laser annealing method, and the amorphous silicon film 301 is crystallized into a polysilicon film 302 as shown in FIG.
  • the lasers that can be used in the embodiments of the present invention include: ArF, KrF, and XeCl, and the corresponding laser wavelengths are 193 nm, 248 nm, and 308 nm, respectively, and the pulse width is between 10 and 50 ns. Since the laser wavelength of the XeCl laser is long, the laser energy is injected into the amorphous silicon film to be deep, and the crystallization effect is good. Therefore, the XeCl laser can be used in the embodiment of the present invention.
  • a photoresist film is formed on the polysilicon film 302; and the substrate on which the photoresist film is formed is exposed by a common mask, and the photoresist is completely retained and the photoresist is completely removed. .
  • the fully retained portion of the photoresist corresponds to the polysilicon layer, and the completely removed portion of the photoresist corresponds to the remaining portion.
  • the polysilicon film of the photoresist is completely removed by dry etching to form the polysilicon layer.
  • the photoresist is completely removed in part by a lift-off process.
  • the dry etching may be performed by plasma etching, reactive ion etching, inductively coupled plasma etching, or the like.
  • the etching gas may be a fluorine- or chlorine-containing gas such as CF 4 , CHF 3 , SF 6 , CCl 2 F 2 or the like or a mixed gas of these gases and O 2 .
  • the gate insulating layer 40 may be deposited by a method such as PECVD, LPCVD, APCVD, or ECR-CVD. Then, a gate metal layer is formed on the gate insulating layer 40 by sputtering, thermal evaporation or PECVD, LPCVD, APCVD, ECR-CVD, or the like, and the gate electrode 50 is formed by a patterning process.
  • the gate insulating layer 40 may be a single layer of silicon oxide, silicon nitride, or a laminate of the two.
  • the thickness of the gate insulating layer 40 may be For example
  • the gate electrode 50 may be made of a conductive material such as a metal or a metal alloy such as molybdenum or molybdenum alloy. Thickness can be For example
  • the active layer 60 includes a source region 601, a drain region 602, and a channel region 603 between the source region 601 and the drain region 602.
  • ion implantation may employ ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid state diffusion implantation.
  • the implantation may be carried out using a boron-containing gas such as B 2 H 6 /H 2 or a mixed gas containing phosphorus such as PH 3 /H 2 according to design requirements.
  • the ion implantation energy may be 10 to 200 keV, for example, 40 to 100 keV, and the implantation dose may be in the range of 1 x 10 11 to 1 x 10 20 atoms/cm 3 , for example, 1 x 10 13 to 8 x 10 15 atoms/cm 3 .
  • activation may be performed by rapid thermal annealing, laser annealing, or furnace annealing after ion implantation.
  • the furnace annealing method is economical, simple, and uniform.
  • an activation heat treatment in an annealing furnace at 300 to 600 ° C for 0.5 to 4 hours (for example, 1 to 3 hours) can be employed.
  • an interlayer insulating layer 70 is formed, and a source electrode 801 and a drain electrode 802 are formed on the interlayer insulating layer 70.
  • the source electrode 801 and the drain electrode 802 are in contact with the source region 601 and the drain region 602 through via holes formed on the interlayer insulating layer 70 and the gate insulating layer 40, respectively.
  • the interlayer insulating layer 70 may be deposited at a temperature of 600 ° C or lower by a method such as PECVD, LPCVD, APCVD, or ECR-CVD. Then, a source/drain metal layer is formed on the gate insulating layer by sputtering, thermal evaporation or PECVD, LPCVD, APCVD, ECR-CVD, or the like, and the source electrode 801 and the drain electrode 802 are formed by a patterning process.
  • a method such as PECVD, LPCVD, APCVD, or ECR-CVD.
  • the interlayer insulating layer 70 may be a single layer of silicon oxide or a stack of silicon oxide and silicon nitride.
  • the thickness of the interlayer insulating layer 70 may be For example
  • the via holes on the interlayer insulating layer 70 may be formed by dry etching. Via holes may be formed by plasma etching, reactive ion etching, inductively coupled plasma etching, or the like.
  • the etching gas may be a fluorine- or chlorine-containing gas such as CF 4 , CHF 3 , SF 6 , CCl 2 F 2 or the like or a mixed gas of these gases and O 2 .
  • the source electrode 801 and the drain electrode 802 may be made of a conductive material such as a metal or a metal alloy such as molybdenum, molybdenum alloy, aluminum, aluminum alloy, or titanium. Thickness can be For example
  • the source electrode 801 and the drain electrode 802 are formed by a patterning process, wet etching or dry etching may be employed.
  • the embodiment of the invention further provides a method for preparing an array substrate, comprising:
  • step S301 As shown in FIG. 8, on the basis of the above step S209, the planarization layer 90 is formed, and the pixel electrode 100 electrically connected to the drain electrode 802 is formed on the planarization layer 90.
  • the material of the planarization layer 100 may be, for example, a photosensitive or non-photosensitive resin material, and may have a thickness of 1.5 ⁇ m to 5 ⁇ m.
  • the material of the pixel electrode 100 may be indium tin oxide (ITO), and the thickness may be ITO.
  • the method may further include:
  • a passivation layer 110 is formed, and
  • the common electrode 120 is formed on the passivation layer 110.
  • the pixel electrode 100 and the common electrode 120 are formed in different layers as an example.
  • the embodiment of the present invention is not limited thereto, and the pixel electrode 100 and the common electrode 120 may be formed in the same layer. .
  • the array substrate provided by the embodiment of the invention can also be used for an OLED type display.
  • Embodiments of the present invention provide a method for preparing a polysilicon film, a polysilicon film transistor, and an array substrate, the method for preparing the polysilicon film, comprising: forming an amorphous silicon film on a substrate; and performing a surface of the amorphous silicon film Treating the nickel salt solution uniformly on the surface of the amorphous silicon film; and treating the amorphous silicon film by an excimer laser annealing method to crystallize the amorphous silicon film into Polysilicon film.
  • nickel remains on the surface of the amorphous silicon film and is subjected to excimer laser annealing treatment.
  • Nickel silicide formed by nickel and silicon as a seed crystal of amorphous silicon can promote the conversion of amorphous silicon to polycrystalline silicon, and make the polycrystalline silicon crystal uniform, the crystal grain size is large, and the crystal quality is high, thereby making the prepared thin film transistor Electrical performance has improved.

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Abstract

一种多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法。该多晶硅薄膜的制备方法包括：在衬底基板（10）上形成非晶硅薄膜（301）；对非晶硅薄膜（301）的表面进行镍盐溶液处理，使镍盐溶液均匀涂于非晶硅薄膜（301）的表面；以及采用准分子激光退火方法对非晶硅薄膜（301）进行处理，使非晶硅薄膜（301）晶化为多晶硅薄膜（302）。利用该方法制造的多晶硅结晶均匀，晶粒尺寸更大，提高了多晶硅薄膜、低温多晶硅薄膜晶体管的电学性能及阵列基板的质量。

Description

多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法 技术领域
本发明的实施例涉及一种多晶硅薄膜的制备方法、低温多晶硅薄膜晶体管的制备方法及阵列基板的制备方法。
背景技术
低温多晶硅薄膜晶体管(Low Temperature Poly-Silicon-Thin Film Transistor，简称LTPS-TFT)显示器具有高分辨率、反应速度快、高亮度、高开口率等优点，加上由于LTPS的特点，使得其具有高的电子移动率；此外，还可以将外围驱动电路同时制作在玻璃基板上，达到系统整合的目的、节省空间及驱动IC的成本，并可减少产品不良率。
低温多晶硅薄膜晶体管包括设置在衬底基板上的有源层、栅绝缘层、栅电极、源电极和漏电极；所述有源层包括源极区域、漏极区域以及位于所述源极区域和漏极区域之间的沟道区等。
有源层一般是通过对多晶硅层进行离子注入工艺后得到的，所述多晶硅层一般通过在衬底基板上形成非晶硅薄膜，之后采用准分子激光退火方法将非晶硅转化为多晶硅，然后通过构图工艺使多晶硅薄膜形成特定图案的多晶硅层。
发明内容
本发明的实施例提供一种多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法。
根据本发明的至少一个实施例，提供一种多晶硅薄膜的制备方法，包括：在衬底基板上形成非晶硅薄膜；对所述非晶硅薄膜的表面进行镍盐溶液处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面；以及采用准分子激光退火方法对所述非晶硅薄膜进行处理，使所述非晶硅薄膜晶化为多晶硅薄膜。
根据本发明的至少一个实施例，提供一种多晶硅薄膜晶体管的制备方法，包括：在衬底基板上形成有源层、位于所述有源层上方的栅绝缘层、栅电极、源电极和漏电极；所述有源层包括源极区、漏极区、位于所述源 极区和所述漏极区之间的沟道区；其中，所述多晶硅层通过对所述多晶硅薄膜进行构图工艺形成，以及所述有源层通过对所述多晶硅层的与所述源极区和所述漏极区相对应的区域进行掺杂工艺形成。
根据本发明的至少一个实施例，提供一种阵列基板的制备方法，包括：形成薄膜晶体管和像素电极；其中所述薄膜晶体管通过上述的多晶硅薄膜晶体管的制备方法形成。
附图说明
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：
图1为根据本发明的实施例提供的一种多晶硅薄膜晶体管的制备方法的流程示意图；
图2-7为根据本发明的实施例提供的一种制备多晶硅薄膜晶体管的结构的过程示意图；
图8为根据本发明的实施例提供的一种阵列基板的结构示意图一；
图9为根据本发明的实施例提供的一种阵列基板的结构示意图二。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不需要做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
发明人注意到，准分子激光作为一种气体激光，其稳定性相对而言较差，单纯使用准分子激光器进行处理所制备得到的多晶硅晶粒均匀性也会 较差，从而造成薄膜晶体管的电学特性均匀性较差。此外，由于通常的准分子激光晶化工艺在很短的时间内使非晶硅熔融再结晶，其晶粒尺寸较小，且结晶质量也不高，限制了薄膜晶体管器件电学性能的提升。
本发明实施例提供了一种多晶硅薄膜的制备方法，包括：在衬底基板上形成非晶硅薄膜；对所述非晶硅薄膜的表面进行镍盐溶液处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面；以及采用准分子激光退火方法对所述非晶硅薄膜进行处理，使所述非晶硅薄膜晶化为多晶硅薄膜。
采用准分子激光退火方法对所述非晶硅薄膜进行处理，使所述非晶硅薄膜晶化为多晶硅薄膜通过如下过程实现，即：采用准分子激光照射处理，在约50～150ns时间内使非晶硅薄膜表面瞬间达到1000℃以上的高温而变成熔融状态；然后对熔融状态的非晶硅进行退火，使之晶化形成多晶硅薄膜。
利用此种处理方式可以保证玻璃衬底基板的温度在400℃左右或以下，原因在于：激光脉冲首先在非晶硅薄膜中激发出热电子-空穴对，之后电子-空穴对再以非辐射复合的方式将能量传递给晶格原子，从而实现非晶硅薄膜的瞬间加热。由于激光脉冲的瞬间能量被非晶硅薄膜吸收并转化为相变能，因此不会有过多的热能传导到玻璃衬底基板，可以避免一般炉退火中使玻璃衬底基板温度升高而产生变形的问题。
在上述基础上，由于在采用准分子激光退火方法对所述非晶硅薄膜进行处理之前，对非晶硅薄膜的表面进行了镍(Ni)盐溶液处理，会有镍残留在非晶硅薄膜的表面，因而，经过准分子激光退火处理，镍与硅会发生反应，生成镍-硅键，形成镍-硅的混合体。由于硅晶化态的自由能比非晶态低，镍-硅键的断裂与重组这一热平衡过程促进了非晶硅到多晶硅局域晶格重组。镍与硅形成的镍硅化物(SiN2)在350℃很容易形成，其晶格常数与硅的晶格常数仅相差0.4％，非常适合作为非晶硅晶化的籽晶，这样一方面可以促进非晶硅向多晶硅转变，另一方面由于有较均匀的形核中心(籽晶)，可以使多晶硅结晶更均匀。而且，由于有镍的催化作用，在同样的温度和时间条件下，催化生长出来的晶粒尺寸更大，从而使得结晶质量更高。
本发明实施例提供了一种多晶硅薄膜的制备方法，包括：在衬底基板上形成非晶硅薄膜；对所述非晶硅薄膜的表面进行镍盐溶液处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面；以及采用准分子激光退火方法对所述非晶硅薄膜进行处理，使所述非晶硅薄膜晶化为多晶硅薄膜。由于 在采用准分子激光退火方法对所述非晶硅薄膜进行处理之前，对非晶硅薄膜的表面进行了镍盐溶液处理，会有镍残留在非晶硅薄膜的表面，经过准分子激光退火处理，镍与硅形成的镍硅化物作为非晶硅晶化的籽晶，可以促进非晶硅向多晶硅转变，并且使得多晶硅结晶更均匀，晶粒尺寸更大，结晶质量更高。当该多晶硅薄膜用于制备薄膜晶体管的有源层时，可使薄膜晶体管的电学性能得到提升。
例如，可以采用浸泡或喷溅的方法，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面。
考虑到镍盐溶液中镍的浓度过大时会造成较多的镍金属离子进入非晶硅层，导致形核中心太多而影响晶粒的生长，使得晶粒尺寸减小，同时，也有可能造成金属离子污染；因此，本发明实施例中的镍盐溶液只需采用含微量镍的溶液，例如，采用的镍浓度为1～1000μg/mg的溶液。
基于上述的描述，为了避免在采用准分子激光退火方法对所述非晶硅薄膜进行处理时，产生氢爆的问题。本发明实施例中在对所述非晶硅薄膜的表面进行镍盐溶液处理之后，采用准分子激光退火方法对所述非晶硅薄膜进行处理之前，对所述非晶硅薄膜进行脱氢工艺处理，使所述非晶硅薄膜中的氢含量在3％以下。
脱氢温度可以在400～600℃，处理时间可在20～120分钟。
需要说明的是，若制备过程中使非晶硅薄膜中氢含量已经控制在3％以下，则此步骤可以省略，具体可根据实际情况进行。
本发明实施例还提供了一种多晶硅薄膜晶体管的制备方法，包括：在衬底基板上形成有源层、位于所述有源层上方的栅绝缘层、栅电极、源电极和漏电极；所述有源层包括源极区、漏极区、位于所述源极区和所述漏极区之间的沟道区。所述多晶硅层通过对上述得到的多晶硅薄膜进行构图工艺形成，而所述有源层通过对多晶硅层的与所述源极区和所述漏极区相对应的区域进行掺杂工艺形成。
由于在采用准分子激光退火方法对所述非晶硅薄膜进行处理之前，对非晶硅薄膜的表面进行了镍盐溶液处理，会有镍残留在非晶硅薄膜的表面，这样，经过准分子激光退火处理，镍与硅形成的镍硅化物作为非晶硅晶化的籽晶，可以促进非晶硅向多晶硅转变，并且使得多晶硅结晶更均匀，晶粒尺寸更大，结晶质量高，使薄膜晶体管的电学性能得到提升。例如，所 述多晶硅层的厚度为
Figure PCTCN2014091542-appb-000001
例如，所述多晶硅层通过对多晶硅薄膜进行构图工艺形成，例如，可以通过如下步骤实现：
S101、在形成有多晶硅薄膜的基板上，形成光刻胶薄膜。
S102、采用普通掩模板对形成有所述光刻胶薄膜的基板进行曝光，显影后形成光刻胶完全保留部分和光刻胶完全去除部分。所述光刻胶完全保留部分与所述多晶硅层对应，而光刻胶完全去除部分对应其余部分。
S103、采用干法刻蚀去除所述光刻胶完全去除部分的所述多晶硅薄膜，形成所述多晶硅层。
干法刻蚀可选用等离子刻蚀、反应离子刻蚀、电感耦合等离子体刻蚀等方法。刻蚀气体可选择含氟、氯的气体，如四氟化碳(CF4)、三氟甲烷(CHF3)、六氟化硫(SF6)、二氟二氯甲烷(CCl2F2)等或者这些气体与氧气(O2)的混合气体。
S104、采用剥离工艺将所述光刻胶完全保留部分去除。
本发明实施例中采用干法刻蚀形成所述多晶硅层，是因为干法刻蚀可以非常好的控制形成的所述多晶硅层的侧壁剖面，即可以控制所述多晶硅层的两侧侧壁能垂直衬底基板，这样，使最终形成的有源层的性能更好，避免了对薄膜晶体管性能的影响。
考虑到玻璃衬底基板中可能包含有害物质，如碱金属离子，其可对多晶硅层性能造成影响，因此，在形成所述多晶硅薄膜之前，可以在所述衬底基板表面形成缓冲层。
基于上述对多晶硅薄膜晶体管的制备方法的描述，本发明实施例提供一示例，以详细描述所述多晶硅薄膜晶体管的制备方法以及所形成的各结构。如图1所示，该方法包括如下步骤：
S201、如图2所示，在衬底基板10上形成缓冲层20。
例如，在经过预先清洗的玻璃等透明衬底基板10上，以等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、大气压化学气相沉积(APCVD)、电子回旋谐振化学气相沉积(ECR-CVD)或者溅射等方法形成缓冲层20，用于阻挡玻璃中所含的杂质扩散进入有源层中，防止对薄膜晶体管元件的阈值电压和漏电流等特性产生影响。
该缓冲层20可以为单层的氧化硅、氮化硅或者二者的叠层。所述缓冲 层20的厚度可以为
Figure PCTCN2014091542-appb-000002
例如为
Figure PCTCN2014091542-appb-000003
在采用沉积方法形成所述缓冲层20时，沉积温度控制在600℃或更低温度下。
此外，因传统碱玻璃中铝、钡和钠等金属杂质含量较高，容易在高温处理工艺中发生金属杂质的扩散，因此，本发明实施例中的玻璃衬底基板可以采用无碱玻璃作为基板。
S202、如图2所示，在完成S201的基础上，在所述缓冲层20上形成非晶硅薄膜301。
例如，可以采用PECVD、LPCVD或者溅射方法形成所述非晶硅薄膜301。在采用沉积方法形成所述非晶硅薄膜301时，沉积温度控制在600℃以下。
非晶硅薄膜301厚度可以为
Figure PCTCN2014091542-appb-000004
例如为
Figure PCTCN2014091542-appb-000005
S203、在完成S202的基础上，以镍盐溶液对所述非晶硅薄膜进行浸泡或喷溅处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面。
例如，采用镍浓度为1～1000μg/mg的镍盐溶液对所述非晶硅薄膜进行浸泡或喷溅处理。
S204、在完成S203的基础上，将形成有非晶硅薄膜的基板置于退火炉中进行脱氢处理。
例如，将该基板置于退火炉中保温一定时间，使非晶硅中的氢含量减少。非晶硅中的氢含量通常需控制在3％以下，以避免在后续进行激光退火工艺时产生爆氢的问题。
脱氢处理温度可在400～600℃，处理时间可在20～120分钟。
S205、在完成S204的基础上，采用准分子激光退火方法对所述非晶硅薄膜301进行处理，使所述非晶硅薄膜301晶化为如图3所示的多晶硅薄膜302。
本发明实施例中可采用的激光器包括：ArF、KrF和XeCl，相应的激光波长分别为193nm、248nm和308nm，脉宽在10～50ns之间。由于XeCl激光器的激光波长较长，激光能量注入非晶硅薄膜较深，晶化效果较好，因此，本发明实施例可以采用XeCl激光器。
S206、在完成S205的基础上，对多晶硅薄膜302进行构图工艺处理，形成如图4所示的多晶硅层30。
例如，在所述多晶硅薄膜302上形成光刻胶薄膜；并采用普通掩模板对形成有所述光刻胶薄膜的基板进行曝光，显影后形成光刻胶完全保留部分和光刻胶完全去除部分。所述光刻胶完全保留部分与所述多晶硅层对应，光刻胶完全去除部分对应其余部分。采用干法刻蚀去除所述光刻胶完全去除部分的所述多晶硅薄膜，形成所述多晶硅层。采用剥离工艺将所述光刻胶完全保留部分去除。
干法刻蚀可选用等离子刻蚀、反应离子刻蚀、电感耦合等离子体刻蚀等方法。刻蚀气体可选择含氟、氯的气体，如CF4、CHF3、SF6、CCl2F2等或者这些气体与O2的混合气体。
S207、如图5所示，在完成S206的基础上，形成栅绝缘层40和栅电极50。
例如，可以采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积栅绝缘层40。然后采用溅射、热蒸发或PECVD、LPCVD、APCVD、ECR-CVD等方法在栅绝缘层40上形成栅金属层，并通过构图工艺形成所述栅电极50。
该栅绝缘层40可以为单层的氧化硅、氮化硅或者二者的叠层。栅绝缘层40的厚度可以为
Figure PCTCN2014091542-appb-000006
例如为
Figure PCTCN2014091542-appb-000007
栅电极50可以由金属、金属合金如钼、钼合金等导电材料构成。厚度可以为
Figure PCTCN2014091542-appb-000008
例如为
Figure PCTCN2014091542-appb-000009
S208、在完成S207的基础上，对多晶硅层30的与所述源极区和所述漏极区相对应的区域进行离子注入工艺，形成如图6所示的有源层60。所述有源层60包括源极区601、漏极区602、位于所述源极区601和所述漏极区602之间的沟道区603。
例如，离子注入可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子体注入或者固态扩散式注入等方法。可根据设计需要采用含硼如B2H6/H2，或者含磷如PH3/H2的混合气体进行注入。离子注入能量可为10～200keV，例如在40～100keV，注入剂量可在1x1011～1x1020atoms/cm3范围内，例如在1x1013～8x1015atoms/cm3。
此外，在离子注入之后可通过快速热退火、激光退火或炉退火的方法进行激活。炉退火的方法较为经济、简单，均匀性较佳，在本发明实施例中可以采用在退火炉中以300～600℃进行0.5～4小时(例如为1～3小时)的激活热处理。
S209、如图7所示，在完成S208的基础上，形成层间绝缘层70，并在所述层间绝缘层70上形成源电极801和漏电极802。所述源电极801和漏电极802分别通过形成在所述层间绝缘层70和所述栅绝缘层40上的过孔与所述源极区601和漏极区602接触。
例如，可以采用PECVD、LPCVD、APCVD或ECR-CVD等方法在600℃以下的温度下沉积所述层间绝缘层70。然后采用溅射、热蒸发或PECVD、LPCVD、APCVD、ECR-CVD等方法在栅绝缘层上形成源漏金属层，并通过构图工艺形成所述源电极801和漏电极802。
该层间绝缘层70可以为单层的氧化硅、或者氧化硅和氮化硅的叠层。层间绝缘层70的厚度可以为
Figure PCTCN2014091542-appb-000010
例如为
Figure PCTCN2014091542-appb-000011
可采用干法刻蚀形成所述层间绝缘层70上的过孔。可选用等离子刻蚀、反应离子刻蚀、电感耦合等离子体刻蚀等方法形成过孔。刻蚀气体可选择含氟、氯的气体，如CF4、CHF3、SF6、CCl2F2等或者这些气体与O2的混合气体。
源电极801和漏电极802可以由金属、金属合金如钼、钼合金、铝、铝合金、钛等导电材料构成。厚度可以为
Figure PCTCN2014091542-appb-000012
例如为
Figure PCTCN2014091542-appb-000013
Figure PCTCN2014091542-appb-000014
在通过构图工艺形成源电极801和漏电极802时，可采用湿法刻蚀或干法刻蚀。
通过上述步骤S201～S209便可以制备得到高质量的低温多晶硅薄膜晶体管。
在上述形成的多晶硅薄膜晶体管的基础上，本发明实施例还提供了一种阵列基板的制备方法，包括：
S301、如图8所示，在上述步骤S209的基础上，形成平坦化层90，并在所述平坦化层90上形成与所述漏电极802电连接的像素电极100。
所述平坦化层100的材料例如可以为感光性或非感光性树脂材料，厚度可以为1.5μm～5μm。
所述像素电极100的材料可以为氧化铟锡(ITO)，厚度可以为
Figure PCTCN2014091542-appb-000015
Figure PCTCN2014091542-appb-000016
在此基础上，所述方法还可以包括：
S302、如图9所示，在上述S301的基础上，形成钝化层110，并在所 述钝化层110上形成公共电极120。
这里，仅以所述像素电极100和所述公共电极120形成于不同层为例进行说明，但本发明实施例并不限于此，所述像素电极100和所述公共电极120可以同层间隔形成。
本发明实施例提供的阵列基板也可以用于OLED型显示器。
本发明实施例提供了一种多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法，所述多晶硅薄膜的制备方法包括在衬底基板上形成非晶硅薄膜；对所述非晶硅薄膜的表面进行镍盐溶液处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面；以及采用准分子激光退火方法对所述非晶硅薄膜进行处理，使所述非晶硅薄膜晶化为多晶硅薄膜。
由于在采用准分子激光退火方法对所述非晶硅薄膜进行处理之前，对非晶硅薄膜的表面进行了镍盐溶液处理，会残留镍在非晶硅薄膜的表面，经过准分子激光退火处理，镍与硅形成的镍硅化物作为非晶硅晶化的籽晶，可以促进非晶硅向多晶硅转变，并且使得多晶硅结晶均匀，晶粒尺寸大，结晶质量高，从而使制备的薄膜晶体管的电学性能得到提升。
以上实施例仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有这样的变化和变形以及等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。
本申请要求于2014年05月14日提交的名称为“多晶硅薄膜、多晶硅薄膜晶体管及阵列基板的制备方法”的中国专利申请No.201410203194.5的优先权，其全文以引用方式合并于本文。

Claims (20)

  1. 一种多晶硅薄膜的制备方法，包括：
    在衬底基板上形成非晶硅薄膜；
    对所述非晶硅薄膜的表面进行镍盐溶液处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面；以及
    采用准分子激光退火对所述非晶硅薄膜进行处理，使所述非晶硅薄膜晶化为多晶硅薄膜。
  2. 根据权利要求1所述的方法，其中，在对所述非晶硅薄膜的表面进行镍盐溶液处理，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面的过程中，采用浸泡或喷溅的方法，使所述镍盐溶液均匀涂于所述非晶硅薄膜的表面。
  3. 根据权利要求1或2所述的方法，其中，所述镍盐溶液中镍的浓度为1～1000μg/mg。
  4. 根据权利要求1-3任一项所述的方法，其中，在对所述非晶硅薄膜的表面进行镍盐溶液处理之后，采用准分子激光退火方法对所述非晶硅薄膜进行处理之前，
    对所述非晶硅薄膜进行脱氢处理，使所述非晶硅薄膜中的氢含量在3％以下。
  5. 根据权利要求4所述的方法，其中，所述脱氢处理在400～600℃进行，处理时间为20～120分钟。
  6. 根据权利要求1-5任一项所述的方法，其中，所述非晶硅薄膜采用沉积方法形成，沉积温度在600℃以下。
  7. 根据权利要求1-6任一项所述的方法，其中，所述准分子激光退火处理采用XeCl激光器进行。
  8. 一种多晶硅薄膜晶体管的制备方法，包括：在衬底基板上形成有源层、位于所述有源层上方的栅绝缘层、栅电极、源电极和漏电极；所述有源层包括源极区、漏极区、位于所述源极区和所述漏极区之间的沟道区；其中，所述有源层是通过对多晶硅层的与所述源极区和所述漏极区相对应的区域进行掺杂形成，并且所述多晶硅层通过对权利要求1-4任一项所述方法制备的多晶硅薄膜进行构图工艺形成。
  9. 根据权利要求8所述的方法，其中，在通过对多晶硅薄膜进行构图工艺形成所述多晶硅层的过程中，
    在形成有多晶硅薄膜的基板上，形成光刻胶薄膜；
    采用普通掩模板对形成有所述光刻胶薄膜的基板进行曝光，显影后形成光刻胶完全保留部分和光刻胶完全去除部分；其中，所述光刻胶完全保留部分与所述多晶硅层对应，光刻胶完全去除部分对应其余部分；
    采用干法刻蚀去除所述光刻胶完全去除部分的所述多晶硅薄膜，形成所述多晶硅层；以及
    采用剥离工艺将所述光刻胶完全保留部分去除。
  10. 根据权利要求8或9所述的方法，其中，所述多晶硅层的厚度为
    Figure PCTCN2014091542-appb-100001
  11. 根据权利要求8-10任一项所述的方法，还包括：在形成所述多晶硅薄膜之前，在所述衬底基板表面形成缓冲层。
  12. 根据权利要求11所述的方法，其中，所述缓冲层为单层的氧化硅、氮化硅或者二者的叠层。
  13. 根据权利要求11或12所述的方法，其中，所述缓冲层采用沉积方法形成，沉积温度为600℃或更低。
  14. 根据权利要求11-13任一项所述的方法，其中，所述缓冲层的厚度为
    Figure PCTCN2014091542-appb-100002
  15. 根据权利要求11-13任一项所述的方法，其中，所述缓冲层的厚度为
    Figure PCTCN2014091542-appb-100003
  16. 根据权利要求8-15任一项所述的方法，其中，所述干法刻蚀包括等离子体刻蚀，反应离子刻蚀，以及电感耦合刻蚀。
  17. 根据权利要求8-16任一项所述的方法，其中，所述刻蚀使用的气体包括CF4、CHF3、SF6、CCl2F2或者其与O2的混合气体。
  18. 根据权利要求8-17任一项所述的方法，其中，所述掺杂通过离子注入实现。
  19. 一种阵列基板的制备方法，包括：形成薄膜晶体管和像素电极；其中所述薄膜晶体管通过权利要求8-18任一项所述的多晶硅薄膜晶体管的制备方法形成。
  20. 根据权利要求19所述的方法，还包括形成公共电极。
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