JP2018503981A - Ltps tft画素ユニット及びその製造方法 - Google Patents
Ltps tft画素ユニット及びその製造方法 Download PDFInfo
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- JP2018503981A JP2018503981A JP2017534662A JP2017534662A JP2018503981A JP 2018503981 A JP2018503981 A JP 2018503981A JP 2017534662 A JP2017534662 A JP 2017534662A JP 2017534662 A JP2017534662 A JP 2017534662A JP 2018503981 A JP2018503981 A JP 2018503981A
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- Prior art keywords
- layer
- insulating layer
- semiconductor pattern
- forming
- electrode
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 125
- 238000000034 method Methods 0.000 claims abstract description 124
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 38
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- H01L21/02587—Structure
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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Abstract
Description
12 バッファ層
121 172 窒化ケイ素層
122 171 シリコン酸化層
13 半導体パターン層
142 第1絶縁層
133 アモルファスシリコン層
134 ポリシリコン層
14 窒化ケイ素層
141 ネガ型フォトレジスト
130 真性領域
131 高濃度ドープ領域
132 低濃度ドープ領域
15 第2絶縁層
16 ゲート電極層
161 ゲート電極
17 第3絶縁層
18 ソース電極
19 ドレイン電極
M1 第1スルーホール
110 第4絶縁層
100 画素電極
M2 第2スルーホール
120 第5絶縁層
130 共通電極
10 LTPS TFT画素ユニット
Claims (14)
- LTPS TFT画素ユニットの製造方法であって、
そのうち、前記方法は、
基板を提供するとともに、前記基板上にバッファ層を形成する手順と、
前記バッファ層上に半導体パターン層と第1絶縁層を形成させ、前記半導体パターン層と前記第1絶縁層を、同じ層に設けるとともに、前記半導体パターン層の高さと前記第1絶縁層の高さを同じにする手順と、からなり、
そのうち、前記基板上にバッファ層を形成する手順は、
前記基板上に窒化ケイ素層とシリコン酸化層を順番に形成する手順からなり、
前記バッファ層上に半導体パターン層と第1絶縁層を形成させ、前記半導体パターン層と前記第1絶縁層を、同じ層に設けるとともに、前記半導体パターン層の高さと前記第1絶縁層の高さを同じにする手順は、
前記バッファ層上にアモルファスシリコン層を形成するとともに、前記アモルファスシリコン層に結晶操作を行うことによって、ポリシリコン層を形成する手順と、
第1フォトマスク工程で前記ポリシリコン層をパターン化することによって、前記半導体パターン層を形成する手順と、
前記半導体パターン層上と、前記半導体パターン層が形成されていない前記バッファ層上に、前記半導体パターン層と高さが同じである窒化ケイ素層を形成する手順と、
前記窒化ケイ素層上における前記半導体パターン層に対応しない位置にネガ型フォトレジストをコーティングする手順と、
第2フォトマスク工程によって前記窒化ケイ素層をパターン化処理する手順と、
さらに、前記半導体パターン層上方の前記窒化ケイ素層にエッチングを行うことによって、前記半導体パターン層上の窒化ケイ素層をエッチングし、前記半導体パターン層の両端に前記半導体パターン層の高さと同じである前記第1絶縁層を形成する手順と、からなる
ことを特徴とする、LTPS TFT画素ユニットの製造方法。 - 前記方法はさらに、
前記半導体パターン層上に第3フォトマスク工程と第1ドーピング工程によって真性領域と前記真性領域の両側に位置する高濃度ドープ領域を形成する手順と、
さらに、前記半導体パターン層上に第4フォトマスク工程と第2ドーピング工程によって前記真性領域と前記高濃度ドープ領域の間に位置する低濃度ドープ領域を形成する手順と、からなる
ことを特徴とする、請求項1に記載の製造方法。 - 前記方法はさらに、
前記半導体パターン層と前記第1絶縁層上に第2絶縁層を形成する手順と、
前記第2絶縁層上にゲート電極層を形成するとともに、第5フォトマスク工程で前記ゲート電極層をパターン化処理することによって、ゲート電極を形成する手順と、
前記ゲート電極上に第3絶縁層を形成する手順と、
前記第3絶縁層上に前記LTPS TFTユニットのソース電極とドレイン電極を形成し、そのうち、前記ソース電極とドレイン電極を、それぞれ前記第2絶縁層と第3絶縁層を通り抜ける第1スルーホールによって前記半導体パターン層と電気的に接続させる手順と、
前記ソース電極とドレイン電極上に第4絶縁層を形成するとともに、前記第4絶縁層上に画素電極を形成し、前記画素電極を、前記第4絶縁層を通り抜ける第2スルーホールによって前記ソース電極またはドレイン電極のうち1つと電気的に接続させる手順と、からなる
ことを特徴とする、請求項2に記載の製造方法。 - 前記方法はさらに、
前記第4絶縁層と、前記ソース電極及びドレイン電極の間にさらに第5絶縁層を形成する手順と、
前記第5絶縁層と前記第4絶縁層の間にさらに共通電極を形成することによって、液晶コンデンサを形成するために前記画素電極を用いる手順と、からなる
ことを特徴とする、請求項3に記載の製造方法。 - LTPS TFT画素ユニットの製造方法であって、そのうち、前記方法は、
基板を提供するとともに、前記基板上にバッファ層を形成する手順と、
前記バッファ層上に半導体パターン層と第1絶縁層を形成し、前記半導体パターン層と前記第1絶縁層を同じ層に設けるとともに、前記半導体パターン層の高さと前記第1絶縁層の高さを同じにする手順と、からなる
ことを特徴とする、LTPS TFT画素ユニットの製造方法。 - 前記基板上にバッファ層を形成する手順は、
前記基板上に窒化ケイ素層とシリコン酸化層を順番に形成する手順からなる
ことを特徴とする、請求項5に記載の製造方法。 - 前記バッファ層上に半導体パターン層と第1絶縁層を形成し、前記半導体パターン層と前記第1絶縁層を同じ層に設けるとともに、前記半導体パターン層の高さと前記第1絶縁層の高さを同じにする手順は、
前記バッファ層上にアモルファスシリコン層を形成するとともに、前記アモルファスシリコン層に結晶操作を行い、ポリシリコン層を形成する手順と、
第1フォトマスク工程によって前記ポリシリコン層をパターン化することで、前記半導体パターン層を形成する手順と、
前記半導体パターン層上と前記半導体パターン層を形成していない前記バッファ層上に前記半導体パターン層と高さが同じである窒化ケイ素層を形成する手順と、
前記窒化ケイ素層上における前記半導体パターン層に対応しない位置にネガ型フォトレジストをコーティングする手順と、
第2フォトマスク工程によって前記窒化ケイ素層をパターン化処理する手順と、
さらに前記半導体パターン層上方の前記窒化ケイ素層にエッチングを行うことによって、前記半導体パターン層上の窒化ケイ素層をエッチングし、前記半導体パターン層の両端に前記半導体パターン層の高さと同じである前記第1絶縁層を形成する手順と、からなる
ことを特徴とする、請求項5に記載の製造方法。 - 前記方法はさらに、
前記半導体パターン層上に第3フォトマスク工程と第1ドーピング工程によって真性領域と前記真性領域の両側に位置する高濃度ドープ領域を形成する手順と、
さらに、前記半導体パターン層上に第4フォトマスク工程と第2ドーピング工程によって前記真性領域と前記高濃度ドープ領域の間に位置する低濃度ドープ領域を形成する手順と、からなる
ことを特徴とする、請求項7に記載の製造方法。 - 前記方法はさらに、
前記半導体パターン層と前記第1絶縁層上に第2絶縁層を形成する手順と、
前記第2絶縁層上にゲート電極層を形成するとともに、第5フォトマスク工程で前記ゲート電極層をパターン化処理することによって、ゲート電極を形成する手順と、
前記ゲート電極上に第3絶縁層を形成する手順と、
前記第3絶縁層上に前記LTPS TFTユニットのソース電極とドレイン電極を形成し、そのうち前記ソース電極とドレイン電極を、それぞれ前記第2絶縁層と第3絶縁層を通り抜ける第1スルーホールによって前記半導体パターン層と電気的に接続させる手順と、
前記ソース電極とドレイン電極上に第4絶縁層を形成するとともに、前記第4絶縁層上に画素電極を形成し、前記画素電極を、前記第4絶縁層を通り抜ける第2スルーホールによって前記ソース電極またはドレイン電極のうちの1つと電気的に接続させる手順と、からなる
ことを特徴とする、請求項8に記載の製造方法。 - 前記方法はさらに、
前記第4絶縁層と、前記ソース電極及びドレイン電極の間にさらに第5絶縁層を形成する手順と、
前記第5絶縁層と前記第4絶縁層の間にさらに共通電極を形成し、液晶コンデンサを形成するために前記画素電極を用いる手順と、からなる
ことを特徴とする、請求項9に記載の製造方法。 - LTPS TFT画素ユニットであって、そのうち、前記LTPS TFTユニットは、基板と、バッファ層と、半導体パターン層と第1絶縁層と、からなり、
前記バッファ層は、前記基板上に設けられ、
前記半導体パターン層と前記第1絶縁層は、前記バッファ層上の同じ層に設けられるとともに、前記半導体パターン層の高さと前記第1絶縁層の高さは同じである
ことを特徴とする、LTPS TFT画素ユニット。 - 前記バッファ層は、前記基板上に順番に設けられる窒化ケイ素層とシリコン酸化層を備える
ことを特徴とする、請求項11に記載のLTPS TFT画素ユニット。 - 前記LTPS TFT画素ユニットは、さらに第2絶縁層と、ゲート電極と、第3絶縁層と、ソース電極とドレイン電極と、第4絶縁層と、画素電極を備え、
前記第2絶縁層は、前記半導体パターン層と前記第1絶縁層上に設けられ、
前記ゲート電極は、前記第2絶縁層上に設けられ、
前記第3絶縁層は、前記ゲート電極上に設けられ、
前記ソース電極とドレイン電極は、前記第3絶縁層上に設けられ、そのうち前記ソース電極とドレイン電極は、それぞれ前記第2絶縁層と第3絶縁層を通り抜ける第1スルーホールによって前記半導体パターン層と電気的に接続され、
前記第4絶縁層は、前記ソース電極とドレイン電極上に設けられ、
前記画素電極は、前記第4絶縁層上に設けられるとともに、前記第4絶縁層を通り抜ける第2スルーホールによって前記ソース電極またはドレイン電極のうちの1つと電気的に接続される
ことを特徴とする、請求項12に記載のLTPS TFT画素ユニット。 - 前記LTPS TFT画素ユニットは、さらに第5絶縁層と、共通電極を備え、
前記第5絶縁層は、前記第4絶縁層と、前記ソース電極及びドレイン電極の間に設けられ、
前記共通電極は、前記第5絶縁層と前記第4絶縁層の間に設けられ、、前記画素電極が液晶コンデンサを形成するのに用いられる
ことを特徴とする、請求項13に記載のLTPS TFT画素ユニット。
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GB201708786D0 (en) | 2017-07-19 |
RU2670219C1 (ru) | 2018-10-19 |
CN104538354B (zh) | 2018-01-09 |
CN104538354A (zh) | 2015-04-22 |
JP6542897B2 (ja) | 2019-07-10 |
KR20170101978A (ko) | 2017-09-06 |
US9589999B2 (en) | 2017-03-07 |
GB2548732A (en) | 2017-09-27 |
KR101963066B1 (ko) | 2019-07-31 |
WO2016106923A1 (zh) | 2016-07-07 |
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US20160343749A1 (en) | 2016-11-24 |
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