WO2019179246A1 - 阵列基板的制作方法、阵列基板及液晶显示面板 - Google Patents

阵列基板的制作方法、阵列基板及液晶显示面板 Download PDF

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Publication number
WO2019179246A1
WO2019179246A1 PCT/CN2019/073859 CN2019073859W WO2019179246A1 WO 2019179246 A1 WO2019179246 A1 WO 2019179246A1 CN 2019073859 W CN2019073859 W CN 2019073859W WO 2019179246 A1 WO2019179246 A1 WO 2019179246A1
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Prior art keywords
insulating layer
layer
array substrate
touch
region
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PCT/CN2019/073859
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English (en)
French (fr)
Inventor
洪光辉
龚强
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武汉华星光电技术有限公司
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Publication of WO2019179246A1 publication Critical patent/WO2019179246A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present application relates to the field of liquid crystal display, and in particular to a method for fabricating an array substrate, an array substrate, and a liquid crystal display panel.
  • LTPS Low temperature poly-silicon
  • the LTPS process is complicated, and the Array of the Array side substrate has many layers. Especially after the In Cell Touch function is added, the Array side generally needs 12 layers or even more layer structures, so that the number of masks is larger. Product production capacity has increased over time, increasing lighting costs, materials and operating costs.
  • the purpose of the embodiments of the present application is to provide a method for fabricating an array substrate, an array substrate, and a liquid crystal display panel, which have the beneficial effects of shortening the process flow.
  • the embodiment of the present application provides a method for fabricating an array substrate, including:
  • the touch/common electrode layer being electrically connected to the touch signal line; the pixel electrode layer being electrically connected to the source/drain .
  • the step of forming the touch/common electrode layer and the pixel electrode layer on the fourth insulating layer includes:
  • a pixel electrode layer is formed on the fifth insulating layer.
  • the step of forming a third insulating layer on the substrate comprises:
  • a third insulating layer is formed on the second insulating layer and the gate line.
  • the second insulating layer and the third insulating layer are provided with a first through hole and a second through hole, wherein the first through hole is insulated from the third
  • the upper surface of the layer penetrates to the polysilicon layer via the second insulating layer, and the second via hole penetrates from the upper surface of the third insulating layer to the polysilicon layer via the second insulating layer;
  • the source/drain are electrically connected to the polysilicon layer through a first via and a second via.
  • the step of forming a polysilicon layer, a second insulating layer, and a gate line on the first insulating layer includes:
  • the polysilicon layer including a first region, a second region, and a third region, wherein the first region is connected to the third region through the second region, and the first region is Performing N+ ion implantation to form a heavily doped region, the source/drain being electrically connected to the heavily doped region through the first via and the second via;
  • the second region is ion implanted to form a lightly doped region, and a channel region is formed in the undoped third region.
  • the fourth insulating layer is provided with a third through hole penetrating the touch signal line, and the touch/common electrode layer passes through the third pass The hole is electrically connected to the touch signal line.
  • the fifth insulating layer is provided with a fifth through hole
  • the fourth insulating layer is provided with a fourth through hole penetrating the source/drain.
  • the fourth through hole is in communication with the fifth through hole;
  • the pixel electrode layer is electrically connected to the source/drain through the fifth via hole and the fourth via hole in sequence.
  • An embodiment of the present application further provides an array substrate, including a substrate, a thin film transistor device layer disposed on the substrate, and a touch/common electrode layer and a pixel electrode layer disposed on the thin film transistor device layer, the array
  • the substrate further includes: a touch signal line and a data signal line disposed between the touch/common electrode layer and the substrate, the touch signal line, and the source/drain of the data signal line and the thin film transistor device Extremely located on the same floor.
  • the array substrate further includes:
  • the thin film transistor device layer is disposed on the first insulating layer, and includes: a polysilicon layer, a second insulating layer, a gate line, and a third insulating layer, which are sequentially disposed on the first insulating layer, the source/drain a pole, the data signal line and the touch signal line are formed on the third insulating layer, and the source/drain are electrically connected to the polysilicon layer;
  • a fourth insulating layer disposed on the source/drain, the data signal line, and the touch signal line.
  • the touch/common electrode layer is disposed on the fourth insulating layer
  • the array substrate further includes a fifth insulating layer disposed on the touch/common electrode layer; the pixel electrode layer is disposed on the fifth insulating layer.
  • the pixel electrode layer is disposed on the fourth insulating layer
  • the array substrate further includes a fifth insulating layer disposed on the pixel electrode layer; the touch/common electrode layer is disposed on the fifth insulating layer.
  • a first via hole and a second via hole are formed in the second insulating layer and the third insulating layer, wherein the first via hole is on the third insulating layer.
  • the surface penetrates to the polysilicon layer via the second insulating layer, and the second via hole penetrates from the upper surface of the third insulating layer to the polysilicon layer via the second insulating layer;
  • the source/drain are electrically connected to the polysilicon layer through a first via and a second via.
  • the fourth insulating layer is provided with a third through hole penetrating the touch signal line, and the touch/common electrode layer passes through the third through hole and the The touch signal line is electrically connected.
  • the fifth insulating layer is provided with a fifth through hole
  • the fourth insulating layer is provided with a fourth through hole penetrating to the source/drain.
  • a four-way hole is connected to the fifth through hole;
  • the pixel electrode layer is electrically connected to the source/drain through the fifth via hole and the fourth via hole in sequence.
  • the embodiment of the present application further provides a liquid crystal display panel including an array substrate, the array substrate including a substrate, a thin film transistor device layer disposed on the substrate, and a touch/common disposed on the thin film transistor device layer An electrode layer and a pixel electrode layer, wherein the array substrate further includes: a touch signal line and a data signal line disposed between the touch/common electrode layer and the substrate, the touch signal line and the The data signal line is on the same layer as the source/drain of the thin film transistor device.
  • the array substrate further includes:
  • the thin film transistor device layer is disposed on the first insulating layer, and includes: a polysilicon layer, a second insulating layer, a gate line, and a third insulating layer, which are sequentially disposed on the first insulating layer, the source/drain a pole, the data signal line and the touch signal line are formed on the third insulating layer, and the source/drain are electrically connected to the polysilicon layer;
  • a fourth insulating layer disposed on the source/drain, the data signal line, and the touch signal line.
  • the touch/common electrode layer is disposed on the fourth insulating layer
  • the array substrate further includes a fifth insulating layer disposed on the touch/common electrode layer; the pixel electrode layer is disposed on the fifth insulating layer.
  • the pixel electrode layer is disposed on the fourth insulating layer
  • the array substrate further includes a fifth insulating layer disposed on the pixel electrode layer; the touch/common electrode layer is disposed on the fifth insulating layer.
  • the first through hole and the second through hole are defined in the second insulating layer and the third insulating layer, wherein the first through hole is from the third insulating layer
  • the upper surface penetrates to the polysilicon layer via the second insulating layer, and the second via hole penetrates from the upper surface of the third insulating layer to the polysilicon layer via the second insulating layer;
  • the source/drain are electrically connected to the polysilicon layer through a first via and a second via.
  • the present application shortens the process flow, improves the production efficiency, and reduces the cost by processing the mask to form the source/drain, the data signal line, and the touch signal line.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate in some embodiments of the present application.
  • FIG. 2 to FIG. 13 are flow diagrams of a method for fabricating an array substrate in some embodiments of the present application.
  • Figure 14 is a block diagram of an array substrate in some embodiments of the present application.
  • 15 is another structural diagram of an array substrate in some embodiments of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality” is two or more unless specifically and specifically defined otherwise.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise specifically defined and defined. Connected, or integrally connected; may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship.
  • Connected, or integrally connected may be mechanically connected, may be electrically connected or may communicate with each other; may be directly connected, or may be indirectly connected through an intermediate medium, may be internal communication of two elements or interaction of two elements relationship.
  • the specific meanings of the above terms in the present application can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may include direct contact of the first and second features, and may also include first and second features, unless otherwise specifically defined and defined. It is not in direct contact but through additional features between them.
  • the first feature “above”, “above” and “above” the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature includes the first feature directly below and below the second feature, or merely the first feature level being less than the second feature.
  • FIG. 1 is a flowchart of a method for fabricating an array substrate according to some embodiments of the present application.
  • the method for fabricating the array substrate includes the following steps:
  • the substrate 10 may be a glass substrate.
  • a first metal layer is deposited on the substrate 10 by physical vapor deposition, and then the first metal layer is patterned by using a first mask to obtain the light shielding layer 20.
  • the light shielding layer can also be made of other non-metal materials with low light transmittance.
  • the first insulating layer 30 may be a silicon dioxide or silicon nitride material.
  • the first insulating layer 30 is deposited on the substrate 10 and the light shielding layer 20 by using a silicon dioxide or a silicon nitride material.
  • step S102 please refer to FIG. 4 and FIG. 5 simultaneously, and in the step S102, the following sub-steps are included:
  • the first region 41 is ion-implanted to form a heavily doped region, and the source/drain is electrically connected to the heavily doped region through a first via and a second via.
  • the photoresist layer 100 is first disposed on the second and third regions of the polysilicon layer 40 and the first insulating layer, and then ion implantation is performed on the first region 41 to form a heavily doped region. The photoresist layer 100 is then removed.
  • the second insulating layer 60 may be formed by depositing silicon nitride or silicon dioxide.
  • a gate line 50 is formed on the second insulating layer 60. As shown in FIG. 5, the gate line 50 is opposed to the metal light shielding layer 20 and the polysilicon layer 400.
  • ion implantation is performed on the second region 42 to form a lightly doped region, and a channel region is formed in the undoped third region 43.
  • the third insulating layer 70 may be formed by depositing silicon nitride or silicon dioxide.
  • the third insulating layer 70 and the second insulating layer 60 define a first through hole 71 and a second through hole 72, wherein the first through hole 71 passes from the upper surface of the third insulating layer 70 via the second
  • the insulating layer 60 penetrates to the polysilicon layer 40, and the second via hole 42 penetrates from the upper surface of the third insulating layer 70 to the polysilicon layer 40 via the second insulating layer 60.
  • the second metal layer is patterned by using a photomask to obtain the source/drain 82 and the data.
  • the source/drain 82 is electrically connected to the polysilicon layer 40 through the first via 71 and the second via 72.
  • the first through hole 71 and the second through hole 72 have a filling metal, and the filling metal is formed together with the second metal layer.
  • the source/drain 82 refers to a source and a drain.
  • the polysilicon layer 40, the second insulating layer 60, the gate line 50, the third insulating layer 70, and the source/drain 82 constitute the thin film transistor device layer.
  • the fourth insulating layer 90 is a flat layer, and the fourth insulating layer 90 may be deposited by silicon dioxide or silicon nitride material. form.
  • a third through hole 91 and a fourth through hole 92 are formed on the fourth insulating layer 90 by a patterning process.
  • the third through hole 91 is connected to the touch signal line 81
  • the touch/common electrode layer 110 is electrically connected to the touch signal line 81 through the third through hole 91 .
  • the third through hole 91 has a metal filler therein.
  • the fourth via 92 extends through the drain of the source/drain 82, and the fourth via 92 has a metal fill therein.
  • the touch/common electrode layer 110 can implement both a touch function and a common electrode function.
  • the fifth insulating layer 120 may be formed by deposition of silicon dioxide or silicon nitride material.
  • a fifth through hole 121 is formed in the fifth insulating layer 120, and the fifth through hole is opposite to and communicates with the fourth through hole 92.
  • the pixel electrode layer 130 is electrically connected to the drains of the source/drain electrodes 82 through the fifth via holes 121 and the fourth via holes 92 in sequence.
  • a metal layer is first deposited on the fifth insulating layer by using indium tin oxide, and then the metal layer is patterned to obtain a plurality of pixel electrode layers 130.
  • the positions of the pixel electrode layer and the common/touch electrode layer may be adjusted, that is, the pixel electrode layer is disposed on the fourth insulating layer; a fifth insulating layer on the pixel electrode layer; the touch/common electrode layer is disposed on the fifth insulating layer.
  • the step S102 may be completed by other steps.
  • a second insulating layer and a fifth metal layer are deposited on the polysilicon layer 40, and the fifth metal layer is etched once by the photomask, so that the polysilicon is The second region of layer 40 and the fifth metal layer on the third region remain, and the fifth metal layer of the other regions is etched away.
  • the first region 41 of the polysilicon layer 40 is ion-implanted to form a heavily doped region.
  • the photoresist layer 100 is not removed at this time.
  • the fifth metal layer is etched a second time through the photomask to form a gate line at a position corresponding to the third region of the metal layer, and then the photoresist layer 100 is removed, and then the second The region is ion implanted to form a lightly doped region, that is, an LDD region. A channel region is formed in the undoped third region 43. This method can reduce a mask.
  • FIG. 13 is a structural diagram of an array substrate in an embodiment of the present application.
  • the array substrate includes: a substrate 10, a light shielding layer 20, a first insulating layer 30, a polysilicon layer 40, a second insulating layer 60, a gate line 50, a third insulating layer 70, a second metal layer 80, and a fourth insulating layer. 90.
  • the light shielding layer 20 , the first insulating layer 30 , the polysilicon layer 40 , the second insulating layer 60 , and the gate lines 50 are sequentially disposed on the substrate 10 .
  • the third insulating layer 70 is disposed on the second insulating layer 60 and the gate line 50.
  • the second metal layer 80 is disposed on the third insulating layer 70.
  • the second metal layer 80 forms an active/drain 82, a data signal line, and a touch signal line 81.
  • the source/drain 82 and the The polysilicon layer 40 is electrically connected.
  • the fourth insulating layer 90 is disposed on the second metal layer 80.
  • the touch/common electrode layer 110 is disposed on the fourth insulating layer 90, and the touch/common electrode layer 110 is electrically connected to the touch signal line 81.
  • the fifth insulating layer 120 is disposed on the touch/common electrode layer 110.
  • the pixel electrode layer 130 is disposed on the fifth insulating layer 120, and the pixel electrode layer 130 is electrically connected to the source/drain 82.
  • the polysilicon layer 40, the second insulating layer 60, the gate line 50, the third insulating layer 70, and the source/drain 82 constitute the thin film transistor device layer.
  • a first through hole 71 and a second through hole 72 are defined in the second insulating layer and the third insulating layer, wherein the first through hole 71 passes from the upper surface of the third insulating layer via the The second insulating layer penetrates into the polysilicon layer, and the second via hole 72 penetrates from the upper surface of the third insulating layer to the polysilicon layer via the second insulating layer.
  • the source/drain are electrically connected to the polysilicon layer through the first via 71 and the second via 72.
  • the fourth insulating layer 90 has a third through hole 91 penetrating through the touch signal line and a fourth through hole 92 penetrating the source/drain 82.
  • the touch/common electrode layer is electrically connected to the touch signal line through the third through hole.
  • a fifth through hole 121 is defined in the fifth insulating layer 120, and the fourth through hole 92 is in communication with the fifth through hole 121; the pixel electrode layer 130 sequentially passes through the fifth through hole 121 and the fourth via 92 are electrically connected to the source/drain 82.
  • the position of the pixel electrode layer 130 and the common/touch electrode layer 110 may be adjusted, that is, the pixel electrode layer 130 is disposed on the fourth insulating layer 90;
  • the fifth insulating layer 120 is disposed on the pixel electrode layer 130, and the touch/common electrode layer 110 is disposed on the fifth insulating layer 120.
  • the present application shortens the process flow, improves the production efficiency, and reduces the cost by processing the mask to form the source/drain, the data signal line, and the touch signal line.
  • the present application also provides a liquid crystal display panel including a color film substrate, a liquid crystal layer, and the array substrate in the above embodiment.
  • the color filter substrate and the array substrate are oppositely disposed, and the liquid crystal layer is disposed between the color filter substrate and the array substrate.

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Abstract

一种阵列基板的制作方法，阵列基板及液晶显示面板。制作方法包括：在基板（10）上形成第三绝缘层（70）；在第三绝缘层（70）上形成第二金属层（80），并对第二金属层（80）一次光罩处理以形成源/漏极（82）、数据信号线以及触控信号线（81）；在第二金属层（80）上形成第四绝缘层（90）；在第四绝缘层（90）上形成触控/公共电极层（110）以及像素电极层（130）。

Description

阵列基板的制作方法、阵列基板及液晶显示面板 技术领域
本申请涉及液晶显示领域，具体涉及一种阵列基板的制作方法、阵列基板及液晶显示面板。
 背景技术
低温多晶硅（Low temperature poly-silicon，简称LTPS），由于其具有高的电子迁移率，可以有效的减小TFT的器件的面积，从而提升像素的开口率。增大面板显示亮度的同时可以降低整体的功耗，使得面板的制造成本大幅度降低，目前已成为液晶显示领域炙手可热的技术。
但是LTPS工艺复杂，Array侧基板阵列成膜的层别较多，尤其是增加In Cell Touch功能后，Array侧一般需要12层甚至是更多的层别结构，这样较多的光罩数量，同时产品制作产能时间增长，增加了光照成本、物料和运营成本。
如何能有效的降低LTPS Array侧阵列基板的制作周期，提升产品的良率，有效提升产品生产产能，降低成本，是目前面板设计行业关注的重点，也是增加公司市场竞争力的有效途。
 技术问题
本申请实施例的目的是提供一种阵列基板的制作方法、阵列基板及液晶显示面板，具有缩短工艺流程的有益效果。
 技术解决方案
本申请实施例提供一种阵列基板的制作方法，包括：
在基板上形成第三绝缘层；
在第三绝缘层上形成第二金属层，并对第二金属层一次光罩处理以形成源/漏极、数据信号线以及触控信号线；
在第二金属层上形成第四绝缘层；
在第四绝缘层上形成触控/公共电极层以及像素电极层，所述触控/公共电极层与所述触控信号线电连接；所述像素电极层与所述源/漏极电连接。
在本申请所述的阵列基板的制作方法中，所述在第四绝缘层上形成触控/公共电极层以及像素电极层的步骤包括：
在第四绝缘层上形成触控/公共电极层；
在触控/公共电极层上形成第五绝缘层；
在第五绝缘层上形成像素电极层。
在本申请所述的阵列基板的制作方法中，所述在基板上形成第三绝缘层的步骤包括：
在基板上依次形成遮光层以及第一绝缘层；
在第一绝缘层上形成多晶硅层、第二绝缘层以及栅极线；
在第二绝缘层以及栅极线上形成第三绝缘层。
在本申请所述的阵列基板的制作方法中，所述第二绝缘层以及所述第三绝缘层上开设第一通孔以及第二通孔，其中，所述第一通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层；
所述源/漏极通过第一通孔以及第二通孔与所述多晶硅层电连接。
在本申请所述的阵列基板的制作方法中，所述在第一绝缘层上形成多晶硅层、第二绝缘层以及栅极线的步骤包括：
在第一绝缘层上形成多晶硅层，所述多晶硅层包括第一区域、第二区域以及第三区域，所述第一区域通过所述第二区域与第三区域连接，对所述第一区域进行N+离子注入以形成重掺杂区域，所述源/漏极通过第一通孔以及第二通孔与所述重掺杂区域电连接；
在多晶硅层以及第一绝缘层上形成第二绝缘层；
在第二绝缘层上形成栅极线；
对第二区域进行离子注入以形成轻掺杂区域，并在未掺杂的第三区域形成沟道区。
在本申请所述的阵列基板的制作方法中，所述第四绝缘层上开设有贯穿至所述触控信号线的第三通孔，所述触控/公共电极层通过所述第三通孔与所述触控信号线电连接。
在本申请所述的阵列基板的制作方法中，所述第五绝缘层上开设有第五通孔，所述第四绝缘层上开设有贯穿至所述源/漏极的第四通孔，所述第四通孔与所述第五通孔连通；
所述像素电极层依次通过所述第五通孔以及所述第四通孔与所述源/漏极电连接。
本申请实施例还提供一种阵列基板，包括基板、设置在所述基板之上的薄膜晶体管器件层以及设置在薄膜晶体管器件层之上的触控/公共电极层以及像素电极层，所述阵列基板还包括：设置在所述触控/公共电极层与所述基板之间的触控信号线以及数据信号线，所述触控信号线以及所述数据信号线与薄膜晶体管器件的源/漏极位于同一层。
在本申请所述的阵列基板中，所述阵列基板还包括：
依次形成于所述基板上遮光层和第一绝缘层；
所述薄膜晶体管器件层位于所述第一绝缘层之上，其包括：依次设置于第一绝缘层上的多晶硅层、第二绝缘层、栅极线、第三绝缘层，所述源/漏极、所述数据信号线以及所述触控信号线形成于所述第三绝缘层上，所述源/漏极与所述多晶硅层电连接；
第四绝缘层，其设置于所述源/漏极、所述数据信号线以及所述触控信号线上。
在本申请所述的阵列基板中，所述触控/公共电极层设置于第四绝缘层上；
所述阵列基板还包括置于所述触控/公共电极层上的第五绝缘层；所述像素电极层设置于第五绝缘层上。
在本申请所述的阵列基板中，所述像素电极层设置于第四绝缘层上；
所述阵列基板还包括置于所述像素电极层上的第五绝缘层；所述触控/公共电极层设置于第五绝缘层上。
在本申请所述的阵列基板中，所述第二绝缘层以及所述第三绝缘层上开设第一通孔以及第二通孔，其中，所述第一通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层；
所述源/漏极通过第一通孔以及第二通孔与所述多晶硅层电连接。
在本申请所述的阵列基板中，所述第四绝缘层上开设有贯穿至所述触控信号线的第三通孔，所述触控/公共电极层通过所述第三通孔与所述触控信号线电连接。
在本申请所述的阵列基板中，所述第五绝缘层上开设有第五通孔，所述第四绝缘层上开设有贯穿至所述源/漏极的第四通孔，所述第四通孔与所述第五通孔连通；
所述像素电极层依次通过所述第五通孔以及所述第四通孔与所述源/漏极电连接。
本申请实施例还提供一种液晶显示面板，其包括阵列基板，所述阵列基板包括基板、设置在所述基板之上的薄膜晶体管器件层以及设置在薄膜晶体管器件层之上的触控/公共电极层以及像素电极层，其中，所述阵列基板还包括：设置在所述触控/公共电极层与所述基板之间的触控信号线以及数据信号线，所述触控信号线以及所述数据信号线与薄膜晶体管器件的源/漏极位于同一层。
在本申请所述的液晶显示面板中，所述阵列基板还包括：
依次形成于所述基板上遮光层和第一绝缘层；
所述薄膜晶体管器件层位于所述第一绝缘层之上，其包括：依次设置于第一绝缘层上的多晶硅层、第二绝缘层、栅极线、第三绝缘层，所述源/漏极、所述数据信号线以及所述触控信号线形成于所述第三绝缘层上，所述源/漏极与所述多晶硅层电连接；
第四绝缘层，其设置于所述源/漏极、所述数据信号线以及所述触控信号线上。
在本申请所述的液晶显示面板中，所述触控/公共电极层设置于第四绝缘层上；
所述阵列基板还包括置于所述触控/公共电极层上的第五绝缘层；所述像素电极层设置于第五绝缘层上。
在本申请所述的液晶显示面板中，所述像素电极层设置于第四绝缘层上；
所述阵列基板还包括置于所述像素电极层上的第五绝缘层；所述触控/公共电极层设置于第五绝缘层上。
在本申请所述的液晶显示面板中，所述第二绝缘层以及所述第三绝缘层上开设第一通孔以及第二通孔，其中，所述第一通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层；
所述源/漏极通过第一通孔以及第二通孔与所述多晶硅层电连接。
 有益效果
本申请通过一次光罩处理以形成源/漏极、数据信号线以及触控信号线，缩短了工艺流程，提高了生产效率，并降低了成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一些实施例中的阵列基板的制作方法的流程图意图。
图2-图13为本申请一些实施例中的阵列基板的制作方法的流程解析图。
图14为本申请一些实施例中的阵列基板的一种结构图。
图15为本申请一些实施例中的阵列基板的另一种结构图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1，图1是本申请一些实施例中的阵列基板的制作方法的流程图，所述阵列基板的制作方法包括以下步骤：
S101、在基板上依次形成遮光层以及第一绝缘层；
S102、在第一绝缘层上形成多晶硅层、第二绝缘层以及栅极线；
S103、在第二绝缘层以及栅极线上形成第三绝缘层。
S104、在第三绝缘层上形成第二金属层，并对第二金属层一次光罩处理以形成源/漏极、数据信号线以及触控信号线；
S105、在第二金属层上形成第四绝缘层，并在第四绝缘层上形成触控/公共电极层，所述触控/公共电极层与所述触控信号线电连接；
S106、在所述触控/公共电极层上形成第五绝缘层；
S107、在第五绝缘层上形成像素电极层，所述像素电极层与所述源/漏极电连接。
下面结合附图对所述阵列基板的制作方法的各个步骤进行详细说明。
在所述步骤S101中，请参照图2，所述基板10可以为玻璃基板。先采用物理气相沉淀在所述基板10沉积得到第一金属层，然后采用第一道光罩对所述第一金属层进行图形化处理，以得到所述遮光层20。当然，所述遮光层也可以采用其它光透过率较低的非金属材料制成。
请参照图3，所述第一绝缘层30可以为二氧化硅或者氮化硅材料。制作时，采用二氧化硅或者氮化硅材料在所述基板10以及遮光层20上沉积形成所述第一绝缘层30。
在一些实施例中，请同时参照图4、图5，在所述步骤S102中，包括以下子步骤：
S1021、在第一绝缘层30上形成多晶硅层（poly层）40，所述多晶硅层40包括第一区域、第二区域以及第三区域，所述第一区域通过所述第二区域与第三区域连接。如图4所示，对所述第一区域41进行离子注入以形成重掺杂区域，所述源/漏极通过第一通孔以及第二通孔与所述重掺杂区域电连接。制作时，先在所述多晶硅层40的第二区域和第三区域以及所述第一绝缘层上设置光阻层100，然后对第一区域41上进行离子注入，以形成重掺杂区域，然后去除光阻层100。
S1022、在多晶硅层40以及第一绝缘层30上形成第二绝缘层60。如图5所示，在所述步骤中，所述第二绝缘层60可以采用氮化硅或者二氧化硅沉积形成。
S1023、在第二绝缘层60上形成栅极线50。如图5所示，所述栅极线50与金属遮光层20以及多晶硅层400相对。
S1024、对第二区域42进行离子注入以形成轻掺杂区域，并在未掺杂的第三区域43形成沟道区。
在一些实施例中，请参照图6，在所述步骤S103中，所述第三绝缘层70可以采用氮化硅或者二氧化硅沉积形成。且所述第三绝缘层70以及第二绝缘层60开设第一通孔71以及第二通孔72，其中，所述第一通孔71从第三绝缘层70的上表面经由所述第二绝缘层贯60穿至所述多晶硅层40，所述第二通孔42从第三绝缘层70的上表面经由所述第二绝缘60层贯穿至所述多晶硅层40。
在一些实施例中，请参照图7，在所述步骤S104中，在形成第二金属层之后，采用光罩对所述第二金属层进行图形化处理，以得到源/漏极82、数据信号线（图未示）以及触控信号线81。所述源/漏极82通过第一通孔71以及第二通孔72与所述多晶硅层40电连接。其中，所述第一通孔71以及第二通孔72有填充金属，所述填充金属与所述第二金属层一起形成。所述源/漏极82指源极以及漏极。其中，所述多晶硅层40、第二绝缘层60、栅极线50、第三绝缘层70、源/漏极82构成了所述薄膜晶体管器件层。
在一些实施例中，请参照图8以及图9，在所述步骤S105中，所述第四绝缘层90为平坦层，所述第四绝缘层90可以为二氧化硅或者氮化硅材料沉积形成。所述第四绝缘层90上通过图形化处理形成有第三通孔91以及第四通孔92。其中，所述第三通孔91贯穿至所述触控信号线81，所述触控/公共电极层110通过所述第三通孔91与所述触控信号线81电连接。所述第三通孔91中有金属填充物。所述第四通孔92贯穿至所述源/漏极82的漏极，所述第四通孔92中有金属填充物。所述触控/公共电极层110既可以实现触控的功能也可以实现公共电极的功能。
在一些实施例中，请参照图10，在所述步骤S106中，所述第五绝缘层120可以采用二氧化硅或者氮化硅材料沉积形成。所述第五绝缘层120上形成有第五通孔121，所述第五通孔与所述第四通孔92相对并连通。
在一些实施例中，请参照图11，像素电极层130依次通过所述第五通孔121以及所述第四通孔92与所述源/漏极82的漏极电连接。制作像素电极层130时，先采用氧化铟锡在所述第五绝缘层上沉积形成金属层，然后对所述金属层进行图形化处理，从而得到多个像素电极层130。
在一些实施例中，所述像素电极层和所述公共/触控电极层的位置可以进行调整，也即是将像素电极层设置于第四绝缘层上；所述阵列基板还包括置于所述像素电极层上的第五绝缘层；所述触控/公共电极层设置于第五绝缘层上。
请参照图12以及图13所示，在一些实施例中，所述步骤S102还可以采用其他步骤完成。例如，完成Poly离子注入后，也即是形成多晶硅层40后，在多晶硅层40上面沉积第二绝缘层和第五金属层，通过光罩对第五金属层进行一次蚀刻，使得在所述多晶硅层40的第二区域以及第三区域上的第五金属层保留，其他区域的第五金属层都被蚀刻掉。蚀刻完成后对所述多晶硅层40的第一区域41进行离子注入，形成重掺杂区域。此时未去除光阻层100。在离子注入之后，通过光罩对第五金属层进行第二次蚀刻，以在所述金属层对应所述第三区域的位置形成栅极线，然后去除光阻层100之后，再对第二区域进行离子注入，形成轻掺杂区域，也就是LDD区域。并在未掺杂的第三区域43形成沟道区。采用这种方法可以减少一道光罩。
请参照图13，图13是本申请一实施例中的阵列基板的结构图。所述阵列基板包括：基板10、遮光层20、第一绝缘层30、多晶硅层40、第二绝缘层60、栅极线50、第三绝缘层70、第二金属层80、第四绝缘层90、触控/公共电极层110、第五绝缘层120以及像素电极层130。所述遮光层20、第一绝缘层30、多晶硅层40、第二绝缘层60、栅极线50依次设置于所述基板10上。所述第三绝缘层70设置于所述第二绝缘层60以及所述栅极线50上。第二金属层80设置于所述第三绝缘层70上，所述第二金属层80形成有源/漏极82、数据信号线以及触控信号线81，所述源/漏极82与所述多晶硅层40电连接。所述第四绝缘层90设置于所述第二金属层80上。触控/公共电极层110设置于第四绝缘层90上，所述触控/公共电极层110与所述触控信号线81电连接。第五绝缘层120设置于所述触控/公共电极层110上。像素电极层130其设置于第五绝缘层120上，所述像素电极层130与所述源/漏极82电连接。
其中，所述多晶硅层40、第二绝缘层60、栅极线50、第三绝缘层70、源/漏极82构成了所述薄膜晶体管器件层。
具体地，所述第二绝缘层以及所述第三绝缘层上开设第一通孔71以及第二通孔72，其中，所述第一通孔71从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔72从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层。所述源/漏极通过第一通孔71以及第二通孔72与所述多晶硅层电连接。
具体地，所述第四绝缘90层上开设有贯穿至所述触控信号线的第三通孔91，以及贯穿至所述源/漏极82的第四通孔92。所述触控/公共电极层通过所述第三通孔与所述触控信号线电连接。
具体地，所述第五绝缘层120上开设有第五通孔121，所述第四通孔92与所述第五通孔121连通；所述像素电极层130依次通过所述第五通孔121以及所述第四通孔92与所述源/漏极82电连接。
在一些实施例子中，请参照图15，所述像素电极层130和所述公共/触控电极层110的位置可以进行调整，也即是将像素电极层130设置于第四绝缘层90上；第五绝缘层120设置在所述像素电极层130上，触控/公共电极层110设置于第五绝缘层120上。
本申请通过一次光罩处理以形成源/漏极、数据信号线以及触控信号线，缩短了工艺流程，提高了生产效率，并降低了成本。
本申请还提供了一种液晶显示面板，其包括彩膜基板、液晶层以及上述实施例中的阵列基板。所述彩膜基板以及所述阵列基板相对设置，所述液晶层设置于彩膜基板与阵列基板之间。
以上对本申请实施例提供的阵列基板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板的制作方法，其包括：
    在基板上形成第三绝缘层；
    在第三绝缘层上形成第二金属层，并对第二金属层一次光罩处理以形成源/漏极、数据信号线以及触控信号线；
    在第二金属层上形成第四绝缘层；
    在第四绝缘层上形成触控/公共电极层以及像素电极层，所述触控/公共电极层与所述触控信号线电连接；所述像素电极层与所述源/漏极电连接。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，所述在第四绝缘层上形成触控/公共电极层以及像素电极层的步骤包括：
    在第四绝缘层上形成触控/公共电极层；
    在触控/公共电极层上形成第五绝缘层；
    在第五绝缘层上形成像素电极层。
  3. 根据权利要求2所述的阵列基板的制作方法，其中，所述在基板上形成第三绝缘层的步骤包括：
    在基板上依次形成遮光层以及第一绝缘层；
    在第一绝缘层上形成多晶硅层、第二绝缘层以及栅极线；
    在第二绝缘层以及栅极线上形成第三绝缘层。
  4. 根据权利要求3所述的阵列基板的制作方法，其中，所述第二绝缘层以及所述第三绝缘层上开设第一通孔以及第二通孔，其中，所述第一通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层；
    所述源/漏极通过第一通孔以及第二通孔与所述多晶硅层电连接。
  5. 根据权利要求4所述的阵列基板的制作方法，其中，所述在第一绝缘层上形成多晶硅层、第二绝缘层以及栅极线的步骤包括：
    在第一绝缘层上形成多晶硅层，所述多晶硅层包括第一区域、第二区域以及第三区域，所述第一区域通过所述第二区域与第三区域连接，对所述第一区域进行离子注入以形成重掺杂区域，所述源/漏极通过第一通孔以及第二通孔与所述重掺杂区域电连接；
    在多晶硅层以及第一绝缘层上形成第二绝缘层；
    在第二绝缘层上形成栅极线；
    对第二区域进行离子注入以形成轻掺杂区域，并在未掺杂的第三区域形成沟道区。
  6. 根据权利要求4所述的阵列基板的制作方法，其中，所述在第一绝缘层上形成多晶硅层、第二绝缘层以及栅极线的步骤包括：
    在第一绝缘层上形成多晶硅层，所述多晶硅层包括第一区域、第二区域以及第三区域，所述第一区域通过所述第二区域与第三区域连接；
    在多晶硅层上沉积第二绝缘层和第五金属层，通过光罩对第五金属层进行一次蚀刻，使得在所述多晶硅层的第二区域以及第三区域上的金属层保留，其他区域的第五金属层都被蚀刻掉；
    对所述多晶硅层的第一区域进行离子注入，形成重掺杂区域；
    通过光罩对第五金属层进行第二次蚀刻，以在所述第五金属层上对应所述第三区域的位置形成栅极线；
    对第二区域进行离子注入，形成轻掺杂区域，并在第三区域形成沟道区。
  7. 根据权利要求3所述的阵列基板的制作方法，其中，所述第四绝缘层上开设有贯穿至所述触控信号线的第三通孔，所述触控/公共电极层通过所述第三通孔与所述触控信号线电连接。
  8. 根据权利要求3所述的阵列基板的制作方法，其中，所述第五绝缘层上开设有第五通孔，所述第四绝缘层上开设有贯穿至所述源/漏极的第四通孔，所述第四通孔与所述第五通孔连通；
    所述像素电极层依次通过所述第五通孔以及所述第四通孔与所述源/漏极电连接。
  9. 一种阵列基板，包括基板、设置在所述基板之上的薄膜晶体管器件层以及设置在薄膜晶体管器件层之上的触控/公共电极层以及像素电极层，其中，所述阵列基板还包括：设置在所述触控/公共电极层与所述基板之间的触控信号线以及数据信号线，所述触控信号线以及所述数据信号线与薄膜晶体管器件的源/漏极位于同一层。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括：
    依次形成于所述基板上遮光层和第一绝缘层；
    所述薄膜晶体管器件层位于所述第一绝缘层之上，其包括：依次设置于第一绝缘层上的多晶硅层、第二绝缘层、栅极线、第三绝缘层，所述源/漏极、所述数据信号线以及所述触控信号线形成于所述第三绝缘层上，所述源/漏极与所述多晶硅层电连接；
    第四绝缘层，其设置于所述源/漏极、所述数据信号线以及所述触控信号线上。
  11. 根据权利要求10所述的阵列基板，其中，所述触控/公共电极层设置于第四绝缘层上；
    所述阵列基板还包括置于所述触控/公共电极层上的第五绝缘层；所述像素电极层设置于第五绝缘层上。
  12. 根据权利要求10所述的阵列基板，其中，所述像素电极层设置于第四绝缘层上；
    所述阵列基板还包括置于所述像素电极层上的第五绝缘层；所述触控/公共电极层设置于第五绝缘层上。
  13. 根据权利要求11所述的阵列基板，其中，所述第二绝缘层以及所述第三绝缘层上开设第一通孔以及第二通孔，其中，所述第一通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层；
    所述源/漏极通过第一通孔以及第二通孔与所述多晶硅层电连接。
  14. 根据权利要求11所述的阵列基板，其中，所述第四绝缘层上开设有贯穿至所述触控信号线的第三通孔，所述触控/公共电极层通过所述第三通孔与所述触控信号线电连接。
  15. 根据权利要求11所述的阵列基板，其中，所述第五绝缘层上开设有第五通孔，所述第四绝缘层上开设有贯穿至所述源/漏极的第四通孔，所述第四通孔与所述第五通孔连通；
    所述像素电极层依次通过所述第五通孔以及所述第四通孔与所述源/漏极电连接。
  16. 一种液晶显示面板，其包括阵列基板，所述阵列基板包括基板、设置在所述基板之上的薄膜晶体管器件层以及设置在薄膜晶体管器件层之上的触控/公共电极层以及像素电极层，其中，所述阵列基板还包括：设置在所述触控/公共电极层与所述基板之间的触控信号线以及数据信号线，所述触控信号线以及所述数据信号线与薄膜晶体管器件的源/漏极位于同一层。
  17. 根据权利要求16所述的液晶显示面板，其中，所述阵列基板还包括：
    依次形成于所述基板上遮光层和第一绝缘层；
    所述薄膜晶体管器件层位于所述第一绝缘层之上，其包括：依次设置于第一绝缘层上的多晶硅层、第二绝缘层、栅极线、第三绝缘层，所述源/漏极、所述数据信号线以及所述触控信号线形成于所述第三绝缘层上，所述源/漏极与所述多晶硅层电连接；
    第四绝缘层，其设置于所述源/漏极、所述数据信号线以及所述触控信号线上。
  18. 根据权利要求17所述的液晶显示面板，其中，所述触控/公共电极层设置于第四绝缘层上；
    所述阵列基板还包括置于所述触控/公共电极层上的第五绝缘层；所述像素电极层设置于第五绝缘层上。
  19. 根据权利要求17所述的液晶显示面板，其中，所述像素电极层设置于第四绝缘层上；
    所述阵列基板还包括置于所述像素电极层上的第五绝缘层；所述触控/公共电极层设置于第五绝缘层上。
  20. 根据权利要求18所述的液晶显示面板，其中，所述第二绝缘层以及所述第三绝缘层上开设第一通孔以及第二通孔，其中，所述第一通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层，所述第二通孔从第三绝缘层的上表面经由所述第二绝缘层贯穿至所述多晶硅层；
    所述源/漏极通过第一通孔以及第二通孔与所述多晶硅层电连接。
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