JP2015514321A - Tft、該tftを製造するマスク、アレイ基板及び表示装置 - Google Patents
Tft、該tftを製造するマスク、アレイ基板及び表示装置 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 90
- 239000010410 layer Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 239000002184 metal Substances 0.000 description 12
- 238000000059 patterning Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 238000002834 transmittance Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 231100000105 margin of exposure Toxicity 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/22—Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
Description
本実施例は、薄膜トランジスタを製造するためのマスクを提供する。図2に示すように、該マスクは、薄膜トランジスタのチャネルに対応するシングルスリットを備え、該シングルスリットは、曲折部Bと曲折部Bの両側に位置する延伸部Aとを有し、曲折部Bのスリット幅は延伸部Aのスリット幅よりも広い。
本実施例は、薄膜トランジスタを製造するためのマスクを提供する。図4に示すように、該マスクは、薄膜トランジスタのチャネルに対応するシングルスリットを備え、該シングルスリットは、曲折部Bと、曲折部Bの両側に位置する延伸部Aとを有し、曲折部Bのスリット幅は延伸部Aのスリット幅よりも広い。
本実施例は薄膜トランジスタを提供する。該薄膜トランジスタのチャネルは、シングルスリットグレースケールマスクによって製造され、該薄膜トランジスタのチャネルの幅は2μm〜6μmである。
本実施例は、薄膜トランジスタを提供する。該薄膜トランジスタのチャネルは、シングルスリットグレースケールマスクによって製造され、該薄膜トランジスタのチャネルの幅は2μm〜6μmである。
本実施例は、実施例1のマスクによって実施例3の薄膜トランジスタを製造する製造方法を提供する。該方法は、基板上に導電性のゲート金属層を形成し、1回目のパターニング工程によって基板上にゲート電極を形成し、そして、ゲート電極の上方にゲート絶縁層を形成し、その後、ゲート絶縁層上に半導体層及びソース・ドレイン電極金属層を形成するステップS1と、前記実施例1に係るシングルスリットグレースケールマスクによって、2回目のパターニング工程を行い、活性層、ソース電極、ドレイン電極及びチャネルを形成するように、前記ソース・ドレイン電極金属層及び前記半導体層をパターン化するステップS2と、を備える。
本実施例は、実施例2に係るマスクによって、実施例4に係る薄膜トランジスタを製造する製造方法を提供する。該方法は、基板上に導電性のゲート金属層を形成し、1回目のパターニング工程によって基板上にゲート電極を形成し、そして、ゲート電極の上方にゲート絶縁層を形成し、その後、ゲート絶縁層上に半導体層及びソース・ドレイン電極金属層を形成するステップS1と、前記実施例2に係るシングルスリットグレースケールマスクによって、2回目のパターニング工程を行い、活性層、ソース電極、ドレイン電極及びチャネルを形成するように、前記ソース・ドレイン電極金属層及び前記半導体層をパターン化するステップS2と、を備える。
2 ドレイン電極に対応する領域
A 延伸部
B 曲折部
Claims (17)
- 薄膜トランジスタであって、前記薄膜トランジスタのチャネルは、シングルスリットグレースケールマスクによって製造され、前記薄膜トランジスタのチャネルは、曲折部と、前記曲折部の両側に位置する延伸部とを有し、且つ前記曲折部のチャネル幅は、前記延伸部のチャネル幅よりも広いことを特徴とする薄膜トランジスタ。
- 前記薄膜トランジスタは、ソース電極及びドレイン電極をさらに備え、前記チャネルは、前記ソース電極と前記ドレイン電極との間に位置し、且つ前記曲折部では、前記ソース電極は、ドレイン電極方向とは逆方向へ凹むように形成されることを特徴とする請求項1に記載の薄膜トランジスタ。
- 前記薄膜トランジスタは、ソース電極及びドレイン電極をさらに備え、前記チャネルは、前記ソース電極と前記ドレイン電極との間に位置し、且つ前記曲折部では、前記ドレイン電極は、ソース電極方向とは逆方向へ凹むように形成されることを特徴とする請求項1に記載の薄膜トランジスタ。
- 前記凹み部分の部分は、矩形、半円形または半楕円形であることを特徴とする請求項2または3に記載の薄膜トランジスタ。
- 前記チャネル幅は、2μm〜6μmであることを特徴とする請求項1から4の何れか一項に記載の薄膜トランジスタ。
- 前記曲折部のチャネル幅は、3μm〜6μmであることを特徴とする請求項1から5の何れか一項に記載の薄膜トランジスタ。
- 前記延伸部のチャネル幅は、2μm〜3.5μmであることを特徴とする請求項1から6の何れか一項に記載の薄膜トランジスタ。
- 薄膜トランジスタを製造するためのマスクであって、前記マスクは、前記薄膜トランジスタのチャネルに対応するシングルスリットを備え、前記シングルスリットは、曲折部と、前記曲折部の両側に位置する延伸部とを備え、且つ前記曲折部のスリット幅は延伸部のスリット幅よりも広いことを特徴とする薄膜トランジスタを製造するためのマスク。
- 前記マスクは、前記薄膜トランジスタのソース電極に対応する第1の領域と、前記薄膜トランジスタのドレイン電極に対応する第2の領域とをさらに備え、前記薄膜トランジスタのチャネルに対応する前記スリットは、前記第1の領域と前記第2の領域との間に位置し、且つ前記曲折部では、前記第1の領域は、前記第2の領域の方向とは逆方向へ凹むように形成されることを特徴とする請求項8に記載の薄膜トランジスタを製造するためのマスク。
- 前記マスクは、前記薄膜トランジスタのソース電極に対応する第1の領域と、前記薄膜トランジスタのドレイン電極に対応する第2の領域とをさらに備え、前記薄膜トランジスタのチャネルに対応する前記スリットは、前記第1の領域と前記第2の領域との間に位置し、且つ前記曲折部では、前記第2の領域は、前記第1の領域の方向とは逆方向へ凹むように形成されることを特徴とする請求項8に記載の薄膜トランジスタを製造するためのマスク。
- 前記凹み部分は、矩形、半円形又は半楕円形であることを特徴とする請求項9または10に記載の薄膜トランジスタを製造するためのマスク。
- 前記第1の領域及び前記第2の領域は、光を透過しない領域であることを特徴とする請求項9から11の何れか一項に記載の薄膜トランジスタを製造するためのマスク。
- 前記スリットの幅は1μm〜5μmであることを特徴とする請求項8から12の何れか一項に記載の薄膜トランジスタを製造するためのマスク。
- 前記曲折部のスリット幅は、2.5μm〜5μmであることを特徴とする請求項8から13の何れか一項に記載の薄膜トランジスタを製造するためのマスク。
- 前記延伸部のスリット幅は、1μm〜4μmであることを特徴とする請求項8から14の何れか一項に記載の薄膜トランジスタを製造するためのマスク。
- 請求項1から7の何れか一項に記載の薄膜トランジスタを備えることを特徴とするアレイ基板。
- 請求項1から7の何れか一項に記載の薄膜トランジスタを備えることを特徴とする表示装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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CN201210100442.4A CN102655175B (zh) | 2012-04-06 | 2012-04-06 | Tft、阵列基板及显示装置、制备该tft的掩模板 |
CN201210100442.4 | 2012-04-06 | ||
PCT/CN2012/086066 WO2013149477A1 (zh) | 2012-04-06 | 2012-12-06 | 薄膜晶体管、制备该薄膜晶体管的掩模板、阵列基板及显示装置 |
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JP2015514321A true JP2015514321A (ja) | 2015-05-18 |
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US (1) | US8952384B2 (ja) |
EP (1) | EP2677543B1 (ja) |
JP (1) | JP2015514321A (ja) |
KR (1) | KR101530460B1 (ja) |
CN (1) | CN102655175B (ja) |
WO (1) | WO2013149477A1 (ja) |
Cited By (1)
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JP2017524259A (ja) * | 2014-10-20 | 2017-08-24 | 深▲セン▼市華星光電技術有限公司 | 薄膜トランジスタ |
Families Citing this family (13)
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CN102655175B (zh) | 2012-04-06 | 2014-07-02 | 京东方科技集团股份有限公司 | Tft、阵列基板及显示装置、制备该tft的掩模板 |
CN104793461A (zh) * | 2015-04-20 | 2015-07-22 | 深圳市华星光电技术有限公司 | 制作薄膜晶体管的掩模板及用该掩模板制作的薄膜晶体管 |
CN104867945B (zh) * | 2015-05-13 | 2018-02-13 | 京东方科技集团股份有限公司 | 阵列基板、阵列基板制造方法和显示装置 |
CN105137710A (zh) * | 2015-07-15 | 2015-12-09 | 深圳市华星光电技术有限公司 | 掩膜版及薄膜晶体管的制造方法 |
CN106950771B (zh) * | 2017-03-31 | 2019-12-24 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
US10446632B2 (en) | 2017-12-28 | 2019-10-15 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Organic light-emitting diode display panel |
CN108183125B (zh) * | 2017-12-28 | 2020-12-29 | 武汉华星光电半导体显示技术有限公司 | 有机发光二极管显示面板 |
CN109541829B (zh) * | 2018-12-19 | 2021-08-24 | 惠科股份有限公司 | 掩膜版、液晶面板和液晶显示装置 |
CN110379849A (zh) * | 2019-07-22 | 2019-10-25 | 深圳市华星光电半导体显示技术有限公司 | 一种薄膜晶体管及显示面板 |
TWI727752B (zh) * | 2020-04-21 | 2021-05-11 | 友達光電股份有限公司 | 主動元件 |
CN112925136B (zh) * | 2021-03-29 | 2023-03-10 | 绵阳惠科光电科技有限公司 | 一种驱动电路的控制开关、阵列基板和显示面板 |
CN112925137B (zh) * | 2021-03-29 | 2023-03-10 | 绵阳惠科光电科技有限公司 | 一种驱动电路的控制开关、阵列基板和显示面板 |
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KR101530460B1 (ko) | 2015-06-19 |
CN102655175A (zh) | 2012-09-05 |
KR20140004078A (ko) | 2014-01-10 |
WO2013149477A1 (zh) | 2013-10-10 |
US8952384B2 (en) | 2015-02-10 |
EP2677543B1 (en) | 2019-10-09 |
EP2677543A1 (en) | 2013-12-25 |
EP2677543A4 (en) | 2015-08-26 |
US20140054702A1 (en) | 2014-02-27 |
CN102655175B (zh) | 2014-07-02 |
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