CN102655175A - Tft、阵列基板及显示装置、制备该tft的掩模板 - Google Patents

Tft、阵列基板及显示装置、制备该tft的掩模板 Download PDF

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CN102655175A
CN102655175A CN2012101004424A CN201210100442A CN102655175A CN 102655175 A CN102655175 A CN 102655175A CN 2012101004424 A CN2012101004424 A CN 2012101004424A CN 201210100442 A CN201210100442 A CN 201210100442A CN 102655175 A CN102655175 A CN 102655175A
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film transistor
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CN102655175B (zh
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崔承镇
刘圣烈
宋泳锡
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BOE Technology Group Co Ltd
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Priority to US13/883,858 priority patent/US8952384B2/en
Priority to PCT/CN2012/086066 priority patent/WO2013149477A1/zh
Priority to JP2015503729A priority patent/JP2015514321A/ja
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract

本发明涉及一种TFT、制备该TFT的掩模板及包括该TFT的显示装置,属于显示技术领域。为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本发明所提供的薄膜晶体管的沟道部结构为通过灰色调掩膜工艺以单隙缝方式来制得,所述沟道部结构的宽度在2μm~6μm之间。通过将薄膜晶体管沟道部内侧U型弯折部处的沟道宽度形成为大于弯折部两侧的延伸部的沟道宽度,从而可以消除现有技术中因为该区域沟道宽度较小而导致的短沟道效应,可以消除现有技术中通过率不高、良品率不足、产率过低的问题。

Description

TFT、阵列基板及显示装置、制备该TFT的掩模板
技术领域
本发明涉及显示技术领域,具体涉及TFT、阵列基板及其显示装置,包括制备该TFT的掩模板。
背景技术
在平板显示领域,薄膜晶体管是制作显示器件的关键器件。目前市场上显示装置的响应速度,显示品质都有了更好的要求,为了实现更好的显示品质,需要不断的改善薄膜晶体管(Thin-Film Transistor,简称TFT)的特性,一般采用改善薄膜特性以及半导体材料的方法,但其制作成本要求较高,为了拥有更好的器件特性,减少沟道宽度也成为研究的趋势之一。目前,为形成更精密的沟道尺寸,常使用SSM(Single Slit Mask,单缝隙掩模板)方式来达到量产沟道宽度为4μm以下的TFT沟道部。目前为了获得更好的TFT特性,采用SSM方式时,在TFT沟道的弯折部容易出现不良。如图1所示,在现有的SSM方式的沟道部设计中,A部分为直道区域和作为内侧U型弯折部的B部分区域中L均指沟道的宽度。为了得到宽度L为3.0~3.5μm的沟道,沟道弯折部B部在曝光机的作用下因其其透过率比A部分会有所降低,这样在沟道弯折部B部分在曝光时容易发生透过率下降,导致光刻胶不能
被完全去除,使得构图工艺后,B部分的源漏极产生短路不良。
由此可见,尽管在应用SSM方式时可以一定程度提高TFT的特性,但在如果需要获得沟道宽度为4μm以以下的薄膜晶体管沟道的情况下,由于弯折部透过率下降导致沟道不良、甚至短路的情况,从而使良品率出现严重下滑,这样的问题是目前相关研究工作须努力突破的目标及方向。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何消除目前SSM方式中因易出现沟道短路而导致良品率过低的问题。
(二)技术方案
为解决上述技术问题,本发明提供一种薄膜晶体管,所述薄膜晶体管的沟道部结构为通过灰色调掩膜工艺以单隙缝方式来制得,所述沟道部结构的内侧弯折处的沟道宽度大于弯折部两侧的延伸部的沟道宽度。
其中,所述沟道部结构的所述内侧的弯折部处,其沟道宽度在3.0μm~6μm之间。
所述沟道部结构的所述弯折部两侧的延伸部处,其沟道宽度在2.0μm~3.5μm。
其中,所述沟道部结构的沟道宽度在2μm~6μm之间。
此外,本发明还提供一种用于制备薄膜晶体管的掩模板,对应所述沟道部结构的单缝隙的宽度,在内侧的弯折处的缝隙宽度大于弯折部两侧的延伸部的缝隙宽度。
其中,所述对应薄膜晶体管沟道部结构在所述内侧的弯折处的缝隙宽度在2.5μm~5μm。
其中,所述对应薄膜晶体管沟道部结构在所述弯折部两侧的延伸部处,其缝隙宽度形成在1.0μm~4μm之间。
其中,所述掩模板的所述对应薄膜晶体管沟道部结构的缝隙宽度形成在1μm~5μm之间。
此外,本发明还提供一种包括上述任一项薄膜晶体管的阵列基板。
此外,本发明还提供一种包括上述任一项薄膜晶体管的显示装置。
(三)有益效果
本发明技术方案相比现有SSM技术中为了保障一定TFT特性的前提下获得较高的通过率而采取降低沟道宽度的技术方案,针对其因部分区域沟道宽度较小而易导致的短沟道效应出现的问题,通过将薄膜晶体管沟道部内侧U型弯折部处的沟道宽度形成为与其余部分不同,具体而言,使其形成的更大一些,来消除短沟道效应,进一步地,可以消除现有技术中透过率不高、良品率不足、产率过低的问题。
附图说明
图1为现有技术中由SSM方式所制造的沟道部结构的示意图;
图2-4为根据本发明具体实施例所提供的沟道部结构的示意图。
具体实施方式
为使本发明的目的、内容和优点更加清楚,下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。
实施例1
为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本实施例提供一种用于制备薄膜晶体管的掩模板,如图2所示,所述掩模板的对应薄膜晶体管沟道部结构的单缝隙的宽度,在内侧的弯折部B区域,其缝隙宽度大于其弯折部两侧的延伸部A的缝隙宽度。
其中,所述掩模板的对应薄膜晶体管沟道部结构的缝隙宽度形成在1μm~5μm之间
其中,所述掩模板的对应薄膜晶体管沟道部结构在内侧的弯折部B区域,其缝隙宽度大于弯折部两侧的延伸部A区域的缝隙宽度。其中,掩模板的所述弯折部B区域,源极部分形成为沿着朝漏极方向的反向凹陷进去,如图2所示的B区域源极部分沿着朝漏极反方向凹陷,凹陷部分的形状为矩形,如图3所示B区域源极部分沿着朝漏极反方向凹陷,凹陷部分的形状为半圆形,从而使弯折部B区域的缝隙宽度变大。其中,凹陷部分的形状可以形成为矩形、半圆形、椭圆形等,但不限于此。
尤其是,如图2所示,单缝隙掩模板中对应薄膜晶体管结构沟道部分所述弯折部处B区域的缝隙宽度优选地形成在2.5μm~5μm之间。该部分区域的缝隙宽度尺寸选择,较之目前通常采用的尺寸要更大一些,由此在制作薄膜晶体管时,可以提高弯折部B区域的透光率规避此处常易出现的沟道不良问题。优选的,掩模板中所述弯折部B区域的尺寸选择界定于4μm以内最好,其原因在于,SSM方式可以实现更为精确的沟道,当薄膜晶体管的沟道宽度在4μm以内时TFT的特性会更好。
然而,对于所述掩模板的对应薄膜晶体管沟道部结构在所述弯折部两侧的延伸部A区域,其缝隙宽度形成在1.0μm~4μm之间。该部分区域的缝隙宽度尺寸选择可以根据产品性能的需要设定。
在使用单缝隙灰度掩模板(SSM)时,为了达到更精确地薄膜晶体管的沟道图案,同时避免薄膜晶体管沟道部内侧弯折部B区域的短路问题,提高掩模板的对应薄膜晶体管结构中内侧弯折部的光透过率,使内侧弯折部B区域的缝隙宽度大于弯折部两侧的延伸部的缝隙宽度,掩模板上整个对应薄膜晶体沟道结构的A区域和B区域的缝隙宽度在1.0μm~5μm之间,利用上述掩模板制得的薄膜晶体管的沟道达到最短的同时确保其沟道的良品率,解决了精确沟道图案的同时,使TFT特性能达到最优状态。
实施例2
为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本实施例提供一种用于制备薄膜晶体管的掩模板,如图4所示,所述掩模板的对应薄膜晶体管沟道部结构的单缝隙的宽度,在内侧的弯折部B区域,其缝隙宽度大于其弯折部两侧的延伸部A的缝隙宽度。
其中,所述掩模板的对应薄膜晶体管沟道部结构的缝隙宽度形成在1μm~5μm之间
其中,所述掩模板的对应薄膜晶体管沟道部结构在内侧的弯折部B区域,其缝隙宽度大于弯折部两侧的延伸部A区域的缝隙宽度。其中,掩模板的所述弯折部B区域,漏极部分形成为沿着朝源极方向的反向凹陷进去,凹陷部分的形状可以形成为半圆形或椭圆形,如图4所示,从而使弯折部B区域的缝隙宽度比弯折部两侧的延伸部A区域的宽度要大,这样可以提高弯折部B区域的光透过率。
尤其是,如图4所示,单缝隙掩模板中对应薄膜晶体管结构沟道部分所述弯折部处B区域的缝隙宽度优选地形成在2.5μm~5μm之间。该部分区域的缝隙宽度尺寸选择,较之目前通常采用的尺寸要更大一些,由此可以规避此处常易出现的短沟道效应及沟道不良问题。优选的,4μm以内最好,其原因在于,SSM方式可以实现更为精确的沟道,当沟道宽度在4μm以内时TFT的特性会更好。
然而,对于所述掩模板的对应薄膜晶体管沟道部结构在所述弯折部两侧的延伸部处A区域,其缝隙宽度形成在1.0μm~4μm之间。该部分区域的缝隙宽度尺寸选择可以根据产品性能的需要设定。
在使用单缝隙灰度掩模板(SSM)时,为了达到更精确地薄膜晶体管的沟道图案,同时避免薄膜晶体管沟道部内侧弯折部B区域的短路问题,提高掩模板内侧弯折部的光透过率,使内侧弯折部B区域的缝隙宽度大于弯折部两侧的延伸部的缝隙宽度,掩模板上整个沟道A区域和B区域的沟道宽度在1.0μm~5μm之间,利用上述掩模板制得的薄膜晶体管的沟道达到最短的同时确保其沟道的良品率,解决了精确沟道图案的同时,使TFT特性能达到最优状态。
实施例3
为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本实施例提供一种薄膜晶体管,所述薄膜晶体管的沟道部结构为通过灰色调掩膜工艺以单隙缝方式来制得,所述薄膜晶体管沟道部结构的宽度在2μm~6μm之间。
其中,在薄膜晶体管中所述沟道部结构在内侧的弯折部B处,其沟道宽度L2大于弯折部两侧的延伸部A处的沟道宽度L1。其中,所述弯折部B处,源极部分形成为沿着朝漏极方向的反向凹陷进去,凹陷部分的形状可以形成为矩形、半圆形、半椭圆形等,但不限于此,从而使弯折部B处的沟道宽度变大。其中,凹陷部分形成为矩形的情况如图2所示,凹陷部分形成为半椭圆形状的情况如图3所示。
尤其是,所述弯折部B处的沟道宽度L2优选地形成在3μm~6μm之间。该部分区域的沟道宽度尺寸通过上述实施例1灰度掩模板单缝隙方式制备而得,所述薄膜晶体管弯折部的宽度较其延伸部的宽度较大,相对应的淹没版B区域的透过率较高,这样可以使薄膜晶体管该处的沟道构图案更精确,从而可以避免沟道问题的发生。
然而,对于所述掩模板的沟道部结构在所述弯折部B处以外的位置,比如所述弯折部B两侧的延伸部A处,A处沟道宽度L1形成在2.0μm~2.5μm之间。该部分区域的沟道宽度尺寸选择可以根据产品性能的需要设定。
在使用单缝隙灰度掩模板(SSM)制备薄膜晶体管时,为了达到更精确地沟道图形,同时避免沟道部内侧弯折部B区域的短路问题,薄膜晶体管内侧弯折部B区域的沟道宽度大于弯折部两侧的延伸部A处的宽度,薄膜晶体管中沟道A区域和B区域的沟道宽度在2.0μm~6μm之间,从而使薄膜晶体管的沟道达到最短的同时确保其沟道的良品率,解决了精确沟道图案的同时,使TFT特性能达到最优状态。
实施例4
为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本实施例提供一种薄膜晶体管,所述薄膜晶体管的沟道部结构为通过灰色调掩膜工艺以单隙缝方式来制得,所述薄膜晶体管沟道部结构的宽度在2μm~6μm之间。
其中,在薄膜晶体管中所述沟道部结构在内侧的弯折部B处,其沟道宽度L2形成的大于弯折部两侧的延伸部A区域的沟道宽度L1。其中,所述弯折部B处,漏极部分形成为沿着朝源极方向的反向凹陷进去,凹陷部分的形状可以形成为矩形、半圆形、半椭圆形等,但不限于此,从而使弯折部B处的沟道宽度变大。其中,凹陷部分形成为半椭圆形状的情况如图4所示。
尤其是,所述弯折部B处的沟道宽度L2优选地形成在3μm~6μm之间。该部分区域的沟道宽度尺寸通过上述实施例2灰色淹没版单缝隙方式制备而得,所述薄膜晶体管弯折部的宽度较其延伸部的宽度较大,相对应的淹没版B区域的透过率较高,这样可以使薄膜晶体管该处的沟道构图案更精确,从而可以避免沟道问题的发生。
然而,对于所述掩模板的沟道部结构在所述弯折部B处以外的位置,比如所述弯折部B两侧的延伸部A处,A处其沟道宽度L1形成在2.0μm~2.5μm之间。该部分区域的沟道宽度尺寸选择可以根据产品性能的需要设定。
在使用单缝隙灰度掩模板(SSM)制备薄膜晶体管时,为了达到更精确地沟道图形,同时避免沟道部内侧弯折部B区域的短路问题,薄膜晶体管内侧弯折部B区域的沟道宽度大于弯折部两侧的延伸部A处的宽度,薄膜晶体管中沟道A区域和B区域的沟道宽度在2.0μm~6μm之间,从而使薄膜晶体管的沟道达到最短的同时确保其沟道的良品率,解决了精确沟道图案的同时,使TFT特性能达到最优状态。
实施例5
为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本实施例提供一种利用实施例1的掩模板来制备实施例3的薄膜晶体管的制备方法,该方法包括如下步骤:
步骤S1:在基板上形成导电性好的栅极金属层,通过第一次构图工艺在基板上形成栅线和栅电极;然后在栅线和栅极上方形成栅绝缘层;接下来在栅绝缘层上形成半导体有源层和源漏极金属层。
步骤S2:利用上述实施例1所提供的单缝隙灰度掩模板进行第二次构图工艺,对所述源漏极金属层和所述半导体有源层进行曝光、显影、连续刻蚀后以形成半导体硅岛、源极、漏极和薄膜晶体管沟道;具体地,首先在源漏极金属层上涂覆一层光刻胶,利用实施例1所提供的单缝隙灰度淹没板进行曝光,形成对应源极和漏极的区域为光刻胶完全保留区域,对应薄膜晶体管沟道区域为光刻胶部分保留区域,其他区域为光刻胶完全除去区域;其次,刻蚀掉光刻胶完全除去区域的源漏极金属层和半导体有源层,形成所述半导体硅岛;然后,通过灰化工艺去除薄膜晶体管沟道区域的光刻胶;最后,刻蚀薄膜晶体管沟道区域的源漏极金属层后,形成源极、漏极和薄膜晶体管沟道,形成薄膜晶体管。
步骤S3:然后通过公知构图工艺形成钝化层和像素电极层,最终形成薄膜晶体管阵列基板。
本实施例中层状结构的形成可以通过旋涂、沉积、溅镀等工艺进行;均可采用常规的光刻、印刷等构图工艺进行。
实施例6
为了消除目前SSM方式中因易出现短沟道效应而导致产率过低、良品率不足的问题,本实施例提供一种利用实施例2的掩模板来制备实施例4的薄膜晶体管的制备方法,该方法包括如下步骤:
步骤S1:在基板上形成导电性好的栅极金属层,通过第一次构图工艺在基板上形成栅线和栅电极;然后在栅线和栅极上方形成栅绝缘层;接下来在栅绝缘层上形成半导体层和源漏极金属层。
步骤S2:利用上述实施例2所提供的单缝隙灰度进行第二次构图工艺,对所述源漏极金属层和所述半导体有源层进行曝光、显影、连续刻蚀后以形成半导体硅岛、源极、漏极和薄膜晶体管沟道;具体地,首先在源漏极金属层上涂覆一层光刻胶,利用实施例1所提供的单缝隙灰度淹没板进行曝光,形成对应源极和漏极的区域为光刻胶完全保留区域,对应薄膜晶体管沟道区域为光刻胶部分保留区域,其他区域为光刻胶完全除去区域;其次,刻蚀掉光刻胶完全除去区域的源漏极金属层和半导体有源层,形成所述半导体硅岛;然后,通过灰化工艺去除薄膜晶体管沟道区域的光刻胶;最后,刻蚀薄膜晶体管沟道区域的源漏极金属层后,形成源极、漏极和薄膜晶体管沟道,形成薄膜晶体管。
步骤S3:然后通过公知构图工艺形成钝化层和像素电极层,最终形成薄膜晶体管阵列基板。
本实施例中层状结构的形成可以通过旋涂、沉积、溅镀等工艺进行;均可采用常规的光刻、印刷等构图工艺进行。
根据上述内容,通过将薄膜晶体管沟道部内侧的U型弯折部处的沟道宽度形成为与其余部分不同,具体而言,使其形成的更大一些,从而既可以避免现有的SSM技术中因为该区域沟道宽度较小而导致的短沟道效应,也可以获得SSM方式所特有的通过率高的优点,由该方案制备的TFT沟道部,可以消除良品率不足、产率过低的问题。
同时,本发明还提供一种阵列基板,所述阵列基板包括上述实施例中任一种的薄膜晶体管。
此外,本发明还提供一种显示装置,所述显示装置包括上述实施例中任一种的薄膜晶体管,所述显示装置可以为:液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和变形,这些改进和变形也应视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管,其特征在于,所述薄膜晶体管的沟道部结构为通过灰色调掩膜工艺以单缝隙方式来制得,所述沟道部结构的内侧弯折处的沟道宽度大于弯折部两侧的延伸部的沟道宽度。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述沟道部结构的所述内侧的弯折部处,其沟道宽度在3.0μm~6μm之间。
3.根据权利要求1所述的薄膜晶体管,其特征在于,所述沟道部结构的所述弯折部两侧的延伸部处,其沟道宽度在2.0μm~3.5μm。
4.根据权利要求1所述的薄膜晶体管,其特征在于,所述沟道部结构的沟道宽度在2μm~6μm之间。
5.一种制备薄膜晶体管的掩模板,其特征在于,对应薄膜晶体管沟道部结构的单缝隙的宽度,在内侧的弯折处的缝隙宽度大于弯折部两侧的延伸部的缝隙宽度。
6.根据权利要求5所述的用于制备薄膜晶体管的掩模板,其特征在于,所述对应薄膜晶体管沟道部结构在所述内侧的弯折处的缝隙宽度宽度在2.5μm~5μm。
7.根据权利要求5所述的用于制备薄膜晶体管的掩模板,其特征在于,所述对应薄膜晶体管沟道部结构在所述弯折部两侧的延伸部处,其缝隙宽度形成在1.0μm~4μm之间。
8.根据权利要求5所述的用于制备薄膜晶体管的掩模板,其特征在于,所述掩模板的所述对应薄膜晶体管沟道部结构的缝隙宽度形成在1μm~5μm之间。
9.一种包括如权利要求1-4任一项所述薄膜晶体管的阵列基板。
10.一种包括如权利要求1-4任一项所述薄膜晶体管的显示装置。
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