WO2017206659A1 - Tft阵列基板及其制备方法、显示装置 - Google Patents

Tft阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2017206659A1
WO2017206659A1 PCT/CN2017/083011 CN2017083011W WO2017206659A1 WO 2017206659 A1 WO2017206659 A1 WO 2017206659A1 CN 2017083011 W CN2017083011 W CN 2017083011W WO 2017206659 A1 WO2017206659 A1 WO 2017206659A1
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Prior art keywords
drain
gate
array substrate
tft array
insulating layer
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PCT/CN2017/083011
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English (en)
French (fr)
Inventor
顾可可
杨妮
胡伟
李少茹
刘信
齐智坚
侯宇松
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/563,587 priority Critical patent/US10510783B2/en
Publication of WO2017206659A1 publication Critical patent/WO2017206659A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
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    • G—PHYSICS
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    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a TFT array substrate and a method of fabricating the same, and a corresponding display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the width-to-length ratio W/L of the TFT plays a large role in the performance of the TFT, where W is the channel width and refers to the extension distance from the start point to the end point of the channel, and L is the channel length and is Refers to the distance between the source and drain of the TFT.
  • W is the channel width and refers to the extension distance from the start point to the end point of the channel
  • L is the channel length and is Refers to the distance between the source and drain of the TFT.
  • the larger the aspect ratio of the TFT the better the performance, and the potential of the pixel electrode can more easily reach the required value.
  • the increase in the TFT aspect ratio can be achieved by increasing the channel width W or decreasing the channel length L.
  • an increase in the channel width W also increases the size of the TFT and reduces the aperture ratio.
  • the reduction in the channel length L can increase the aspect ratio of the TFT and reduce the size of the TFT, and also increases the aperture ratio. Therefore, reducing the channel length L is an optimum choice for increasing the aspect ratio of the TFT.
  • the channel length L is reduced to achieve a narrow channel design of the array substrate while increasing the aperture ratio of the array substrate.
  • a TFT array substrate includes a carrier substrate, gate lines and data lines disposed on the carrier substrate, pixel regions defined by the gate lines and the data lines, and thin film transistors, pixel electrodes, and active layers disposed in the pixel regions.
  • the gate of the thin film transistor is connected to the gate line
  • the source is The data lines are connected and the drain is connected to the pixel electrodes.
  • an insulating layer is further formed over the source of the thin film transistor, and a drain trench is formed in the insulating layer. Further, a drain of the thin film transistor is located in the drain trench and is connected to the source through an active layer.
  • the TFT array substrate has a bottom gate structure, the insulating layer includes a passivation layer, and the pixel electrode is directly formed over the drain of the thin film transistor.
  • a common electrode line is further disposed on the TFT array substrate.
  • each common electrode line is used as a storage capacitor.
  • each common electrode line is used to generate an electric field together with the pixel electrode to deflect the liquid crystal molecules.
  • a common electrode insulating layer is further provided over the common electrode line, and a common electrode via hole is further formed in such a common electrode insulating layer, wherein the common electrode via hole is filled with a drain material.
  • a via connection line is directly formed over the drain material.
  • the common electrode via and the drain trench are formed in the same patterning process, the drain material and the drain are formed in the same patterning process, and the pixel electrode is connected to the via.
  • the line is formed in a patterning process.
  • the TFT array substrate has a top gate structure, and the insulating layer includes an insulating layer between the source and the drain of the thin film transistor.
  • a method of fabricating a TFT array substrate comprises the following steps: Step 1. Forming gate lines and gates, a gate insulating layer, an active layer, and data lines and sources layer by layer on the carrier substrate; Step 2. Forming gate lines and gates, gates a thin film of an insulating layer is further deposited on the insulating layer, the active layer, and the carrier substrate of the data line and the source, and a drain trench is formed in the insulating layer film by a patterning process; and step 3, in which the drain trench is formed A drain metal thin film is further deposited on the carrier substrate, and a drain is formed by a patterning process, and the drain is connected to the source through the active layer.
  • Step 1 above that is, the steps of forming a gate line and a gate, a gate insulating layer, an active layer, and a data line and a source layer on a carrier substrate, specifically comprising the following substeps: depositing a gate metal layer on the carrier substrate, And forming a gate line and a gate by a patterning process, the gate line is connected to the gate; further depositing a gate insulating layer film on the carrier substrate on which the gate line and the gate are formed to form a gate insulating layer; and forming a gate insulating layer An active layer film and a data metal layer film are further deposited on the carrier substrate of the layer, and an active layer, a data line and a source are respectively formed by a patterning process, wherein the data line and the source are connected.
  • the above preparation method further includes: forming a common electrode line while forming a gate line and a gate by a patterning process.
  • the above preparation method further includes: forming a common electrode via in the insulating layer film while forming a drain trench by a patterning process, the common electrode via being located above the common electrode line.
  • the above preparation method further includes: filling the drain material in the common electrode via while forming the drain by the patterning process.
  • the above preparation method further includes: further depositing a pixel electrode metal film on the carrier substrate on which the drain is formed, and forming a pixel electrode by a patterning process, the pixel electrode being directly connected to the drain.
  • the above preparation method further includes forming a via connection line while forming a pixel electrode by a patterning process.
  • a third aspect of the present disclosure another method of fabricating a TFT array substrate is also provided.
  • the preparation method comprises the following steps: Step 21, forming an active layer, a data line and a source on the carrier substrate respectively; Step 22, further depositing an insulating layer film on the carrier substrate on which the active layer, the data line and the source are formed And forming a drain trench in the insulating layer film by a patterning process; and step 23, further depositing a drain metal film on the carrier substrate on which the drain trench is formed, and forming a drain by a patterning process, A drain is connected to the source through the active layer.
  • the above preparation method further includes: Step 24, further forming a gate insulating layer, a gate electrode, a passivation layer, and a pixel electrode on the carrier substrate on which the drain is formed.
  • a display device comprising the TFT array substrate of any of the above embodiments.
  • FIG. 1a is a plan view of a bottom gate structure TFT array substrate in accordance with an embodiment of the present disclosure
  • Figure 1b is a cross-sectional view of the TFT array substrate shown in Figure 1a taken along line A-A;
  • 1c is a cross-sectional view of a top gate structure TFT array substrate in accordance with an embodiment of the present disclosure
  • 1d is a cross-sectional view of another top gate structure TFT array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2a is a plan view of a gate line and a gate, a gate insulating layer, an active layer, and data lines and sources on a bottom gate structure TFT array substrate, in accordance with an embodiment of the present disclosure
  • Figure 2b is a cross-sectional view of the TFT array substrate shown in Figure 2a taken along line B-B;
  • FIG 3 is a cross-sectional view of a drain on a bottom gate structure TFT array substrate in accordance with an embodiment of the present disclosure.
  • the TFT array substrate provided by the embodiments of the present disclosure, a method for fabricating the same, and a corresponding display device are described in detail below with reference to the accompanying drawings.
  • a TFT array substrate includes a carrier substrate 101, gate lines 102 and data lines 103 interleaved on the carrier substrate 101, and pixels defined by the gate lines 102 and the data lines 103. a region, and a thin film transistor, a pixel electrode 104, and an active layer 106 disposed in the pixel region.
  • the gate 21 of the thin film transistor is connected to the gate line 102
  • the source 22 is connected to the data line 103
  • the drain 23 is connected to the pixel electrode 104.
  • a passivation layer (also referred to herein as an insulating layer) 107 is formed over the source electrode 22, and is fabricated in the passivation layer 107.
  • a drain trench 24 is located in the drain trench 24 and is connected to the source 22 through the active layer 106.
  • the source and drain are located in the same layer and are formed in one patterning process. Therefore, according to such a typical TFT array substrate structure and its preparation process, the reduction of the channel length L easily causes a risk of short-circuiting of the source and the drain, and the technical implementation is also complicated.
  • the drain 23 is located in the drain layer 107. Inside the pole trench 24. Thus, the drain 23 and the source 22 are not in the same layer, and they are spaced apart by the passivation layer 107 therebetween. Therefore, the length L of the TFT channel can be reduced, and the risk of short-circuiting of the source 22 and the drain 23 does not occur. In this way, a narrow channel design of the array substrate can be achieved. Moreover, such a narrow channel design can increase the aperture ratio of the TFT array substrate while ensuring the performance of the TFT.
  • the insulating layer between the source 21 and the drain 22 may be selected as a passivation layer. As shown in FIGS. 1c and 1d, in the embodiment of the TFT array substrate having the top gate structure, the insulating layer between the source 21 and the drain 22 needs to be separately fabricated.
  • the TFT array substrate includes, in order from bottom to top, a carrier substrate 201, an active layer 202 formed on the carrier substrate 201, and a data line and a source 22 formed above the active layer 202.
  • the pixel electrode formed on the passivation layer is not shown in FIG. 1c.
  • FIG. 1d The structure shown in Figure 1d is similar to Figure 1c. The difference is that the data line and the source 22 are first formed on the carrier substrate 201, then the edge layer 202 is formed, and the insulating layer 203 is formed over the active layer 202. Finally, a drain 23 is formed in the insulating layer 203. The structure thereafter is the same as that shown in Fig. 1c and will not be described again here.
  • the drain 23 and the source 22 are not located in the same layer, and they are spaced apart by the insulating layer 203 therebetween. Therefore, the length L of the TFT channel can be reduced and the risk of short-circuiting of the source 22 and the drain 23 does not occur. In this way, a narrow channel design of the array substrate can be achieved.
  • suitable channel shapes include a plurality of different channel shapes, such as U-shaped, double U-shaped, L-shaped, semi-circular or inline, etc. .
  • the pixel electrode 104 can also be formed directly above the drain 23.
  • the drain of the TFT needs to be connected to the pixel electrode through a via.
  • this metal lead seriously affects the aperture ratio. If the pixel electrode 104 is directly formed over the drain 23, the drain 23 and the pixel electrode 104 are no longer required to be connected by via holes. Instead, connect directly to the opposite. This avoids the fabrication of a metal lead having a large size, so that the aperture ratio of the TFT array substrate can be further increased.
  • a plurality of juxtaposed common electrode lines 301 are further provided on the bottom gate structure TFT array substrate. These common electrode lines 301 need to be bridged through the common electrode vias in some cases. However, the greater the depth of the vias and the greater the number, the easier it is to produce panel strain on the display panel.
  • the common electrode via 302 may be formed in the common electrode insulating layer above the common electrode line 301.
  • the common electrode insulating layer may be the passivation layer 107, but is not limited to the passivation layer 107.
  • the common electrode insulating layer may be any insulating layer that insulates the respective parallel common electrode lines from each other.
  • the drain material 303 may be filled in the common electrode via 302.
  • the hole depth of the common electrode via 302 is reduced, and the probability of causing undesirable problems such as panel strain on the surface of the display panel is reduced.
  • the drain material 303 may even fill the entire common electrode via 302 and connect different common electrode vias 302 to each other.
  • the via connection line 304 can be formed directly over the drain material 303 regardless of whether the drain material 303 has been connected to a different common electrode via 302.
  • the via connection 304 can connect different common electrode vias.
  • the via connection 304 can reinforce the connection when the drain material 303 has been connected to a different common electrode via.
  • the common electrode via 302 may be formed in the same patterning process as the drain trench 24.
  • drain material 303 can be formed in the same patterning process as drain 24.
  • the via connection line 304 can be formed with the pixel electrode 104 in one patterning process. In this way, the simultaneous formation of one patterning process can reduce the number of patterning processes and save costs.
  • embodiments of the present disclosure also provide a method of fabricating a TFT array substrate for a bottom gate structure.
  • the preparation method specifically includes the following steps, and specifically refers to FIGS. 2a, 2b, 3, and 1a and 1b.
  • Step 1 Form the gate line 102 and the gate 21 layer by layer on the carrier substrate 101, and the gate insulation Layer 105, active layer 106, and data line 103 and source 22.
  • the step 1 specifically includes the following sub-steps: first, a gate metal layer is deposited on the carrier substrate 101, and a gate line 102 and a gate electrode 21 are formed by a patterning process, the gate line 102 and the gate electrode.
  • a gate insulating layer film is further deposited on the carrier substrate 101 on which the gate line 102 and the gate electrode 21 are formed to form the gate insulating layer 105; and finally, further deposited on the carrier substrate 101 on which the gate insulating layer 105 is formed
  • the active layer film and the data metal layer film are formed, and the active layer 106, the data line 103, and the source 22 are separately formed by a patterning process. It should be noted that the drain 23 is not formed at this time, and the data line 103 and the source 22 are connected.
  • the drain 23 is not formed temporarily, and preparation for the subsequent preparation of the drain 23 is made.
  • the above preparation method further includes: forming the common electrode line 301 on the TFT array substrate while forming the gate line 102 and the gate electrode 22 by the patterning process in the step 1. Cost can be saved by forming the gate line 102, the gate electrode 21, and the common electrode line 301 in one patterning process.
  • the common electrode line 301 may be made of an indium tin oxide (ITO) material, and it is not necessary to use a gate metal material.
  • Step 2 further depositing an insulating layer film on the carrier substrate 101 on which the gate line 102 and the gate electrode 21, the gate insulating layer 105, the active layer 106, and the data line 103 and the source 22 are formed, and by patterning the film on the insulating layer A drain trench 23 and a passivation layer 107 are formed in the middle.
  • the above preparation method further includes: forming a drain trench 24 and an insulating layer 107 by a patterning process in step 2, forming a common electrode via 302 in the insulating layer film, wherein the common electrode The via 302 is located above the common electrode line 301. Cost can be saved by forming the drain trench 24 and the common electrode via 302 in one patterning process.
  • Step 3 Further depositing a drain metal film on the carrier substrate 101 on which the drain trench 24 and the insulating layer 107 are formed, and forming the drain 23 by a patterning process.
  • the drain 23 is connected to the source 22 through the active layer 106;
  • the preparation method further includes: filling the drain electrode 23 in the common electrode via 302 while forming the drain 23 by the patterning process in the above step 3. Cost can be saved by forming the drain 23 and the drain material 303 in one patterning process.
  • the above preparation method may further include the following step 4: further depositing a pixel electrode metal film on the carrier substrate 101 on which the drain electrode 23 is formed, and forming a pattern by a patterning process
  • the pixel electrode 104 is in which the pixel electrode 104 is directly connected to the drain electrode 23.
  • the above preparation method further includes: forming a via connection line 304 while forming the pixel electrode 104 by a patterning process in step 4. Cost can be saved by forming the pixel electrode 104 and the via connection line 304 in one patterning process.
  • the formed TFT array substrate structure is as shown in Figs. 1a and 1b.
  • embodiments of the present disclosure also provide a method of fabricating a TFT array substrate for a top gate structure.
  • the preparation method specifically includes the following steps.
  • Step 21 Form an active layer, a data line, and a source on the carrier substrate. It is to be noted that, in step 21, the order in which the active layers are formed and the order in which the data lines and sources are made can be interchanged.
  • Step 22 Further depositing an insulating layer film on the carrier substrate on which the active layer, the data line and the source are formed, and forming a drain trench in the insulating layer film by a patterning process.
  • Step 23 Further depositing a drain metal film on the carrier substrate on which the drain trench is formed, and forming a drain by a patterning process, wherein the drain is connected to the source through the active layer.
  • the above preparation method further includes: further forming a gate insulating layer, a gate electrode, a passivation layer, and a pixel electrode on the carrier substrate on which the drain is formed, in step 24 subsequent to step 23.
  • the formed TFT array substrate structure is as shown in Fig. 1c or Fig. 1d.
  • embodiments of the present disclosure also provide a display device.
  • the display device includes the TFT array substrate provided by any of the above embodiments.
  • the display device can achieve the same technical effects as the TFT array substrate described above, and details are not described herein again.

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Abstract

本公开涉及显示技术领域，并且公开了薄膜晶体管（TFT）阵列基板及其制备方法，以及对应的显示装置，以便实现阵列基板的窄沟道设计。该TFT阵列基板包括：承载基底（101），在承载基底（101）上交叉设置的栅线（102）和数据线（103），由栅线（102）和数据线（103）限定的像素区域，以及设置在像素区域内的薄膜晶体管、像素电极（104）和有源层（106）。具体地，薄膜晶体管的栅极（21）与栅线（102）连接、源极（22）与数据线（103）连接而漏极（23）与像素电极（104）连接。进一步地，在薄膜晶体管的源极（22）的上方形成有绝缘层（107），并且该绝缘层（107）中制作有漏极沟槽（24）。此外，薄膜晶体管的漏极（23）位于该漏极沟槽（24）中并且通过有源层（106）与源极（22）相连。本公开提供的TFT阵列基板适用于制作显示装置。

Description

TFT阵列基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及TFT阵列基板及其制备方法，以及对应的显示装置。
背景技术
在薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)行业中，主要通过像素电极和公共电极之间产生的电场来控制液晶分子的转动，以达到所要显示画面的效果。像素电极的电位能否达到要求值，主要是由TFT的开启电流Ion来决定。
在相同工艺条件下，TFT的宽长比W/L对TFT的性能起很大作用，其中W为沟道宽度并且是指沟道的起点至终点的延伸距离，而L为沟道长度并且是指TFT的源极和漏极之间的距离。在其他条件不变的情况下，TFT的宽长比越大，其性能就越好，并且像素电极的电位就能够更容易地达到要求值。TFT宽长比的增加可以通过增加沟道宽度W或减小沟道长度L来实现。
然而，沟道宽度W的增加还会增大TFT的尺寸，并且减小开口率。沟道长度L的减小既能增大TFT的宽长比又能减小TFT的尺寸，而且还增大开口率。因此，减小沟道长度L是用于增加TFT宽长比的最佳选择。
发明内容
本公开的目的在于提供一种TFT阵列基板及其制备方法，以及对应的显示装置，用于至少消除或者减缓以上提及的问题中的一个或多个，特别地在不引起短路风险并且保证TFT性能的前提下，减小沟道长度L，以实现阵列基板的窄沟道设计，而同时使阵列基板的开口率增大。
根据本公开的第一方面，提供了一种TFT阵列基板。该TFT阵列基板包括：承载基底，在承载基底上交叉设置的栅线和数据线，由栅线和数据线限定的像素区域，以及设置在像素区域内的薄膜晶体管、像素电极和有源层。具体地，薄膜晶体管的栅极与栅线连接、源极与 数据线连接而漏极与像素电极连接。进一步地，在薄膜晶体管的源极上方还形成有绝缘层，并且该绝缘层中制作有漏极沟槽。此外，薄膜晶体管的漏极位于该漏极沟槽中并且通过有源层与源极相连。
在上述TFT阵列基板的一个实施方案中，TFT阵列基板具有底栅结构，绝缘层包括钝化层，并且像素电极直接形成在薄膜晶体管的漏极上方。
根据底栅结构的实施方案，不论是在TN模式(twisted nematic liquid crystal mode，其中液晶分子扭曲角为90度的液晶模式)中，还是在ADS模式(Advanced Super Dimension Switch，又称为高级超维场转换技术，其中利用同一平面内的电极产生的横向电场引起液晶的偏转以实现图像显示的模式)中，TFT阵列基板上还设有公共电极线。具体地，在TN模式下，各个公共电极线用作存储电容。相应地，在ADS模式下，各个公共电极线用于与像素电极一起产生电场以使液晶分子发生偏转。然而，在TN模式和ADS模式下，不同行的公共电极线都需要经由过孔进行连接。因此，在本公开中，在公共电极线上方还设有公共电极绝缘层，并且这样的公共电极绝缘层中进一步制作有公共电极过孔，其中利用漏极材料来填充该公共电极过孔。
在上述底栅结构的TFT阵列基板中，在漏极材料上方直接形成过孔连接线。
此外，在底栅结构的TFT阵列基板中，公共电极过孔与漏极沟槽在同一次构图工艺中形成，漏极材料与漏极在同一次构图工艺中形成，并且像素电极与过孔连接线在一次构图工艺中形成。
在上述TFT阵列基板的另一个实施方案中，TFT阵列基板具有顶栅结构，并且绝缘层包括薄膜晶体管的源极和漏极之间的绝缘层。
根据本公开的第二方面，提供了一种用于TFT阵列基板的制备方法。该制备方法包括以下步骤：步骤1、在承载基底上逐层形成栅线和栅极、栅绝缘层、有源层以及数据线和源极；步骤2、在形成有栅线和栅极、栅绝缘层、有源层以及数据线和源极的承载基底上进一步沉积绝缘层薄膜，并且通过构图工艺在该绝缘层薄膜中形成漏极沟槽；以及步骤3、在形成有漏极沟槽的承载基板上进一步沉积漏极金属薄膜，并且通过构图工艺形成漏极，所述漏极通过所述有源层与所述源极相连。
上述步骤1，即，在承载基底上逐层形成栅线和栅极、栅绝缘层、有源层以及数据线和源极的步骤，具体包括以下子步骤：在承载基底上沉积栅金属层，并且通过构图工艺形成栅线和栅极，所述栅线和栅极相连；在形成有栅线和栅极的承载基底上进一步沉积栅绝缘层薄膜以形成栅绝缘层；以及在形成有栅绝缘层的承载基底上进一步沉积有源层薄膜和数据金属层薄膜，并且通过构图工艺分别形成有源层、数据线和源极，其中所述数据线和源极相连。
根据具体实施例，上述制备方法还包括：在通过构图工艺形成栅线和栅极的同时，形成公共电极线。
根据具体实施例，上述制备方法还包括：在通过构图工艺形成漏极沟槽的同时，在绝缘层薄膜中形成公共电极过孔，所述公共电极过孔位于公共电极线上方。
根据具体实施例，上述制备方法还包括：在通过构图工艺形成漏极的同时，在公共电极过孔中填充漏极材料。
此外，根据具体实施例，上述制备方法还包括：在形成有漏极的承载基板上进一步沉积像素电极金属薄膜，并且通过构图工艺形成像素电极，所述像素电极与所述漏极直接相连。
根据具体实施例，上述制备方法还包括：在通过构图工艺形成像素电极的同时，形成过孔连接线。
根据本公开的第三方面，还提供了另一种用于TFT阵列基板的制备方法。该制备方法包括以下步骤：步骤21、在承载基底上分别形成有源层、数据线和源极；步骤22、在形成有有源层、数据线和源极的承载基底上进一步沉积绝缘层薄膜，并且通过构图工艺在所述绝缘层薄膜中形成漏极沟槽；以及步骤23、在形成有漏极沟槽的承载基板上进一步沉积漏极金属薄膜，并且通过构图工艺形成漏极，所述漏极通过所述有源层与所述源极相连。
根据具体实施例，上述制备方法还包括：步骤24、在形成有漏极的承载基板上进一步分别形成栅绝缘层、栅极、钝化层和像素电极。
根据本公开的第四方面，提供了一种显示装置，包括上述任一个实施例所述的TFT阵列基板。
附图说明
此处要说明的附图是用来提供对本公开的进一步理解，并且构成本公开的一部分。本公开的示意性实施例及其说明用于解释本公开，而并不构成对本公开的不当限定。在附图中：
图1a为根据本公开的实施例的底栅结构TFT阵列基板的平面示意图；
图1b为图1a所示的TFT阵列基板沿A-A线的剖视图；
图1c为根据本公开的实施例的一种顶栅结构TFT阵列基板的剖视图；
图1d为根据本公开的实施例的另一种顶栅结构TFT阵列基板的剖视图；
图2a为根据本公开的实施例的底栅结构TFT阵列基板上的栅线和栅极、栅绝缘层、有源层以及数据线和源极的平面示意图；
图2b为图2a所示的TFT阵列基板沿B-B线的剖视图；以及
图3为根据本公开的实施例的底栅结构TFT阵列基板上的漏极的剖视图。
具体实施方式
为便于理解，下面结合说明书附图，对本公开的实施例提供的TFT阵列基板及其制备方法，以及对应的显示装置进行详细描述。
参照图1a和图1b，根据本公开的实施例的TFT阵列基板包括：承载基底101，在承载基底101上交叉设置的栅线102和数据线103，由栅线102和数据线103限定的像素区域，以及设置在像素区域内的薄膜晶体管、像素电极104和有源层106。具体地，薄膜晶体管的栅极21与栅线102连接、源极22与数据线103连接而漏极23与像素电极104连接。另外，在图1a和图1b所示的具有底栅结构的实施例中，在源极22上方形成有钝化层(在本文中又称为绝缘层)107，并且该钝化层107中制作有漏极沟槽24。此外，漏极23位于该漏极沟槽24中，并且通过有源层106与源极22相连。
典型地，在TFT阵列基板中，源极和漏极位于同一层并且在一次构图工艺中形成。因此，按照这样的典型TFT阵列基板结构及其制备工艺，沟道长度L的减小容易引起源极和漏极短路的风险，而且技术实现也较复杂。然而，在本实施例中，漏极23位于钝化层107中的漏 极沟槽24内。这样，漏极23和源极22不位于同一层，并且它们二者之间通过钝化层107间隔开。因此，可以将TFT沟道的长度L缩小，并且不会发生源极22和漏极23短路的风险。以这样的方式，能够实现阵列基板的窄沟道设计。而且，这样的窄沟道设计能够在保证TFT性能的前提下增大TFT阵列基板的开口率。
在具有底栅结构的TFT阵列基板的实施例中，源极21和漏极22之间的绝缘层可以选取为钝化层。如图1c和1d所示，在具有顶栅结构的TFT阵列基板的实施例中，源极21和漏极22之间的绝缘层需要单独制作。
在图1c所示的结构中，TFT阵列基板由下至上依次包括：承载基板201，制作在承载基板201上的有源层202，形成在有源层202上方的数据线和源极22，形成在源极22上方的绝缘层203，形成在绝缘层203中的漏极23，形成在漏极上方的栅绝缘层204，形成在栅绝缘层204上的栅线和栅极21，以及形成在栅线和栅极21上方的钝化层205。另外，在图1c中未示出形成在钝化层上的像素电极。
图1d所示的结构与图1c相似。所不同的是，首先在承载基板201上形成数据线和源极22，之后再形成有缘层202，并且在有源层202上方形成绝缘层203。最后，在绝缘层203中形成漏极23。此后的结构与图1c所示相同，此处不再赘述。
同样地，在具有顶栅结构的TFT阵列基板中，漏极23和源极22不位于同一层，并且它们二者之间通过绝缘层203间隔开。因此，可以缩小TFT沟道的长度L并且不会发生源极22和漏极23短路的风险。这样，能够实现阵列基板的窄沟道设计。
在上述底栅和顶栅结构TFT阵列基板的窄沟道设计中，适用的沟道形状包括多种不同的沟道形状，诸如U形、双U形、L形、半圆形或一字形等。
作为对上述底栅结构实施例的一种改进，还可以在漏极23的上方直接形成像素电极104。在典型的TFT阵列基板结构中，TFT的漏极需要通过过孔与像素电极相连。为此目的，需要在过孔下方制备较大尺寸的漏极金属引线，以保证漏极与像素电极之间的连接的可靠性。然而，该金属引线严重影响了开口率。如果在漏极23上方直接形成像素电极104，则漏极23和像素电极104就不再需要借助过孔进行连接， 而是相反地直接连接。这避免了尺寸较大的金属引线的制作，从而能够进一步增大TFT阵列基板的开口率。
此外，在上述底栅结构TFT阵列基板上还设有多条并列的公共电极线301。这些公共电极线301在某些情况下需要通过公共电极过孔进行桥接。然而，过孔的深度越大、数量越多，就越容易在显示面板上产生面板应变(即，panel strain)。作为对上述实施例的一种改进，可以在上述公共电极线301上方的公共电极绝缘层中制作公共电极过孔302。在本实施例中，该公共电极绝缘层可以为钝化层107，但是并不限于钝化层107。该公共电极绝缘层可以为任何绝缘层，其使得各个平行的公共电极线彼此绝缘。在制作公共电极过孔302之后，可以在公共电极过孔302中填充漏极材料303。这样，通过使用漏极材料303填充公共电极过孔302，减小了公共电极过孔302的孔深，并且降低了显示面板表面产生面板应变等不良问题的几率。
在一些情况下，漏极材料303甚至可以充满整个公共电极过孔302，并且使不同的公共电极过孔302彼此连接。作为改进，不论漏极材料303是否已经连接了不同的公共电极过孔302，都可以在漏极材料303上方再直接形成过孔连接线304。当漏极材料303仅填充公共电极过孔302的一部分时，过孔连接线304可以连接不同的公共电极过孔。当漏极材料303已经连接了不同的公共电极过孔时，过孔连接线304可以加强该连接。
需要说明的是，在本文中通过填充漏极材料303减小过孔深度的做法并不局限于公共电极过孔302。在其他类似情况下，其它类型的过孔也可以适用。
另外，在根据本公开的实施例的底栅结构TFT阵列基板中，公共电极过孔302可以与漏极沟槽24在同一次构图工艺中形成。此外，漏极材料303可以与漏极24在同一次构图工艺中形成。再进一步地，过孔连接线304可以与像素电极104在一次构图工艺中形成。这样，通过一次构图工艺的同时形成可以减少构图工艺的次数，并且节省成本。
除上述TFT阵列基板之外，本公开的实施例还提供了一种用于底栅结构TFT阵列基板的制备方法。该制备方法具体包括下面的步骤，并且具体地参照图2a、图2b、图3以及图1a和图1b所示。
步骤1、在承载基底101上逐层形成栅线102和栅极21、栅绝缘 层105、有源层106以及数据线103和源极22。如图2a和2b所示，该步骤1具体包括以下子步骤：首先，在承载基底101上沉积栅金属层，并且通过构图工艺形成栅线102和栅极21，所述栅线102和栅极21相连；其次，在形成有栅线102和栅极21的承载基底101上进一步沉积栅绝缘层薄膜以形成栅绝缘层105；并且最后，在形成有栅绝缘层105的承载基底101上进一步沉积有源层薄膜和数据金属层薄膜，并且通过构图工艺分别形成有源层106、数据线103和源极22。需要指出的是，此时并没有形成漏极23，而且数据线103和源极22相连。
在上述步骤1中，暂不形成漏极23，并且为后续漏极23的制备做好准备工作。
根据具体实施例，上述制备方法还包括：在所述步骤1中通过构图工艺形成栅线102和栅极22的同时，在TFT阵列基板上形成公共电极线301。通过在一次构图工艺中形成栅线102、栅极21和公共电极线301，可以节省成本。此外，公共电极线301可以采用氧化铟锡(ITO)材料制成，并且不必使用栅金属材料。
步骤2、在形成有栅线102和栅极21、栅绝缘层105、有源层106以及数据线103和源极22的承载基底101上进一步沉积绝缘层薄膜，并且通过构图工艺在绝缘层薄膜中形成漏极沟槽23和钝化层107。进一步地，根据具体实施例，上述制备方法还包括：在步骤2中通过构图工艺形成漏极沟槽24和绝缘层107的同时，在该绝缘层薄膜中形成公共电极过孔302，其中公共电极过孔302位于公共电极线301上方。通过在一次构图工艺中形成漏极沟槽24和公共电极过孔302，可以节省成本。
步骤3、在形成有漏极沟槽24和绝缘层107的承载基板101上进一步沉积漏极金属薄膜，并且通过构图工艺形漏极23。此外，漏极23通过有源层106与源极22相连；
具体地，如图3所示，这样的制备方法还包括：在上述步骤3中通过构图工艺形成漏极23的同时，在公共电极过孔302中填充漏极材料303。通过在一次构图工艺中形成漏极23和漏极材料303，可以节省成本。
此外，上述制备方法还可以包括以下步骤4：在形成有漏极23的承载基板101上进一步沉积像素电极金属薄膜，并且通过构图工艺形 成像素电极104，其中像素电极104与漏极23直接相连。
根据具体实施例，上述制备方法还包括：在步骤4中通过构图工艺形成像素电极104的同时，形成过孔连接线304。通过在一次构图工艺中形成像素电极104和过孔连接线304，可以节省成本。
在上述步骤4之后，所形成的TFT阵列基板结构如图1a和1b所示。
此外，本公开的实施例还提供了一种用于顶栅结构TFT阵列基板的制备方法。该制备方法具体包括下面的步骤。
步骤21、在承载基底上分别形成有源层、数据线和源极。要指出的是，在步骤21中，有源层的制作顺序与数据线和源极的制作顺序可以互换。
步骤22、在形成有有源层、数据线和源极的承载基底上进一步沉积绝缘层薄膜，并且通过构图工艺在绝缘层薄膜中形成漏极沟槽。
步骤23、在形成有漏极沟槽的承载基板上进一步沉积漏极金属薄膜，并且通过构图工艺形成漏极，其中漏极通过有源层与源极相连。
根据具体实施例，上述制备方法还包括：在步骤23之后的步骤24、在形成有漏极的承载基板上进一步分别形成栅绝缘层、栅极、钝化层和像素电极。
在步骤24之后，所形成的TFT阵列基板结构如图1c或图1d所示。
最后，本公开的实施例还提供了一种显示装置。该显示装置包括由上述任一个实施例提供的TFT阵列基板。该显示装置能够达到与上述TFT阵列基板相同的技术效果，此处不再赘述。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但是本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可以容易想到各种变化或替换，并且其都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
附图标记列表：
101、201-承载基底  102-栅线
103-数据线         104-像素电极
105、204-栅绝缘层  106、202-有源层
107、205-钝化层    21-栅极
22-源极            23-漏极
24-漏极沟槽        203-绝缘层
301-公共电极线     302-公共电极过孔
303-漏极材料       304-过孔连接线

Claims (16)

  1. 一种TFT阵列基板，包括：
    承载基底，
    在所述承载基底上交叉设置的栅线和数据线，
    由所述栅线和数据线限定的像素区域，以及
    设置在所述像素区域内的薄膜晶体管、像素电极和有源层，所述薄膜晶体管的栅极与所述栅线连接、源极与所述数据线连接而漏极与所述像素电极连接，其中
    在所述薄膜晶体管的源极上方还形成有绝缘层，所述绝缘层中制作有漏极沟槽，并且
    所述薄膜晶体管的漏极位于所述漏极沟槽中并通过所述有源层与所述源极相连。
  2. 根据权利要求1所述的TFT阵列基板，其中
    所述TFT阵列基板具有底栅结构，
    所述绝缘层包括钝化层，并且
    所述像素电极直接形成在所述薄膜晶体管的漏极上方。
  3. 根据权利要求2所述的TFT阵列基板，其中
    所述TFT阵列基板上还设有公共电极线，所述公共电极线的上方设有公共电极绝缘层，并且
    所述公共电极绝缘层中制作有公共电极过孔，所述公共电极过孔中填充有漏极材料。
  4. 根据权利要求3所述的TFT阵列基板，其中
    在所述漏极材料上方直接形成过孔连接线，所述过孔连接线连接不同的公共电极过孔。
  5. 根据权利要求4所述的TFT阵列基板，其中
    所述公共电极过孔与所述漏极沟槽在同一次构图工艺中形成，
    所述漏极材料与所述漏极在同一次构图工艺中形成，并且
    所述像素电极与所述过孔连接线在一次构图工艺中形成。
  6. 根据权利要求1所述的TFT阵列基板，其中
    所述TFT阵列基板具有顶栅结构，并且
    所述绝缘层包括所述薄膜晶体管的源极和漏极之间的绝缘层。
  7. 一种用于TFT阵列基板的制备方法，包括以下步骤：
    在承载基底上逐层形成栅线和栅极、栅绝缘层、有源层以及数据线和源极；
    在形成有所述栅线和栅极、栅绝缘层、有源层以及数据线和源极的承载基底上进一步沉积绝缘层薄膜，并且通过构图工艺在所述绝缘层薄膜中形成漏极沟槽；以及
    在形成有所述漏极沟槽的承载基板上进一步沉积漏极金属薄膜，并且通过构图工艺形成漏极，所述漏极通过所述有源层与所述源极相连。
  8. 根据权利要求7所述的用于TFT阵列基板的制备方法，其中，在承载基底上逐层形成栅线和栅极、栅绝缘层、有源层以及数据线和源极的步骤包括以下子步骤：
    在承载基底上沉积栅金属层，并且通过构图工艺形成栅线和栅极，所述栅线和栅极相连；
    在形成有所述栅线和栅极的承载基底上进一步沉积栅绝缘层薄膜以形成栅绝缘层；以及
    在形成有所述栅绝缘层的承载基底上进一步沉积有源层薄膜和数据金属层薄膜，并且通过构图工艺分别形成有源层、数据线和源极，其中所述数据线和所述源极相连。
  9. 根据权利要求8所述的用于TFT阵列基板的制备方法，还包括：
    在通过构图工艺形成栅线和栅极的同时，形成公共电极线。
  10. 根据权利要求9所述的用于TFT阵列基板的制备方法，还包括：在通过构图工艺形成漏极沟槽的同时，在所述绝缘层薄膜中形成公共电极过孔，所述公共电极过孔位于所述公共电极线上方。
  11. 根据权利要求10所述的用于TFT阵列基板的制备方法，还包括：在通过构图工艺形成漏极的同时，在所述公共电极过孔中填充漏极材料。
  12. 根据权利要求7或8所述的用于TFT阵列基板的制备方法，还包括：
    在形成有所述漏极的承载基板上进一步沉积像素电极金属薄膜，并且通过构图工艺形成像素电极，所述像素电极与所述漏极直接相连。
  13. 根据权利要求12所述的用于TFT阵列基板的制备方法，还包 括：在通过构图工艺形成像素电极的同时，形成过孔连接线。
  14. 一种用于TFT阵列基板的制备方法，包括以下步骤：
    在承载基底上分别形成有源层、数据线和源极；
    在形成有所述有源层、数据线和源极的承载基底上进一步沉积绝缘层薄膜，并且通过构图工艺在所述绝缘层薄膜中形成漏极沟槽；以及
    在形成有所述漏极沟槽的承载基板上进一步沉积漏极金属薄膜，并且通过构图工艺形成漏极，所述漏极通过所述有源层与所述源极相连。
  15. 根据权利要求14所述的用于TFT阵列基板的制备方法，还包括：
    在形成有所述漏极的承载基板上进一步分别形成栅绝缘层、栅极、钝化层和像素电极。
  16. 一种显示装置，包括如权利要求1-6中任一项所述的TFT阵列基板。
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