WO2016188015A1 - 一种阵列基板及其制备方法、显示面板和显示装置 - Google Patents

一种阵列基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2016188015A1
WO2016188015A1 PCT/CN2015/091821 CN2015091821W WO2016188015A1 WO 2016188015 A1 WO2016188015 A1 WO 2016188015A1 CN 2015091821 W CN2015091821 W CN 2015091821W WO 2016188015 A1 WO2016188015 A1 WO 2016188015A1
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Prior art keywords
insulating layer
array substrate
metal layer
layer
common electrode
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PCT/CN2015/091821
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English (en)
French (fr)
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崔贤植
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京东方科技集团股份有限公司
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Priority to US15/462,289 priority Critical patent/US10345665B2/en
Publication of WO2016188015A1 publication Critical patent/WO2016188015A1/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present disclosure relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a method for fabricating the same, a display panel, and a display device.
  • flat panel displays have replaced CRT (Cathode Ray Tube) displays as mainstream products in the display field.
  • CRT Cathode Ray Tube
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • TFT Thin Film Transistor
  • the pixel electrode In the ADS (ADvanced Super Dimension Switch) mode, two transparent electrodes (which can be made of indium tin oxide ITO) are formed on the array substrate, and one of the ITO electrodes is usually applied as a common electrode. (Vcom), and another layer of ITO electrode is applied as a pixel electrode (Vpixel).
  • Vcom common electrode
  • Vpixel pixel electrode
  • the pixel electrode In the conventional structure, usually the pixel electrode is located above the common electrode as shown in FIG. In this configuration, the common electrode is a structure without a slit. Since the pixel is disturbed by the electric field of the side pixel in the structure without the slit, color mixing is liable to occur.
  • the prior art proposes a PCI (Pixel Inversion) structure in which a common electrode is located above a pixel electrode as shown in FIG.
  • PCI Pixel Inversion
  • the gate lines are progressive scan, all the data lines will be turned on when scanning each row of gate lines; in order to avoid deflection of liquid crystal molecules caused by an electric field formed by the opening of the data lines, shading is formed by the common electrodes.
  • the portion (the portion between the common electrode and the gate line/data line (S/D) edge) whose width needs to be not less than 3 ⁇ m, so that a maximum of one slit can be formed between the common electrodes, which lowers the liquid crystal efficiency. , causing the drive voltage to rise.
  • the present disclosure provides an array substrate and method of fabricating the same, a display panel, and a display device that are capable of at least partially alleviating or eliminating problems in the prior art.
  • the number of common electrode slits formed may include at least two, in order to avoid the influence of adjacent pixels. At the same time as the color mixing problem, the liquid crystal efficiency is improved.
  • a first aspect of the present disclosure provides an array substrate, which may include a plurality of gate lines and a plurality of data lines disposed at intersections, the plurality of gate lines and the plurality of data lines disposed at the intersection defining a plurality of pixel regions, each The pixel region includes a thin film transistor, the array substrate further includes a first insulating layer disposed above the thin film transistor and the data line, a metal layer disposed above the first insulating layer, and a second layer above the metal layer An insulating layer; and a pixel electrode and a common electrode disposed above the second insulating layer, a third insulating layer is disposed between the pixel electrode and the common electrode, and the common electrode in each of the pixel regions includes at least two a slit; wherein the metal layer covers the data line, and the pixel electrode passes through at least a via hole penetrating the first insulating layer and the second insulating layer and a first pole of the thin film transistor Connected, the first source or drain.
  • the metal layer may be electrically connected to the common electrode through via holes penetrating the second insulating layer and the third insulating layer.
  • the metal layer may include any one or more of the following: molybdenum, copper or aluminum.
  • the width of the metal layer may be greater than the width of the data line, and the center of the width of the metal layer may be on the same line as the center of the width of the data line.
  • the metal layer may have a width of 3 to 4 um.
  • the distance between the edge of the metal layer and the edge of the data line may be between 0.8 and 1.5 um.
  • the distance between adjacent data lines may be no more than 14 um.
  • a second aspect of the present disclosure provides a display panel, which may include a color substrate disposed opposite to each other and the array substrate described above.
  • a third aspect of the present disclosure provides a display device that can include the display panel described above.
  • a fourth aspect of the present disclosure provides a method of fabricating an array substrate, which may include:
  • Forming a pattern including a first pole, a second pole, and a data line, the first pole and the second pole being one of a source and a drain, respectively;
  • a pixel electrode Forming a pixel electrode, the pixel electrode being located above the second insulating layer, and the pixel electrode is electrically connected to the first electrode through a via hole penetrating at least the first insulating layer and the second insulating layer ;
  • a common electrode is formed, the common electrode is located above the third insulating layer, and the common electrode includes at least two slits.
  • the array substrate preparation method may further include:
  • a via hole penetrating at least the second insulating layer and the third insulating layer is formed, the metal layer being electrically connected to the common electrode through a via hole penetrating at least the second insulating layer and the third insulating layer.
  • the method may further include:
  • An active layer is formed on the gate insulating layer.
  • the function of the common electrode light shielding portion in the original array substrate is realized by providing a metal layer in the array substrate, so that when the common electrode is formed, A plurality of slits can be formed according to actual needs, so that the influence between adjacent pixels can be reduced, and the liquid crystal efficiency can be improved, and the driving voltage can be lowered.
  • FIG. 1 is a schematic view of an array substrate in the prior art
  • FIG. 2 is a schematic diagram of an array substrate of a PCI structure in the prior art
  • FIG. 3 is a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic flow chart showing an implementation process of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • 5a-5j are schematic views of a process of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides an array substrate, a preparation method thereof, a display panel, and a display device.
  • An embodiment of the present disclosure provides an array substrate including a plurality of gate lines and a plurality of data lines disposed in a cross, a plurality of gate lines and a plurality of data lines disposed in a plurality of pixel regions, each of the pixel regions including a thin film
  • the array substrate further includes:
  • a first insulating layer 31 disposed over the thin film transistor and the data line, a metal layer 32 disposed over the first insulating layer, and a second insulating layer 33 over the metal layer 32; and a pixel electrode disposed over the second insulating layer 34 and a common electrode 35, wherein a third insulating layer 36 is disposed between the pixel electrode 34 and the common electrode 35, and the common electrode 35 in each pixel region includes at least two slits.
  • the metal layer 32 covers the data line, and the pixel electrode 34 is electrically connected to the drain of the thin film transistor through a via hole penetrating the first insulating layer 31 and the second insulating layer 33.
  • the pixel electrode 34 is electrically connected to the drain of the thin film transistor through a via penetrating through the first insulating layer 31 and the second insulating layer 33
  • the pixel The electrode 34 is electrically connected to the source of the thin film transistor through a via hole penetrating the first insulating layer 31 and the second insulating layer 33.
  • the metal layer 32 may be electrically connected to the common electrode 35 through via holes penetrating the second insulating layer 33 and the third insulating layer 36.
  • the metal layer 32 may be a metal having a small resistance value or an alloy of several metals, which is not limited in the embodiment of the present disclosure.
  • the metal layer may use one or more of the following metals: molybdenum, copper, aluminum, and the like.
  • a low-reflection metal such as molybdenum
  • the metal blocks light, it can actually It functions as a black matrix (BM) (ie, a light blocking portion). Based on this, in the embodiment of the present disclosure, the BM width of the color substrate can be reduced or a color substrate without BM can be employed.
  • the width center of the metal layer is on the same line as the center of the data line width, and for example, the distance between the edge of the metal layer and the edge of the data line is 0.8 to 1.5 um.
  • the width of the metal layer may be formed to be about 3 to 4 um.
  • the array substrate provided by the embodiment of the present disclosure is particularly suitable for the case of ultra high resolution (600-800 PPI), that is, the distance between adjacent data lines is not more than 14 um.
  • the array substrate may further include a glass substrate 41, a gate electrode 42, a gate insulating layer 43 and an active layer 44, as shown in FIG. 5i, wherein the gate electrode 42 is located on the glass substrate 41, and the gate insulating layer 43 Located above the gate 42 , the active layer 44 is located above the gate insulating layer, wherein the data lines are disposed in the same layer as the source and drain (S/D), and the gate lines are disposed in the same layer as the gate 42.
  • S/D source and drain
  • the first insulating layer 31 is disposed above the gate line and the data line
  • the metal layer 32 is disposed above the first insulating layer 31
  • the second insulating layer 33 is located above the metal layer 32
  • the pixel electrode 34 and the common electrode 35 (not shown)
  • a third insulating layer 36 is disposed between the pixel electrode 34 and the common electrode 35.
  • the array substrate provided by the embodiment of the present disclosure further adds a second insulating layer as compared with the array substrate using the PCI structure.
  • the thickness thereof may be half or less of the existing PCI structure.
  • the function of the light shielding portion in the existing PCI structure is realized by the metal layer, so that when the common electrode is formed, it is not necessary to consider the distance between the common electrode and the edge of the data line, so that a plurality of narrows can be formed according to actual needs.
  • the slit can improve the liquid crystal efficiency and reduce the driving voltage while avoiding the problem of color mixing caused by adjacent pixels.
  • an embodiment of the present disclosure further provides an array substrate manufacturing method, a display panel, and a display device. Since the principle of the above method and device solves the problem is similar to the above array substrate, the implementation of the above method and device can be seen. The implementation of the array substrate will not be repeated here.
  • a schematic flowchart of an implementation process of a method for fabricating an array substrate according to an embodiment of the present disclosure may include the following steps.
  • a gate metal film is deposited on the glass substrate, and a gate line and a gate electrode are formed by a patterning process.
  • FIG. 5a is a cross-sectional view of the glass substrate, which is not shown. Grid line.
  • a gate insulating layer is deposited on the glass substrate on which step S41 is completed.
  • a schematic structural view of the glass substrate treated in step S42 is as shown in FIG. 5b.
  • a semiconductor thin film is deposited on the gate insulating layer, and an active layer is formed by a patterning process.
  • the active layer in order to reduce the contact resistance between the active layer and the source and drain, the active layer may have a two-layer structure, specifically, a doped semiconductor film is deposited on the gate insulating layer, and is formed by a patterning process.
  • a nitrogen-doped amorphous silicon layer N+a-Si may be formed between the active layer and the source and the drain. .
  • the active layer may also be a metal oxide semiconductor such as IZGO (indium gallium zinc oxide) or the like.
  • a source/drain metal film is deposited on the glass substrate on which step S43 is completed, and source and drain electrodes and data lines (S/D) are formed by a patterning process.
  • a schematic structural view of the glass substrate treated in step S44 is as shown in FIG. 5d.
  • a pattern of the first insulating layer is formed by a patterning process on the glass substrate on which the step S44 is completed.
  • a schematic structural view of the glass substrate processed in step S45 is as shown in FIG. 5e.
  • a metal layer is formed over the first insulating layer.
  • a schematic structural view of the glass substrate processed in step S46 is as shown in FIG. 5f.
  • a pattern of the second insulating layer is formed by a patterning process on the glass substrate on which the step S46 is completed, and a via hole penetrating at least the first insulating layer and the second insulating layer is formed.
  • a schematic structural view of the glass substrate processed in step S47 is as shown in FIG. 5g.
  • a pixel electrode is formed on the glass substrate on which step S47 is completed.
  • the pixel electrode is located above the second insulating layer, and the pixel electrode is electrically connected to the drain through a via hole penetrating at least the first insulating layer and the second insulating layer.
  • a schematic structural view of the glass substrate processed in step S48 is as shown in FIG. 5h.
  • the pixel electrode may be ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) or the like.
  • a third insulating layer is formed on the glass substrate on which step S48 is completed, and via holes penetrating at least the third insulating layer and the second insulating layer are formed.
  • a schematic structural view of the glass substrate processed in step S49 is as shown in FIG. 5i.
  • a common electrode is formed on the third insulating layer, and the common electrode includes at least two slits.
  • the common electrode is located above the third insulating layer.
  • a schematic structural view of the glass substrate processed in step S410 is as shown in FIG. 5j.
  • the flow shown in FIG. 4 is a flow chart for preparing an array substrate of a bottom gate structure.
  • the array substrate may also be a top gate structure.
  • the gate is located above the active layer.
  • the common electrode may be selected from ITO (indium tin oxide) or IZO (indium zinc oxide).
  • the embodiment of the present disclosure further provides a display panel comprising the above array substrate and a color substrate, wherein the array substrate and the color substrate are disposed on the box, and the liquid crystal is filled between the array substrate and the color substrate.
  • the color substrate included in the display panel provided by the embodiment of the present disclosure may adopt a color substrate without BM or adopt A color substrate with a reduced BM width.
  • Embodiments of the present disclosure also provide a display device including the above display panel.

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Abstract

一种阵列基板及其制备方法、显示面板和显示装置，使得形成的公共电极狭缝个数可以包括至少两个，从而在避免相邻像素影响形成混色问题的同时，提高液晶效率。阵列基板包括交叉设置的多条栅线和多条数据线，所述交叉设置的多条栅线和多条数据线限定多个像素区域，每一所述像素区域包括薄膜晶体管。阵列基板还包括设置在所述薄膜晶体管和所述数据线上方的第一绝缘层（31），设置于第一绝缘层（31）上方的金属层（32）和位于金属层（32）上方的第二绝缘层（33）；以及设置在第二绝缘层（33）上方的像素电极（34）和公共电极（35），在所述像素电极（34）和公共电极（35）之间设置有第三绝缘层（36），每个所述像素区域中的所述公共电极（35）至少包括两个狭缝；其中，所述金属层（32）覆盖在所述数据线上方。

Description

一种阵列基板及其制备方法、显示面板和显示装置 技术领域
本公开涉及液晶显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
随着液晶显示技术的发展，平板显示器已经取代CRT(Cathode Ray Tube，阴极射线管)显示器成为显示器领域的主流产品。目前，常用的平板显示器包括LCD(Liquid Crystal Display，液晶显示器)和OLED(Organic Light-Emitting Diode，有机发光二极管)显示器。在成像过程中，LCD显示器中每一液晶像素点都集成TFT(Thin Film Transistor，薄膜晶体管)以用于驱动，然后通过配合外围驱动电路，实现图像显示。
在ADS(ADvanced Super Dimension Switch，高级超维场转换技术)模式下，在阵列基板上形成有两层透明电极(可以由氧化铟锡ITO来制作)，通常将其中一层ITO电极应用为公共电极(Vcom)，而将另外一层ITO电极应用为像素电极(Vpixel)。传统结构中，通常像素电极位于公共电极的上方，如图1所示。这种结构下，公共电极为没有狭缝的结构。由于在没有狭缝的结构下，像素受到旁边像素的电场的干扰，因而容易发生混色。为了解决该问题，现有技术提出了PCI(像素反转)结构，即公共电极位于像素电极上方，如图2所示。然而，在PCI结构下，由于栅线为逐行扫描，在对每一行栅线进行扫描时，所有数据线均将打开；为了避免数据线打开形成的电场造成液晶分子偏转，通过公共电极形成遮光部(公共电极与栅线/数据线(S/D)边缘之间的部分)，其宽度需要不小于3um，这样，使得在公共电极之间最多可以形成1个狭缝，这降低了液晶效率，使得驱动电压升高。
发明内容
本公开提供一种阵列基板及其制备方法、显示面板和显示装置，其能够至少部分地缓解或消除现有技术中的问题。具体地，其使得形成的公共电极狭缝个数可以包括至少两个，在避免相邻像素影响形成 混色问题的同时，提高液晶效率。
本公开的第一方面提供一种阵列基板，其可以包括交叉设置的多条栅线和多条数据线，所述交叉设置的多条栅线和多条数据线限定多个像素区域，每一所述像素区域包括薄膜晶体管，所述阵列基板还包括设置在所述薄膜晶体管和所述数据线上方的第一绝缘层，设置于第一绝缘层上方的金属层和位于金属层上方的第二绝缘层；以及设置在第二绝缘层上方的像素电极和公共电极，所述像素电极和公共电极之间设置有第三绝缘层，每个所述像素区域中的所述公共电极至少包括两个狭缝；其中，所述金属层覆盖在所述数据线上方，所述像素电极通过至少贯穿所述第一绝缘层和所述第二绝缘层的过孔与所述薄膜晶体管的第一极电连接，所述第一极为源极或漏极。
根据一个实施例，所述金属层可以通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述公共电极电连接。
根据另一实施例，所述金属层可以包括以下任一种或多种：钼、铜或者铝。
根据又一实施例，所述金属层的宽度可以大于所述数据线的宽度，且所述金属层的宽度中心可以与所述数据线的宽度中心位于同一直线上。
根据再一实施例，所述金属层的宽度可以为3～4um。
根据另外的实施例，所述金属层的边缘与所述数据线的边缘之间的距离可以为0.8～1.5um。
根据实施例，相邻数据线之间的距离可以不大于14um。
本公开的第二方面提供一种显示面板，其可以包括相对设置的彩色基板和上述的阵列基板。
本公开的第三方面提供一种显示装置，其可以包括上述的显示面板。
本公开的第四方面提供一种制备阵列基板的方法，其可以包括：
形成包括第一极、第二极和数据线的图形，第一极和第二极分别为源极和漏极中的一个；
在所述数据线上方形成第一绝缘层；
形成金属层，所述金属层位于所述第一绝缘层的上方，且所述金属层覆盖在所述数据线上方；
在所述金属层上方形成第二绝缘层，并形成至少贯穿第一绝缘层和第二绝缘层的过孔；
形成像素电极，所述像素电极位于所述第二绝缘层的上方，且所述像素电极通过至少贯穿所述第一绝缘层和所述第二绝缘层的过孔与所述第一极电连接；
在所述像素电极上方形成第三绝缘层；
形成公共电极，所述公共电极位于第三绝缘层上方，且所述公共电极至少包括两个狭缝。
根据一个实施例，阵列基板制备方法还可以包括：
形成至少贯穿所述第二绝缘层和第三绝缘层的过孔，所述金属层通过至少贯穿所述第二绝缘层和第三绝缘层的过孔与所述公共电极电连接。
根据另一实施例，在所述形成包括第一极、第二极和数据线的图形的步骤之前，还可以包括：
在衬底基板上形成栅极；
在所述栅极上沉积栅绝缘层；
在所述栅绝缘层上形成有源层。
在本公开实施例提供的阵列基板及其制备方法、显示面板和显示装置中，通过在阵列基板中设置金属层来实现原阵列基板中公共电极遮光部的功能，这样，在形成公共电极时，可以根据实际需要形成多个狭缝，从而能够减小相邻像素之间的影响，并提高液晶效率，降低驱动电压。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为现有技术中的阵列基板的示意图；
图2为现有技术中的PCI结构的阵列基板的示意图；
图3为根据本公开的实施例的阵列基板的剖面示意图；
图4为根据本公开实施例的阵列基板制备方法的实施流程示意图；
图5a-图5j为根据本公开实施例的阵列基板制备过程中的示意图。
具体实施方式
为了避免由于相邻像素相互影响而造成混色问题，本公开实施例提供了一种阵列基板及其制备方法、显示面板和显示装置。
以下结合说明书附图对本公开的示例实施例进行说明。应当理解，此处所描述的示例实施例仅用于说明和解释本公开，并不用于限定本公开，并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
本公开的一个实施例提供的阵列基板包括交叉设置的多条栅线和多条数据线，交叉设置的多条栅线和多条数据线限定多个像素区域，每一所述像素区域包括薄膜晶体管，如图3所示，该阵列基板还包括：
设置在薄膜晶体管和数据线上方的第一绝缘层31，设置于第一绝缘层上方的金属层32和位于金属层32上方的第二绝缘层33；以及设置在第二绝缘层上方的像素电极34和公共电极35，其中，在像素电极34和公共电极35之间设置有第三绝缘层36，每一像素区域中的公共电极35至少包括两个狭缝。在具体实施时，金属层32覆盖在数据线上方，像素电极34通过贯穿第一绝缘层31和第二绝缘层33的过孔与薄膜晶体管的漏极电连接。
需要指出的是，尽管在上述实施例中，像素电极34通过贯穿第一绝缘层31和第二绝缘层33的过孔与薄膜晶体管的漏极电连接，但是在可替换的实施例中，像素电极34通过贯穿第一绝缘层31和第二绝缘层33的过孔与薄膜晶体管的源极电连接。
在具体实施时，金属层32可以通过贯穿第二绝缘层33和第三绝缘层36的过孔与公共电极35电连接。
在具体实施时，金属层32可以使用电阻值小的金属，也可以为几种金属的合金，本公开实施例对此不做限定。例如，金属层可以使用以下金属中的一种或者多种：钼、铜、铝等。需要说明的是，当金属层使用低反射金属(例如钼)时，由于金属阻挡光，因此实际上可以 起到黑矩阵(BM)(即遮光部)的作用。基于此，在本公开实施例中，可以将彩色基板的BM宽度减小或者采用无BM的彩色基板。
在具体实施时，金属层的宽度中心与数据线宽度中心位于同一直线上，且例如金属层的边缘与数据线的边缘之间的距离为0.8～1.5um。在数据线宽度为2um时，金属层的宽度形成为约3～4um即可。
需要说明的是，本公开实施例提供的阵列基板尤其适用于超高分辨率(600～800PPI)的情况，即相邻的数据线之间的距离不大于14um。
在具体实施时，上述阵列基板还可以包括玻璃基板41、栅极42、栅绝缘层43和有源层44，如图5i所示，其中：栅极42位于玻璃基板41上，栅绝缘层43位于栅极42上方，有源层44位于栅绝缘层上方，其中，数据线与源漏极(S/D)同层设置，栅线与栅极42同层设置。第一绝缘层31设置于栅线和数据线上方，金属层32设置于第一绝缘层31的上方，第二绝缘层33位于金属层32的上方，像素电极34和公共电极35(未示出)设置于第二绝缘层33的上方，像素电极34和公共电极35之间设置有第三绝缘层36。
与采用PCI结构的阵列基板相比，本公开实施例提供的阵列基板还增加第二绝缘层。在具体实施时，在形成第一绝缘层时，其厚度可以为现有的PCI结构中的一半或者更小一些。
在本公开实施例中，通过金属层实现现有的PCI结构中的遮光部的功能，使得在形成公共电极时，无需考虑公共电极与数据线边缘的距离，从而可以根据实际需要形成多个狭缝，在避免相邻像素影响造成混色问题的同时，还能够提高液晶效率，降低驱动电压。
基于同一发明构思，本公开实施例还提供了一种阵列基板制备方法、显示面板和显示装置，由于上述方法和装置解决问题的原理与上述的阵列基板相似，因此上述方法和装置的实施可以参见阵列基板的实施，重复之处不再赘述。
如图4所示，为本公开实施例提供的阵列基板制备方法的实施流程示意图，可以包括以下步骤。
在S41处，在玻璃基板上沉积栅金属薄膜，通过构图工艺形成栅线、栅极。
在具体实施时，经过步骤S41处理后的玻璃基板的结构示意图如图5a所示，需要说明的是，图5a为玻璃基板的横截面图，其中未显示 栅线。
在S42处，在完成步骤S41的玻璃基板上沉积栅绝缘层。
在具体实施时，经过步骤S42处理后的玻璃基板的结构示意图如图5b所示。
在S43处，在栅绝缘层上沉积半导体薄膜，并通过构图工艺形成有源层。
在具体实施时，经过步骤S43处理后的玻璃基板的结构示意图如图5c所示。在具体实施过程中，为了减少有源层与源漏极之间的接触电阻，有源层可以为两层结构，具体地，在栅绝缘层上沉积掺杂半导体薄膜，并通过构图工艺形成位于有源层与源极和漏极之间的欧姆接触层，以提高TFT的性能。举例说明，针对利用非晶硅半导体层材料制作有源层的情况，可以在有源层与源极和漏极之间制作经氮离子掺杂过的非晶硅层(N+a-Si)。
在具体实施时，有源层还可以是金属氧化物半导体，如IZGO(indium gallium zinc oxide，铟镓锌氧化物)等。
在S44处，在完成步骤S43的玻璃基板上沉积源漏金属膜，并通过构图工艺形成源漏电极和数据线(S/D)。
在具体实施时，经过步骤S44处理后的玻璃基板的结构示意图如图5d所示。
在S45处，在完成步骤S44的玻璃基板上通过构图工艺形成第一绝缘层的图案。
在具体实施时，经过步骤S45处理后的玻璃基板的结构示意图如图5e所示。
在S46处，在第一绝缘层上方形成金属层。
其中，金属层位于第一绝缘层的上方，且所述金属层覆盖在数据线上方。在具体实施时，经过步骤S46处理后的玻璃基板的结构示意图如图5f所示。
在S47处，在完成步骤S46的玻璃基板上通过构图工艺形成第二绝缘层的图案，并且形成至少贯穿第一绝缘层和第二绝缘层的过孔。
在具体实施时，经过步骤S47处理后的玻璃基板的结构示意图如图5g所示。
在S48处，在完成步骤S47的玻璃基板上形成像素电极。
其中，像素电极位于第二绝缘层的上方，且像素电极通过至少贯穿第一绝缘层和所述第二绝缘层的过孔与所述漏极电连接。在具体实施时，经过步骤S48处理后的玻璃基板的结构示意图如图5h所示。
在具体实施时，像素电极可以为ITO(铟锡氧化物)或者IZO(铟锌氧化物)等。
在S49处，在完成步骤S48的玻璃基板上形成第三绝缘层，并形成至少贯穿第三绝缘层和第二绝缘层的过孔。
其中，金属层通过至少贯穿所述第二绝缘层和第三绝缘层的过孔与所述公共电极电连接。在具体实施时，经过步骤S49处理后的玻璃基板的结构示意图如图5i所示。
在S410处，在第三绝缘层上形成公共电极，公共电极至少包括两个狭缝。
其中，公共电极位于第三绝缘层上方。
在具体实施时，经过步骤S410处理后的玻璃基板的结构示意图如图5j所示。
需要说明的是，图4所示的流程为底栅结构的阵列基板的制备流程图。在具体实施时，阵列基板还可以为顶栅结构，在顶栅结构的阵列基板制备过程中，栅极位于有源层上方。
在具体实施时，公共电极可以选用ITO(铟锡氧化物)或者IZO(铟锌氧化物)等。
本公开实施例还提供一种显示面板，包括上述的阵列基板和彩色基板，其中阵列基板和彩色基板对盒设置，并且在阵列基板和彩色基板之间填充有液晶。
特别的，如果本公开实施例提供的阵列基板中的金属层使用低反射金属(如钼等)实现时，本公开实施例提供的显示面板中包含的彩色基板可以采用无BM的彩色基板或者采用减小BM宽度的彩色基板。
本公开实施例还提供一种显示装置，包括上述的显示面板。
尽管已描述了本公开的示例实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括示例实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不 脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种阵列基板，包括交叉设置的多条栅线和多条数据线，所述交叉设置的多条栅线和多条数据线限定多个像素区域，每一所述像素区域包括薄膜晶体管，其中，所述阵列基板还包括设置在所述薄膜晶体管和所述数据线上方的第一绝缘层；设置于第一绝缘层上方的金属层和位于金属层上方的第二绝缘层；以及设置在第二绝缘层上方的像素电极和公共电极，在所述像素电极和公共电极之间设置有第三绝缘层，每个所述像素区域中的所述公共电极至少包括两个狭缝；其中，所述金属层覆盖在所述数据线上方，所述像素电极通过至少贯穿所述第一绝缘层和所述第二绝缘层的过孔与所述薄膜晶体管的第一极电连接，所述第一极为源极或漏极。
  2. 如权利要求1所述的阵列基板，其中，所述金属层通过贯穿所述第二绝缘层和所述第三绝缘层的过孔与所述公共电极电连接。
  3. 如权利要求1所述的阵列基板，其中，所述金属层包括以下任一种或多种：钼、铜或者铝。
  4. 如权利要求1所述的阵列基板，其中，所述金属层的宽度大于所述数据线的宽度，且所述金属层的宽度中心与所述数据线的宽度中心位于同一直线上。
  5. 如权利要求4所述的阵列基板，其中，所述金属层的宽度为3～4um。
  6. 如权利要求1所述的阵列基板，其中，所述金属层的边缘与所述数据线的边缘之间的距离为0.8～1.5um。
  7. 如权利要求1所述的阵列基板，其中，相邻数据线之间的距离不大于14um。
  8. 一种显示面板，包括相对设置的彩色基板和权利要求1～7中任一个所述的阵列基板。
  9. 一种显示装置，包括权利要求8所述的显示面板。
  10. 一种制备阵列基板的方法，包括：
    形成包括第一极、第二极和数据线的图形，第一极和第二极分别为源极和漏极中的一个；
    在所述数据线上方形成第一绝缘层；
    形成金属层，所述金属层位于所述第一绝缘层的上方，且所述金属层覆盖在所述数据线上方；
    在所述金属层上方形成第二绝缘层，并形成至少贯穿第一绝缘层和第二绝缘层的过孔；
    形成像素电极，所述像素电极位于所述第二绝缘层的上方，且所述像素电极通过至少贯穿所述第一绝缘层和所述第二绝缘层的过孔与所述第一极电连接；
    在所述像素电极上方形成第三绝缘层；
    形成公共电极，所述公共电极位于第三绝缘层上方，且所述公共电极至少包括两个狭缝。
  11. 如权利要求10所述的方法，还包括：
    形成至少贯穿所述第二绝缘层和第三绝缘层的过孔，所述金属层通过至少贯穿所述第二绝缘层和第三绝缘层的过孔与所述公共电极电连接。
  12. 如权利要求10或11所述的方法，其中，在所述形成包括第一极、第二极和数据线的图形的步骤之前，还包括：
    在衬底基板上形成栅极；
    在所述栅极上沉积栅绝缘层；
    在所述栅绝缘层上形成有源层。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI553839B (zh) * 2015-04-15 2016-10-11 群創光電股份有限公司 顯示面板
CN104834139A (zh) 2015-05-25 2015-08-12 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置
CN107797352B (zh) * 2017-11-17 2020-06-05 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板、显示设备及阵列基板的制作方法
CN111474786B (zh) * 2020-05-12 2021-07-06 深圳市华星光电半导体显示技术有限公司 液晶显示面板
CN111580316B (zh) * 2020-05-19 2023-01-24 深圳市华星光电半导体显示技术有限公司 显示面板及电子装置
US11119375B1 (en) 2020-05-19 2021-09-14 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and electronic device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020131003A1 (en) * 2001-03-15 2002-09-19 Nec Corporation Active matrix type liquid crystal display device and method of manufacturing the same
CN103077944A (zh) * 2013-01-18 2013-05-01 京东方科技集团股份有限公司 显示装置、阵列基板及其制作方法
CN103176302A (zh) * 2011-12-22 2013-06-26 乐金显示有限公司 液晶显示器件及其制造方法
CN103472646A (zh) * 2013-08-30 2013-12-25 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN103676374A (zh) * 2013-12-06 2014-03-26 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN104834139A (zh) * 2015-05-25 2015-08-12 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004172090A (ja) * 2002-10-31 2004-06-17 Seiko Epson Corp エレクトロルミネッセンス装置の製造方法及びエレクトロルミネッセンス装置、並びに電子機器
CN103852941A (zh) * 2012-12-07 2014-06-11 瀚宇彩晶股份有限公司 主动元件阵列基板与显示面板
US9397282B2 (en) * 2012-12-13 2016-07-19 Cbrite Inc. Active matrix light emitting diode array and projector display comprising it
CN103309108B (zh) * 2013-05-30 2016-02-10 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103309105B (zh) 2013-07-05 2016-02-03 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020131003A1 (en) * 2001-03-15 2002-09-19 Nec Corporation Active matrix type liquid crystal display device and method of manufacturing the same
CN103176302A (zh) * 2011-12-22 2013-06-26 乐金显示有限公司 液晶显示器件及其制造方法
CN103077944A (zh) * 2013-01-18 2013-05-01 京东方科技集团股份有限公司 显示装置、阵列基板及其制作方法
CN103472646A (zh) * 2013-08-30 2013-12-25 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN103676374A (zh) * 2013-12-06 2014-03-26 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN104834139A (zh) * 2015-05-25 2015-08-12 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置

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