CN101382728B - 灰阶掩膜版结构 - Google Patents

灰阶掩膜版结构 Download PDF

Info

Publication number
CN101382728B
CN101382728B CN2007101215316A CN200710121531A CN101382728B CN 101382728 B CN101382728 B CN 101382728B CN 2007101215316 A CN2007101215316 A CN 2007101215316A CN 200710121531 A CN200710121531 A CN 200710121531A CN 101382728 B CN101382728 B CN 101382728B
Authority
CN
China
Prior art keywords
region
gray level
mask plate
plate structure
shield bars
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101215316A
Other languages
English (en)
Other versions
CN101382728A (zh
Inventor
董敏
刘圣烈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing BOE Optoelectronics Technology Co Ltd filed Critical Beijing BOE Optoelectronics Technology Co Ltd
Priority to CN2007101215316A priority Critical patent/CN101382728B/zh
Priority to KR1020080050458A priority patent/KR100932995B1/ko
Priority to JP2008141724A priority patent/JP4959631B2/ja
Priority to US12/128,724 priority patent/US7871743B2/en
Publication of CN101382728A publication Critical patent/CN101382728A/zh
Application granted granted Critical
Publication of CN101382728B publication Critical patent/CN101382728B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/32Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/50Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

本发明涉及一种灰阶掩膜版结构,包括掩膜版,所述掩膜版上设置有可掩膜出源极的源极区域和可掩膜出漏极的漏极区域,以及在所述源极区域与所述漏极区域之间的沟道区域,在所述沟道区域内均匀设置有数个挡光条,所述挡光条与所述沟道区域的中心线垂直。采用本发明所提供的灰阶掩膜版结构进行曝光工艺,由于存在多个狭缝使光发生多重干涉,使挡光条下的光刻胶得到均匀度较高的光强,减小光刻胶表面突起的数量与突起的尺寸,从而获得一定高度的且均匀度较高的光刻胶表面,灰化后进而进行二次刻蚀,改善了掩膜工艺的均匀性问题,降低了由于均匀性不良而出现源/漏层短路等问题的几率,获得性能优良的薄膜晶体管源/漏层沟道。

Description

灰阶掩膜版结构
技术领域
本发明涉及一种灰阶掩膜版结构,尤其是一种应用于四次掩膜工艺,在制备源/漏层(Source/Drain;以下简称:S/D层)过程中改善光刻胶均匀性的灰阶掩膜版结构。
背景技术
目前,在液晶面板的生产过程中,四次掩膜工艺由于对比五次掩膜工艺减少了一道掩膜工序,缩短了工艺周期,因而被广泛应用。其将五次掩膜工艺中的制备有源层和源/漏层合并为一道掩膜工序,通过狭缝/挡光条的组合形成一定高度的灰阶光刻胶,再通过两次刻蚀形成沟道。如图9所示,目前S/D层制造过程曝光工艺使所用的灰阶掩膜版,其上设置有可掩膜出源极的源极区域20和可掩膜出漏极的漏极区域10,源极区域20的端部位于漏极区域10“U”形状内,形成“U”形沟道区域,并在形成的沟道区域中沿沟道方向设置挡光条60,所述挡光条与源极区域20、漏极区域10之间形成狭缝50’,由于双缝干涉原理,在进行曝光工艺时,可在沟道区域对应位置形成较为平整的灰阶光刻胶(指高度与源/漏极光刻胶的高度成一定比例的光刻胶,例如比例为1/2),进而在灰化后能够进行二次刻蚀,获得需要的沟道表面。
但是,应用沿“U”形沟道结构方向设置挡光条的掩膜版进行S/D层曝光工艺时,通过双缝干涉得到的光的强度分布如图10中所示,虽然最终获得了灰阶光刻胶表面,但由于双缝透过的光强度的不均匀性,使得在“U”形沟道中的沟道拐角部分、沟道中心及边缘部分容易存在光刻胶厚度的差异,所以仍然容易造成此处光刻胶表面出现较多的突起,导致沟道的有源层残留或S/D层短路等不良现象的发生。
发明内容
本发明的实施例提供一种灰阶掩膜版结构,用以改善现有掩膜版结构制造S/D层的光刻胶突起的问题,使S/D层获得均匀性较好的沟道。
本发明通过一些实施例提供了如下的技术方案:
一种灰阶掩膜版结构,包括掩膜版,所述掩膜版上设置有可掩膜出源极的源极区域和可掩膜出漏极的漏极区域,以及在所述源极区域与所述漏极区域之间的沟道区域,在所述沟道区域内均匀设置有数个挡光条,所述挡光条与所述沟道区域的中心线垂直。
采用本发明实施例所提供的灰阶掩膜版用于进行S/D层曝光工艺,由于存在多个狭缝使光发生多重干涉,使挡光条下的光刻胶得到均匀度较高的光强,减小光刻胶表面突起的数量与突起的尺寸,从而获得一定高度的且均匀度较高的光刻胶表面,灰化后进而进行二次刻蚀,改善了掩膜工艺的均匀性问题,降低由于均匀性不良而出现S/D层短路等问题的几率,获得性能优良的薄膜晶体管S/D层沟道。
下面结合附图和具体实施例进一步说明本发明的技术方案。
附图说明
图1为本发明U形状灰阶掩膜版结构示意图;
图2为本发明U形状灰阶掩膜版结构接收光强示意图;
图3为本发明平行状灰阶掩膜版结构示意图;
图4-8为制造本发明灰阶掩膜版工艺流程示意图;
图9为现有U形状灰阶掩膜版结构示意图;
图10为现有U形状灰阶掩膜版结构接收光强示意图。
具体实施方式
图1为本发明U形状灰阶掩膜版结构的示意图,包括掩膜版,掩膜版上设置有可掩膜出源极的源极区域20和可掩膜出漏极的漏极区域10,以及在源极区域20与漏极区域10之间的沟道区域30,在沟道区域30内均匀设置有数个挡光条40,挡光条40与沟道区域30的中心线垂直。
在掩膜工艺中,源极区域20与漏极区域10分别用于掩膜形成源极和漏极,沿垂直于沟道结构30中心线的方向均匀设置数个挡光条40,各个挡光条之间形成狭缝50。当光透过狭缝时,众多光束发生多重干涉,由于挡光条均匀设置,因此在狭缝50以及挡光条40的下方将得到强度均匀的光照,如图2所示,得到均匀平整的且具有一定高度的光刻胶表面,所述高度为源极区域与漏极区域光刻胶高度的一定比例(低于源极区域与漏极区域光刻胶高度);然后可灰化后进行二次刻蚀,得到S/D层沟道,最终挡光条下的光刻胶表面的均匀度决定了刻蚀后S/D层沟道表面的均匀度。与现有应用沿沟道方向设置挡光条的掩膜版形成S/D层相比,采用本发明实施例所提供的灰阶掩膜版进行曝光的过程中,由于存在多个狭缝使光发生多重干涉,使挡光条下的光刻胶得到均匀度较高的光照,减小光刻胶表面突起的数量与突起的尺寸,从而获得一定高度的且均匀度较高的光刻胶表面,灰化后进而进行二次刻蚀,改善了掩膜工艺的均匀性问题,降低了由于均匀性不良而出现S/D层短路等问题的几率,获得性能优良的S/D层沟道。
在本发明上述技术方案基础上,可以将挡光条设置成条形状,保证光在发生多重干涉后形成具有较高的均匀度。进一步地,为了避免由于挡光条的端部与源极区域、漏极区域接触面较大而产生光照死角,可将挡光条的端部设置成尖角形状或梯形形状,即挡光条的端部与源极区域、漏极区域以角度形式连接,使得挡光条的端部与源极区域、漏极区域以较少面积接触。这样即使光刻胶表面出现突起,但由于多个挡光条的设置使光刻胶突起呈离散分布,并且由于挡光条的端部与源极区域、漏极区域以角度相接,确保后续形成的S/D残留与源/漏极是不接触的,进一步降低了S/D层短路现象的发生,获得均匀性较好的沟道结构。
如图1所示,本发明U形状灰阶掩膜版结构的漏极区域10为U形状,源极区域20的端部为矩形状,源极区域20的端部伸入U形状漏极区域10内,使源极区域20与U形状漏极区域10的两边内侧边形成沟道区域30,在沟道区域30内设置数个挡光条40,挡光条40与沟道区域30的中心线垂直。挡光条40的端部与源极区域10、漏极区域20接触形成的角度φ为20°~70°,挡光条的宽度a为1~3μm,各挡光条均匀设置,且间距b为1~3μm;其优选实施方式为挡光条与狭缝等宽设置。
图3为本发明平行状灰阶掩膜版结构示意图,漏极区域10和源极区域20均为矩形状,漏极区域10和源极区域20的相邻边之间形成沟道区域30,垂直于漏极区域10和源极区域20的相邻边方向,设置数个挡光条40。挡光条40的端部与漏极区域10、源极区域20接触形成的角度φ为20°~70°,挡光条的宽度a为1~3μm,各挡光条均匀设置,且间距b为1~3μm;其优选实施方式为挡光条与狭缝等宽设置。
具有U形结构的灰阶掩膜版可以通过下面的方法制造:
首先,如图4所示,使用磁控溅射方法,在玻璃基板1上沉积一层金属薄膜2,所述金属材料通常使用铬(Cr);
然后,如图5所示,在金属薄膜2上涂敷光刻胶3,利用激光照射使光刻胶形成具有特定形状的图形,如图6所示,图6为掩膜版的俯视图,光刻胶图形包括以下图形区域:光刻胶漏极区域10’和光刻胶源极区域20’,光刻胶源极区域20’与光刻胶漏极区域10’之间的光刻胶沟道区域30’,以及光刻胶沟道区域30’内的数个光刻胶挡光条区域40’,并将光刻胶挡光条区域40’与光刻胶沟道区域30’的中心线垂直设置;
接下来,如图7所示,通过刻蚀工艺,使得仅在具有特定图形的光刻胶3下方保留金属层;
最后,如图8所示,通过剥离工艺,将玻璃基板1上的光刻胶3剥离掉,形成掩膜版,包括可掩膜出漏极的漏极区域10和可掩膜出源极的源极区域20,源极区域20与漏极区域10之间的沟道区域30,以及沟道区域30内的数个挡光条40,并将挡光条40与沟道区域30的中心线垂直设置。
制备平行状灰阶掩膜版工艺流程与上述制备U形状灰阶掩膜版的工艺流程相似,仅在形成有特定形状的光刻胶的流程上有所不同,可按照要求将光刻胶制备成相应形状即可。
最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (7)

1.一种灰阶掩膜版结构,包括掩膜版,所述掩膜版上设置有可掩膜出源极的源极区域和可掩膜出漏极的漏极区域,以及在所述源极区域与所述漏极区域之间的沟道区域,其特征在于:在所述沟道区域内均匀设置有数个挡光条,所述挡光条与所述沟道区域的中心线垂直。
2.根据权利要求1所述的灰阶掩膜版结构,其特征在于:与所述源极区域和漏极区域接触的所述挡光条的端部为尖角或梯形形状。
3.根据权利要求2所述的灰阶掩膜版结构,其特征在于:所述挡光条的具有尖角或梯形形状的端部与所述源极区域、漏极区域之间形成的角度为20°~70°。
4.根据权利要求1所述的灰阶掩膜版结构,其特征在于:所述挡光条宽度为1~3μm。
5.根据权利要求1所述的灰阶掩膜版结构,其特征在于:所述挡光条的间距为1~3μm。
6.根据权利要求1至5所述的任一灰阶掩膜版结构,其特征在于:所述漏极区域为U形状,矩形状的源极区域端部位于所述U形状内。
7.根据权利要求1至5所述的任一灰阶掩膜版结构,其特征在于:所述源极区域和漏极区域为矩形状。
CN2007101215316A 2007-09-07 2007-09-07 灰阶掩膜版结构 Expired - Fee Related CN101382728B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007101215316A CN101382728B (zh) 2007-09-07 2007-09-07 灰阶掩膜版结构
KR1020080050458A KR100932995B1 (ko) 2007-09-07 2008-05-29 그레이 스케일 마스크
JP2008141724A JP4959631B2 (ja) 2007-09-07 2008-05-29 グレースケールマスク
US12/128,724 US7871743B2 (en) 2007-09-07 2008-05-29 Gray scale mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2007101215316A CN101382728B (zh) 2007-09-07 2007-09-07 灰阶掩膜版结构

Publications (2)

Publication Number Publication Date
CN101382728A CN101382728A (zh) 2009-03-11
CN101382728B true CN101382728B (zh) 2010-07-28

Family

ID=40432214

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101215316A Expired - Fee Related CN101382728B (zh) 2007-09-07 2007-09-07 灰阶掩膜版结构

Country Status (4)

Country Link
US (1) US7871743B2 (zh)
JP (1) JP4959631B2 (zh)
KR (1) KR100932995B1 (zh)
CN (1) CN101382728B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI390339B (zh) * 2009-08-31 2013-03-21 Au Optronics Corp 用於製造薄膜電晶體的光罩及製造薄膜電晶體的源極/汲極的方法
CN102655175B (zh) * 2012-04-06 2014-07-02 京东方科技集团股份有限公司 Tft、阵列基板及显示装置、制备该tft的掩模板
CN102799059B (zh) * 2012-08-15 2014-10-15 京东方科技集团股份有限公司 灰阶掩膜版、阵列基板及其制备方法、显示装置
KR101949389B1 (ko) * 2012-11-07 2019-02-18 엘지디스플레이 주식회사 마스크리스 노광장치를 이용한 패턴 형성 방법
CN103969940A (zh) * 2014-04-22 2014-08-06 京东方科技集团股份有限公司 相移掩模板和源漏掩模板
US9921471B2 (en) 2014-09-24 2018-03-20 Micron Technology, Inc. Methods of forming photonic device structures
CN104765245A (zh) * 2015-04-10 2015-07-08 深圳市华星光电技术有限公司 一种灰色调掩膜及其制作方法
WO2019082380A1 (ja) * 2017-10-27 2019-05-02 シャープ株式会社 グレイトーンマスク
CN109541829B (zh) * 2018-12-19 2021-08-24 惠科股份有限公司 掩膜版、液晶面板和液晶显示装置
CN113759655A (zh) * 2021-08-19 2021-12-07 惠科股份有限公司 掩膜版、阵列基板的制作方法及显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1440080A (zh) * 2002-02-22 2003-09-03 日本电气株式会社 沟道蚀刻薄膜晶体管
CN1584718A (zh) * 2003-08-21 2005-02-23 Nec液晶技术株式会社 包括用于减少泄漏电流的tft的lcd设备
CN1655039A (zh) * 2004-02-10 2005-08-17 Nec液晶技术株式会社 薄膜晶体管、使用其的液晶显示器、以及其制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04218046A (ja) * 1990-06-21 1992-08-07 Matsushita Electron Corp ホトマスク及びその製造方法
JPH04251253A (ja) * 1991-01-09 1992-09-07 Fujitsu Ltd 露光マスク
JPH04311025A (ja) * 1991-04-10 1992-11-02 Fujitsu Ltd 露光方法
JP3179520B2 (ja) * 1991-07-11 2001-06-25 株式会社日立製作所 半導体装置の製造方法
JP3508306B2 (ja) * 1995-07-17 2004-03-22 ソニー株式会社 マスクパターン補正方法とそれを用いたマスク、露光方法および半導体装置
JP4264675B2 (ja) * 1998-08-17 2009-05-20 栄 田中 液晶表示装置とその製造方法
CN1139837C (zh) * 1998-10-01 2004-02-25 三星电子株式会社 液晶显示器用薄膜晶体管阵列基板及其制造方法
US6255130B1 (en) * 1998-11-19 2001-07-03 Samsung Electronics Co., Ltd. Thin film transistor array panel and a method for manufacturing the same
JP2001339072A (ja) * 2000-03-15 2001-12-07 Advanced Display Inc 液晶表示装置
KR100494683B1 (ko) * 2000-05-31 2005-06-13 비오이 하이디스 테크놀로지 주식회사 4-마스크를 이용한 박막 트랜지스터 액정표시장치의제조시에 사용하는 할프톤 노광 공정용 포토 마스크
JP4954401B2 (ja) * 2000-08-11 2012-06-13 株式会社半導体エネルギー研究所 半導体装置の製造方法
JP4267245B2 (ja) * 2001-03-14 2009-05-27 エーエスエムエル マスクツールズ ビー.ブイ. 解像度以下の補助フィーチャとして罫線ラダー・バーを利用した光近接補正方法
KR100589041B1 (ko) * 2001-03-30 2006-06-13 삼성전자주식회사 마스크 및 그 형성방법
KR100464204B1 (ko) * 2001-06-08 2005-01-03 엘지.필립스 엘시디 주식회사 그레이톤 마스크 및 이를 이용한 액정디스플레이 제조방법
KR100391157B1 (ko) * 2001-10-25 2003-07-16 엘지.필립스 엘시디 주식회사 액정 표시 장치용 어레이 기판 및 그의 제조 방법
JP2004233861A (ja) * 2003-01-31 2004-08-19 Nikon Corp マスク、露光方法及びデバイス製造方法
KR100903176B1 (ko) * 2003-06-30 2009-06-17 에이에스엠엘 마스크툴즈 비.브이. 서브-하프 파장 리소그래피 패터닝을 위한 개선된스캐터링 바아 opc 적용 방법
JP2005202102A (ja) * 2004-01-15 2005-07-28 Fujitsu Ltd 露光用マスク及びそのパターン補正方法並びに半導体装置の製造方法
JP4480442B2 (ja) * 2004-03-31 2010-06-16 Nec液晶テクノロジー株式会社 液晶表示装置の製造方法
TWI368327B (en) * 2005-01-17 2012-07-11 Samsung Electronics Co Ltd Optical mask and manufacturing method of thin film transistor array panel using the optical mask
JP5110821B2 (ja) * 2005-08-12 2012-12-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7914971B2 (en) * 2005-08-12 2011-03-29 Semiconductor Energy Laboratory Co., Ltd. Light exposure mask and method for manufacturing semiconductor device using the same
CN1949080B (zh) * 2005-10-13 2010-05-12 群康科技(深圳)有限公司 薄膜晶体管的制造装置和制造方法
JP5416881B2 (ja) * 2005-10-18 2014-02-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101211086B1 (ko) * 2006-02-03 2012-12-12 삼성디스플레이 주식회사 박막 트랜지스터 기판과 이의 제조 방법 및 박막트랜지스터 기판 제조용 마스크
KR20080004005A (ko) * 2006-07-04 2008-01-09 삼성전자주식회사 박막 트랜지스터 기판의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1440080A (zh) * 2002-02-22 2003-09-03 日本电气株式会社 沟道蚀刻薄膜晶体管
CN1584718A (zh) * 2003-08-21 2005-02-23 Nec液晶技术株式会社 包括用于减少泄漏电流的tft的lcd设备
CN1655039A (zh) * 2004-02-10 2005-08-17 Nec液晶技术株式会社 薄膜晶体管、使用其的液晶显示器、以及其制造方法

Also Published As

Publication number Publication date
KR100932995B1 (ko) 2009-12-21
US7871743B2 (en) 2011-01-18
JP2009063995A (ja) 2009-03-26
CN101382728A (zh) 2009-03-11
US20090068571A1 (en) 2009-03-12
JP4959631B2 (ja) 2012-06-27
KR20090026022A (ko) 2009-03-11

Similar Documents

Publication Publication Date Title
CN101382728B (zh) 灰阶掩膜版结构
CN101762916B (zh) 阵列基板和液晶面板及其制造方法
KR101024477B1 (ko) 마스크 블랭크 및 포토마스크
US9632366B2 (en) Mask and method of manufacturing photoresist spacers with the mask
CN102707575B (zh) 掩模板及制造阵列基板的方法
US9978595B2 (en) Photo mask and exposure system
KR101071471B1 (ko) 포토마스크 블랭크 및 포토마스크와 그들의 제조 방법
CN103034049A (zh) 金属线及阵列基板的制作方法
KR20130130259A (ko) 컬러필터 기판 및 그 제조방법
CN103034045B (zh) 一种半色调掩模板及其制造方法
CN108508695B (zh) 掩膜板、阵列基板、显示器及阵列基板的制备方法
CN102645839A (zh) 一种掩模板及其制造方法
US7897300B2 (en) Gray scale mask
US20070263288A1 (en) Diffusive Reflecting Structure and Its Manufacturing Method, and Display Device Using It
CN105759564A (zh) 一种掩膜板及其制作方法
CN101373325A (zh) 半色调掩模板结构及其制造方法
CN101650529B (zh) 用于制造tft的掩膜及制造tft的源极/漏极的方法
CN102033345A (zh) 液晶显示器及阵列基板的制造方法
US11099481B2 (en) Mask plate, array substrate, and preparation method thereof
CN106054516A (zh) 一种掩膜板、阵列基板、其制作方法及显示装置
KR20020067889A (ko) 박막 트랜지스터, 액정 표시기 및 그 제조 방법
CN108693698A (zh) 一种光罩及接触孔的制作方法
CN102103323B (zh) 半色调掩模板及其制作方法
CN105261621A (zh) 阵列基板及其制作方法、显示装置
CN109560196B (zh) 显示面板的制备方法及显示面板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY

Effective date: 20141209

Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD

Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD.

Effective date: 20141209

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 100176 DAXING, BEIJING TO: 100015 CHAOYANG, BEIJING

TR01 Transfer of patent right

Effective date of registration: 20141209

Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No.

Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd.

Patentee after: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd.

Address before: 100176 Beijing economic and Technological Development Zone, West Central Road, No. 8

Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100728

Termination date: 20210907