US7871743B2 - Gray scale mask - Google Patents
Gray scale mask Download PDFInfo
- Publication number
- US7871743B2 US7871743B2 US12/128,724 US12872408A US7871743B2 US 7871743 B2 US7871743 B2 US 7871743B2 US 12872408 A US12872408 A US 12872408A US 7871743 B2 US7871743 B2 US 7871743B2
- Authority
- US
- United States
- Prior art keywords
- mask region
- mask
- light
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 42
- 238000000034 method Methods 0.000 description 20
- 239000000758 substrate Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000000873 masking effect Effects 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical group O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910000423 chromium oxide Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
- G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Definitions
- the present invention relates to a gray scale mask, and particularly, to a gray scale mask used for forming the source/drain layer (S/D layer) of a thin film transistor (TFT).
- S/D layer source/drain layer
- TFT thin film transistor
- the array substrate includes a TFT as a switching element for each pixel.
- a five-mask (5Mask) technology is commonly used to form an array substrate comprising TFTs.
- 5Mask five-mask
- 4Mask four-mask
- the masking processes for forming an active layer and for forming a source/drain layer in the 5Mask process are combined into a single one.
- a gray scale photoresist pattern is formed with a mask having combination of slits and light-blocking bars, and the channel of a TFT is formed by performing two etching processes.
- FIG. 9 shows a conventional gray scale mask used for the exposure process for forming the source/drain layer.
- An end of the source mask region 20 is located within the drain mask region 10 of U-shape, so that a U-shaped channel region is formed in the TFT after photolithography and etching.
- a light-blocking bar 60 is arranged along the extending direction of the channel in the region where the channel region is to form. Slits 50 ′ are formed between the light-blocking bar 60 and the source mask region 20 and between the light-blocking bar 60 and the drain mask region 10 , respectively.
- a gray scale photoresist pattern is obtained, of which a relatively flat gray scale photoresist portion (i.e., a photoresist portion whose height is in proportion to that of the photoresist portions for the source/drain, and the ratio of height between the portions is for example 1/2) is formed in the region where the channel region is to form.
- a relatively flat gray scale photoresist portion i.e., a photoresist portion whose height is in proportion to that of the photoresist portions for the source/drain, and the ratio of height between the portions is for example 1/2
- a first etching is performed to obtain a source/drain pattern, and after ashing on the photoresist pattern, a second etching can be performed to obtain the desired channel.
- the intensity of light obtained with the double-slit interference is shown in FIG. 10 .
- non-uniform thickness of the photoresist may be generated in a corner portion, central portion, and/or edge portion of the U-shaped channel region due to the non-uniform intensity of the light passing through the slits and may cause projections at the surface of the above portions of the photoresist pattern. These projections may give rise to residues of the active layer or short circuit in the source/drain layer in the channel of the TFT after etching with the gray scale photoresist pattern.
- a gray scale mask for fabricating a thin film transistor comprising: a source mask region; a drain mask region; and a channel mask region between the source mask region and the drain mask region, wherein a plurality of light-blocking bars are arranged regularly in the channel mask region, and the light-blocking bars are perpendicular to a center line of the channel mask region.
- FIG. 1 is a schematic view showing a U-shaped gray scale mask according to an embodiment of the present invention
- FIG. 2 is a schematic view showing the light intensity produced by the U-shaped gray scale mask of the embodiment
- FIG. 3 is a schematic view showing a strip-shaped gray scale mask according to another embodiment of the present invention.
- FIGS. 4-8 are schematic cross-sectional views showing the processes for fabricating a gray scale mask according to an embodiment of the invention.
- FIG. 9 is a schematic view showing a conventional U-shaped gray scale mask.
- FIG. 10 is a schematic view showing the light intensity produced by the conventional U-shaped gray scale mask.
- FIG. 1 is a schematic view showing a U-shaped gray scale mask according to an embodiment of the present invention.
- the mask 100 is used to form a TFT on an array substrate of a LCD, and particularly, to form the source/drain and the channel of the TFT.
- a source mask region 20 for forming the source of the TFT there are arranged a source mask region 20 for forming the source of the TFT, a drain mask region 10 for forming the drain of the TFT, and a channel mask region 30 for forming the channel of the TFT between the source mask region 20 and the drain mask region 10 .
- a plurality of light-blocking bars 40 are arranged regularly in the channel mask region 30 , and, for example, are perpendicular to the center line of the channel mask region 30 .
- the source mask region 20 and the drain mask region 10 of the gray scale mask 100 are used to form the source and drain of the TFT, respectively.
- the plurality of light-blocking bars 40 are regularly disposed to be perpendicular to the center line of the channel mask region 30 , and slits 50 are formed between the neighboring light-blocking bars 40 .
- incident light passes through the light-blocking bars 40 in the channel mask region 30 , multiple interferences occur among the light beams. Since the light-blocking bars 40 are regularly arranged, uniform light illumination can be obtained under the mask 100 with the slits 50 and the light-blocking bars 40 , as shown in FIG. 2 .
- a semiconductor layer, an ohmic contact layer, and a source/drain metal layer are sequentially deposited on a substrate, and a layer of photoresist is coated on the resultant structure.
- the photoresist is exposed and developed with the mask 100 to form a gray scale photoresist pattern with difference in height on the surface of the photoresist.
- the height of the photoresist in the channel region is a specific fraction of that in the source region and the drain region, e.g., lower than the height of the photoresist in the source region and the drain region which has not been exposed.
- the source/drain metal layer, the ohmic contact layer, and the semiconductor layer are etched for the first time, and then an ashing process is performed on the photoresist pattern to remove the photoresist corresponding to the channel region but retain the photoresist corresponding to the source/drain regions.
- the source/drain metal layer and the ohmic contact layer in the channel region are etched for the second time, so as to form the desired source/drain and channel of the TFT.
- the surface evenness of the channel region after etching is determined by the surface evenness of the photoresist under the mask with the light-blocking bars.
- the light-blocking bars are arranged to extend in the direction of the channel for forming the source/drain layer.
- a plurality of slits on the mask to induce multiple interferences of light.
- the photoresist under mask having the light-blocking bars are illuminated uniformly to reduce the number and size of projections occurring on the photoresist surface, and a photoresist surface with a predetermined height and a high evenness can be obtained.
- a second etching is performed after ashing, and the uniformity of the masking process is improved.
- probability of short circuit occurrence in the source/drain layer due to poor uniformity can be reduced, and a channel with excellent performance can be obtained.
- the light-blocking bars on the mask can be formed in a strip shape to ensure a high uniformity of light after multiple interferences.
- the ends of the light-blocking bars can be shaped into a wedge angle or a trapezoid, i.e., the ends of the light-blocking bars contact the source/drain mask regions in a form of an angle to some extent, so that the ends of the light-blocking bars contact the source/drain mask regions with a relatively small area.
- the plurality of light-blocking bars are arranged to cause the projections of the photoresist discretely distributed, and the ends of the light-blocking bars contact the source/drain mask regions in a form of an angle, the source/drain residues formed in the following processes cannot contact the source/drain, which in turn reduces the probability of short circuit occurrence in the source/drain layer and improves the uniformity of the channel.
- the sides of the light-blocking bars may be formed in a curve.
- the light-blocking bars may be in an oval or elliptical shape as a whole.
- the drain mask region 10 is U-shaped, an end of the source mask region 20 is rectangular and extends into the U-shaped drain mask region 10 , so that channel mask region 30 is formed between the internal side of the source mask region 20 and that of the U-shaped drain mask region 10 .
- a plurality of light-blocking bars 40 are arranged in the channel mask region 30 and each is perpendicular to the center line of the channel mask region 30 .
- the ends of the light-blocking bars 40 contact with the source mask region 20 and the drain mask region 10 with an angle ⁇ , that is, an angle between the side of the end of the light-blocking bar 40 and the side of the source mask region 20 or that of the U-shaped drain mask region 10 , as shown in FIG. 1 .
- the angle ⁇ is preferably about 20° to 70°.
- the light-blocking bars have a width “a” of about 1 ⁇ m to 3 ⁇ m.
- the light-blocking bars are arranged regularly and have a spacing “b” of about 1 ⁇ m to 3 ⁇ m therebetween.
- the light-blocking bars are formed with a width the same as that of the slits, that is, the width “a” is equal to the spacing “b.”
- FIG. 3 is a schematic view showing a strip-shaped gray scale mask 200 according to another embodiment of the invention.
- Both the drain mask region 10 and the source mask region 20 have a rectangular end and the ends are arranged opposite to each other.
- the channel mask region 30 is formed between the adjacent rectangular ends of the drain mask region 10 and the source mask region 20 .
- a plurality of light-blocking bars 40 are arranged along the direction perpendicular to the opposing ends of the drain mask region 10 and the source mask region 20 .
- the ends of the light-blocking bars 40 can contact with the drain mask region 10 and the source mask region 20 with an angle ⁇ .
- the angle ⁇ is preferably about 20° to 70°.
- the light-blocking bars have a width “a” of about 1 ⁇ m to 3 ⁇ m, and the light-blocking bars are arranged regularly and have a spacing “b” of about 1 ⁇ m to 3 ⁇ m, similar to the above embodiment.
- the light-blocking bars are arranged with a width the same as that of the slits, that is, the width “a” is equal to the spacing “b.”
- a layer of metal thin film 2 is deposited on a transparent substrate 1 , e.g. a glass substrate, by magnetron sputtering.
- the metal thin film 2 may be a chromium (Cr) film.
- the metal thin film 2 can be replaced with a chromium oxide (CrO x ) film.
- FIG. 6 is a top view showing the pattern to be formed on the substrate 1 .
- the photoresist pattern includes the following pattern regions: the photoresist drain mask region 10 ′, the photoresist source mask region 20 ′, the photoresist channel mask region 30 ′ between the photoresist drain mask region 10 ′ and the photoresist source mask region 20 ′, and a plurality of photoresist light-blocking bars 40 ′ in the photoresist channel mask region 30 ′.
- the photoresist light-blocking bars 40 ′ are arranged perpendicular to the center line of the photoresist channel mask region 30 ′.
- an etching process is performed, so that the metal thin film 2 only remains under the photoresist pattern 3 .
- the resultant mask includes a drain mask region 10 for forming the drain, a source mask region 20 for forming the source, a channel mask region 30 between the drain mask region 10 and the source mask region 20 , and a plurality of light-blocking bars 40 in the channel mask region 30 , for example, as shown in FIG. 1 .
- the light-blocking bars 40 are arranged perpendicular to the center line of the channel mask region 30 .
- the manufacturing process for a strip-shaped gray scale mask is similar to that described above with respect to a U-shaped gray scale mask, except the specific pattern of the photoresist, and the photoresist layer can be formed to have corresponding pattern as necessary.
Abstract
Description
Claims (12)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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CN200710121531.6 | 2007-09-07 | ||
CN200710121531 | 2007-09-07 | ||
CN2007101215316A CN101382728B (en) | 2007-09-07 | 2007-09-07 | Gray level mask plate structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090068571A1 US20090068571A1 (en) | 2009-03-12 |
US7871743B2 true US7871743B2 (en) | 2011-01-18 |
Family
ID=40432214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/128,724 Expired - Fee Related US7871743B2 (en) | 2007-09-07 | 2008-05-29 | Gray scale mask |
Country Status (4)
Country | Link |
---|---|
US (1) | US7871743B2 (en) |
JP (1) | JP4959631B2 (en) |
KR (1) | KR100932995B1 (en) |
CN (1) | CN101382728B (en) |
Cited By (2)
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US20110053323A1 (en) * | 2009-08-31 | 2011-03-03 | Au Optronics Corp. | Photomask and method for fabricating source/drain electrode of thin film transistor |
US9921471B2 (en) | 2014-09-24 | 2018-03-20 | Micron Technology, Inc. | Methods of forming photonic device structures |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102655175B (en) * | 2012-04-06 | 2014-07-02 | 京东方科技集团股份有限公司 | TFT (thin film transistor), array base plate, display device and mask plate for preparing TFT |
CN102799059B (en) * | 2012-08-15 | 2014-10-15 | 京东方科技集团股份有限公司 | Grayscale mask, array substrate and its preparation method thereof, and display device |
KR101949389B1 (en) * | 2012-11-07 | 2019-02-18 | 엘지디스플레이 주식회사 | Method of forming pattern using mask-less exposure equipment |
CN103969940A (en) * | 2014-04-22 | 2014-08-06 | 京东方科技集团股份有限公司 | Phase shift mask plate and source drain mask plate |
CN104765245A (en) * | 2015-04-10 | 2015-07-08 | 深圳市华星光电技术有限公司 | Gray-tone mask and preparation method thereof |
WO2019082380A1 (en) * | 2017-10-27 | 2019-05-02 | シャープ株式会社 | Gray tone mask |
CN109541829B (en) * | 2018-12-19 | 2021-08-24 | 惠科股份有限公司 | Mask, liquid crystal panel and liquid crystal display device |
CN113759655A (en) * | 2021-08-19 | 2021-12-07 | 惠科股份有限公司 | Mask, manufacturing method of array substrate and display panel |
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-
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- 2008-05-29 US US12/128,724 patent/US7871743B2/en not_active Expired - Fee Related
- 2008-05-29 KR KR1020080050458A patent/KR100932995B1/en active IP Right Grant
- 2008-05-29 JP JP2008141724A patent/JP4959631B2/en not_active Expired - Fee Related
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US20110053323A1 (en) * | 2009-08-31 | 2011-03-03 | Au Optronics Corp. | Photomask and method for fabricating source/drain electrode of thin film transistor |
US8153337B2 (en) * | 2009-08-31 | 2012-04-10 | Au Optronics Corp. | Photomask and method for fabricating source/drain electrode of thin film transistor |
US8530144B2 (en) | 2009-08-31 | 2013-09-10 | Au Optronics Corp. | Photomask and method for fabricating source/drain electrode of thin film transistor |
US9921471B2 (en) | 2014-09-24 | 2018-03-20 | Micron Technology, Inc. | Methods of forming photonic device structures |
US10663859B2 (en) | 2014-09-24 | 2020-05-26 | Micron Technology, Inc. | Methods of forming photonic device structures and electronic devices |
Also Published As
Publication number | Publication date |
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CN101382728A (en) | 2009-03-11 |
US20090068571A1 (en) | 2009-03-12 |
KR100932995B1 (en) | 2009-12-21 |
CN101382728B (en) | 2010-07-28 |
JP4959631B2 (en) | 2012-06-27 |
KR20090026022A (en) | 2009-03-11 |
JP2009063995A (en) | 2009-03-26 |
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