CN113759655A - Mask, manufacturing method of array substrate and display panel - Google Patents
Mask, manufacturing method of array substrate and display panel Download PDFInfo
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- CN113759655A CN113759655A CN202110957387.XA CN202110957387A CN113759655A CN 113759655 A CN113759655 A CN 113759655A CN 202110957387 A CN202110957387 A CN 202110957387A CN 113759655 A CN113759655 A CN 113759655A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
- G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
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Abstract
The invention discloses a mask, a manufacturing method of an array substrate and a display panel. Wherein, the mask includes: the device comprises a first exposure area corresponding to the channel area, a second exposure area located on one side of the first exposure area and used for forming a source electrode, a third exposure area located on the other side opposite to the first exposure area and used for forming a drain electrode, and a fourth exposure area located on the edge of the second exposure area and not overlapped with the first exposure area, wherein the first exposure area and the fourth exposure area are semi-transparent areas. In the process of exposure and development of the mask plate, part of the light resistance can be left in the areas corresponding to the first exposure area and the fourth exposure area, and the area where the channel is to be formed and the area where the source electrode is to be formed are protected, so that the processing size of the source electrode is ensured, and the stability of parasitic capacitance formed by the source electrode and the grid electrode is improved.
Description
Technical Field
The invention relates to the technical field of display panel preparation, in particular to a mask, a manufacturing method of an array substrate and a display panel.
Background
Because a Thin film transistor liquid crystal display (TFT-LCD) has the advantages of low radiation, small volume, low energy consumption, etc., it is widely applied to various electronic information products. With the development of technology, the quality of TFT-LCD is required to be higher and higher in the market, and the improvement of the quality of the display screen is the key to improve the quality, wherein the parasitic capacitance Cgs between the source and the gate in the TFT switch design has a large influence on the quality of the display screen. At present, the switch design of the TFT adopts a four-pass lithography (4mask) design, the peripheral position of the source needs to be etched twice in the etching process, the loss of the critical dimension is large, generally 1 um-2 um, and due to the difference between the two etching solutions and the etching time, the loss of the dimension of the source of the TFT switch in different display areas is large, so that the difference of the parasitic capacitance Cgs in different places is large.
Disclosure of Invention
The invention mainly aims to provide a mask plate, which can enable part of light resistance to remain at the peripheral edges of a channel region to be formed and a source electrode to be formed in the exposure and development processes by ashing the parts of the mask plate corresponding to the channel region and the peripheral edges of the source electrode, so as to protect the light resistance, effectively reduce the critical dimension loss of the peripheral edge of the source electrode, and aim to solve the problem of large difference of parasitic capacitance between the source electrode and a grid electrode at different positions.
In order to achieve the above object, the mask provided by the present invention is used for preparing an array substrate, the array substrate includes a thin film transistor, the thin film transistor includes a gate, a source, and a drain arranged at an interval, a channel region is formed between the source and the drain, and the mask includes:
the device comprises a first exposure area corresponding to the channel area, a second exposure area located on one side of the first exposure area and used for forming a source electrode, a third exposure area located on the other side opposite to the first exposure area and used for forming a drain electrode, and a fourth exposure area located on the edge of the second exposure area and not overlapped with the first exposure area, wherein the first exposure area and the fourth exposure area are semi-transparent areas.
In an embodiment of the present application, the second exposure region is in a long strip shape, and the fourth exposure region is disposed at a position where a long edge of the second exposure region corresponds to the source and the gate overlapping each other.
In an embodiment of the present application, a length of a portion of the fourth exposure region not corresponding to the gate is L, where L is greater than or equal to 1.5 μm.
In an embodiment of the present application, a width of the fourth exposure region in a direction perpendicular to the source length direction ranges from 0.5 μm to 2 μm;
and/or the fourth exposure area and the second exposure area are arranged without gaps.
In an embodiment of the present application, the mask is a halftone mask, the light transmittance at each position of the first exposure area is the same, the light transmittance at each position of the fourth exposure area is the same, and the light transmittance of the first exposure area is the same as the light transmittance of the fourth exposure area.
In an embodiment of the present application, the first exposure region includes a first full-transmission portion and a first cover portion, and the first full-transmission portion and the first cover portion are spaced apart from each other in an extending direction perpendicular to the first exposure region; the fourth exposure area comprises a second full-transparent part and a second cover part, and the second full-transparent part and the second cover part are arranged at intervals in the extending direction perpendicular to the fourth exposure area.
In an embodiment of the present application, the first covering portion and the second covering portion are both in a long strip shape, and the width range of the first covering portion and the width range of the second covering portion are both 0.6 μm to 1 μm; the width ranges of the first full-transparent part and the second full-transparent part are both 0.6-1 mu m;
and/or the first covering part and the second covering part are made of chromium.
The invention also provides a method for manufacturing an array substrate by adopting the mask, which comprises the following steps:
providing a substrate, and sequentially forming a grid electrode, a grid electrode insulating layer, a semiconductor layer, a metal layer and a light resistance layer on the substrate from bottom to top, wherein a channel region is arranged at the position of the semiconductor layer corresponding to the grid electrode;
arranging the mask above the light resistance layer, and exposing and developing the light resistance layer;
carrying out first etching to remove the metal layer and the semiconductor layer which are not covered by the photoresist layer;
performing ashing process to remove the photoresist layer of the channel region and the photoresist layer of the fourth exposure region;
and performing second etching to remove the metal layer and part of the semiconductor layer in the channel region and the metal layer and the semiconductor layer in the fourth exposure region, and forming an active layer, and a source electrode and a drain electrode which are contacted with two ends of the active layer and are arranged at intervals.
The invention further provides a display panel which comprises a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are arranged in a box-to-box mode, and the array substrate is prepared by adopting the manufacturing method of any one of the array substrates.
In the technical scheme of the invention, the first exposure region of the mask corresponding to the channel region between the drain and the source is a semi-transparent region, and the fourth exposure region corresponding to the periphery of the source to be formed is also set as the semi-transparent region. Therefore, when the mask is used for manufacturing the array substrate, in the process of exposure and development, partial photoresist is left in the areas corresponding to the first exposure area and the fourth exposure area, the channel area to be formed and the area around the source electrode to be formed are protected, the etched probability is reduced, the size loss of the channel area and the size loss of the source electrode are effectively reduced, the processing size of the source electrode is ensured, the parasitic capacitance formed between the source electrode and the grid electrode is stable, the difference between the parasitic capacitances at different positions is small, the problems of bright and dark lines, uneven display, residual shadows and the like of pictures are solved, and the picture quality is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic top view of a mask according to an embodiment of the present disclosure;
FIG. 2 is a top view of another embodiment of a reticle of the first embodiment of the present application;
FIG. 3 is a top view of a mask according to another embodiment of the present disclosure;
FIG. 4 is a schematic top view illustrating the application of the mask shown in FIG. 1 to an array substrate according to one embodiment of the present disclosure;
fig. 5 is a flowchart illustrating a method for manufacturing an array substrate according to a second embodiment of the present application;
fig. 6 is a cross-sectional view of the array substrate corresponding to step S1 in the method for manufacturing the array substrate shown in fig. 5 according to the second embodiment of the present application;
fig. 7 is a cross-sectional view of the array substrate corresponding to steps S2 and S3 in the method for manufacturing the array substrate shown in fig. 5 according to the second embodiment of the present application;
fig. 8 is a cross-sectional view of the array substrate corresponding to step S4 in the method for manufacturing the array substrate shown in fig. 5 according to the second embodiment of the present application;
fig. 9 is a cross-sectional view of the array substrate corresponding to step S5 in the method for manufacturing the array substrate shown in fig. 5 according to the second embodiment of the present application;
fig. 10 is a cross-sectional view of a third display panel according to an embodiment of the present application.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
200 | |
| 10 | |
201 | |
| 20 | |
2011 | First full- |
| 30 | |
2013 | |
| 40 | |
203 | |
| 41 | |
205 | |
| 43 | Active layer | 207 | A |
| 50 | |
2071 | Second full- |
| 51 | |
2073 | |
| 53 | Drain electrode | 209 | A |
| 60 | The |
300 | |
| 80 | |
400 | |
| 90 | |
500 | Liquid crystal layer |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The first embodiment is as follows:
the invention provides a mask 200 for manufacturing an array substrate.
Referring to fig. 1 to 4, it can be known that the array substrate includes a thin film transistor, the thin film transistor includes a gate, a source 51 and a drain 53 that are disposed at intervals, and a channel region 41 is formed between the source 51 and the drain 53. The reticle 200 includes: a first exposure region 201 corresponding to the channel region 41, a second exposure region 203 located at one side of the first exposure region 201 and used for forming a source 51, a third exposure region 205 located at the other side opposite to the first exposure region 201 and used for forming a drain 53, and a fourth exposure region 207 located at a partial edge of the second exposure region 203 and not overlapped with the first exposure region 201, wherein the first exposure region 201 and the fourth exposure region 207 are semi-transparent regions.
Here, in order to form a tft with a desired shape, that is, the source electrode 51 and the drain electrode 53 located above the gate electrode and the channel region therebetween, a part of the mask 200 needs to be transparent, and a part of the mask needs to be opaque or semi-transparent. In order to increase the charging rate and display effect of the array substrate 100, the width-to-length ratio of the channel region 41 is generally designed to be as large as possible, and the opening of the channel region 41 is substantially U-shaped, so that the first exposure region 201 is U-shaped. The second exposure region 203 corresponds to the position of the source 51, so that the second exposure region 203 is substantially rectangular, is located in the space enclosed by the channel region 41, and extends towards the opening side of the channel region 41, and the formed source 51 is conveniently connected with the data line 80. The third exposed region 205 corresponds to the position of the drain 53, so the drain 53 is also U-shaped, thereby enclosing a U-shaped channel. Of course, in other embodiments, the opening of the channel region 41 may also be semicircular, rectangular, or other shapes, and in this case, the drain 53 may be rectangular, directional, or semicircular. Referring to fig. 1 and 2, the fourth exposure region 207 is at a partial edge of the second exposure region 203 and does not overlap with the first exposure region 201, for example, at an edge position on one side or both sides of the source 51.
Parasitic capacitance is formed between the source 51 and the gate located right below and spaced apart from the source 51, that is, the parasitic capacitance is formed in a projection range of the source 51 on the gate, and therefore, the size of the source 51 affects the magnitude of the parasitic capacitance. The mask 200 is provided with the first exposure region 201 and the fourth exposure region 207 which are both semi-transparent regions, and no matter whether the used photoresist is a positive photoresist or a negative photoresist, after exposure and development, the photoresist corresponding to the first exposure region 201 and the fourth exposure region 207 can be partially washed off and partially left, so that the size loss of the outer peripheries of the channel region 41 and the source 51 can be reduced in the subsequent etching process.
In the technical solution of the present invention, the first exposure region 201 of the mask 200 corresponding to the channel region 41 between the drain 53 and the source 51 is a semi-transparent region, and the periphery corresponding to the source 51 to be formed, that is, the fourth exposure region 207 is also set as a semi-transparent region. Thus, when the mask 200 is used for manufacturing an array substrate, in the process of exposure and development, a part of photoresist is left in the corresponding regions of the first exposure region 201 and the fourth exposure region 207, namely, the region to be formed with the channel region 41 and the region to be formed with the edge of the source 51 are protected, the probability of being etched is reduced, the size loss of the edge of the channel region 41 and the edge of the source 51 is effectively reduced, and the processing size of the source 51 is ensured.
In addition, in order to ensure the size of each position of the drain electrode 53, the outer peripheral edge of the third exposure region 205 may be a semi-transparent region, so as to ensure the processing size of the drain electrode 53, and increase the aperture ratio of the array substrate without occupying the area of the display region.
With reference to fig. 1, in an optional embodiment of the present application, on the basis of the first embodiment, the second exposure region 203 is in a long strip shape, and the fourth exposure region 207 is disposed at a position where a long edge of the second exposure region 203 corresponds to the source 51 and the gate overlapping each other.
In this embodiment, the second exposure region 203 is in a long strip shape, so the source 51 formed on the corresponding array substrate is also in a long strip shape and extends outward from the channel region 41. In the length direction, the projection of the end of the source 51 far from the channel region 41 on the gate is located outside the gate, so that the width of the source 51 is only required to ensure the size of the parasitic capacitance formed by the source 51 and the gate. Therefore, the fourth exposure regions 207 are disposed at the two long edges of the second exposure region 203, and the fourth exposure regions 207 are disposed corresponding to the overlapping positions of the source 51 and the gate, where the overlapping position of the source and the gate is the region where a is located, that is, the fourth exposure regions 207 are located at the two sides of the region a, so that the edge of the source 51 where the parasitic capacitance is formed can be protected more accurately, the size loss of the edge position of the source 51 is reduced, the accuracy of the critical dimension of the source 51 is improved, and the difference of the parasitic capacitance between the plurality of display regions is effectively reduced.
Referring to fig. 4, in an alternative embodiment of the present application, on the basis of the first embodiment, a length of a portion of the fourth exposure region 207 not corresponding to the gate is L, where L is greater than or equal to 1.5 μm.
In this embodiment, in order to further ensure the stability of the parasitic capacitance between the source 50 and the gate, the fourth exposure region 207 is extended along the length direction of the source 51 toward the end away from the channel region 41, that is, the extended portion of the fourth exposure region 207 is not corresponding to the gate, where the portion of the source 51 not corresponding to the gate is set as a B region, that is, the projection of the end of the fourth exposure region 207 away from the channel region 41 on the gate is located outside the gate, that is, at two sides of the B region, so as to extend the length of the photoresist capable of ensuring the small width dimension of the source 51, thereby preventing the unstable overlapping area of the source 51 with the gate when the source 51 moves towards the channel region 41 in the extending direction during the processing, and further improving the dimensional stability of the parasitic capacitance between the source 51 and the gate.
Here, the length of the portion of the fourth exposure region 207 not corresponding to the gate electrode is set to L, and the value of L is not excessively large in order to reduce the manufacturing cost of the mask 200, and certainly, the value of L is not excessively small in order to ensure the stability of the parasitic capacitance, so that the length of L is set to be 1.5 μm or more, for example, 1.5 μm, 2 μm, 3 μm, and the like, thereby ensuring the stability of the parasitic capacitance and saving the cost.
In an embodiment of the present application, the width of the fourth exposure region 207 in a direction perpendicular to the length direction of the source 51 is in a range of 0.5 μm to 2 μm;
and/or the fourth exposure region 207 is disposed without a gap from the second exposure region 203.
In this embodiment, in order to ensure the size of the edge of the source 51 as much as possible, the fourth exposure region 207 and the second exposure region 203 are disposed without a gap, so that the excessive etching and the size loss of the edge of the source 51 caused by the etching solution entering the gap during etching can be avoided, and the stability of the size of the source 51 can be effectively improved.
Here, in the direction perpendicular to the length direction of the source 51, the width range of the fourth exposure region 207 should not be too large, otherwise the processing cost for manufacturing the mask 200 is increased, and certainly, the width range of the fourth exposure region 207 should not be too small, otherwise, the loss rate of the critical dimension of the source 51 cannot be reduced. Therefore, the width of the fourth exposure region 207 is set to be 0.5 μm to 2 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, etc., so that the edge of the source 51 can be well protected, the loss of the critical dimension can be reduced, the cost can be effectively saved, the inaccurate dimension of the source 51 caused by the small etching dimension can be avoided, and the design dimension of the source 51 can be effectively ensured.
In addition, it can be understood that, the width of the channel region 41 is generally set to be 3 to 5 μm, in order to ensure the width of the channel region 41, the first exposure region is a semi-transparent region, which is protected by the photoresist that is not completely etched, and here, the width of the first exposure region 201 is set to be 3 to 5 μm, for example, 3 μm, 4 μm or 5 μm, which matches the width of the channel region 41, and the second exposure region 203 is disposed without a gap from the first exposure region 201, and the third exposure region 205 is disposed without a gap from the first exposure region 201, thereby ensuring the width of the channel region 41 and the charging rate of the array substrate 100.
Referring to fig. 1 again, in an embodiment of the present disclosure, the mask 200 is a halftone mask, light transmittances of positions of the first exposure region 201 are the same, light transmittances of positions of the fourth exposure region 207 are the same, and the light transmittance of the first exposure region 201 is the same as the light transmittance of the fourth exposure region 207.
In this embodiment, the Mask 200 is a halftone Mask (HTM) that combines two exposure processes into one, and one exposure process is omitted, so as to shorten the production period, improve the production efficiency, and reduce the production cost. Here, the light transmittance at each position of the first exposure region 201 of the reticle 200 is the same, and the light transmittance at each position of the fourth exposure region 207 is the same. Meanwhile, in order to ensure the etching consistency, the light transmittance of the first exposure region 201 and the light transmittance of the fourth exposure region 207 are set to be the same, so that the thicknesses of the portions of the photoresist which are reserved after exposure and development are approximately the same, and then in the subsequent patterning process, a more consistent etching rate can be obtained at the same time, so that the peripheral size of the source electrode 51 can be ensured while a more accurate channel size is obtained, the loss is reduced, the design size of the thin film transistor is reduced, and the dimensional stability of a parasitic capacitor formed by the source electrode 51 and the grid electrode is ensured.
Specifically, the light transmittance of the first and fourth exposure regions 201 and 207 may be 30% to 50%, for example, 30%, 34%, 40%, etc., thereby obtaining a superior protective effect.
Referring to fig. 3 again, in another embodiment of the present application, the first exposure region 201 includes a first full-transparent portion 2011 and a first cover portion 2013, and the first full-transparent portion 2011 and the first cover portion 2013 are spaced apart from each other in a direction perpendicular to an extending direction of the first exposure region 201; the fourth exposure region 207 includes a second full-transparent portion 2071 and a second cover portion 2073, and the second full-transparent portion 2071 and the second cover portion 2073 are spaced apart from each other in a direction perpendicular to the extending direction of the fourth exposure region 207.
In this embodiment, the Mask 200 is a Gray Tone Mask (GTM), that is, the first exposure region 201 includes a first full transparent portion 2011 and a first covering portion 2013, the first full transparent portion 2011 is a portion through which light can pass completely, that is, the glass substrate is not processed, and thus the first full transparent portion 2011 can be formed. The first cover 2013 is a light-tight part, so that part of light can be shielded for exposure, and light entering from the first full-transmission part 2011 is diffracted to reduce light transmittance. Thus, in the extending direction perpendicular to the first exposure region 201, the first cover portions 2013 and the first full-transparent portions 2011 are arranged at intervals, so that the whole region of the first exposure region 201 has a semi-transparent effect, and therefore partial light resistance can be reserved for the light resistance corresponding to the first exposure region 201, so that the part to be formed into the channel region 41 is protected, the size loss of the channel region is effectively reduced, and the size of the channel region 41 is ensured.
Similarly, the fourth exposure region 207 is also provided with a second full-transparent part 2071 and a second covering part 2073, where the second full-transparent part 2071 has the same structure as the first full-transparent part 2011, the second covering part 2073 has the same structure as the first covering part 2013, and is used for shading and diffracting light, and the second full-transparent part 2071 and the second covering part 2073 are arranged at an interval, so that the fourth exposure region 207 also forms a semi-transparent effect. Therefore, a part of the photoresist can be reserved at the part corresponding to the fourth exposure region 207, the edge position of the source electrode 51 to be formed is protected, the size loss of the source electrode is effectively reduced, the width size of the source electrode 51 is ensured, and the stability of the parasitic capacitance is further realized.
In an embodiment of the present application, each of the first cover part 2013 and the second cover part 2073 has a long bar shape, and each of the first cover part 2013 and the second cover part 2073 has a width in a range of 0.6 μm to 1 μm; the width ranges of the first full-transparent part 2011 and the second full-transparent part 2071 are both 0.6-1 μm;
and/or the first cover part 2013 and the second cover part 2073 are both made of chromium.
In this embodiment, in order to further improve the light transmission uniformity of the first exposure region 201 and the fourth exposure region 207, the first masking part 2013 and the second masking part 2073 are both set to be strip-shaped, and the widths of the first masking part 2013 and the first full-transmission part 2011 are set to be the same, so that the proportion of the light transmission region and the light non-transmission region of the first exposure region 201 is ensured to be the same, the reserved amount of the photoresist in the extending direction of the channel region 41 is ensured to be the same, and the size etching of the channel region 41 is more uniform. Similarly, the width of the second cap 2073 is the same as the width of the second fully transparent part 2071, so that the ratio of the transparent region to the opaque region of the fourth exposure region 207 is the same, the same amount of photoresist in the extending direction of the source 51 is ensured, the etching of the edge of the source 51 is uniform, and the difference of the parasitic capacitances in different regions is reduced. Meanwhile, optionally, the width of the first covering part 2013 and the width of the second covering part 2073 are the same, so that the processing can be performed in one process, the operation is convenient and fast, and the processing efficiency is effectively improved.
Specifically, the width of the first cap 2013 and the width of the second cap 2073 are both set to be in the range of 0.6 μm to 1 μm, for example, 0.6 μm, 0.8 μm, 1 μm, etc., and the width of the first full transmission part 2011 and the width of the second full transmission part 2071 are both set to be in the range of 0.6 μm to 1 μm, for example, 0.6 μm, 0.8 μm, 1 μm, etc., so that the dimensional loss ratio of the edge of the source 51 is minimized, and the stability of the parasitic capacitance formed with the gate is improved. Of course, the width of the first cover part 2013 and the second cover part 2073 may be different, or the width of the first full-transparency part 2011 and the width of the second full-transparency part 2071 may be different, as in the other embodiments.
Here, the material of the first covering portion 2013 and the second covering portion 2073 is chromium, that is, a chromium layer is coated on the glass substrate, so that the first covering portion 2013 and the second covering portion 2073 are formed, the structural stability of the material is good, and the shading effect is effectively ensured.
Furthermore, optionally, for the design of the reticle 200, a fifth exposure region 209 is also provided on the side of the fourth exposure region 207 facing away from the third exposure region 205. Here, the fifth exposure region 209 and the fourth exposure region 207 are also disposed without a gap, so that the size of the fourth exposure region 207 can be easily changed when necessary, thereby satisfying the process protection for array substrates 100 of different sizes.
Of course, in other embodiments, the fifth exposure area 209 may not be set for saving material.
Example two:
referring to fig. 5 to 9, the present invention further provides a method for manufacturing an array substrate by using the mask of any of the above embodiments, including the following steps:
please refer to fig. 6, step S1: providing a substrate 10, and sequentially forming a gate 20, a gate insulating layer 30, a semiconductor layer 40, a metal layer 50 and a photoresist layer on the substrate 10 from bottom to top, wherein a channel region 41 is formed in a position of the semiconductor layer 40 corresponding to the gate 20.
It can be understood that the array substrate 100 is a multi-layer structure, and each layer of structure is formed by stacking a coating process, an exposure process, a development process and an etching process, and can be completed by four photolithography (4MASK) processes. Specifically, the array substrate 100 includes a substrate 10, the substrate 10 provides a basic carrier, and the substrate 10 is transparent, and the material of the substrate may be a transparent glass plate or a quartz plate, which is not limited herein, and does not affect the penetration of the backlight source. Since the substrate 10 is not conductive, a medium for displaying, such as liquid crystal, needs to be driven by electrons for movement and arrangement, the array substrate 100 further includes conductive Data lines 80 (DL), scan lines 90 (SL), thin film transistors (TFT switches), Pixel Electrodes (PE), and the like. Looking down the array substrate 100, the data lines 80 and the scan lines 90 are arranged in a crossed manner to divide the array substrate 100 into a plurality of pixel regions, each of the regions is provided with a corresponding pixel electrode and a corresponding thin film transistor, the data lines 80 and the scan lines 90 are opaque, so that the portions of the data lines and the scan lines form a non-display region of the pixel regions, the thin film transistors are also arranged in the non-display region, and the pixel electrodes form a display region of the pixel regions.
First, a gate 20 is formed on a substrate 10 by a first photolithography process, which includes depositing a metal layer on the substrate 10, and patterning the metal layer through a mask to form the gate 20 on the substrate 10. Here, the process of patterning through the mask is to deposit photoresist on the metal layer, expose and develop after being covered by the mask, and then form the gate 20 by etching, and at the same time, form the scan line 90 on the same layer as the gate 20, the scan line 90 is connected with the gate 20, so as to provide on/off voltage for the thin film transistor. The material of the metal layer is an opaque conductive metal material, such as one or a combination of molybdenum, titanium, chromium, and aluminum, which is not limited herein. Then, a gate insulating layer 30 is deposited on the surfaces of the substrate 10, the gate electrode 20 and the data line 80, wherein the material of the gate insulating layer 30 may be one or more of silicon oxide and silicon nitride.
Since the active layer 43 is made of a semiconductor, the semiconductor layer 40 is formed, and a material of the semiconductor layer 40 may be selected from amorphous silicon, polycrystalline silicon, and the like. The material of the metal layer 50 may be the same as that of the metal layer forming the gate, for example, titanium, chromium, etc., and the semiconductor layer 40, the metal layer 50, and the photoresist layer 60 are sequentially deposited on the surface of the gate insulating layer 30, and the layout areas of the three layers may be the same. The channel region 41 for forming the channel may be marked corresponding to the position of the gate electrode 20 in advance when the semiconductor layer 40 is deposited, thereby facilitating the subsequent placement of the reticle 200.
Please refer to fig. 7, step S2: the mask 200 is disposed above the photoresist layer 60, and the photoresist layer 60 is exposed and developed.
Here, the mask 200 may be disposed above the photoresist layer 60 such that the first exposure region 201 corresponds to the channel region 41 of the semiconductor layer 40. When the photoresist layer 60 is a positive photoresist, the photoresist layer 60 corresponding to the transparent region can be changed in properties by exposure to light, and can be washed away after development, while the photoresist layer 60 corresponding to the opaque region can be left. According to this characteristic, the first exposure region 201 of the reticle 200 corresponding to the channel region 41 is set as a semi-transparent region, and after exposure and development, the photoresist layer 60 corresponding to the first exposure region 201 can be partially washed away and partially left, so that the size loss of the channel region 41 can be reduced in the subsequent etching process. The second exposure region 203 corresponding to the source 51 and the third exposure region 205 corresponding to the drain 53 are required to be opaque regions, so that the corresponding photoresist layer 60 can be left. The fifth exposed region 209 is a fully transparent region, so that the photoresist layer 60 in the fifth exposed region 209 can be washed away by development after receiving light. Meanwhile, in order to also protect the edge size of the source electrode 51, the fourth exposure region 207 is also set as a semi-transparent region, so that after exposure and development, the photoresist layer 60 corresponding to the remaining portion is on the outer periphery of the metal layer 50 where the source electrode 51 is to be formed.
Of course, in other embodiments, when the photoresist layer 60 is a negative photoresist, the second exposure region 203 and the third exposure region 205 are transparent regions, and the fifth exposure region 209 is an opaque region.
Please refer to fig. 7, step S3: performing a first etching to remove the metal layer 50 and the semiconductor layer 40 uncovered by the photoresist layer 60;
here, the portion not covered by the photoresist layer 60 is the exposed portion, and when the metal layer 50 and the semiconductor layer 40 are both laid on the whole pixel unit, the covered area of the mask 200 does not involve the edge area of the fourth exposure region 207, so that the metal layer 50 and the semiconductor layer 40 at the edge of the fourth exposure region 207 can be removed by the etching solution during the first etching.
Referring to fig. 8, step S4: performing an ashing process to remove the photoresist layer 60 in the channel region 41 and the photoresist layer 60 in the fourth exposure region 207; the ashing process is a plasma ashing process selected to remove the photoresist layer 60 in the channel region 41 and the fourth exposed region 207, i.e., the photoresist layer 60 left after development.
Referring to fig. 9, step S5: and performing second etching to remove the metal layer and part of the semiconductor layer of the channel region 41 and the metal layer and the semiconductor layer of the fourth exposure region, and forming an active layer, and source and drain electrodes which are in contact with two ends of the active layer and are arranged at intervals.
Here, the metal layer 50 and a portion of the semiconductor layer 40 of the channel region 41, and the metal layer 50 and the semiconductor layer 40 of the fourth exposure region 207 are etched away, and the active layer 43, the source electrode 51 and the drain electrode 53 which are in contact with both ends of the active layer 43 and are spaced apart are formed. The etching here may be selected as dry etching, removing the metal layer 50 corresponding to the first exposure region 201 and partially removing the semiconductor layer 40 corresponding to the first exposure region 201, and simultaneously removing the metal layer 50 and the semiconductor layer 40 corresponding to the fourth exposure region 207 and exposing the edge of the source electrode 51.
Of course, it is finally necessary to remove the photoresist layer 60 completely remained corresponding to the opaque region, so as to form the final active layer 43 on the gate insulating layer 30, and the spaced apart source and drain electrodes 51 and 53 on the active layer 43.
In the manufacturing method of the array substrate according to the technical scheme of the invention, the gate electrode 20 and the gate insulating layer 30 are formed, then the semiconductor layer 40, the metal layer 50 and the photoresist layer 60 are laid, and a mask 200 is provided, wherein the first exposure region 201 of the mask 200, which corresponds to the channel region 41 of the semiconductor layer 40, is a semi-transparent region, and corresponds to the edge of the source electrode 51 to be formed, that is, the fourth exposure region 207 is also set as a semi-transparent region. Thus, in the process of performing exposure and development, a part of the photoresist layer 60 remains in the first exposure region 201 and the fourth exposure region 207, and the semiconductor layer 40 and the metal layer 50 are protected, so that in the process of patterning the semiconductor layer 40 and the metal layer 50, the size loss of the channel region 41 and the edge of the source electrode 51 can be effectively reduced, the processing size of the source electrode 51 can be ensured, the stability of a parasitic capacitor formed between the source electrode 51 and the gate electrode 20 can be improved, and the difference can be reduced.
Finally, after the thin film transistor is formed, a passivation layer (not shown) is further deposited on the source electrode 51, the drain electrode 53 and the gate insulating layer 30, and the passivation layer is patterned through a photomask process to form a via hole penetrating through the passivation layer, wherein the via hole can expose a portion of the drain electrode 53; and then forming a transparent conductive layer on the passivation layer, patterning the transparent conductive layer through a photomask process to form a pixel electrode with a specific shape, wherein the pixel electrode is electrically contacted with the drain electrode 53 through the via hole, so that a capacitor for liquid crystal movement is provided for the display area corresponding to the display area of the pixel unit, and the manufacturing of the array substrate is completed.
Example three:
referring to fig. 10, the present invention further provides a display panel 300, where the display panel 300 includes a color film substrate 400, an array substrate 100 and a liquid crystal layer 500, the color film substrate 400 and the array substrate 300 are arranged in a box-to-box manner, and the array substrate 100 is prepared by using the manufacturing method of the array substrate according to any of the above embodiments. Since the display panel 300 includes all technical solutions of all the embodiments, at least all the advantages brought by the technical solutions of the embodiments are provided, and are not described in detail herein.
Referring to fig. 4 and 9, the array substrate 100 includes a substrate 10, and a gate 20, an active layer 43, a drain 53, and a source 51 sequentially disposed on the substrate 10, and edges of a channel region 41 and the source 51 of the semiconductor layer 40 are protected by a semi-transparent region of the mask 200, so that size losses of the two are reduced, and accuracy of a design size is improved, thereby ensuring a parasitic capacitance between the source 51 and the gate 20, reducing a difference between parasitic capacitances of different regions, and effectively improving picture quality.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. The utility model provides a mask for preparation array substrate, array substrate includes thin film transistor, thin film transistor includes grid, source electrode and the drain electrode that the interval set up, be formed with the channel region between source electrode and the drain electrode, its characterized in that, the mask includes:
the device comprises a first exposure area corresponding to the channel area, a second exposure area located on one side of the first exposure area and used for forming a source electrode, a third exposure area located on the other side opposite to the first exposure area and used for forming a drain electrode, and a fourth exposure area located on the edge of the second exposure area and not overlapped with the first exposure area, wherein the first exposure area and the fourth exposure area are semi-transparent areas.
2. The mask according to claim 1, wherein the second exposure region has a strip shape, and the fourth exposure region is disposed at a position where a long edge of the second exposure region overlaps the source and the drain.
3. The reticle of claim 2, wherein the fourth exposure region is disposed at a position where a long side edge of the second exposure region does not correspond to a portion of the gate electrode.
4. The reticle of claim 3, wherein a portion of the fourth exposure region not corresponding to the gate is L, wherein L is 1.5 μm or greater.
5. The reticle of claim 2, wherein the fourth exposure region has a width in a range of 0.5 μm to 2 μm in a direction perpendicular to the source length direction;
and/or the fourth exposure area and the second exposure area are arranged without gaps.
6. The reticle of any one of claims 1 to 5, wherein the reticle is a halftone reticle, the light transmittance at each location of the first exposure area is the same, the light transmittance at each location of the fourth exposure area is the same, and the light transmittance of the first exposure area is the same as the light transmittance of the fourth exposure area.
7. The reticle of any one of claims 1 to 5, wherein the first exposure region comprises a first full-transmission portion and a first cover portion, the first full-transmission portion and the first cover portion being spaced apart in a direction perpendicular to an extension direction of the first exposure region; the fourth exposure area comprises a second full-transparent part and a second cover part, and the second full-transparent part and the second cover part are arranged at intervals in the extending direction perpendicular to the fourth exposure area.
8. The mask according to claim 7, wherein the first cover portion and the second cover portion are both in a strip shape, and the width ranges of the first cover portion and the second cover portion are both 0.6 μm to 1 μm; the width ranges of the first full-transparent part and the second full-transparent part are both 0.6-1 mu m;
and/or the first covering part and the second covering part are made of chromium.
9. A method for fabricating an array substrate using the mask as claimed in any one of claims 1 to 8, the method comprising the steps of:
providing a substrate, and sequentially forming a grid electrode, a grid electrode insulating layer, a semiconductor layer, a metal layer and a light resistance layer on the substrate from bottom to top, wherein a channel region is arranged at the position of the semiconductor layer corresponding to the grid electrode;
arranging the mask above the light resistance layer, and exposing and developing the light resistance layer;
carrying out first etching to remove the metal layer and the semiconductor layer which are not covered by the photoresist layer;
performing ashing process to remove the photoresist layer of the channel region and the photoresist layer of the fourth exposure region;
and performing second etching to remove the metal layer and part of the semiconductor layer in the channel region and the metal layer and the semiconductor layer in the fourth exposure region, and forming an active layer, and a source electrode and a drain electrode which are contacted with two ends of the active layer and are arranged at intervals.
10. A display panel, comprising a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are arranged in a box-to-box manner, and the array substrate is prepared by the method for manufacturing the array substrate according to claim 9.
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