CN106960881B - Thin film transistor and preparation method thereof - Google Patents
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- CN106960881B CN106960881B CN201710348174.0A CN201710348174A CN106960881B CN 106960881 B CN106960881 B CN 106960881B CN 201710348174 A CN201710348174 A CN 201710348174A CN 106960881 B CN106960881 B CN 106960881B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Abstract
The invention provides a thin film transistor and a preparation method thereof. The thin film transistor comprises a gate electrode arranged on a substrate, a gate insulating layer covering the gate electrode, and a first electrode, an active layer and a second electrode which are sequentially stacked on the surface of the gate electrode away from the substrate. The preparation method comprises the following steps: forming a gate electrode and a gate insulating layer on a substrate; and forming a first electrode, an active layer and a second electrode which are sequentially stacked on the surface of the gate electrode, which is far away from the substrate, on the gate insulating layer. According to the invention, the first electrode, the active layer and the second electrode are sequentially stacked on the surface of the gate electrode far away from the substrate, and the orthographic projections of the first electrode, the active layer and the second electrode on the substrate are at least partially overlapped with the orthographic projection of the gate electrode on the substrate, so that the size of the thin film transistor is effectively reduced, the aperture opening ratio is improved, high-resolution display is realized, the alignment precision and line width control are ensured, and the yield is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor and a preparation method thereof.
Background
A Thin Film Transistor liquid crystal Display (TFT-LCD) is used as a flat panel Display device, and is increasingly applied to the field of high performance Display due to its characteristics of small size, low power consumption, no radiation, relatively low manufacturing cost, and the like. The main structure of the TFT-LCD comprises an array substrate and a color film substrate which are paired, wherein the array substrate comprises a plurality of pixel units which are arranged in a matrix mode, each pixel unit is vertically crossed and limited by a plurality of grid lines and a plurality of data lines, and a thin film transistor is arranged at the crossed position of the grid lines and the data lines.
Fig. 1A is a schematic structural view of a conventional array substrate, and fig. 1B is a sectional view taken along a line a-a in fig. 1A. As shown in fig. 1A and 1B, the array substrate includes a gate line 20, a data line 30, a pixel electrode 17, and a thin film transistor, wherein the thin film transistor and the pixel electrode 17 are located in a pixel unit defined by the vertical intersection of the gate line 20 and the data line 30. The thin film transistor includes: a gate electrode 11 disposed on the substrate 10, a gate insulating layer 12 covering the gate electrode 11, an active layer 13 disposed on the gate insulating layer 12, and a source electrode 14 and a drain electrode 15 disposed on the active layer 13. Wherein, the gate electrode 11 is connected with the gate line 20, the overlapped part of the data line 30 and the gate electrode 11 is used as the source electrode 14 of the thin film transistor, the drain electrode 15 is arranged opposite to the source electrode 14, a horizontal channel is formed in the region between the source electrode and the drain electrode 15, and the drain electrode 15 is connected with the pixel electrode 17 through a via hole on the passivation layer 16. When a gate scanning signal is applied to the gate electrode, the active layer over the gate electrode changes from a semiconductor state to a conductive state, and a display signal from the data line is applied to the pixel electrode through the source electrode, the active layer, and the drain electrode.
In recent years, high-resolution display panels have become an industry trend. Generally, the resolution (PPI) of the display panel is related to the pixel aperture ratio of the array substrate, and the pixel aperture ratio of the array substrate is related to the size of the tft of each pixel unit, the larger the tft occupies, the smaller the pixel aperture ratio, and the lower the resolution of the display panel, so reducing the size of the tft is one of the important ways to improve the resolution. However, for the thin film transistor structure with the source and drain electrodes arranged in parallel as shown in fig. 1A and fig. 1B, the reduction of the size of the thin film transistor in the structure form is greatly restricted by the influence of the width of the data line, the alignment precision and the line width control in the manufacturing process, and the like, so that the resolution of the thin film transistor in the existing structure form is difficult to improve by reducing the size.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a thin film transistor and a method for manufacturing the same, so as to overcome the problem that the resolution of the existing thin film transistor is difficult to improve by reducing the size.
In order to solve the above technical problem, an embodiment of the present invention provides a thin film transistor, which includes a gate electrode disposed on a substrate, a gate insulating layer covering the gate electrode, and a first electrode, an active layer, and a second electrode sequentially stacked on a surface of the gate electrode away from the substrate.
Optionally, the first electrode, the active layer and the second electrode sequentially stacked on the surface of the gate electrode away from the substrate include: the first electrode is arranged on the gate insulating layer, the orthographic projection of the first electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate, the active layer is arranged on the first electrode, the orthographic projection of the active layer on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate, the second electrode is arranged on the active layer, the orthographic projection of the second electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate, and the first electrode, the active layer and the second electrode which are sequentially overlapped form a vertical channel structure.
Optionally, at least partially overlapping an orthographic projection of the first electrode, the active layer, or the second electrode on the substrate with an orthographic projection of the gate electrode on the substrate includes: the orthographic projection range of the first electrode, the active layer or the second electrode on the substrate is completely the same as the orthographic projection range of the gate electrode on the substrate, or the orthographic projection range of the first electrode, the active layer or the second electrode on the substrate is positioned in the orthographic projection range of the gate electrode on the substrate.
Optionally, the active layer comprises polysilicon or metal oxide and has a thickness of 2000-8000 angstroms.
Optionally, the width of the orthographic projection of the gate electrode on the substrate is 1.2-1.3 times that of the orthographic projection of the first electrode or the second electrode on the substrate.
In order to solve the above technical problem, an embodiment of the present invention further provides a method for manufacturing a thin film transistor, including:
forming a gate electrode and a gate insulating layer on a substrate;
and forming a first electrode, an active layer and a second electrode which are sequentially stacked on the surface of the gate electrode, which is far away from the substrate, on the gate insulating layer.
Optionally, the forming, on the gate insulating layer, a first electrode, an active layer, and a second electrode sequentially stacked on a surface of the gate electrode away from the substrate includes:
forming a first electrode on the gate insulating layer through a patterning process, wherein the orthographic projection of the first electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate; forming an active layer on the first electrode through a patterning process, wherein the orthographic projection of the active layer on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate; and forming a second electrode on the active layer through a patterning process, wherein the orthographic projection of the second electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate.
Optionally, the forming, on the gate insulating layer, a first electrode, an active layer, and a second electrode sequentially stacked on a surface of the gate electrode away from the substrate includes:
forming a first electrode and an active layer which are overlapped on the gate insulating layer through a composition process of a half-tone mask or a gray-tone mask, wherein orthographic projections of the first electrode and the active layer on the substrate are at least partially overlapped with orthographic projections of the gate electrode on the substrate; and forming a second electrode on the active layer through a patterning process, wherein the orthographic projection of the second electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate.
Optionally, the forming, on the gate insulating layer, a first electrode, an active layer, and a second electrode sequentially stacked on a surface of the gate electrode away from the substrate includes:
forming a first electrode on the gate insulating layer through a patterning process, wherein the orthographic projection of the first electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate; and forming an active layer and a second electrode which are overlapped on the first electrode through a composition process of a half-tone mask or a gray-tone mask, wherein orthographic projections of the active layer and the second electrode on the substrate are at least partially overlapped with orthographic projections of the gate electrode on the substrate.
Optionally, at least partially overlapping an orthographic projection of the first electrode, the active layer, or the second electrode on the substrate with an orthographic projection of the gate electrode on the substrate includes: the orthographic projection range of the first electrode, the active layer or the second electrode on the substrate is completely the same as the orthographic projection range of the gate electrode on the substrate, or the orthographic projection range of the first electrode, the active layer or the second electrode on the substrate is positioned in the orthographic projection range of the gate electrode on the substrate.
Optionally, the width of the orthographic projection of the gate electrode on the substrate is 1.2-1.3 times that of the orthographic projection of the first electrode or the second electrode on the substrate.
The embodiment of the invention also provides an array substrate, which comprises a grid line, a data line, a pixel electrode and the thin film transistor, wherein the grid line is connected with the gate electrode of the thin film transistor, the pixel electrode is connected with the second electrode of the thin film transistor, the orthographic projection of the data line on a substrate and the orthographic projection of the gate electrode on the substrate have an overlapping region, and the part of the data line corresponding to the overlapping region is used as the first electrode of the thin film transistor.
The embodiment of the invention also provides a display panel which comprises the array substrate.
According to the thin film transistor and the preparation method thereof provided by the embodiment of the invention, the first electrode, the active layer and the second electrode are sequentially overlapped on the surface of the gate electrode, which is far away from the substrate, and the orthographic projections of the first electrode, the active layer and the second electrode on the substrate are at least partially overlapped with the orthographic projection of the gate electrode on the substrate, so that the size of the thin film transistor is effectively reduced, the aperture opening ratio can be improved, high-resolution display is realized, the alignment precision and line width control can be ensured, and the yield is improved.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the embodiments of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention. The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.
Fig. 1A is a schematic structural view of a conventional array substrate, and fig. 1B is a sectional view taken along a line a-a in fig. 1A;
FIG. 2 is a schematic structural diagram of a TFT according to an embodiment of the present invention;
FIG. 3A is a schematic diagram of a first embodiment of the present invention after gate electrodes and gate line patterns are formed, and FIG. 3B is a cross-sectional view taken along line A-A in FIG. 3A;
fig. 4A is a schematic diagram after forming source electrode and data line patterns according to the first embodiment of the present invention, and fig. 4B is a cross-sectional view taken along a-a in fig. 4A;
FIG. 5A is a schematic view showing an active layer pattern formed according to the first embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line A-A in FIG. 5A;
fig. 6A is a schematic view illustrating a drain electrode pattern according to the first embodiment of the present invention, and fig. 6B is a cross-sectional view taken along a-a direction in fig. 6A;
FIG. 7 is a diagram illustrating a source electrode, a data line and an active layer pattern according to a second embodiment of the present invention;
FIG. 8 is a schematic view showing a drain electrode pattern formed according to the second embodiment of the present invention;
fig. 9 is a schematic view after forming an active layer and a drain electrode pattern according to a third embodiment of the present invention;
fig. 10A is a schematic structural view of an array substrate of the present invention, and fig. 10B is a sectional view taken along line a-a in fig. 10A.
Description of reference numerals:
| 10-a substrate; | 11-a gate electrode; | 12-a gate insulating layer; |
| 13-an active layer; | 14-a first (source) electrode; | 15-a second (drain) electrode; |
| 16-a passivation layer; | 17-pixel electrode. |
Detailed Description
The following detailed description of embodiments of the invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
At present, the existing thin film transistor generally adopts a horizontal channel structure with source and drain electrodes arranged in parallel, and is influenced by the width of a data line, the alignment precision and the line width control in a preparation process and the like, so that the size of the thin film transistor adopting the structure form is difficult to be substantially reduced. In order to overcome the problem that the resolution of the existing thin film transistor is difficult to improve by reducing the size of the thin film transistor, the embodiment of the invention provides a thin film transistor, an array substrate and a display panel.
Fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the invention. As shown in fig. 2, the thin film transistor includes a gate electrode and a gate insulating layer, and a first electrode, an active layer and a second electrode sequentially stacked on a surface of the gate electrode away from the substrate. Specifically, the thin film transistor includes:
a gate electrode 11 disposed on the substrate 10;
a gate insulating layer 12 covering the gate electrode 11;
a first electrode 14 disposed on the gate insulating layer 12 and having an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the gate electrode 11 on the substrate;
an active layer 13 disposed on the first electrode 14 and having an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the gate electrode 11 on the substrate;
and the second electrode 15 is arranged on the active layer 13, and the orthographic projection of the second electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode 11 on the substrate.
Wherein, the first electrode 14, the active layer 13 and the second electrode 15 stacked in sequence form a vertical channel structure. The first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode and the second electrode is a source electrode. The thickness of the active layer is 2000-8000 angstroms, the active layer material can be polysilicon to form a Low Temperature Polysilicon (LTPS) thin film transistor, and can also be metal Oxide to form an Oxide (Oxide) thin film transistor. The width of the orthographic projection of the first electrode and the second electrode on the substrate is 3-5 micrometers, the width of the orthographic projection of the gate electrode on the substrate is 4-6 micrometers, the width of the gate electrode is 1.0-2.0 times of the width of the first electrode or the second electrode, and preferably the width of the gate electrode is 1.2-1.3 times of the width of the first electrode or the second electrode.
The embodiment provides a thin film transistor with a vertical channel structure, because the first electrode, the active layer and the second electrode are sequentially stacked on the surface of the gate electrode, which is far away from the substrate, and the orthographic projections of the first electrode, the active layer and the second electrode on the substrate are at least partially overlapped with the orthographic projection of the gate electrode on the substrate, the size of the thin film transistor is effectively reduced, the aperture opening ratio can be improved, high-resolution display is realized, the alignment precision and line width control can be ensured, and the yield is improved.
The technical scheme of the embodiment of the invention is further illustrated by the preparation process.
First embodiment
FIGS. 3A-6B are schematic diagrams of a first embodiment of the present invention for fabricating a TFT. The "patterning process" in this embodiment includes processes such as depositing a film, coating a photoresist, exposing a mask, developing, etching, and stripping the photoresist, and is a well-established manufacturing process. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
In the first patterning process, a gate electrode and a gate line pattern are formed on a substrate through a patterning process. Forming the gate electrode and the gate line pattern includes: depositing a first metal film on a substrate 10, coating a layer of photoresist on the first metal film, exposing and developing the photoresist by adopting a single-tone mask, forming unexposed areas at the positions of a gate electrode and a grid line pattern, reserving the photoresist, forming a completely exposed area at other positions, removing the photoresist, etching the first metal film in the completely exposed area and stripping the residual photoresist to form patterns of the gate electrode 11 and the grid line 20. Subsequently, a gate insulating layer 12 is deposited, and the gate insulating layer 12 covers the gate electrode 11 and the gate line 20 pattern, as shown in fig. 3A and 3B. The substrate can be a glass substrate or a quartz substrate, the first metal film can be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W and the like, and the gate insulating layer can be a silicon nitride SiNx, silicon oxide SiOx or SiNx/SiOx composite film.
In the second patterning process, source electrode and data line patterns are formed on the substrate on which the gate electrode pattern and the gate insulating layer are formed through the patterning process. Forming the source electrode and the data line pattern includes: depositing a second metal film on the gate insulating layer 12, coating a layer of photoresist on the second metal film, exposing and developing the photoresist by using a single-tone mask, forming unexposed regions at the positions of the source electrode and the data line pattern, leaving the photoresist, forming a completely exposed region at other positions, removing the photoresist, etching the second metal film in the completely exposed region, and stripping the remaining photoresist to form patterns of the source electrode 14 and the data line 30, wherein the portion of the overlapping region of the data line 30 and the gate electrode 11 is used as the source electrode 14, i.e., the source electrode 14 is located on the surface of the gate electrode 11 away from the substrate, and the orthographic projection of the source electrode 14 on the substrate at least partially coincides with the orthographic projection of the gate electrode 11 on the substrate, as shown in fig. 4A and 4B. The second metal film may be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, and the like.
In the third patterning process, an active layer pattern is formed on the substrate on which the active electrode pattern is formed through the patterning process. The forming of the active layer pattern includes: depositing an active layer film on the substrate with the pattern, coating a layer of photoresist on the active layer film, exposing and developing the photoresist by using a single-tone mask, forming an unexposed region at the position of the active layer pattern, leaving the photoresist, forming a completely exposed region at other positions, removing the photoresist, etching the active layer film in the completely exposed region and stripping the residual photoresist to form a pattern of an active layer 13, wherein the active layer 13 is positioned on the surface of the gate electrode 11 away from the substrate, and the orthographic projection of the active layer 13 on the substrate is at least partially overlapped with the orthographic projection of the gate electrode 11 on the substrate, as shown in fig. 5A and 5B. The active layer has a thickness of 2000-8000 angstroms, and the material may be amorphous silicon, polycrystalline silicon or microcrystalline silicon to form an LTPS thin film transistor, or may be a metal Oxide material to form an Oxide thin film transistor, where the metal Oxide material may be Indium Gallium Zinc Oxide (IGZO) or Indium Tin Zinc Oxide (ITZO).
In the fourth patterning process, a drain electrode is formed on the substrate on which the active layer pattern is formed through the patterning process. Forming the drain electrode pattern includes: depositing a third metal film on the substrate with the pattern, coating a layer of photoresist on the third metal film, exposing and developing the photoresist by using a single-tone mask, forming an unexposed region at the position of the drain electrode pattern, leaving the photoresist, forming a completely exposed region at other positions, removing the photoresist, etching the third metal film in the completely exposed region and stripping the residual photoresist to form a drain electrode 15 pattern, wherein the drain electrode 15 is positioned on the surface of the gate electrode 11 away from the substrate, and the orthographic projection of the drain electrode 15 on the substrate is at least partially overlapped with the orthographic projection of the gate electrode 11 on the substrate, as shown in fig. 6A and 6B. The third metal film may be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, and the like.
As can be seen from the processes of manufacturing the thin film transistor shown in fig. 3A to 6B, in this embodiment, the thin film transistor with the vertical channel structure is formed through 4 patterning processes of the common mask. In the existing thin film transistor with the horizontal channel structure, because the source electrode and the drain electrode are arranged in parallel, and the source electrode, the drain electrode and the channel are all arranged on the gate electrode, the width of the gate electrode needs to be designed to be larger than the sum of the widths of the source electrode, the drain electrode and the channel, so that the width of the gate electrode is equivalent to the width of three data lines. In this embodiment, the source electrode, the active layer, and the drain electrode are sequentially stacked on the surface of the gate electrode away from the substrate, and the orthographic projections of the source electrode, the active layer, and the drain electrode on the substrate are at least partially overlapped with the orthographic projection of the gate electrode on the substrate, so that the width of the gate electrode is designed to be equal to or slightly larger than the width of the source electrode (i.e., the data line) or the drain electrode. Compared with the thin film transistor with the existing horizontal channel structure, the size of the thin film transistor can be reduced by 50% -60%, the size of the thin film transistor is effectively reduced, poor display caused by factors such as alignment precision in preparation is effectively avoided, the aperture opening rate is improved, and the yield is improved.
In this embodiment, "width" refers to a characteristic dimension of the array substrate in a data line width direction, or a characteristic dimension perpendicular to a data line length direction. Therefore, the width of the gate electrode or the width of the orthographic projection of the gate electrode on the substrate means the characteristic dimension of the cross section of the gate electrode in the direction perpendicular to the length of the data line (the a-a direction as shown in fig. 3A to 6B). The width of the source and drain electrodes or the width of the orthographic projections of the source and drain electrodes on the substrate means the characteristic dimension of the cross section of the source electrode and the cross section of the drain electrode in the direction perpendicular to the length of the data line (direction a-a as shown in fig. 3A to 6B). In practical implementation, the overlapped portion of the data line and the gate electrode is usually used as the source electrode, so the width of the source electrode is equal to the width of the data line, or the width of the orthographic projection of the source electrode on the substrate is equal to the width of the data line. In addition, in the present embodiment, "at least partially overlap" means that the orthographic projection range of the source electrode, the drain electrode or the active layer on the substrate is completely the same as the orthographic projection range of the gate electrode on the substrate, namely the orthographic projection width of the source electrode, the drain electrode or the active layer on the substrate is equal to the orthographic projection width of the gate electrode on the substrate, or the orthographic projection range of the source electrode, the drain electrode or the active layer on the substrate is positioned within the orthographic projection range of the gate electrode on the substrate, i.e. the width of the orthographic projection of the source electrode, the drain electrode or the active layer on the substrate is smaller than the width of the orthographic projection of the gate electrode on the substrate, or means that the orthographic projection range of the gate electrode on the substrate is positioned within the orthographic projection range of the source electrode, the drain electrode or the active layer on the substrate, that is, the width of the orthographic projection of the source electrode, the drain electrode or the active layer on the substrate is larger than the width of the orthographic projection of the gate electrode on the substrate. In practical implementation, the positional relationship among the source electrode, the active layer and the drain electrode may also be set, and the orthographic projection of one of the source electrode, the active layer and the drain electrode on the substrate is identical to the orthographic projection of the other one or two of the source electrode and the drain electrode on the substrate, or the orthographic projection of one of the source electrode and the drain electrode on the substrate is located within the orthographic projection of the other one or two of the source electrode and the drain electrode on the substrate.
Second embodiment
Fig. 7 to 8 are schematic diagrams illustrating a second embodiment of the present invention for fabricating a thin film transistor. The present embodiment is based on an extension of the first embodiment, and is different from the first embodiment in that the present embodiment adopts 3 patterning processes to form a thin film transistor with a vertical channel structure.
In the first patterning process, a gate electrode and a gate line pattern are formed on the substrate through a patterning process, as shown in fig. 3A and 3B. The first patterning process of this embodiment is the same as that of the first embodiment, and is not described here again.
In the second patterning process, a source electrode, a data line and an active layer pattern are formed on the substrate on which the gate electrode pattern and the gate insulating layer are formed through the patterning process. Forming the source electrode, the data line and the active layer pattern includes: depositing a second metal film and an active layer film on the gate insulating layer 12 in sequence, coating a layer of photoresist on the active layer film, carrying out step exposure and development on the photoresist by adopting a halftone mask or a gray tone mask, forming an unexposed area at the pattern position of the active layer, forming a photoresist with a first thickness, forming a partial exposed area at the data line pattern position, forming a photoresist with a second thickness, forming a complete exposed area at the rest positions, having no photoresist, and the first thickness being greater than the second thickness. Etching away the active layer film and the second metal film in the complete exposure area by the first etching process, performing photoresist ashing to remove the second thickness of the photoresist on the whole and expose the active layer film in the partial exposure area, etching away the active layer film in the partial exposure area by the second etching process, and stripping away the remaining photoresist to form patterns of the source electrode 14, the data line 30 (not shown) and the active layer 13, wherein the source electrode 14 is located on the gate insulating layer 12, the active layer 13 is located on the source electrode 14, the patterns of the source electrode 14 and the active layer 13 are the same, and the orthographic projections of the source electrode 14 and the active layer 13 on the substrate are at least partially overlapped with the orthographic projection of the gate electrode 11 on the substrate, as shown in fig. 7.
In the third patterning process, a drain electrode is formed on the substrate on which the above-described pattern is formed through a patterning process, as shown in fig. 8. The third patterning process of this embodiment is the same as the fourth patterning process of the first embodiment, and is not described herein again.
In practical implementation, the second patterning process may also use a patterning process of a common mask to form the source electrode, the data line, and the active layer pattern, specifically: depositing a second metal film and an active layer film on the gate insulating layer in sequence, coating a layer of photoresist on the active layer film, exposing and developing the photoresist by adopting a common mask, forming unexposed areas at the positions of the source electrode and the data line pattern, keeping the photoresist, forming completely exposed areas at other positions and having no photoresist. And etching the active layer film and the second metal film in the complete exposure area by an etching process, and stripping the residual photoresist to form a source electrode, a data line and an active layer pattern. Wherein, an active layer film is remained on the data line.
As can be seen from the processes of manufacturing the thin film transistor shown in fig. 3A, 3B, 7 and 8, in this embodiment, the thin film transistor with the vertical channel structure is formed through 3 patterning processes, where the 3 patterning processes may be 2 times of the common mask and 1 time of the halftone mask or the gray tone mask, and may also be 3 times of the common mask. In this embodiment, the parameters of the film layer, such as material and thickness, are the same as those of the first embodiment. Compared with the thin film transistor with the existing horizontal channel structure, the size of the thin film transistor can be reduced by 50% -60%.
Third embodiment
FIGS. 9-10 are schematic diagrams of a third embodiment of the present invention for fabricating a thin film transistor. The present embodiment is based on an extension of the first embodiment, and is different from the first embodiment in that the present embodiment adopts 3 patterning processes to form a thin film transistor with a vertical channel structure.
In the first patterning process, a gate electrode and a gate line pattern are formed on the substrate through a patterning process, as shown in fig. 3A and 3B. The first patterning process of this embodiment is the same as that of the first embodiment, and is not described here again.
In the second patterning process, source electrode and data line patterns are formed on the substrate on which the gate electrode pattern and the gate insulating layer are formed through the patterning process, as shown in fig. 4A and 4B. The second patterning process of this embodiment is the same as the second patterning process of the first embodiment, and is not described here again.
In the third patterning process, an active layer and a drain electrode pattern are formed on the substrate on which the active electrode and the data line pattern are formed through the patterning process. The forming of the active layer and the drain electrode pattern includes: depositing an active layer film and a third metal film on the substrate with the patterns in sequence, coating a layer of photoresist on the third metal film, carrying out step exposure and development on the photoresist by adopting a halftone mask or a gray tone mask, forming an unexposed area at the position of the drain electrode pattern, forming the photoresist with a first thickness, forming a partial exposed area at the position of the active layer pattern, forming the photoresist with a second thickness, forming a complete exposed area at the rest positions, and having no photoresist, wherein the first thickness is larger than the second thickness. Etching away the third metal film and the active layer film in the complete exposure area by the first etching process, performing photoresist ashing to remove the second thickness of the photoresist on the whole and expose the third metal film in the partial exposure area, etching away the third metal film in the partial exposure area by the second etching process, and stripping away the remaining photoresist to form patterns of the active layer 13 and the drain electrode 15, wherein the active layer 13 is located on the source electrode 14, the drain electrode 15 is located on the active layer 13, the orthographic projection width of the drain electrode 15 on the substrate is smaller than that of the active layer 13 on the substrate, and the orthographic projections of the active layer 13 and the drain electrode 15 on the substrate are at least partially overlapped with that of the gate electrode 11 on the substrate, as shown in fig. 9.
In practical implementation, the third patterning process may also adopt a patterning process of a common mask to form the active layer and the drain electrode pattern, specifically: depositing an active layer film and a third metal film on the substrate with the patterns in sequence, coating a layer of photoresist on the third metal film, exposing and developing the photoresist by adopting a common mask, forming an unexposed area at the pattern position of the drain electrode, keeping the photoresist, and forming a completely exposed area at the rest positions without the photoresist. And etching the third metal film and the active layer film in the complete exposure area by an etching process, and stripping the residual photoresist to form active layer and drain electrode patterns. Wherein, the drain electrode and the active layer have the same pattern.
As can be seen from the processes of manufacturing the thin film transistor shown in fig. 3A, 3B, 4A, 4B and 9, in this embodiment, the thin film transistor with the vertical channel structure is formed through 3 patterning processes, where the 3 patterning processes may be 2 times of common masks and 1 time of halftone masks or gray tone masks, or may be 3 times of common masks. In this embodiment, the parameters of the film layer, such as material and thickness, are the same as those of the first embodiment. Compared with the thin film transistor with the existing horizontal channel structure, the size of the thin film transistor can be reduced by 50% -60%.
Fourth embodiment
On the basis of the technical solutions of the first to third embodiments, the present application further provides an array substrate including the thin film transistor. The preparation process of the array substrate comprises the following steps:
a thin film transistor is formed on a substrate.
Depositing a passivation layer on a substrate on which a thin film transistor is formed, coating a layer of photoresist on the passivation layer, exposing and developing the photoresist by adopting a single-tone mask, forming a complete exposure area at the position of a through hole pattern of the passivation layer, removing the photoresist, forming an unexposed area at the rest positions, reserving the photoresist, etching the passivation layer in the complete exposure area and stripping the residual photoresist to form a through hole pattern of the passivation layer, wherein the through hole of the passivation layer is positioned at the position of a second electrode. The passivation layer can be made of silicon nitride SiNx, silicon oxide SiOx or a SiNx/SiOx composite film.
Depositing a transparent conductive film on the passivation layer, coating a layer of photoresist on the transparent conductive film, exposing and developing the photoresist by using a single-tone mask, forming an unexposed region at the position of the pixel electrode pattern, reserving the photoresist, forming a completely exposed region at the rest positions, removing the photoresist, etching the transparent conductive film in the completely exposed region and stripping the residual photoresist to form a pixel electrode 17 pattern, wherein the pixel electrode is connected with the second electrode through a passivation layer through hole, as shown in fig. 10A and 10B.
The array substrate prepared in this embodiment includes: the pixel structure comprises a grid line, a data line, a thin film transistor and a pixel electrode, wherein the thin film transistor and the pixel electrode are positioned in a pixel unit defined by the vertical intersection of the grid line and the data line, the grid line is connected with a grid electrode of the thin film transistor, the pixel electrode is connected with a second electrode of the thin film transistor, an orthographic projection of the data line on a substrate and an orthographic projection of the grid electrode on the substrate have an overlapping area, and a part of the data line corresponding to the overlapping area is used as a first electrode of the thin film transistor. Specifically, the array substrate includes:
a gate electrode 11 and a gate line 20 disposed on the substrate 10;
a gate insulating layer 12 covering the gate electrode 11 and the gate line 20;
a first electrode 14 and a data line 30 disposed on the gate insulating layer 12, wherein the first electrode 14 is an overlapping portion of the data line 30 and the gate electrode 11, and an orthographic projection on the substrate at least partially overlaps with an orthographic projection of the gate electrode 11 on the substrate;
an active layer 13 disposed on the first electrode 14, an orthographic projection of which on the substrate at least partially coincides with an orthographic projection of the gate electrode 11 on the substrate;
a second electrode 15 disposed on the active layer 13 and having an orthographic projection on the substrate at least partially coincident with an orthographic projection of the gate electrode 11 on the substrate;
a passivation layer 16 covering the pattern, wherein a passivation layer through hole is formed at the position of the second electrode 15;
and a pixel electrode 17 disposed on the passivation layer 16, the pixel electrode 17 being connected to the second electrode 15 through the passivation layer via hole.
Wherein, the first electrode 14, the active layer 13 and the second electrode 15 stacked in sequence form a vertical channel structure. The first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode and the second electrode is a source electrode. The thickness of the active layer is 2000-8000 angstroms, the active layer can be made of polysilicon to form an LTPS thin film transistor, and can also be made of metal Oxide to form an Oxide thin film transistor. The width of the orthographic projection of the first electrode and the second electrode on the substrate is 3-5 micrometers, the width of the orthographic projection of the gate electrode on the substrate is 4-6 micrometers, the width of the gate electrode is 1.0-2.0 times of the width of the first electrode or the second electrode, and preferably the width of the gate electrode is 1.2-1.3 times of the width of the first electrode or the second electrode.
The embodiment provides an array substrate, because first electrode, active layer and second electrode superpose in proper order and establish on the surface that the gate electrode is kept away from the basement, and the orthographic projection of first electrode, active layer and second electrode on the basement and the orthographic projection of gate electrode on the basement at least partly coincide, have less thin film transistor size, not only can improve the aperture opening ratio, realize high resolution display, can guarantee counterpoint precision and line width control moreover, improved the yields.
Fifth embodiment
Based on the inventive concept of the foregoing embodiments, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including:
s1, forming a gate electrode and a gate insulating layer on the substrate;
and S2, forming a first electrode, an active layer and a second electrode which are sequentially overlapped on the surface of the gate electrode far away from the substrate on the gate insulating layer.
In one embodiment, step S2 may include:
s211, forming a first electrode on the gate insulating layer through a composition process, wherein the orthographic projection of the first electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate;
s212, forming an active layer on the first electrode through a composition process, wherein the orthographic projection of the active layer on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate;
and S213, forming a second electrode on the active layer through a patterning process, wherein the orthographic projection of the second electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate.
In another embodiment, step S2 may include:
s221, forming a first electrode and an active layer which are overlapped on the gate insulating layer through a composition process of a half-tone mask or a gray-tone mask, wherein orthographic projections of the first electrode and the active layer on the substrate are at least partially overlapped with orthographic projections of the gate electrode on the substrate;
s222, forming a second electrode on the active layer through a patterning process, wherein the orthographic projection of the second electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate.
In another embodiment, step S2 may include:
s231, forming a first electrode on the gate insulating layer through a composition process, wherein the orthographic projection of the first electrode on the substrate is at least partially overlapped with the orthographic projection of the gate electrode on the substrate;
and S232, forming a superposed active layer and a superposed second electrode on the first electrode through a composition process of a half-tone mask or a gray-tone mask, wherein orthographic projections of the active layer and the second electrode on the substrate are at least partially overlapped with orthographic projections of the gate electrode on the substrate.
The first electrode, the active layer and the second electrode which are sequentially stacked form a vertical channel structure. The first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode and the second electrode is a source electrode. The thickness of the active layer is 2000-8000 angstroms, the active layer can be made of polysilicon to form an LTPS thin film transistor, and can also be made of metal Oxide to form an Oxide thin film transistor. The width of the orthographic projection of the first electrode and the second electrode on the substrate is 3-5 micrometers, the width of the orthographic projection of the gate electrode on the substrate is 4-6 micrometers, the width of the gate electrode is 1.0-2.0 times of the width of the first electrode or the second electrode, and preferably the width of the gate electrode is 1.2-1.3 times of the width of the first electrode or the second electrode.
Sixth embodiment
Based on the inventive concept of the foregoing embodiments, embodiments of the present invention also provide a display panel including the thin film transistor or the array substrate employing the foregoing embodiments. The display panel may be: any product or component with a Display function, such as a mobile phone, a tablet computer, a television, a Display, a notebook computer, a digital photo frame, a navigator, etc., may be a Liquid Crystal Display (LCD) Display panel, or an Organic Light-Emitting Diode (OLED) Display panel, etc.
In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A thin film transistor comprises a gate electrode arranged on a substrate and a gate insulating layer covering the gate electrode, and is characterized by further comprising a first electrode, an active layer and a second electrode which are sequentially overlapped on the surface of the gate electrode, which is far away from the substrate; the patterns of the first electrode and the active layer are the same, namely the orthographic projection of the first electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; or, the patterns of the second electrode and the active layer are the same, that is, the orthographic projection of the second electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; the orthographic projection range of the first electrode, the active layer and the second electrode on the substrate is located within the orthographic projection range of the gate electrode on the substrate, and the orthographic projection width of the gate electrode on the substrate is 1.2-1.3 times that of the orthographic projection width of the first electrode or the second electrode on the substrate.
2. The thin film transistor according to claim 1, wherein the first electrode, the active layer, and the second electrode which are sequentially stacked on a surface of the gate electrode away from the substrate comprise: the first electrode is arranged on the gate insulating layer, the active layer is arranged on the first electrode, the second electrode is arranged on the active layer, and the first electrode, the active layer and the second electrode which are sequentially overlapped form a vertical channel structure.
3. The thin film transistor according to claim 1, wherein the material of the active layer comprises polysilicon or metal oxide, and has a thickness of 2000 to 8000 angstroms.
4. A method for manufacturing a thin film transistor includes:
forming a gate electrode and a gate insulating layer on a substrate;
forming a first electrode, an active layer and a second electrode which are sequentially overlapped on the surface of the gate electrode, which is far away from the substrate, on the gate insulating layer; the patterns of the first electrode and the active layer are the same, namely the orthographic projection of the first electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; or, the patterns of the second electrode and the active layer are the same, that is, the orthographic projection of the second electrode on the substrate is completely the same as the orthographic projection of the active layer on the substrate; the orthographic projection range of the first electrode, the active layer and the second electrode on the substrate is located within the orthographic projection range of the gate electrode on the substrate, and the orthographic projection width of the gate electrode on the substrate is 1.2-1.3 times that of the orthographic projection width of the first electrode or the second electrode on the substrate.
5. The method according to claim 4, wherein the forming of the first electrode, the active layer, and the second electrode on the gate insulating layer, which are sequentially stacked on the surface of the gate electrode away from the substrate, comprises:
forming a first electrode on the gate insulating layer through a patterning process; forming an active layer on the first electrode through a patterning process; a second electrode is formed on the active layer through a patterning process.
6. The method according to claim 4, wherein the forming of the first electrode, the active layer, and the second electrode on the gate insulating layer, which are sequentially stacked on the surface of the gate electrode away from the substrate, comprises:
forming a first electrode and an active layer which are overlapped on the gate insulating layer through a composition process of a half-tone mask or a gray-tone mask; a second electrode is formed on the active layer through a patterning process.
7. The method according to claim 4, wherein the forming of the first electrode, the active layer, and the second electrode on the gate insulating layer, which are sequentially stacked on the surface of the gate electrode away from the substrate, comprises:
forming a first electrode on the gate insulating layer through a patterning process; and forming a stacked active layer and a second electrode on the first electrode through a patterning process of a half-tone mask or a gray-tone mask.
8. The method according to claim 4, wherein the active layer comprises polysilicon or metal oxide with a thickness of 2000-8000 angstroms.
9. An array substrate, comprising a gate line, a data line, a pixel electrode and the thin film transistor of any one of claims 1 to 3, wherein the gate line is connected to the gate electrode of the thin film transistor, the pixel electrode is connected to the second electrode of the thin film transistor, an orthographic projection of the data line on a substrate and an orthographic projection of the gate electrode on the substrate have an overlapping region, and a portion of the data line corresponding to the overlapping region is used as the first electrode of the thin film transistor.
10. A display panel comprising the array substrate according to claim 9.
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| CN107845676A (en) * | 2017-10-23 | 2018-03-27 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array base palte and display device |
| CN107845687B (en) * | 2017-10-27 | 2021-10-29 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof and electronic equipment |
| US10790311B2 (en) * | 2018-01-22 | 2020-09-29 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display substrate |
| CN108257981B (en) * | 2018-01-22 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Display substrate |
| CN109087928B (en) | 2018-08-16 | 2021-01-26 | 京东方科技集团股份有限公司 | Photoelectric detection substrate, preparation method thereof and photoelectric detection device |
| CN109686744B (en) * | 2018-12-25 | 2020-06-26 | 武汉天马微电子有限公司 | TFT substrate, OLED display panel and manufacturing method |
| CN111370496B (en) * | 2020-03-18 | 2021-10-26 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN111505876A (en) * | 2020-05-25 | 2020-08-07 | 成都中电熊猫显示科技有限公司 | Array substrate, manufacturing method thereof and display panel |
| WO2023245604A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method therefor, and display device |
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| KR101862539B1 (en) * | 2010-03-26 | 2018-05-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR20130074954A (en) * | 2011-12-27 | 2013-07-05 | 한국전자통신연구원 | Vertical channel thin film transistor |
| KR101985246B1 (en) * | 2012-07-06 | 2019-06-03 | 엘지디스플레이 주식회사 | Thin film transistor substrate having metal oxide and manufacturing method thereof |
| CN102842601B (en) * | 2012-08-17 | 2015-05-13 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof |
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