CN102543867A - Method for manufacturing metal oxide thin film transistor array substrate - Google Patents
Method for manufacturing metal oxide thin film transistor array substrate Download PDFInfo
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- CN102543867A CN102543867A CN2012100596097A CN201210059609A CN102543867A CN 102543867 A CN102543867 A CN 102543867A CN 2012100596097 A CN2012100596097 A CN 2012100596097A CN 201210059609 A CN201210059609 A CN 201210059609A CN 102543867 A CN102543867 A CN 102543867A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 44
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 51
- 238000001259 photo etching Methods 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims description 84
- 239000010410 layer Substances 0.000 claims description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 40
- 238000000151 deposition Methods 0.000 claims description 16
- 238000003384 imaging method Methods 0.000 claims description 15
- 238000013459 approach Methods 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000004380 ashing Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910003437 indium oxide Inorganic materials 0.000 claims description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical group [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 239000011701 zinc Substances 0.000 claims description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005499 laser crystallization Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a method for manufacturing a metal oxide thin film transistor array substrate. The method comprises the following steps of: forming gate scanning line patterns, gate electrode patterns and gate scanning line terminal patterns on a substrate by a first photoetching process; forming metal oxide layer patterns and etching barrier layer patterns by using a halftone mask or a gray tone mask through a second photoetching process; forming data line patterns, data line terminal patterns, source electrode patterns and drain electrode patterns by a third photoetching process; forming drain electrode contact hole patterns, gate scanning line terminal contact hole patterns and data line terminal contact hole patterns by a fourth photoetching process; and forming pixel electrode patterns, gate scanning line terminal contact electrode patterns and data line terminal contact electrode patterns by a fifth photoetching process. By the method, the photoetching times in the process for manufacturing the array substrate can be reduced, the production efficiency is improved, and the production cost is reduced.
Description
Technical field
The present invention relates to the LCD Technology field, particularly a kind of manufacturing approach of metal oxide thin-film transistor array base palte.
Background technology
Along with the continuous increase of LCD size, the frequency of drive circuit improves constantly in recent years, and existing amorphous silicon film transistor mobility is difficult to meet the demands.The thin-film transistor of high mobility has polycrystalline SiTFT and metal oxide thin-film transistor, though wherein polycrystalline SiTFT is studied early, its homogeneity is poor, complex manufacturing technology; Metal oxide thin-film transistor is than the advantage of polycrystalline SiTFT: need not adopt the crystallization technology, save processing step, improve evening ratio and qualification rate; Technology is simple, adopts traditional sputter and wet-etching technique just passable; In addition, present laser crystallization technology does not also reach the requirement of large size panel, and oxide transistor does not then have the restriction of size because do not need laser crystallization.Because the advantage of these several respects, metal oxide thin-film transistor enjoys people to pay close attention to, and becomes the focus of research in recent years.
Tradition amorphous silicon film transistor array base palte is generally photoetching process 5 times; And in the metal oxide thin-film transistor substrate manufacture; The metal-oxide film etching liquid is generally with nitric acid and hydrochloric acid, and source-drain electrode is if Al equally also is to use with nitric acid and phosphoric acid.The protection metal oxide layer is not destroyed when preventing to leak metal electrode in the formation source, thereby improves the performance of metal oxide thin-film transistor, need on metal-oxide film, form etching barrier layer; The material of etching barrier layer generally is SiO2 or SiNx; Therefore the manufacturing of metal oxide array base palte needs 6 photoetching processes usually, and comprising: the scan line relational pattern forms, and metal oxide layer pattern forms; The etching barrier layer pattern forms; The data wire relational pattern forms, and contact hole pattern forms, and pixel electrode pattern forms.And adopt 6 photoetching processes to reduce production efficiency with respect to 5 photoetching processes, increased cost.
Summary of the invention
Goal of the invention: to the problem and shortage of above-mentioned prior art existence; The manufacturing approach that the purpose of this invention is to provide a kind of metal oxide thin-film transistor array base palte; To reduce the photoetching number of times of array base palte production process, enhance productivity, reduce production costs.
Technical scheme: for realizing the foregoing invention purpose, the technical scheme that the present invention adopts is a kind of manufacturing approach of metal oxide thin-film transistor array base palte, comprises the steps:
(100) pass through for the first time photoetching process forms grid scan line pattern, gate electrode pattern and grid scan line terminal patterns on underlay substrate;
(200) on the underlay substrate that forms above-mentioned pattern, form metal oxide layer pattern and etching barrier layer pattern through the photoetching process second time of using intermediate tone mask version or gray tone mask;
(300) pass through for the third time photoetching process forms data wire pattern, data wire terminal patterns, source electrode pattern and drain electrode pattern on the underlay substrate that forms the said pattern of step (200);
(400) on the underlay substrate that forms the said pattern of step (300), form drain electrode contact hole pattern, grid scan line termination contact sectional hole patterns and data wire termination contact sectional hole patterns through the 4th photoetching process;
(500) on the underlay substrate that forms the said pattern of step (400), form pixel electrode pattern, grid scan line termination contact electrode pattern and data wire termination contact electrode pattern through the 5th photoetching process.
Said underlay substrate can be clear glass or transparent plastic.
Said step (100) also can comprise the steps:
(101) depositing metal films on underlay substrate;
(102) on metallic film, apply photoresist;
(103) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(104) metallic film is carried out etching, etch away to be positioned at and remove regional metallic film fully, form grid scan line pattern, gate electrode pattern and grid scan line terminal patterns.
Said step (200) also can comprise the steps:
(201) deposition gate insulator layer film, metal-oxide film and etching barrier layer film on the underlay substrate that forms above-mentioned pattern;
(202) on the etching barrier layer film, apply photoresist;
(203) adopt intermediate tone mask version or gray tone mask that photoresist is carried out the exposure imaging operation, form and comprise complete reserve area, half reserve area with remove fully regional;
(204) etching barrier layer film and metal-oxide film are carried out the etching first time, etch away to be positioned at and remove regional etching barrier layer film and metal-oxide film fully;
(205) thickness according to the photoresist that is positioned at half reserve area carries out ashing treatment to the photoresist that is positioned at complete reserve area and half complete reserve area;
(206) the etching barrier layer film is carried out the etching second time, etch away the etching barrier layer that is positioned at half reserve area, the photoresist that keeps is carried out lift-off processing, form metal oxide layer pattern and etching barrier layer pattern.
Said step (300) also can comprise the steps:
(301) depositing metal films on the underlay substrate that forms the said pattern of step (200);
(302) on metallic film, apply photoresist;
(303) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(304) metallic film is carried out etching, etch away to be positioned at and remove regional metallic film fully, form data wire pattern, data wire terminal patterns, source electrode pattern and drain electrode pattern.
Said step (400) also can comprise the steps:
(401) deposition protective layer film on the underlay substrate that forms the said pattern of step (300);
(402) on the protective layer film, apply photoresist;
(403) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(404) the protective layer film is carried out etching operation, etch away to be positioned at and remove regional protective layer film fully, form drain electrode contact hole pattern, grid scan line termination contact sectional hole patterns and data wire termination contact sectional hole patterns.
Said step (500) also can comprise the steps:
(501) pixel deposition electrode film on the underlay substrate that forms the said pattern of step (400);
(502) on the pixel electrode film, apply photoresist;
(503) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(504) the pixel electrode film is carried out etching operation, etch away to be positioned at and remove regional pixel electrode film fully, form pixel electrode pattern, grid scan line termination contact electrode pattern and data wire termination contact electrode pattern.
Said metal oxide can be indium oxide gallium zinc or indium zinc oxide etc.
The material of said data wire pattern, grid scan line pattern, data wire terminal patterns, grid scan line terminal patterns, source electrode pattern and drain electrode pattern can be in chromium, tungsten, titanium, tantalum, molybdenum, aluminium and the copper any one or multiple.
The shape of said drain electrode contact hole pattern, grid scan line termination contact sectional hole patterns and data wire termination contact sectional hole patterns can be rectangle or circular.
Said intermediate tone mask version can comprise transparent area, semi-opaque region and resistance light district; Said gray tone mask comprises transparent area, semi-opaque region and resistance light district, in photoetching process, corresponds respectively to complete reserve area, half reserve area on the array base palte and removes the zone fully.Said common mask can comprise transparent area and resistance light district, in photoetching process, corresponds respectively to the complete reserve area on the array base palte and removes the zone fully.
The material of said gate insulator layer film, etching barrier layer film and protective layer film can be a kind of in oxide, nitride or the nitrogen oxide.
Beneficial effect: the present invention forms metal oxide layer pattern and etching barrier layer pattern in the second time in the photoetching process through using intermediate tone mask version or gray tone mask, saves photoetching process one time, can save production cost, enhances productivity.
Description of drawings
Fig. 1 is the fragmentary top TV structure sketch map after the photoetching process for the first time in the embodiment of the invention;
Fig. 2 be among Fig. 3 A-A to dissecing side cross-sectional view;
Fig. 3 is the fragmentary top TV structure sketch map after the photoetching process for the second time in the embodiment of the invention;
Fig. 4 be among Fig. 5 B-B to dissecing side cross-sectional view;
Fig. 5 is an exposure technology sketch map in the photoetching process for the second time in the embodiment of the invention;
Fig. 6 is an etching technics sketch map for the first time in the photoetching process for the second time in the embodiment of the invention;
Fig. 7 is an ashing treatment process schematic representation in the photoetching process for the second time in the embodiment of the invention;
Fig. 8 is an etching technics sketch map for the second time in the photoetching process for the second time in the embodiment of the invention;
Fig. 9 be in the embodiment of the invention for the second time in the photoetching process photoresist lift off for the second time handle sketch map;
Figure 10 is a photoetching process fragmentary top TV structure sketch map for the third time in the embodiment of the invention;
Figure 11 be among Figure 10 C-C to dissecing side cross-sectional view;
Figure 12 is the 4th photoetching process fragmentary top TV structure sketch map in the embodiment of the invention;
Figure 13 be among Figure 12 D-D to dissecing side cross-sectional view;
Figure 14 is the 5th photoetching process fragmentary top TV structure sketch map in the embodiment of the invention;
Figure 15 be among Figure 14 E-E to dissecing side cross-sectional view.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment; Further illustrate the present invention; Should understand these embodiment only be used to the present invention is described and be not used in the restriction scope of the present invention; After having read the present invention, those skilled in the art all fall within the application's accompanying claims institute restricted portion to the modification of the various equivalent form of values of the present invention.
Concrete steps of the present invention are following:
Step 100, on underlay substrate, forms grid scan line pattern 13 through photoetching process for the first time, gate electrode pattern 2 and grid scan line terminal patterns 10 specifically comprise:
Step 101, on underlay substrate 1 depositing metal films.This step specifically can for: with transparent glass substrate or transparent plastic substrate as underlay substrate 1; On underlay substrate 1, adopt the method depositing metal films of sputter, the material of metallic film can select for use in chromium, tungsten, titanium, tantalum, molybdenum, aluminium and the copper any one or multiple;
Step 102, on metallic film, apply photoresist;
Step 103, the common mask of employing are carried out the exposure imaging operation to photoresist, form complete reserve area and remove the zone fully;
Step 104, metallic film is carried out etching, etch away and be positioned at the metallic film of removing the zone fully, form grid scan line pattern 13, gate electrode pattern 2 and grid scan line terminal patterns 10.
Fig. 1 is the fragmentary top TV structure sketch map after the photoetching process for the first time in the embodiment of the invention.Fig. 2 be among Fig. 1 A-A to dissecing side cross-sectional view.
Step 200, the photoetching process second time of intermediate tone mask version or gray tone mask of passing through to use form metal oxide layer pattern 4 and etching barrier layer pattern 5 on the underlay substrate 1 that forms above-mentioned pattern, specifically comprise:
Step 201, deposition gate insulator layer film 3, metal-oxide film 40 and etching barrier layer film 50;
Step 202, on the etching barrier layer film, apply photoresist 16;
Step 204, etching barrier layer film and metal-oxide film are carried out the etching first time, as shown in Figure 6, etch away and be positioned at etching barrier layer film and the metal-oxide film of removing the zone fully;
Step 205, according to the thickness of the photoresist that is positioned at half reserve area to be positioned at complete reserve area and half fully the photoresist of reserve area carry out ashing treatment, as shown in Figure 7;
Step 206, the etching barrier layer film is carried out the etching second time; As shown in Figure 8, etch away the etching barrier layer that is positioned at half reserve area, the photoresist that keeps is carried out lift-off processing; Like Fig. 9, finally form burning layer pattern as shown in Figure 64 and etching barrier layer pattern 5.
Fig. 3 is the fragmentary top TV structure sketch map after the photoetching process for the second time in the embodiment of the invention.Fig. 4 be among Fig. 5 B-B to dissecing side cross-sectional view.
Step 300, on the underlay substrate that forms above-mentioned pattern, form data wire pattern 12, data wire terminal patterns 18, source electrode pattern 6 and drain electrode pattern 7, specifically comprise through photoetching process for the third time:
Step 301, forming depositing metal films on the underlay substrate of above-mentioned pattern;
Step 302, on metallic film, apply photoresist;
Step 303, the common mask of employing are carried out the exposure imaging operation to photoresist, form to comprise complete reserve area and remove the zone fully;
Step 304, metallic film is carried out etching operation, etch away and be positioned at the metallic film of removing the zone fully, form data wire pattern 12, data wire terminal patterns 18, source electrode pattern 6 and drain pattern 7.
Figure 10 is a photoetching process fragmentary top TV structure sketch map for the third time in the embodiment of the invention.Figure 11 be among Figure 10 C-C to dissecing side cross-sectional view.
Step 400, on the underlay substrate that forms above-mentioned pattern, form drain electrode contact hole pattern 15, grid scan line termination contact sectional hole patterns 14 and data wire termination contact sectional hole patterns 19, specifically comprise through the 4th photoetching process:
Step 401, deposition protective layer film 8;
Step 402, on the protective layer film, apply photoresist;
Step 403, the common mask of employing are carried out the exposure imaging operation to photoresist, form to comprise complete reserve area and remove the zone fully;
Step 404, the protective layer film is carried out etching operation, etch away and be positioned at the protective layer film of removing the zone fully, form drain electrode contact hole pattern 15, grid scan line termination contact sectional hole patterns 14 and data wire termination contact sectional hole patterns 19.
Figure 12 is the 4th photoetching process fragmentary top TV structure sketch map in the embodiment of the invention; Figure 13 be among Figure 12 D-D to dissecing side cross-sectional view;
Step 500, on the underlay substrate that forms above-mentioned pattern, form pixel electrode pattern 9, grid scan line termination contact electrode pattern 11 and data wire termination contact electrode pattern 20, specifically comprise through the 5th photoetching process:
Step 501, pixel deposition electrode film;
Step 502, on the pixel electrode film, apply photoresist;
Step 503, the common mask of employing are carried out the exposure imaging operation to photoresist, form to comprise complete reserve area and remove the zone fully;
Step 504, the pixel electrode film is carried out etching operation, etch away and be positioned at the pixel electrode film of removing the zone fully, form pixel electrode pattern 9, grid scan line termination contact electrode pattern 11 and data wire termination contact electrode pattern 20.
Claims (10)
1. the manufacturing approach of a metal oxide thin-film transistor array base palte comprises the steps:
(100) pass through for the first time photoetching process forms grid scan line pattern, gate electrode pattern and grid scan line terminal patterns on underlay substrate;
(200) on the underlay substrate that forms above-mentioned pattern, form metal oxide layer pattern and etching barrier layer pattern through the photoetching process second time of using intermediate tone mask version or gray tone mask;
(300) pass through for the third time photoetching process forms data wire pattern, data wire terminal patterns, source electrode pattern and drain electrode pattern on the underlay substrate that forms the said pattern of step (200);
(400) on the underlay substrate that forms the said pattern of step (300), form drain electrode contact hole pattern, grid scan line termination contact sectional hole patterns and data wire termination contact sectional hole patterns through the 4th photoetching process;
(500) on the underlay substrate that forms the said pattern of step (400), form pixel electrode pattern, grid scan line termination contact electrode pattern and data wire termination contact electrode pattern through the 5th photoetching process.
2. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said step (100) also comprises the steps:
(101) depositing metal films on underlay substrate;
(102) on metallic film, apply photoresist;
(103) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(104) metallic film is carried out etching, etch away to be positioned at and remove regional metallic film fully, form grid scan line pattern, gate electrode pattern and grid scan line terminal patterns.
3. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said step (200) also comprises the steps:
(201) deposition gate insulator layer film, metal-oxide film and etching barrier layer film on the underlay substrate that forms above-mentioned pattern;
(202) on the etching barrier layer film, apply photoresist;
(203) adopt intermediate tone mask version or gray tone mask that photoresist is carried out the exposure imaging operation, form and comprise complete reserve area, half reserve area with remove fully regional;
(204) etching barrier layer film and metal-oxide film are carried out the etching first time, etch away to be positioned at and remove regional etching barrier layer film and metal-oxide film fully;
(205) thickness according to the photoresist that is positioned at half reserve area carries out ashing treatment to the photoresist that is positioned at complete reserve area and half complete reserve area;
(206) the etching barrier layer film is carried out the etching second time, etch away the etching barrier layer that is positioned at half reserve area, the photoresist that keeps is carried out lift-off processing, form metal oxide layer pattern and etching barrier layer pattern.
4. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said step (300) also comprises the steps:
(301) depositing metal films on the underlay substrate that forms the said pattern of step (200);
(302) on metallic film, apply photoresist;
(303) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(304) metallic film is carried out etching, etch away to be positioned at and remove regional metallic film fully, form data wire pattern, data wire terminal patterns, source electrode pattern and drain electrode pattern.
5. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said step (400) also comprises the steps:
(401) deposition protective layer film on the underlay substrate that forms the said pattern of step (300);
(402) on the protective layer film, apply photoresist;
(403) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(404) the protective layer film is carried out etching operation, etch away to be positioned at and remove regional protective layer film fully, form drain electrode contact hole pattern, grid scan line termination contact sectional hole patterns and data wire termination contact sectional hole patterns.
6. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said step (500) also comprises the steps:
(501) pixel deposition electrode film on the underlay substrate that forms the said pattern of step (400);
(502) on the pixel electrode film, apply photoresist;
(503) adopt common mask that photoresist is carried out the exposure imaging operation, formation comprises complete reserve area and removes the zone fully;
(504) the pixel electrode film is carried out etching operation, etch away to be positioned at and remove regional pixel electrode film fully, form pixel electrode pattern, grid scan line termination contact electrode pattern and data wire termination contact electrode pattern.
7. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said metal oxide is indium oxide gallium zinc or indium zinc oxide.
8. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: the material of said data wire pattern, grid scan line pattern, data wire terminal patterns, grid scan line terminal patterns, source electrode pattern and drain electrode pattern be in chromium, tungsten, titanium, tantalum, molybdenum, aluminium and the copper any one or multiple.
9. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1, it is characterized in that: said drain electrode contact hole pattern, grid scan line termination contact sectional hole patterns and data wire termination contact sectional hole patterns be shaped as rectangle or circular.
10. according to the manufacturing approach of the said a kind of metal oxide thin-film transistor array base palte of claim 1; It is characterized in that: said intermediate tone mask version comprises transparent area, semi-opaque region and resistance light district, and said gray tone mask comprises transparent area, semi-opaque region and resistance light district.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100596097A CN102543867A (en) | 2012-03-08 | 2012-03-08 | Method for manufacturing metal oxide thin film transistor array substrate |
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| CN2012100596097A CN102543867A (en) | 2012-03-08 | 2012-03-08 | Method for manufacturing metal oxide thin film transistor array substrate |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103500738A (en) * | 2013-10-14 | 2014-01-08 | 南京中电熊猫液晶显示科技有限公司 | Semiconductor device containing etching barrier layer as well as manufacturing method and application of semiconductor device |
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| CN103337522A (en) * | 2013-06-17 | 2013-10-02 | 南京中电熊猫液晶显示科技有限公司 | Metal oxide thin film transistor array substrate and manufacturing method thereof |
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| CN105093753A (en) * | 2015-08-21 | 2015-11-25 | 武汉华星光电技术有限公司 | Mask plate, array substrate and manufacturing method of array substrate |
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| CN110874990A (en) * | 2019-12-02 | 2020-03-10 | 武汉天马微电子有限公司 | Display panel and display device |
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| WO2022267189A1 (en) * | 2021-06-23 | 2022-12-29 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method therefor |
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