JP5110821B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to an exposure mask used in a photolithography process and a method for manufacturing a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) using the exposure mask. For example, the present invention relates to a method for manufacturing an electronic device in which an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

In manufacturing a semiconductor device including a thin film transistor (hereinafter referred to as TFT), many steps are required before and after forming a mask made of a photoresist. For example, substrate cleaning, resist material application, pre-baking, exposure, development, and post-baking.

Further, the mask made of the photoresist needs to be removed after the etching process or the doping process, and many processes are required for the removal. For example, there are an ashing process using a gas selected from O ₂ , H ₂ O, CF ₄ or the like, a peeling process using various chemical solutions, or a peeling process combining the ashing process and a process using a chemical solution. At this time, a peeling process using a chemical solution requires a process such as a chemical solution process, a rinse process with pure water, and a substrate drying process.
Therefore, the use of a mask made of a photoresist has a problem that the number of manufacturing steps of the semiconductor device is increased. In order to shorten the processing period and reduce costs, it is required to reduce the number of photolithography processes, that is, to reduce the number of masks used in the photolithography process.

As a method for reducing the number of masks, a light-transmitting substrate capable of transmitting exposure light, a light-shielding portion made of chromium or the like formed on the light-transmitting substrate, and lines and spaces made of a light-shielding material with a predetermined line width There has been proposed an exposure method using an exposure mask provided with a transflective portion having a light intensity reduction function in which is repeatedly formed. An exposure mask having a semi-transmissive portion formed by lines and spaces is also referred to as a gray tone exposure mask, and exposure using this exposure mask is also referred to as gray tone exposure. By using this exposure mask, one photoresist layer can be developed to at least two different film thicknesses. Then, by etching the layer to be etched while ashing the photoresist, two layers to be etched can be formed in different patterns in one photolithography process. According to this, one photolithography process, that is, the number of masks can be reduced (see, for example, Patent Document 1).

For example, in the case of an exposure apparatus with an equal projection magnification, the exposure mask provided with the semi-transmissive part is formed so that the line and space widths of the semi-transmissive part are smaller than the resolution (resolution limit) of the exposure apparatus. As a result, the lines and spaces are blurred without being resolved on the substrate, so that the exposure amount of the exposure light that has passed through the semi-transmissive portion on the substrate is an amount of light that is substantially uniform over almost the entire semi-transmissive portion. As a result, the thickness of the photoresist layer can be reduced in the semi-transmissive portion.
JP2002-151523

However, when the exposure apparatus has a high resolution, even if the lines and spaces are formed smaller than the resolution, the thickness of the photoresist layer cannot be reduced, or the thickness can be reduced evenly. In some cases, it could not be formed.
An example is shown in FIG. FIG. 13A schematically shows a cross-sectional view of an exposure mask, and FIG. 13B shows a cross-sectional photograph of a photoresist layer obtained by exposure and development using this exposure mask. . The position of the exposure mask in FIG. 13A substantially corresponds to the position of the cross-sectional photograph of the photoresist layer in FIG. An exposure apparatus having a projection magnification of the same magnification and a resolution of 1.5 μm was used. As shown in FIG. 13A, even when an exposure mask whose lines and spaces are smaller than the resolution is used, a photoresist layer having a thin film thickness and a uniform film thickness in the thin film thickness area is formed. Sometimes it could not be formed. In the exposure mask of FIG. 13A, in the region where the line and space width are 1.0 μm and the space width is 0.5 μm, the photoresist layer is not thin, and is almost the same as the light shielding portion. It was formed thick .

Therefore, the present invention can form a photoresist layer having a thin region for the purpose of improving the productivity or reducing the cost of a semiconductor device provided with a TFT, and also in the thin region. An exposure mask that can be uniformly formed is provided. A method for manufacturing a semiconductor device is provided in which the number of photolithography steps (number of masks) required for manufacturing a TFT substrate using the exposure mask is reduced.

In order to solve the above-mentioned problems, the present invention provides a light-shielding material in a semi-transmissive part in an exposure mask comprising a transmissive part, a light-shielding part, and a semi-transmissive part having a light intensity reducing function in which lines and spaces are repeatedly formed. The sum of the line width L and the space width S between the light-shielding materials is expressed as follows. When the exposure apparatus resolution is n and the projection magnification is 1 / m (m ≧ 1), the relationship between n and m is (n / 3). ) meets × m ≦ L + S ≦ ( 3n / 2) × conditional expression m, and, n, m, the relationship of L is characterized by using the L <(2n / 3) exposure mask that meets the × m And

Desirably, the sum of the L and S, n, the relationship between the m is, meets the (2n / 3) × m ≦ L + S ≦ (6n / 5) × conditional expression m, and, n, m, L relationship is characterized by using the exposure mask that meets the L <(2n / 3) × m.

For example, the resolution n is 1.5μm exposure apparatus, when the projection magnification 1 / m is equal magnification (m = 1), the line width L of the semi-transmissive portion satisfying the L <1.0 .mu.m.

The exposure mask is also called a photomask or a reticle. As the exposure apparatus, a projection type exposure apparatus can be used. As the projection magnification, an exposure device having the same magnification can be used, or a reduction projection type exposure device having a projection magnification (reduction magnification) of 1 / m times can be used.

The resolution n indicates the resolution limit on the surface to be exposed, while the line width L and the space width S are the sizes on the exposure mask. Therefore, when using an exposure apparatus with an equal projection magnification, the magnitude relationship between the resolution n and L and S can be simply compared, but the projection magnification (reduction magnification) is reduced by 1 / m times. When a projection type exposure apparatus is used, the magnitude relationship between the resolution n and L and S cannot be simply compared. In this case, by multiplying the resolution n by the reciprocal m of the projection magnification (reduction magnification) 1 / m, it is possible to compare the magnitude relationship between the resolution n and L and S even in the reduced projection exposure apparatus. This is the reason why the resolution n is multiplied by the reciprocal m (m ≧ 1) of the projection magnification (reduction magnification) in the above relational expression. When an exposure apparatus having a projection magnification of 1 × is used, the reciprocal m of the projection magnification 1 / m is 1.

According to the present invention, there is provided a resist pattern having a first region having a large film thickness and a second region having a smaller film thickness than the first region on a side portion of the first region, using the exposure mask. And the etching target film is selectively etched using the resist pattern.

As the semi-transmission part of the exposure mask, one in which lines and spaces are repeatedly provided in a striped shape (stripe shape, slit shape) can be used. In addition, a rectangular pattern made of a light shielding material in which a lattice pattern or a geometrically arranged periodic pattern can be used. Other patterns can also be used as long as they have a certain width. Moreover, the line which comprises a translucent part consists of a light shielding material, and can be provided using the same light shielding material as a light shielding part.

It is particularly effective to use an exposure mask satisfying the above relationship in which the transflective portion is disposed on the side of the light shielding portion.

In addition, in a method for manufacturing a semiconductor device of the present invention, an insulating film is formed over a semiconductor layer, a conductive film is formed over the insulating film, and an exposure mask including a semi-transmissive portion is formed over the conductive film. Forming a resist pattern having a first region having a large film thickness and a second region having a film thickness smaller than that of the first region on a side portion of the first region, and using the resist pattern, the conductive pattern The film is etched to form a gate electrode having a first region having a large thickness and a second region having a thickness smaller than that of the first region on a side portion of the first region. An impurity element is implanted into the semiconductor layer using the electrode as a mask, and the source region and the drain region are passed outside the gate electrode, and the second region of the gate electrode is passed through the second region of the gate electrode. A first impurity region and a second impurity region in a region overlapping with To form the door. In the formation of the resist pattern, the sum of the line width L of the light-shielding material and the space width S between the light-shielding materials in the semi-transmissive portion is n as the resolution of the exposure apparatus and 1 / m (m ≧ 1) as the projection magnification. then, (n / 3) × m ≦ L + S ≦ (3n / 2) meets the condition of × m, and, n, m, the relationship of L is, L <(2n / 3) exposure that meets the × m It is characterized by using a mask.

Desirably, the sum of the L and S, n, the relationship between the m is, meets the (2n / 3) × m ≦ L + S ≦ (6n / 5) × conditional expression m, and, n, m, L relationship is characterized by using the exposure mask that meets the L <(2n / 3) × m.

For example, the resolution n is 1.5μm exposure apparatus, when the projection magnification 1 / m is equal magnification (m = 1), the line width L of the semi-transmissive portion satisfying the L <1.0 .mu.m.

The first and second impurity regions include an n-type or p-type impurity element at a lower concentration than the source region and the drain region.

An example of exposure and development using an exposure mask that actually satisfies the above relationship is shown in FIG. FIG. 12A schematically shows a cross-sectional view of an exposure mask, and FIG. 12B shows a cross-sectional photograph of a photoresist layer obtained by exposure and development using this exposure mask. . The position of the exposure mask in FIG. 12A substantially corresponds to the position of the cross-sectional photograph of the photoresist layer in FIG. An exposure apparatus having a projection magnification of the same magnification and a resolution of 1.5 μm was used. In the exposure mask of FIG. 12A, the line and space widths are 0.5 μm and 1.0 μm, and the lines and spaces satisfy the above relationship. When exposure and development are performed using this exposure mask, a photoresist layer having a thin film thickness as shown in FIG. 12B and a substantially uniform film thickness is formed in the thin film thickness area. We were able to.

By performing exposure using an exposure mask having a semi-transmissive portion that satisfies the above relationship, the exposure amount of the exposure light that has passed through the semi-transmissive portion is substantially uniform in the semi-transmissive portion. The thickness of the photoresist layer in the transmission portion can be reduced and the thickness can be formed uniformly. The etched layer can be etched using the thin portion of the photoresist layer. The portion where the thickness of the photoresist layer is thin can be formed to be thinner than the portion where the thickness is thick. The pattern of the layer to be etched can be formed in a portion where the thickness of the photoresist layer is thin different from that of the portion where the thickness is thick. By using this resist pattern, it is possible to accurately form a gate electrode, other electrode, wiring, or the like having a desired pattern. When a gate electrode having a thick first region and a second region thinner than the first region is formed on the side of the first region using the exposure mask, By using the electrode as a mask for ion doping, a low concentration impurity region (L _ov region) overlapping with the gate electrode can be formed in a self-aligned manner on both sides or one side of the channel formation region.

Thus, by manufacturing a semiconductor device including a TFT (GOLD structure: Gate-drain overlapped LDD) having a low concentration impurity region (L _ov region) overlapping with the gate electrode in a self-aligning manner, the number of masks can be increased. Reduction can be realized, and at the same time, fine alignment is not required when producing the GOLD structure. As a result, many processes such as substrate cleaning, resist material application, pre-baking, exposure, development, and post-baking can be reduced, and the processing time can be shortened. And manufacturing cost can be reduced and the yield of a product can be improved.

By using an exposure mask with a transflective portion that satisfies the above relationship, the L _ov region can be formed in a self-aligned manner, and the length (length in the channel length direction) is not limited, and the length is sufficient. Can be secured. In addition, the lengths of the L _ov regions on both sides of the channel formation region can be made different.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below, and various modifications are allowed without departing from the spirit of the present invention.

(Embodiment 1)
In this embodiment mode, an exposure mask including a semi-transmissive portion formed with lines and spaces or rectangular patterns and spaces will be described with reference to FIG.

Specific examples of top views of the exposure mask are shown in FIGS. An example of the light intensity distribution when using an exposure mask is shown in FIG. The exposure mask shown in FIGS. 1A to 1C includes a light shielding portion P, a semi-transmissive portion Q, and a transmissive portion R. In the semi-transmissive portion Q of the exposure mask shown in FIG. 1A, a line 203 and a space 204 are repeatedly provided in a stripe shape (stripe shape, slit shape), and the line 203 and the space 204 are formed at the end portion 202 of the light shielding portion P. They are arranged in parallel directions. In this semi-transmissive portion, the width of the line 203 made of the light shielding material is L, the width of the space 204 between the light shielding materials is S, the sum of L and S, the resolution n of the exposure apparatus, and the projection magnification 1 / m (m ≧ 1) relationship between the, (n / 3) × m ≦ L + S ≦ (3n / 2) meets the condition of × m, and, n, m, the relationship of L is, L <(2n / 3) × meet m using Suyo exposure mask. Desirably, the sum of L and S, n, the relationship between m, (2n / 3) × m ≦ L + S ≦ (6n / 5) meet the conditional expression × m, and, n, m, of L relationships using L <(2n / 3) Suyo exposure mask meet × m. The line 203 is made of a light shielding material and can be provided using the same light shielding material as the light shielding portion P. The line 203 is formed in a rectangular shape, but is not limited to this. It is only necessary to have a certain width. For example, it may have a shape with rounded corners.

By using an exposure mask that satisfies the above relationship, the exposure amount on the exposed surface of the exposure light that has passed through the semi-transmissive portion becomes a substantially uniform light amount in the semi-transmissive portion, and the photoresist layer in the exposed portion of the semi-transmissive portion The film thickness can be made thin and the film thickness can be formed uniformly, and a desired pattern can be obtained with high accuracy.

FIG. 1B shows another example, in which the semi-transmissive portion Q of the exposure mask is provided with a line 207 and a space 208 in stripes, and the line 207 and the space 208 are perpendicular to the end portion 206 of the light shielding portion P. Is arranged. The relationship between the width L of the line 207, the width S of the space 208, the resolution n of the exposure apparatus, and the projection magnification 1 / m (m ≧ 1) satisfies the same conditions as in FIG. An exposure mask is used. That is, the relationship between the sum of L and S, the resolution n of the exposure apparatus, and the projection magnification 1 / m (m ≧ 1) is a conditional expression of (n / 3) × m ≦ L + S ≦ (3n / 2) × m. meets, and, n, m, the relationship of L uses L <(2n / 3) Suyo exposure mask meet × m. Desirably, the sum of L and S, n, the relationship between m, (2n / 3) × m ≦ L + S ≦ (6n / 5) meet the conditional expression × m, and, n, m, of L relationships using L <(2n / 3) Suyo exposure mask meet × m. Further, the end portion 206 of the light shielding portion P and the end portion of the line 207 of the semi-transmissive portion Q may be in contact with each other, or may be arranged with a distance T as illustrated. The distance T should be smaller than (n × m) obtained by multiplying the resolution n of the exposure apparatus by the reciprocal m of the projection magnification. Except for the arrangement of lines and spaces, the same materials (materials, shapes, etc.) as those in FIG. 1A can be used.

As the direction of the line and space of the semi-transmissive portion Q, any of the directions of FIG. 1 (A) and FIG. 1 (B) can be used. Further, FIG. 1A and FIG. 1B can be used in combination. Further, the line and space directions of the semi-transmissive portion Q can be arranged in a direction between FIGS. 1A and 1B, that is, in an oblique direction with respect to the end portion of the light shielding portion P. . Also in this case, the same materials (materials, shapes, etc.) as those in FIG. 1A can be used except for the arrangement of lines and spaces.

Further, as the semi-transmissive portion Q, as shown in FIGS. 1 (A) and 1 (B), lines and spaces arranged in stripes may be used, or other patterns may be used. For example, as shown in FIG. 1C, a rectangular pattern 212 made of a light shielding material may be used which is periodically arranged in a lattice shape or geometrically. In FIG. 1C, the width L in the short side direction of the rectangular pattern 212 corresponds to the line width L. The width S of the space 213 in the short side direction corresponds to the width S of the space. The relationship between the sum of the width L of the rectangular pattern 212 and the width S of the space 213, the resolution n of the exposure apparatus, and the projection magnification 1 / m (m ≧ 1) satisfies the same upper condition as in FIG. An exposure mask is used. That is, the relationship between the sum of L and S, the resolution n of the exposure apparatus, and the projection magnification 1 / m (m ≧ 1) is a conditional expression of (n / 3) × m ≦ L + S ≦ (3n / 2) × m. meets, and, n, m, the relationship of L uses L <(2n / 3) Suyo exposure mask meet × m. Desirably, the sum of L and S, n, the relationship between m, (2n / 3) × m ≦ L + S ≦ (6n / 5) meet the conditional expression × m, and, n, m, of L relationships using L <(2n / 3) Suyo exposure mask meet × m. The rectangular pattern 212 is made of a light shielding material and can be provided using the same light shielding material as the light shielding portion P.

Moreover, the line and space (or rectangular pattern and space) of a semi-transmissive part may be arrange | positioned periodically like FIG. 1 (A)-(C), and may be arrange | positioned aperiodically. . In the case of non-periodic arrangement, adjacent lines and spaces (or rectangular patterns and spaces) need only satisfy the above conditions.
By adjusting the width of lines and spaces (or rectangular patterns and spaces) within the range that satisfies the above conditions, it is possible to change the substantial exposure amount, and to reduce the film thickness after development of the exposed resist. It is possible to adjust.

  Note that a negative resist is difficult to apply as a resist used in the photolithography process, and therefore, the pattern of the exposure mask is premised on a positive resist. As the exposure apparatus, a projection type exposure apparatus can be used. As the projection magnification, an exposure device with the same magnification can be used, or a reduction projection exposure device with a projection magnification of 1 / m can be used.

When the exposure mask shown in FIGS. 1A to 1C is irradiated with exposure light, the light intensity of the light shielding portion P is almost zero and the light intensity of the transmission portion R is almost 100%. On the other hand, the light intensity of the semi-transmissive portion can be adjusted in a range of 10 to 70%, and an example of a typical light intensity distribution is shown in a light intensity distribution 214 in FIG. The adjustment of the light intensity of the semi-transmissive portion Q in the exposure mask can be realized by adjusting the line width L and the space width S (or the width L in the short side direction and the space S in the short side direction of the rectangular pattern). it can.

An exposure mask that satisfies the above relationship is one in which the semi-transmissive portion Q is disposed on the side of the light-shielding portion P, that is, the semi-transmissive portion Q is disposed between the light-shielding portion P and the transmissive portion R. It is particularly effective to use it.

(Embodiment 2)
In this embodiment mode, a TFT gate electrode is patterned using the exposure mask shown in Embodiment Mode 1, and this gate electrode is used as a mask for ion doping, so that low-concentration impurity regions are formed on both sides of a channel formation region. A process for forming in a self-aligned manner is shown together with FIG.

  First, a first insulating film (base insulating film) 102 is formed over a substrate 101 having an insulating surface. As the substrate 101 having an insulating surface, a light-transmitting substrate such as a glass substrate, a crystallized glass substrate, or a plastic substrate can be used. When a thin film transistor to be formed later is applied to a top emission type (upward emission type) light emitting display device or a reflection type liquid crystal display device, a ceramic substrate, a semiconductor substrate, a metal substrate, or the like can also be used. .

As the first insulating film 102, a single layer or a stacked layer of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is used. Next, the semiconductor layer 103 is formed over the first insulating film 102.

  The semiconductor layer 103 is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like), forming a crystalline semiconductor film crystallized by heat treatment, After forming a resist film over the crystalline semiconductor film, a crystalline semiconductor film is formed into a desired shape using a first resist mask obtained by exposure and development.

  The semiconductor layer 103 is formed with a thickness of 25 to 80 nm (preferably 30 to 70 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  The heat treatment may be a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof.

  Alternatively, the crystalline semiconductor film may be formed by a thermal crystallization method in which the above heat treatment is performed after adding a catalyst such as nickel. Note that in the case where a crystalline semiconductor film is obtained by crystallization using a thermal crystallization method using a catalyst such as nickel, it is preferable to perform a gettering treatment for removing the catalyst such as nickel after crystallization.

When a crystalline semiconductor film is formed by a laser crystallization method, a continuous-wave (CW) laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) is used. be able to. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. This laser can be emitted by CW or pulsed oscillation. When injected at a CW, the power density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, a great improvement in output can be expected.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  When a semiconductor film is annealed using a linear beam having a uniform intensity obtained in this manner and an electronic device is manufactured using this semiconductor film, the characteristics of the electronic device are good and uniform.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the semiconductor layer in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, after removing the first resist mask, the oxide film on the surface of the semiconductor layer is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the semiconductor layer is washed. Then, a second insulating film (gate insulating film) 104 covering the semiconductor layer is formed. The second insulating film 104 is formed by plasma CVD, sputtering, or thermal oxidation, and has a thickness of 1 to 200 nm, preferably 70 to 120 nm. As the second insulating film 104, a film formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by plasma CVD.

In addition, after forming an insulating layer, a semiconductor layer, a gate insulating layer, an interlayer insulating layer, or the like as a substrate, a base film, the substrate, an insulating layer as a base film by performing oxidation or nitridation using plasma treatment, The surfaces of the semiconductor layer, the gate insulating layer, and the interlayer insulating layer may be oxidized or nitrided. When a semiconductor layer or an insulating layer is oxidized or nitrided using plasma treatment, the surface of the semiconductor layer or the insulating layer is modified, so that the insulating film becomes denser than an insulating film formed by a CVD method or a sputtering method. be able to. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved. The plasma treatment as described above can also be performed on the gate electrode layer, the source electrode layer, the drain electrode layer, the wiring layer, and the like, and a nitride film or an oxide film can be formed by performing nitridation or oxidation.

Note that in the case of oxidizing a film by plasma treatment, an oxygen atmosphere (for example, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen and hydrogen are used. (H ₂ ) and a rare gas atmosphere or dinitrogen monoxide and a rare gas atmosphere). On the other hand, in the case of nitriding a film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or nitrogen and hydrogen And a rare gas atmosphere or NH ₃ and a rare gas atmosphere). As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating film formed by the plasma treatment contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing, and when Ar is used, the insulating film Contains Ar.

In the case where the second insulating film 104 is subjected to plasma treatment, the plasma treatment is performed in an atmosphere of the gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and a plasma electron temperature of 1.5 eV or less. . More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the electron temperature of plasma is 0.5 eV to 1.5 eV. Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the second insulating film 104 functioning as a gate insulating layer) formed on the substrate is low, Damage can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower by 100 degrees or more than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

  Next, a stack of the first conductive layer 105a and the second conductive layer 106a is formed. Further, the stacking is not limited to two layers of the first conductive layer and the second conductive layer, and may be three or more layers.

  The first conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. It is formed with a thickness of ˜50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm.

  Here, two layers, that is, the first conductive layer and the second conductive layer are used as different conductive materials so that a difference in etching rate is generated in an etching process performed later. TaN is used as the first conductive layer, and a tungsten film is used as the second conductive layer.

Next, after a resist film is applied over the entire surface of the second conductive layer 106a, exposure is performed using an exposure mask illustrated in FIG. Here, a resist film having a thickness of 1.5 μm is applied, and exposure is performed using an exposure apparatus having a resolution of 1.5 μm and a projection magnification of equal magnification. The light used for exposure is i-line (wavelength 365 nm), and the exposure energy is selected from the range of 20 to 140 mJ / cm ² . The light is not limited to i-line, and light obtained by mixing i-line, g-line (wavelength 436 nm) and h-line (wavelength 405 nm) may be used for exposure.

In FIG. 2A, an exposure mask is a light in which a light-blocking portion 401 made of a metal film such as Cr is formed on a light-transmitting substrate 400 that can transmit exposure light, and lines and spaces are repeatedly formed with a predetermined line width. A semi-transmissive portion 402 having a strength reducing function is provided. In the exposure mask, when the line width of the light shielding material in the semi-transmissive portion is L and the space width between the light shielding materials is S, the sum of L and S, the resolution n of the exposure apparatus, and the projection magnification 1 / m (m ≧ 1) ) relationship with the, (n / 3) meets × m ≦ L + S ≦ ( 3n / 2) × conditional expression m, and, n, m, the relationship of L is, L <(2n / 3) × m the less than using the Suyo mask. Desirably, the sum of L and S, n, the relationship between m, (2n / 3) × m ≦ L + S ≦ (6n / 5) meet the conditional expression × m, and, n, m, of L relationships using L <(2n / 3) Suyo exposure mask meet × m.

For example, an exposure apparatus having a resolution of 1.5 μm and a projection magnification of 1 × can be used, and an exposure mask having a translucent portion line width L of 0.5 μm and a semi-transmissive portion space width S of 1.0 μm can be used. .

When the resist film is exposed using the exposure mask shown in FIG. 2A, a non-exposed region 403a and an exposed region 403b are formed in the resist film. At the time of exposure, exposure light wraps around the light shielding portion 401 or passes through the semi-transmissive portion 402, thereby forming an exposure region 403b shown in FIG.

Then, when the development is performed, the exposed region 403b is removed, and as shown in FIG. 2B, a resist pattern 107a having a thick film region and a thin film region on the side portion is formed on the side. Obtained on two conductive layers 106a. In the resist pattern 107a, in a thin region, the resist film thickness can be adjusted by adjusting the exposure energy. By using the exposure mask shown in FIG. 2A, the film thickness can be uniformly formed even in a region where the resist film thickness is thin.

Next, the second conductive layer 106a and the first conductive layer 105a are etched by dry etching. Dry etching is performed while ashing the resist pattern 107a. As the etching gas, CF ₄ , SF ₆ , Cl ₂ , and O ₂ are used. In order to improve the etching rate, a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) is used. Note that, depending on the etching conditions, the second insulating film 104 is also etched, and the film thickness is partially reduced.

  Although an example using an ICP etching apparatus is shown here, the invention is not particularly limited. For example, a parallel plate etching apparatus, a magnetron etching apparatus, an ECR etching apparatus, or a helicon etching apparatus may be used. Further, the method is not limited to the dry etching method, and a wet etching method may be used, or a combination of the dry etching method and the wet etching method may be used.

Thus, as shown in FIG. 2C, a conductive laminated pattern including the first conductive layer 105b and the second conductive layer 106b is formed over the second insulating film 104. By etching, both side walls of the first conductive layer 105b are exposed, and further, a region that does not overlap with the second conductive layer 106b is exposed. Note that both side walls of the first conductive layer 105b may have a tapered shape. Further, both side walls of the second conductive layer 106b may be tapered.

  Next, after removing the resist pattern 107 b, one conductivity type impurity is added to the semiconductor layer 103. Here, phosphorus (or As) is used as an ion of one conductivity type impurity, and an n-channel TFT is manufactured. An LDD region, a source region, and a drain region can be formed in a self-aligning manner using a conductive laminated pattern without forming a sidewall.

In the case of performing a doping process for forming a source region and a drain region located outside the gate electrode, ions of one conductivity type impurity are added to the semiconductor layer 103 using the conductive layer pattern as a mask, and the one conductivity type impurity having a high concentration is added. The regions 110 and 111 may be formed. The doping conditions for forming the source region and the drain region are an acceleration voltage of 50 to 100 kV. The impurity concentration of the high-concentration one-conductivity type impurity regions 110 and 111 is 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ (peak value in SIMS measurement).

In addition, in the case of performing a doping process for forming an LDD region overlapping with the gate electrode, ions of one conductivity type impurity are passed through the first conductive layer 105b in a region not stacked with the second conductive layer. Low-concentration one-conductivity type impurity regions 109a and 109b may be formed by adding to the layer 103. This doping condition depends on the film thickness of the second insulating layer or the first conductive layer, but in this case, an acceleration voltage of 60 to 100 kV is required. The impurity concentration of the low-concentration one-conductivity type impurity regions 109a and 109b is 1 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ (peak value in SIMS measurement) assuming the LDD region.

Note that the order of doping is not particularly limited, and the doping process for forming the LDD region may be performed after the doping process for forming the source region and the drain region is performed first. In addition, after performing the doping process for forming the LDD region, the doping process for forming the source region and the drain region may be performed.

  Although an example in which the doping process is divided into two times to form impurity regions having different concentrations has been described here, the impurity regions having different concentrations can be formed by one doping process by adjusting the processing conditions. Good.

Moreover, although the example which removed the resist pattern before doping was shown, you may remove a resist pattern after performing a doping process. When doping is performed with the resist pattern remaining, doping can be performed while protecting the surface of the second conductive layer with the resist pattern.

Note that in the doping process, the semiconductor layer in a position overlapping with the second conductive layer is a region to which ions of one conductivity type impurity are not added, and functions as a channel formation region of a TFT to be formed later.

In addition, the conductive stacked pattern (the first conductive layer 105 b and the second conductive layer 106 b) serves as a gate electrode at a portion intersecting with the semiconductor layer 103. The low concentration impurity regions 109a and 109b overlapping with the gate electrode are referred to as L _ov regions. The L _ov region is formed using a region of the first conductive layer 105b that does not overlap the second conductive layer 106b. The length of the required L _ov region may be determined in accordance with the type and application of the circuit having the TFT, and the photomask and etching conditions may be set based on the length.

  Thereafter, a third insulating film 112 using silicon nitride oxide is formed. Then, the impurity element added to the semiconductor layer is activated and hydrogenated.

  Next, a light-transmitting inorganic material (silicon oxide, silicon nitride, silicon oxynitride, etc.) or a low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material such as polyimide or polybenzoxazole) is used. The fourth insulating film 113 is formed by using this. Alternatively, the fourth insulating film may be formed using a material containing siloxane. Siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, a resist mask is formed using a third photomask, and a third insulating film 112 that functions as an interlayer insulating film, a fourth insulating film 113, and a second insulating film 104 that functions as a gate insulating film are formed. A contact hole is formed by selective etching. Then, the resist mask is removed.

  Next, after a metal laminated film is formed over the fourth insulating film 113 by a sputtering method, a resist mask is formed using a fourth photomask, and the metal laminated film is selectively etched to form a semiconductor layer. A source electrode 114 or a drain electrode 115 in contact with the electrode is formed.

  A connection electrode (an electrode for electrically connecting a plurality of TFTs) and a terminal electrode (an electrode for connecting to an external power source) are also formed on the fourth insulating film 113 simultaneously with the source electrode 114 or the drain electrode 115 of the TFT. can do. Then, the resist mask is removed. Note that the metal stacked film is a three-layer stack including a Ti film with a thickness of 100 nm, an Al film containing a small amount of Si with a thickness of 350 nm, and a Ti film with a thickness of 100 nm. The metal laminated film is preferably formed continuously in the same metal sputtering apparatus.

  Through the above steps, a top-gate TFT having low-concentration impurity regions 109a and 109b on both sides of the channel formation region shown in FIG. 2D is completed.

  As described above, in the present embodiment, by using an exposure mask having a semi-transmissive portion as shown in FIG. 2A, the thickness of the photoresist layer in the semi-transmissive portion is thin, and A resist pattern 107a having a uniform film thickness is formed, and a gate electrode is obtained using the resist pattern. The gate electrode is used as a mask during ion doping, and low-concentration impurity regions overlapping with the gate electrode are formed on both sides of the channel formation region in a self-aligned manner.

Thus, by manufacturing a semiconductor device including a TFT (GOLD structure: Gate-drain overlapped LDD) having a low-concentration impurity region (referred to as a L _ov region) overlapping with the gate electrode in a self-aligning manner, the number of masks Can be realized, and at the same time, fine alignment is not required when fabricating the GOLD structure. As a result, many processes such as substrate cleaning, resist material application, pre-baking, exposure, development, and post-baking can be reduced, and the processing time can be shortened. And manufacturing cost can be reduced and the yield of a product can be improved.

In the present embodiment, generation of hot carriers can be suppressed by forming the L _ov region, and deterioration of the semiconductor element can be prevented. The L _ov region can be formed in a self-aligned manner, and the length (the length in the channel length direction) is not limited, and the length can be sufficiently secured. In addition, the lengths of the L _ov regions on both sides of the channel formation region can be made different.

In addition, various circuits are included in the semiconductor device, and depending on the circuit, a GOLD structure having a L _ov region that has an excellent hot carrier countermeasure effect may be suitable, or a L _off region ( A structure having a low-concentration impurity region that does not overlap with the gate electrode may be suitable. In some cases, a structure having only a source region and a drain region without a low-concentration impurity region may be suitable. In this embodiment mode, a GOLD structure or other structures can be formed separately for each circuit over the same substrate.

  In this embodiment mode, a thicker first region is formed using an exposure mask provided with a semi-transmissive portion as shown in FIG. 2A, and a film is formed on the side of the first region than the first region. An example of forming a gate electrode having a thin second region is shown. However, not only the gate electrode, but also when forming other electrodes, wirings, etc., if necessary, using an exposure mask having a semi-transmissive portion as shown in FIG. An electrode, wiring, or the like having a thick region and a thin region on the side of the region can be obtained.

  In this embodiment mode, an n-channel TFT has been described. However, a p-type impurity element (such as boron) is used instead of an n-type impurity element (group 15 impurity element represented by phosphorus or arsenic). A p-channel TFT can be formed by using a typical Group 13 impurity element in the periodic table.

  Further, an n-channel TFT and a p-channel TFT can be formed on the same substrate, and a CMOS circuit can be configured by combining these TFTs in a complementary manner. A CMOS circuit is a circuit having at least one n-channel TFT and one p-channel TFT (inverter circuit, NAND circuit, AND circuit, NOR circuit, OR circuit, shift register circuit, sampling circuit, D / A converter) Circuit, A / D converter circuit, latch circuit, buffer circuit, etc.). In addition, by combining these CMOS circuits, memory elements such as SRAM and DRAM and other elements can be formed on the substrate. It is also possible to configure a CPU on a substrate by integrating various elements and circuits.

Further, the top gate type TFT having the above structure (the structure having the L _ov region having the same width on both sides of the channel formation region) and the channel formation region on the same substrate without increasing the number of steps only by changing the exposure mask. Both top-gate TFTs having a structure in which one side of each has a wider L _ov region than the other side can also be formed.

  Although this embodiment mode is described using a single-gate top-gate TFT, a top-gate TFT having a multi-gate structure having a plurality of channel formation regions can also be formed. In addition, a single-gate top gate TFT and a multi-gate top gate TFT can be formed on the same substrate without changing the number of steps simply by changing the exposure mask.

  Therefore, various circuits can be configured by assigning transistors having an optimal structure on the same substrate without increasing the number of steps.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1.

(Embodiment 3)
Although formation of the conductive laminated pattern shown in Embodiment 2 is not particularly limited, an example in which the conductive laminated pattern is formed by changing the etching conditions a plurality of times in the middle is shown in FIG.

  First, in the same manner as in Embodiment Mode 2, a resist pattern 307a is formed on the second conductive layer 306a. FIG. 3A corresponds to FIG.

In FIG. 3A, a first insulating film (base insulating film) 302, a semiconductor layer 303, and a second insulating film (gate insulating film) 304 are formed over a substrate 301, and a first conductive layer 305a, A second conductive layer 306a is formed.

  Next, etching is performed under a first etching condition, so that a resist pattern 307b and a second conductive layer 306b having a step shape as shown in FIG. 3B are formed. A tapered portion is formed in part of the second conductive layer 306b under the first etching conditions.

  Next, etching is continuously performed under the first etching condition to obtain the state of FIG. At this stage, a resist pattern 307c having no step is formed. In addition, the thickness of the second conductive layer 306c is reduced while forming a tapered portion.

  Next, etching is continued under the first etching condition to obtain the state of FIG. Further, the resist pattern is reduced to form a resist pattern 307d. A convex second conductive layer 306d having a thick first region and a second region having a smaller thickness than the first region is formed on both sides of the first region. A part of one conductive layer 305a is exposed.

  Next, etching is performed under the second etching condition, and the first conductive layer 305b is formed by etching using the convex second conductive layer 306d as a mask.

  Next, anisotropic etching is performed under a third etching condition to form the second conductive layer 306e. In this anisotropic etching, it is important that the difference in etching rate between the first conductive layer and the second conductive layer is large, and it is preferable to use different conductive materials for the first conductive layer and the second conductive layer. Further, by adjusting the third etching condition, it is possible to prevent the second insulating film from being partially thinned by this anisotropic etching.

  Thus, by forming the conductive laminated pattern by finely changing the etching conditions, variations in the shape of the conductive laminated pattern can be suppressed.

  Since the subsequent steps are the same as those of the second embodiment, detailed description thereof is omitted here.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

(Embodiment 4)
Here, only by changing the exposure mask, without increasing the number of processes, the top gate TFT of the above structure (structure having L _ov regions of the same width on both sides of the channel formation region) on the same substrate and the drain side FIG. 4 shows an example of forming a top gate type TFT having a structure having a L _ov region wider than the source side.

  In FIG. 4A, a semiconductor layer 502 and a semiconductor layer 503 are formed over a substrate 500 and an insulating layer 508. A gate insulating layer 504, a first conductive film 505, and a second conductive film 506 are formed so as to cover the semiconductor layer 502 and the semiconductor layer 503, and a resist pattern 529 and a resist pattern 539 having different shapes using an exposure mask , And a resist pattern 549 are formed.

These resist patterns can be formed using an exposure mask shown in FIG. As in the first or second embodiment, the width of the line made of the light shielding material in the semi-transmissive portion is L, the width of the space between the light shielding materials is S, the sum of L and S, and the resolution of the exposure apparatus n, the relationship between the projection magnification 1 / m (m ≧ 1) is, (n / 3) × meets m ≦ L + S ≦ (3n / 2) × conditional expression m, and, n, m, the relationship of L uses L <(2n / 3) Suyo exposure mask meet × m. Desirably, the sum of L and S, n, the relationship between m, (2n / 3) × m ≦ L + S ≦ (6n / 5) meet the conditional expression × m, and, n, m, of L relationships using L <(2n / 3) Suyo exposure mask meet × m. The arrangement, material, shape, etc. of the semi-transmissive portion can be the same as those shown in the first and second embodiments. As the exposure apparatus, a projection type exposure apparatus can be used. As the projection magnification, an exposure device with the same magnification can be used, or a reduction projection exposure device with a projection magnification of 1 / m can be used.

  The resist pattern 529 is formed by a mask provided with a semi-transmissive portion 552 having the same width on both sides of the light shielding portion 551. The resist pattern 539 is formed by an exposure mask in which a wide semi-transmissive portion 554 is provided on one side of the light shielding portion 553 and a narrow semi-transmissive portion 554 is provided on the other side. The resist pattern 549 is formed by an exposure mask provided with only the light shielding portion 555. The resist pattern 529 has a shape having gentle steps on both sides (symmetrical shape in the cross section of FIG. 4A), and the resist pattern 539 has a shape in which the convex portion is shifted from the center (FIG. 4A). The resist pattern 549 has a shape with no step and unevenness (a shape that is symmetrical in the cross section of FIG. 4A).

  Patterning is performed by etching using the resist pattern 529, the resist pattern 539, and the resist pattern 549, and the first gate electrode layer 521, the second gate electrode layer 522, the first gate electrode layer 531, and the second gate are formed. An electrode layer 532, a first wiring layer 541, and a second wiring layer 542 are formed.

  Using the second gate electrode layer 522 and the second gate electrode layer 532 as masks, an impurity element having one conductivity type is added to the semiconductor layer 502 and the semiconductor layer 503, so that the low concentration impurity region 524a and the low concentration impurity region are added. A low concentration impurity region 534a and a low concentration impurity region 534b are formed (see FIG. 4B).

  Further, the semiconductor layer 502 and the semiconductor layer 503 have one conductivity type using the first gate electrode layer 521, the second gate electrode layer 522, the first gate electrode layer 531 and the second gate electrode layer 532 as a mask. An impurity element is added to form a high concentration impurity region 525a, a high concentration impurity region 525b, a high concentration impurity region 535a, and a high concentration impurity region 535b.

  Further, the resist pattern 523, the resist pattern 533, and the resist pattern 543 are removed.

  Thus, the first TFT portion 520, the second TFT portion 530, and the wiring portion 540 can be formed on the same substrate. In the first TFT portion 520, a TFT having a low concentration impurity region 526a on the source side and a low concentration impurity region 526b on the drain side is formed. The low concentration impurity region 526a and the low concentration impurity region 526b are formed with the same width. In the second TFT portion 530, a TFT having low-concentration impurity regions 536a and 536b on both sides of the channel formation region is manufactured. Note that the low concentration impurity region 536b is wider than the low concentration impurity region 536a (see FIG. 4C). Further, in the wiring portion 540, a stack in which the positions of the end faces coincide, that is, a stack of the first wiring layer 541 and the second wiring layer 542 is obtained.

  In addition, by using the same resist pattern, the same structure as the second TFT portion 530 can be formed, and the capacitor and the TFT can be formed on the same substrate. In that case, a capacitor using the gate insulating layer 504 as a dielectric can be formed.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3.

(Embodiment 5)
In this embodiment mode, a structure of an active matrix light-emitting device will be described below together with a manufacturing method with reference to FIGS.

First, a base insulating film is formed over the substrate 610 having an insulating surface. In the case where light emission is extracted using the substrate 610 side as a display surface, a light-transmitting glass substrate or quartz substrate may be used as the substrate 610. Alternatively, a light-transmitting plastic substrate having heat resistance that can withstand the processing temperature may be used. In the case where light emission is extracted using a surface opposite to the substrate 610 side as a display surface, a substrate in which an insulating film is formed on the surface of a silicon substrate, a metal substrate, or a stainless steel substrate in addition to the above substrate may be used. Here, a glass substrate is used as the substrate 610. The refractive index of the glass substrate is around 1.55.

  As the base insulating film 611, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example in which a single layer structure is used as the base film is shown, but a structure in which two or more insulating films are stacked may be used. Note that the base insulating film is not necessarily formed if unevenness of the substrate or impurity diffusion from the substrate is not a problem.

  Next, a semiconductor layer is formed over the base insulating film. The semiconductor layer is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and then known crystallization treatment (laser crystallization method, thermal crystallization method). The crystalline semiconductor film obtained by performing a thermal crystallization method using a catalyst such as nickel or the like is patterned into a desired shape using a first photomask to form a semiconductor layer. Note that when a plasma CVD method is used, a base insulating film and a semiconductor film having an amorphous structure can be stacked successively without being exposed to the air. The semiconductor film is formed with a thickness of 25 to 80 nm (preferably 30 to 70 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  Here, as a technique for crystallizing a semiconductor film having an amorphous structure, the technique described in JP-A-8-78329 is used for crystallization. The technology described in this publication is based on a crystal structure in which an amorphous silicon film (also referred to as an amorphous silicon film) is selectively added with a metal element that promotes crystallization, and heat treatment is performed to expand the added region as a starting point. The semiconductor film which has this is formed.

  Hereinafter, an example of a method for forming a crystalline semiconductor film will be described in detail.

  First, a nickel acetate solution is applied to a surface of a semiconductor film having an amorphous structure by applying a nickel acetate solution containing 1 to 100 ppm of a metal element having a catalytic action for promoting crystallization (here, nickel) by weight with a spinner. Form a layer. As a means other than the method for forming the nickel-containing layer by coating, a means for forming an extremely thin film by sputtering, vapor deposition, or plasma treatment may be used. Although an example in which the coating is performed on the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Next, heat treatment is performed to perform crystallization. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Thus, a semiconductor film having a crystal structure is formed. Note that the concentration of oxygen contained in the crystallized semiconductor film is desirably 5 × 10 ¹⁸ / cm ³ or less. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C. to 650 ° C. for 4 to 24 hours) is performed. When crystallization is performed by irradiation with strong light, any one of infrared light, visible light, and ultraviolet light, or a combination thereof can be used. Note that if necessary, heat treatment for releasing hydrogen contained in the semiconductor film having an amorphous structure may be performed before irradiation with strong light. In addition, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. In consideration of productivity, it is desirable to perform crystallization by irradiation with strong light.

In the crystalline semiconductor film thus obtained, a metal element (here, nickel) remains. Although it is not uniformly distributed in the film, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ in terms of an average concentration. Of course, various semiconductor elements including TFT can be formed even in such a state, but the element is removed by a gettering method described below.

  Here, the natural oxide film formed in the crystallization step is removed before the laser light irradiation. Since this natural oxide film contains nickel in high concentration, it is preferably removed.

Next, the crystalline semiconductor film is irradiated with laser light in order to increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains. When laser light is irradiated, distortion and ridges are formed in the semiconductor film, and a thin surface oxide film (not shown) is formed on the surface. As this laser light, an excimer laser light having a wavelength of 400 nm or less emitted from a pulsed laser light source, or a second harmonic or a third harmonic of a YAG laser may be used. In addition, a solid-state laser capable of continuous oscillation may be used as the laser light, and the second to fourth harmonics of the fundamental wave may be used. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied.

  Next, first heat treatment (heat treatment in which the semiconductor film is instantaneously heated to about 400 to 1000 ° C.) for reducing distortion of the crystalline semiconductor film is performed in a nitrogen atmosphere to obtain a flat semiconductor film. As the heat treatment for instantaneously heating, heating may be performed by heat treatment for irradiating strong light, or heat treatment for putting a substrate into a heated gas and leaving it for several minutes, and then removing the substrate. Further, depending on the conditions of this heat treatment, it is possible to reduce the distortion and repair defects left in the crystal grains, that is, improve the crystallinity. This heat treatment also reduces the strain and makes it easier for the nickel to be gettered in a later gettering step. When the temperature in this heat treatment is lower than the crystallization temperature, nickel moves in the film while the silicon film remains in a solid state.

  Next, a semiconductor film containing a rare gas element is formed above the crystalline semiconductor film. An oxide film (referred to as a barrier layer) serving as an etching stopper may be formed with a thickness of 1 to 10 nm before forming a semiconductor film containing a rare gas element. The barrier layer may be formed at the same time by heat treatment for reducing distortion of the semiconductor film.

  The semiconductor film containing a rare gas element is formed by a plasma CVD method or a sputtering method to form a gettering site with a thickness of 10 nm to 300 nm. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Among them, argon (Ar) which is an inexpensive gas is preferable.

Here, the PCVD method is used, monosilane and argon are used as source gases, and the ratio (monosilane: argon) is controlled to 0.1: 99.9 to 1: 9, preferably 1:99 to 5:95. Film. In addition, the RF power density during film formation is desirably 0.0017 W / cm ^{2 to} 0.48 W / cm ² . When the RF power density is high, the film quality is such that a gettering effect can be obtained, and in addition, the film formation speed is improved. The pressure during film formation is preferably 1.333 Pa (0.01 Torr) to 133.322 Pa (1 Torr). The higher the pressure, the higher the deposition rate. However, the higher the pressure, the lower the concentration of Ar contained in the film. Further, it is desirable that the film forming temperature be 300 ° C. to 500 ° C. Thus, plasma CVD is performed on a semiconductor film containing argon at a concentration of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ^{3 in} the film. The film can be formed by the method. By adjusting the film formation conditions of the semiconductor film containing the rare gas element within the above range, damage to the barrier layer during film formation can be reduced. It is possible to prevent the occurrence of a defect that a hole is formed in the surface.

There are two meanings of including a rare gas element ion which is an inert gas in the film. One is to form a dangling bond, and the other is to strain the semiconductor film. Distortion of the semiconductor film is remarkably obtained when an element having a larger atomic radius than silicon, such as argon (Ar), krypton (Kr), or xenon (Xe), is used. In addition, by including a rare gas element in the film, not only the semiconductor film is distorted but also a dangling bond is formed, which contributes to the gettering action.

  Next, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the crystalline semiconductor film. As the heat treatment for performing gettering, heat treatment may be performed by irradiating with strong light, heat treatment using a furnace, or by putting the substrate into a heated gas, leaving it for a few minutes, and taking it out. Here, second heat treatment for performing gettering (heat treatment in which the semiconductor film is instantaneously heated to about 400 to 1000 ° C.) is performed in a nitrogen atmosphere.

  By this second heat treatment, the metal element moves to the semiconductor film containing the rare gas element, and the metal element contained in the crystalline semiconductor film covered with the barrier layer is removed or the concentration of the metal element is reduced. The metal element contained in the crystalline semiconductor film moves in a direction perpendicular to the substrate surface and toward the semiconductor film containing a rare gas element.

The distance that the metal element moves during gettering may be about the thickness of the crystalline semiconductor film, and the gettering can be completed in a relatively short time. Here, nickel is transferred to a semiconductor film containing a rare gas element so as not to segregate in the crystalline semiconductor film, and the nickel contained in the crystalline semiconductor film is almost absent, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm. Gettering is sufficiently performed so that it is ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less. Note that not only a semiconductor film containing a rare gas element but also a barrier layer functions as a gettering site.

Next, only the semiconductor film containing a rare gas element is selectively removed using the barrier layer as an etching stopper. As a method of selectively etching only a semiconductor film containing a rare gas element, dry etching without using plasma with ClF ₃ , hydrazine, tetramethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NOH) (abbreviation TMAH) It can be performed by wet etching with an alkaline solution such as an aqueous solution containing. Note that in order to prevent pinholes from being formed in the crystalline semiconductor film by this etching, the overetching time is reduced.

  Next, the barrier layer is removed with an etchant containing hydrofluoric acid.

Further, before the semiconductor film containing a rare gas element is formed, a flushing process may be performed using a flash substance in order to remove impurities such as F in the chamber. A process (flushing) that coats the inner wall of the chamber by using monosilane as a flash substance and continuously introduces a gas flow rate of 8 to 10 SLM into the chamber for 5 to 20 minutes, preferably 10 to 15 minutes, and prevents adhesion of impurities to the substrate. Treatment, also called silane flash). Note that 1 SLM is 1000 sccm, that is, 0.06 m ³ / h.

  Through the above steps, a good crystalline semiconductor film can be obtained.

After the crystalline semiconductor film is patterned into a desired shape using a first photomask, the resist mask is removed. Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the semiconductor layer in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film on the surface of the semiconductor layer is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the semiconductor layer is washed.

Then, an insulating film covering the semiconductor layer is formed. The insulating film is formed by plasma CVD or sputtering and has a thickness of 1 to 200 nm. It is preferably formed as a single layer or a laminated structure of an insulating film containing silicon by thinning to 10 nm to 50 nm, and then surface nitriding treatment using plasma by microwave is performed. The insulating film functions as a gate insulating film of a TFT formed later.

Next, a first conductive film with a thickness of 20 to 100 nm and a second conductive film with a thickness of 100 to 400 nm are stacked over the insulating film. In this embodiment mode, a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 370 nm are sequentially stacked over the insulating film 613, and the transflective function having the light intensity reduction function described in Embodiment Modes 1 and 2 is applied. Each gate electrode and each wiring are formed using the exposure mask provided with the part. As the exposure apparatus, a projection type exposure apparatus can be used. As the projection magnification, an exposure device with the same magnification can be used, or a reduction projection exposure device with a projection magnification of 1 / m can be used.

Here, the conductive film is a laminate of a TaN film and a W film, but is not particularly limited, and an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy containing the above element as a main component You may form by lamination | stacking of material or a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked. Also good.

  An ICP (Inductively Coupled Plasma) etching method may be used for etching the first conductive film and the second conductive film (first etching process and second etching process). Using the ICP etching method, the film is formed into a desired shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.). It can be etched.

Next, in order to add an impurity element imparting n-type conductivity to the semiconductor layer, a first doping step is performed in which the entire surface is doped using the gate electrode as a mask. The first doping step may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 kV. By adding the impurity element to the semiconductor layer through the first conductive film in the region not stacked with the second conductive film in the first doping step, the low-concentration impurity region overlapping the gate electrode is formed. Can be formed. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity.

  Next, after forming a mask made of a resist, a second doping step is performed for doping the semiconductor with an impurity element imparting n-type at a higher concentration than in the first doping step. The mask includes a source region and a drain region of a semiconductor layer forming a p-channel TFT in the pixel portion, and a peripheral region thereof, a part of the n-channel TFT in the pixel portion, and a p-channel TFT in the driver circuit portion. Are provided to protect the source region, the drain region, and the peripheral region of the semiconductor layer forming the semiconductor layer.

The conditions of the ion doping method in the second doping step are a dose amount of 5 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 50 to 100 kV. The source region and the drain region of the n-channel TFT are formed by the second doping process. Note that the acceleration voltage in the second doping step is lower than that in the first doping step.

  Next, after removing the mask, a new mask made of resist is formed, and a third doping step for doping the semiconductor with p-type impurity element (typically boron) at a high concentration is performed. The mask includes a source region and a drain region of a semiconductor layer in which an n-channel TFT in the pixel portion is formed, and a peripheral region thereof, and a source region and a drain region in a semiconductor layer in which the n-channel TFT in the driver circuit portion is formed, And their surrounding areas are provided for protection. The source region and drain region of the p-channel TFT are formed by the third doping step.

  Thereafter, the resist mask is removed. Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer.

  Next, after an insulating film containing hydrogen is formed by an LPCVD method, a plasma CVD method, or the like, the impurity element added to the semiconductor layer is activated and hydrogenated. As the insulating film containing hydrogen, a silicon nitride oxide film (SiNO film) obtained by a PCVD method is used. Here, the thickness of the insulating film containing hydrogen is 50 nm to 200 nm. Note that the insulating film containing hydrogen is the first layer of the interlayer insulating film and contains silicon oxide.

  Next, an inorganic insulating film serving as a second layer of the interlayer insulating film is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. As the inorganic insulating film, a single layer or a stacked layer of insulating films such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Here, the thickness of the inorganic insulating film is 600 nm to 800 nm.

Next, a resist mask is formed using a photomask, and the insulating film is selectively etched to form contact holes. Then, the resist mask is removed.

  Next, after a metal film is stacked by sputtering, a mask made of a resist is formed using a photomask, and the metal stacked film is selectively etched to form an electrode that functions as a source electrode or a drain electrode of the TFT. . The metal laminated film is continuously formed in the same metal sputtering apparatus. Then, the resist mask is removed.

  Through the above steps, top-gate TFTs 636, 637, 638, and 639 using a polysilicon film as an active layer can be manufactured over the same substrate.

Note that the TFT 638 arranged in the pixel portion is an n-channel TFT having a plurality of channel formation regions in one TFT. The TFT 638 is a double gate type TFT. The TFT 638 includes low-concentration impurity regions on both sides of the channel formation region. The low concentration impurity region has a region overlapping with the gate electrode (L _ov region) and a region not overlapping with the gate electrode (L _off region). In the pixel portion, a TFT 639 that is electrically connected to a light-emitting element to be formed later is provided. Here, a double gate p-channel TFT is shown as the TFT 639 in order to reduce off-state current; however, there is no particular limitation, and a single gate TFT may be used.

Further, the TFT 636 disposed in the driver circuit portion is an n-channel TFT provided with low-concentration impurity regions (L _ov regions) on both sides of the channel formation region. The low concentration impurity region overlaps the gate electrode in a self-aligning manner. The TFT 637 is a p-channel TFT provided with impurity regions having the same width on both the source side and the drain side. Both are single-gate TFTs. In the driver circuit portion, a CMOS circuit can be configured by complementarily connecting the TFT 636 and the TFT 637, and various types of circuits can be realized. If necessary, a multi-gate TFT can be formed.

Next, the first electrode 623, that is, the anode (or cathode) of the organic light emitting element is formed. As the first electrode 623, a material having a high work function, for example, an element selected from Ni, W, Cr, Pt, Zn, Sn, In, or Mo, or an alloy material containing the element as a main component, for example, TiN, A single layer film or a laminated film thereof may be used in a total film thickness range of 100 nm to 800 nm using TiSi _X N _Y , WSi _X , WN _X , WSi _X N _Y , and NbN.

  Specifically, a transparent conductive film formed using a light-transmitting conductive material may be used as the first electrode 623, and includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, and titanium oxide. Indium oxide, indium tin oxide containing titanium oxide, or the like can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can also be used.

  In addition, compositional proportions of each light-transmitting conductive material will be described. The composition ratio of indium oxide containing tungsten oxide may be 1.0 wt% tungsten oxide and 99.0 wt% indium oxide. The composition ratio of indium zinc oxide containing tungsten oxide may be 1.0 wt% tungsten oxide, 0.5 wt% zinc oxide, and 98.5 wt% indium oxide. The indium oxide containing titanium oxide may be 1.0 wt% to 5.0 wt% titanium oxide and 99.0 wt% to 95.0 wt% indium oxide. The composition ratio of indium tin oxide (ITO) may be 10.0 wt% tin oxide and 90.0 wt% indium oxide. The composition ratio of indium zinc oxide (IZO) may be 10.7 wt% zinc oxide and 89.3 wt% indium oxide. The composition ratio of indium tin oxide containing titanium oxide may be 5.0 wt% titanium oxide, 10.0 wt% tin oxide, and 85.0 wt% indium oxide. The above composition ratio is an example, and the ratio of the composition ratio may be set as appropriate.

Note that after forming an electrode functioning as a source electrode or a drain electrode of the TFT, a second interlayer insulating film made of an inorganic insulating film is formed with a thickness of 100 to 150 nm, a contact hole reaching the TFT 639 is formed, and then the first interlayer insulating film is formed. An electrode 623 may be formed. As the second interlayer insulating film, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used, and these insulating films may be formed as a single layer or two or more layers. . As a method for forming the inorganic insulating film, a sputtering method, an LPCVD method, a plasma CVD method, or the like may be used. The thickness of the second interlayer insulating film may be formed in the range of 50 nm to 500 nm (preferably 100 nm to 300 nm).
By forming the second interlayer insulating film, it is possible to prevent and protect the TFT, the wiring, and the like of the driving circuit portion from being exposed.

Next, an insulating film (e.g., an organic resin film) obtained by a coating method is patterned to form an insulator 629 (referred to as a bank, a partition, a barrier, a bank, or the like) that covers an end portion of the first electrode 623. Note that the formation of the insulator 629 is not limited to patterning using a mask, and may be formed only by exposure and development using a photosensitive material.

  Next, a layer 624 containing an organic compound is formed by an evaporation method or a coating method.

The layer 624 containing an organic compound is a stacked layer, and a buffer layer may be used as one layer of the layer 624 containing an organic compound. The buffer layer is a composite material including an organic compound and an inorganic compound, and the inorganic compound exhibits an electron accepting property with respect to the organic compound. The buffer layer is a composite material including an organic compound and an inorganic compound, and the inorganic compound includes titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and oxide. One or more selected from the group consisting of manganese and rhenium oxide. The buffer layer is a composite material including an organic compound having a hole transporting property and an inorganic compound.

For example, a stack containing an organic compound (a stack of a buffer layer and an organic compound layer) is preferably provided between the first electrode 623 and the second electrode. The buffer layer includes a metal oxide (molybdenum oxide, tungsten oxide, rhenium oxide, etc.) and an organic compound (a material having a hole transporting property (for example, 4,4′-bis [N- (3-methylphenyl) -N-phenylamino). ] Biphenyl (abbreviation: TPD), 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD), 4,4′-bis {N- [4- ( N, N-di-m-tolylamino) phenyl] -N-phenylamino} biphenyl (abbreviation: DNTPD) and the like)). An EL layer is provided on the buffer layer. The EL layer is formed of, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ) or tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ). Alternatively, α-NPD or the like can be used. The EL layer may contain a dopant material. For example, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, rubrene, or the like can be used. A stack including an organic compound provided between the first electrode and the second electrode may be formed by an evaporation method such as a resistance heating method.

  By adjusting the thickness of the buffer layer, the distance between the first electrode and the organic compound layer can be controlled to increase the light emission efficiency. By adjusting the thickness of the buffer layer, it is possible to display an excellent image in which the emission color from each light emitting element is clearly displayed, and to realize a light emitting device with low power consumption.

  Next, a second electrode 625, that is, a cathode (or an anode) of the organic light emitting element is formed. As the second electrode 625, an alloy such as MgAg, MgIn, or AlLi, or a transparent conductive film (such as ITO) is used.

  Next, the protective layer 626 is formed by an evaporation method or a sputtering method. The protective layer 626 protects the second electrode 625. In the case where light emitted from the light-emitting element is extracted through the protective layer 626, a transparent material is preferably used. Note that the protective layer 626 is not necessarily provided if not necessary.

  Next, the sealing substrate 633 is attached with a sealant 628 to seal the light-emitting element. That is, the light emitting display device is sealed with a pair of substrates by surrounding the outer periphery of the display region with a sealant. Since the interlayer insulating film of the TFT is provided on the entire surface of the substrate, when the sealing material pattern is drawn on the inner side of the outer peripheral edge of the interlayer insulating film, one of the interlayer insulating films located outside the sealing material pattern. There is a risk of moisture and impurities entering from the part. Therefore, the outer periphery of the insulating film used as the interlayer insulating film of the TFT is overlapped with the inside of the sealing material pattern, preferably the sealing material pattern so as to cover the end portion of the insulating film. Note that a region surrounded by the sealant 628 is filled with a filler 627. Alternatively, the region surrounded by the sealant 628 is filled with a dry inert gas.

  Finally, the FPC 632 is attached to the terminal electrode by an anisotropic conductive film 631 by a known method. A cross-sectional view at this stage is shown in FIG. Note that the transparent conductive film obtained in the same step as the first electrode 623 is preferably used for the terminal electrode, and the terminal electrode is formed over the terminal electrode formed at the same time as the gate wiring.

  6 shows a top view of the pixel portion, and a cross section taken along a chain line EF in FIG. 6 corresponds to the cross-sectional structure of the p-channel TFT 639 in the pixel portion in FIG. A cross section taken along a chain line ML in FIG. 6 corresponds to the cross-sectional structure of the n-channel TFT 638 in the pixel portion in FIG. Note that the solid line indicated by 680 in FIG. 6 indicates the periphery of the insulator 629. However, in FIG. 6, only the second conductive layer is shown, and the first conductive layer is not shown. The electrodes functioning as the source electrode or the drain electrode of the n-channel TFT 638 and the p-channel TFT 639 in the pixel portion may be arranged so as to overlap with the semiconductor layer. You may arrange | position so that it may not overlap a layer.

Through the above steps, the pixel portion, the driver circuit, and the terminal portion can be formed over the same substrate.

In this embodiment mode, in order to reduce off-state current, the TFT in the pixel portion has a double gate structure, and the TFT in Embodiment Mode 2 is used for the TFT in the pixel portion and the driver circuit.

  In the light emitting device, the light emitting display surface of the light emitting device may be one surface or both surfaces. In the case where the first electrode 623 and the second electrode 625 are formed using a transparent conductive film, light from the light-emitting element passes through the substrate 610 and the sealing substrate 633 and is extracted to both sides. In this case, it is preferable to use a transparent material for the sealing substrate 633 and the filler 627.

  In the case where the second electrode 625 is formed using a metal film and the first electrode 623 is formed using a transparent conductive film, light emitted from the light-emitting element passes through only the substrate 610 and is extracted to one side, that is, bottom emission. Become a mold. In this case, the sealing substrate 633 and the filler 627 need not use a transparent material.

  In the case where the first electrode 623 is formed using a metal film and the second electrode 625 is formed using a transparent conductive film, light emitted from the light-emitting element passes through only the sealing substrate 633 and is extracted to one side, that is, Top emission type. In this case, the substrate 610 need not use a transparent material.

In addition, materials for the first electrode 623 and the second electrode 625 need to be selected in consideration of a work function. However, each of the first electrode and the second electrode can be an anode or a cathode depending on the pixel configuration. When the polarity of the driving TFT is a p-channel type, the first electrode may be an anode and the second electrode may be a cathode. In the case where the polarity of the driving TFT is an N-channel type, it is preferable that the first electrode be a cathode and the second electrode be an anode.

  FIG. 7 shows an equivalent circuit diagram in the pixel portion of this embodiment in the case of full color display. The switching TFT 638 in FIG. 7 corresponds to the TFT 638 in FIG. 5, and the current control TFT 639 in FIG. 7 corresponds to the TFT 639 in FIG. In FIG. 7, reference numeral 704 denotes a source wiring, and reference numeral 705 denotes a gate wiring. In the pixel displaying red, an OLED 703R that emits red light is connected to the drain region of the current control TFT 639, and an anode-side power supply line (R) 706R is provided in the source region. The OLED 703R is provided with a cathode side power supply line 700. In the pixel displaying green, an OLED 703G that emits green light is connected to the drain region of the current control TFT, and an anode power supply line (G) 706G is provided in the source region. In the pixel displaying blue, an OLED 703B that emits blue light is connected to the drain region of the current control TFT, and an anode power supply line (B) 706B is provided in the source region. Different voltages are applied to the pixels of different colors depending on the EL material.

  In the light emitting device, a driving method for screen display is not particularly limited, and for example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the light-emitting device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

  Further, in a light emitting device in which a video signal is digital, there are a video signal input to a pixel having a constant voltage (CV) and a constant current (CC). A video signal having a constant voltage (CV) includes a signal having a constant voltage applied to the light emitting element (CVCV) and a signal having a constant current applied to the light emitting element (CVCC). . In addition, when the video signal has a constant current (CC), the signal voltage applied to the light emitting element is constant (CCCV), and the signal applied to the light emitting element has a constant current (CCCC). There is.

  In the light emitting device, a protection circuit (such as a protection diode) for preventing electrostatic breakdown may be provided.

Although an example of an active matrix light-emitting device is described here as a display device, the present invention can also be applied to an active matrix liquid crystal display device. Even when applied to an active matrix liquid crystal display device, the exposure mask including the semi-transmissive portion having the light intensity reduction function described in Embodiment Mode 1 or Embodiment Mode 2 is used for the pixel portion or the driver circuit portion. Each gate electrode and each wiring to be formed can be formed. As a result, a reduction in the number of masks can be realized, and at the same time, fine alignment is not required when the GOLD structure is manufactured. And many processes, such as a board | substrate washing | cleaning, resist material application | coating, prebaking, exposure, image development, and post-baking, can be reduced and processing time can be shortened.

Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4.

(Embodiment 6)
In the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment, the example in which the exposure mask provided with the semi-transmissive portion having the light intensity reducing function is used for forming the gate electrode and the wiring is shown. An exposure mask having a transflective portion having a light intensity reducing function may be used for forming contact openings in the interlayer insulating film.

  In this embodiment, an example in which an exposure mask having a transflective portion having a light intensity reduction function is used when forming a contact opening in an interlayer insulating film and when forming a pattern of a connection wiring is shown in FIG. I will explain.

  In accordance with Embodiment 2, a base insulating film 718 is provided over a substrate 710 having an insulating surface, and then a semiconductor layer and a gate insulating film 714 covering the semiconductor layer are formed. Then, the first conductive film and the second conductive film are stacked, a resist pattern is formed using an exposure mask provided with a semi-transmissive portion having a light intensity reducing function, and etching is performed to form a gate electrode and a wiring.

Here, as in Embodiment Mode 2, the first conductive layer 731 and the second conductive layer 732 are formed in the first TFT portion 730, and the first conductive layer 721 and the second conductive layer are formed in the second TFT portion 720. 722 is formed. Since these electrode structures have been described in the second embodiment, detailed description thereof is omitted here.

  8A, in the wiring portion and the contact portion 740, the first conductive layer 744 is wider than the second conductive layer 745 at a place where it is in contact with the upper wiring. In this way, even if a misalignment of the wiring with the upper layer occurs, the first conductive layer can be contacted. In addition, in the wiring other than the portion to be contacted, the end portions of the first conductive layer 741 and the second conductive layer 742 are formed to coincide with each other.

  Next, after forming a resist pattern covering the second TFT portion 720, an impurity element imparting n-type conductivity is added to the semiconductor layer. By adding the impurity element imparting n-type conductivity, the drain region 735a, the source region 735b, the first LDD region 736a, and the second LDD region 736b are formed in a self-aligned manner. Note that the addition of the impurity element imparting n-type conductivity may be performed by one doping process, or the doping process may be performed in a plurality of times.

  As shown in FIG. 8A, the first LDD region 736a has substantially the same width in the channel length direction as the second LDD region 736b. In addition, the first LDD region 736 a and the second LDD region 736 b overlap with the first conductive layer 731 with the gate insulating film 714 interposed therebetween.

  Next, after removing the resist pattern, a resist pattern covering the first TFT portion 730 is newly formed. Then, an impurity element imparting p-type conductivity is added to the semiconductor layer. By the addition of the impurity element imparting p-type, the drain region 725a, the source region 725b, the third LDD region 726a, and the fourth LDD region 726b are formed in a self-aligned manner.

As shown in FIG. 8A, the third LDD region 726a has substantially the same width in the channel length direction as the fourth LDD region 726b. In addition, the third LDD region 726 a and the fourth LDD region 726 b overlap with the first conductive layer 721 with the gate insulating film 714 interposed therebetween.

  The order of adding the impurity elements is not particularly limited. For example, the impurity element imparting p-type conductivity may be added to the semiconductor layer first, and then the impurity element imparting n-type conductivity may be added to the semiconductor layer.

  Next, after the impurity element added to the semiconductor layer is activated, an interlayer insulating film 715 is formed, and a resist film is applied thereon.

  Next, the resist film is exposed and developed using an exposure mask provided with a semi-transmissive portion 781 having a light intensity reducing function shown in FIG. 8A to form a resist pattern 750 shown in FIG. . The resist pattern 750 is a mask for forming an opening in a lower insulating film, and openings having different depths are provided by an exposure mask provided with a semi-transmissive portion 781. In the wiring portion and contact portion 740, since only one layer of the interlayer insulating film 715 is provided on the second conductive layer 745, a shallow opening is provided above the second conductive layer 745. In contrast, in the first TFT portion 730 and the second TFT portion 720, two layers of an interlayer insulating film 715 and a gate insulating film 714 are provided on the source region and the drain region, respectively. A deep opening is provided above the drain region. As the conditions for the semi-transmissive portion 781 of the exposure mask used here (the shape, size, arrangement, etc. of the lines and spaces), an exposure mask having conditions different from those shown in Embodiment Mode 1 can be used. As described above, the present invention can be used in combination with the exposure mask having the conditions described in the first embodiment and the like and the exposure mask having other conditions.

  Next, etching is performed using the resist pattern 750 to form openings in the interlayer insulating film 715 and the gate insulating film 714. In this etching, openings of the interlayer insulating film 715 and the gate insulating film 714 are formed while the resist pattern 750 is etched, so that openings with different depths can be formed.

  Next, the resist pattern is removed. A cross-sectional view at this stage is illustrated in FIG.

  Next, a stack of a third conductive layer (such as a titanium nitride film) and a fourth conductive layer (such as an aluminum film) is formed. Then, patterning is performed to connect the third conductive layer 761 of the connection wiring, the fourth conductive layer 766 of the connection wiring, the third conductive layer 762 of the drain wiring, the fourth conductive layer 767 of the drain wiring, and the third conductive layer of the source wiring. A conductive layer 763 and a fourth conductive layer 768 of a source wiring are formed. In addition, in the second TFT portion, a third conductive layer 765 as a connection electrode, a fourth conductive layer 770 as a connection electrode, a third conductive layer 769 as a source electrode, and a fourth conductive layer 764 as a source electrode are formed. Here, an exposure mask provided with a semi-transmissive portion having a light intensity reducing function is used for pattern formation of the connection electrodes. The third conductive layer 765 of the connection electrode has a larger area than the fourth conductive layer 770 of the connection electrode.

  Next, plasma treatment is performed to oxidize the fourth conductive layer to form an oxide film 771 on the surface of the fourth conductive layer.

Note that when the fourth conductive layer is oxidized by plasma treatment, the atmosphere is an oxygen atmosphere (for example, an atmosphere of oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or Plasma treatment is performed in an atmosphere of oxygen and hydrogen (H ₂ ) and a rare gas atmosphere or a dinitrogen monoxide and rare gas atmosphere. On the other hand, in the case of nitriding a film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) or nitrogen and hydrogen And a rare gas atmosphere or NH ₃ and a rare gas atmosphere). As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating film formed by the plasma treatment contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing, and when Ar is used, the insulating film Contains Ar.

In addition, when plasma treatment is performed on the fourth conductive layer, the plasma treatment is performed in an atmosphere of the above gas with an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the electron temperature of plasma is 0.5 eV to 1.5 eV. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (herein, the fourth conductive layer) formed on the substrate is low, damage to the object to be processed can be prevented. . In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower by 100 degrees or more than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma.

Next, one electrode 772 included in the light-emitting element is formed. The electrode 772 is disposed so as to partially overlap with the third conductive layer 765 of the connection electrode, and is electrically connected to the TFT. The electrode 772 is made of a material having a high work function, for example, an element selected from Ni, W, Cr, Pt, Zn, Sn, In, or Mo, or an alloy material containing the element as a main component, for example, TiN, TiSi _X N _A single layer film or a stacked film thereof may be used in a total film thickness range of 100 nm to 800 nm using _Y , WSi _X , WN _X , WSi _X N _Y , and NbN.

  Next, an insulator 773 (referred to as a bank, a partition, a barrier, a bank, or the like) is formed to cover an end portion of one electrode 772 included in the light-emitting element.

  Next, a layer 774 containing an organic compound is formed over the electrode 772 by an evaporation method or a coating method.

  Next, another electrode 775 which forms a light-emitting element is formed over the layer 774 containing an organic compound. For the electrode 775, an alloy such as MgAg, MgIn, or AlLi, or a transparent conductive film (such as ITO) may be used.

  Thus, the second TFT portion 720 includes a light-emitting element including one electrode 772, a layer 774 containing an organic compound, and the other electrode 775, and a p-channel TFT connected to the light-emitting element. Is formed. The TFT connected to the light emitting element preferably has an LDD region having the same width in order to reduce off current.

  In addition, as a TFT constituting a part of the buffer circuit of the driver circuit, an n-channel TFT shown in the first TFT portion 730 is preferably arranged. The n-channel TFT shown in the first TFT portion 730 can alleviate electric field strength near the drain and suppress circuit deterioration.

Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, or Embodiment Mode 5.

(Embodiment 7)
Here, an example in which an FPC or a driving IC for driving is mounted on a light-emitting display panel will be described with reference to FIG.

FIG. 9A illustrates an example of a top view of a light-emitting device in which an FPC 1209 is attached to four terminal portions 1208. Over a substrate 1210, a pixel portion 1202 including a light emitting element and a TFT, a gate side driver circuit 1203 including a TFT, and a source side driver circuit 1201 including a TFT are formed. The active layer of the TFT is composed of a semiconductor film having a crystal structure, and these circuits are formed on the same substrate. Therefore, an EL display panel that realizes system-on-panel can be manufactured.

Note that the substrate 1210 is covered with a protective film except for the contact portion, and a base layer containing a substance having a photocatalytic function is provided over the protective film.

  In addition, connection regions 1207 provided at two positions so as to sandwich the pixel portion are provided in order to contact the second electrode of the light emitting element with a lower wiring. Note that the first electrode of the light-emitting element is electrically connected to a TFT provided in the pixel portion.

  Further, the sealing substrate 1204 is fixed to the substrate 1210 with a sealant 1205 that surrounds the pixel portion and the driver circuit and a filling material that is surrounded by the sealant. Moreover, it is good also as a structure filled with the filling material containing a transparent desiccant. Further, a desiccant may be disposed in a region that does not overlap with the pixel portion.

  Further, the structure shown in FIG. 9A shows a preferable example of a light emitting device having a relatively large size (for example, 4.3 inches diagonal) of the XGA class, but FIG. 9B shows a narrow frame. This is an example in which a suitable COG method is adopted with a small size (for example, a diagonal of 1.5 inches).

In FIG. 9B, a driver IC 1301 is mounted on a substrate 1310, and an FPC 1309 is mounted on a terminal portion 1308 arranged at the tip of the driver IC. From the viewpoint of improving productivity, a plurality of driver ICs 1301 to be mounted are preferably formed on a rectangular substrate having one side of 300 mm to 1000 mm, and more than 1000 mm. That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit are formed on the substrate, and finally, the drive ICs may be taken out by dividing them. The long side of the driving IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel portion and the pixel pitch. Or a length obtained by adding one side of the pixel portion and one side of each driver circuit.

  The advantage of the external dimensions of the driving IC over the IC chip is the length of the long side. When a driving IC having a long side of 15 to 80 mm is used, the number required for mounting corresponding to the pixel portion is obtained. This is less than when an IC chip is used, and the manufacturing yield can be improved. Further, when the driving IC is formed over the glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

  Alternatively, a TAB method may be employed. In that case, a plurality of tapes may be attached and a driving IC may be mounted on the tapes. As in the case of the COG method, a single drive IC may be mounted on a single tape. In this case, a metal piece or the like for fixing the drive IC may be attached together due to strength problems. .

  A connection region 1307 provided between the pixel portion 1302 and the driver IC 1301 is provided in order to contact the second electrode of the light-emitting element with a lower wiring. Note that the first electrode of the light-emitting element is electrically connected to a TFT provided in the pixel portion.

  In addition, the sealing substrate 1304 is fixed to the substrate 1310 with a sealing material 1305 surrounding the pixel portion 1302 and a filling material surrounded by the sealing material.

  In the case where an amorphous semiconductor film is used as the active layer of the TFT in the pixel portion, it is difficult to form a driver circuit over the same substrate. It becomes.

  Although an example of an active matrix light-emitting device is shown here as a display device, it is needless to say that the present invention can also be applied to an active matrix liquid crystal display device. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, thereby arranging the pixel electrode provided on the element substrate and the counter electrode provided on the counter substrate. The optical modulation of the liquid crystal layer is performed, and this optical modulation is recognized by the observer as a display pattern. The counter substrate and the element substrate are arranged at equal intervals and filled with a liquid crystal material. The liquid crystal material may be a method of dropping the liquid crystal under reduced pressure so that bubbles do not enter with the sealing material as a closed pattern, and bonding both substrates together, or providing a sealing pattern having an opening, and a TFT substrate Alternatively, a dip type (pumping type) in which liquid crystal is injected by using a capillary phenomenon after bonding may be used.

  The present invention can also be applied to a liquid crystal display device using a field sequential driving method that uses an optical shutter and flashes RGB three-color backlight light sources at high speed without using a color filter.

  As described above, various electronic devices can be completed by implementing the present invention, that is, by using any one of the manufacturing methods or configurations of Embodiments 1 to 6.

(Embodiment 8)
As a semiconductor device and an electronic device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook personal computer, a game device, a mobile phone An information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device (specifically, a digital versatile disc (DVD)) provided with a recording medium, and the image is displayed. And a device equipped with a display that can be used. Specific examples of these electronic devices are shown in FIGS.

FIG. 10A illustrates a digital camera, which includes a main body 2101, a display portion 2102, an imaging portion, operation keys 2104, a shutter 2106, and the like. Note that FIG. 10A is a view from the display portion 2102 side, and the imaging portion is not shown. According to the present invention, a highly reliable digital camera having a high-definition display portion can be realized.

  FIG. 10B illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. According to the present invention, a notebook personal computer having a high-definition display portion and high reliability can be realized.

  FIG. 10C illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. A display portion A2403 mainly displays image information, and a display portion B2404 mainly displays character information. Note that an image reproducing device provided with a recording medium includes a home game machine and the like. According to the present invention, a highly reliable image reproducing device having a high-definition display portion can be realized.

FIG. 10D illustrates a display device, which includes a housing 1901, a supporting base 1902, a display portion 1903, speakers 1904, a video input terminal 1905, and the like. This display device is manufactured by using a thin film transistor formed by the manufacturing method described in the above embodiment for the display portion 1903 and a driver circuit. The display device includes a liquid crystal display device, a light emitting device, and the like, and specifically includes all information display devices such as a computer, a television receiver, and an advertisement display. According to the present invention, a highly reliable display device having a high-definition display portion and particularly a large display device having a large screen of 22 inches to 50 inches can be realized.

Further, by forming an antenna or the like in addition to the thin film integrated circuit having the TFT of the present invention, it can be used as a non-contact type thin film integrated circuit device (also referred to as a wireless IC tag, RFID (also referred to as radio frequency identification)). it can. In addition, by attaching the IC tag to various electronic devices, the distribution route of the electronic devices can be clarified.

FIG. 10E shows a state where the wireless IC tag 1942 is attached to the passport 1941. A wireless IC tag may be embedded in the passport 1941. Similarly, you can attach or embed a wireless IC tag to a driver's license, credit card, banknote, coin, securities, gift certificate, ticket, traveler's check (T / C), health insurance card, resident card, family register copy, etc. it can. In this case, only information indicating authenticity is input to the wireless IC tag, and an access right is set so that information cannot be read or written illegally. This can be realized by using the memory shown in the other embodiments. By using it as a tag in this way, it becomes possible to distinguish it from a forged one. In addition, a wireless IC tag can be used as a memory. In addition, by providing wireless IC tags in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, and the like, it is possible to improve the efficiency of systems such as inspection systems.

  11 includes a main body (A) 901 provided with operation switches 904, a microphone 905, and the like, a display panel (A) 908, a display panel (B) 909, a speaker 906, and the like. A main body (B) 902 is connected with a hinge 910 so as to be opened and closed. The display panel (A) 908 and the display panel (B) 909 are housed in the housing 903 of the main body (B) 902 together with the circuit board 907. The pixel portions of the display panel (A) 908 and the display panel (B) 909 are arranged so as to be visible from an opening window formed in the housing 903.

  In the display panel (A) 908 and the display panel (B) 909, specifications such as the number of pixels can be set as appropriate in accordance with the function of the mobile phone 900. For example, the display panel (A) 908 can be combined as a main screen and the display panel (B) 909 can be combined as a sub-screen.

  According to the present invention, a highly reliable mobile phone having a high-definition display portion can be realized.

  The mobile phone according to the present embodiment can be transformed into various modes depending on the function and application. For example, a mobile phone with a camera may be obtained by incorporating an image sensor at the hinge 910. In addition, the above-described effects can be obtained even when the operation switches 904, the display panel (A) 908, and the display panel (B) 909 are housed in one housing. Moreover, even if the configuration of the present embodiment is applied to an information display terminal having a plurality of display units, the same effect can be obtained.

  As described above, various electronic devices can be completed using the manufacturing method or the structure according to any one of Embodiments 1 to 7 according to the present invention.

(Embodiment 9)
Actually, the sum of the line width L of the light-shielding material and the space width S between the light-shielding materials in the semi-transmissive portion is n, m when the resolution of the exposure apparatus is n and the projection magnification is 1 / m (m ≧ 1). relationship, and meets the expression (n / 3) × m ≦ L + S ≦ (3n / 2) × m, and, n, m, the relationship of L is, L <a (2n / 3) × m an example of exposed and developed by using an exposure mask that meets shown in FIG. FIG. 14A schematically shows a sectional view of an exposure mask, and FIG. 14B shows a sectional photograph of a resist pattern obtained by performing exposure and development using this exposure mask. The position of the exposure mask in FIG. 14A substantially corresponds to the position of the cross-sectional photograph of the resist pattern in FIG. An exposure apparatus having a projection magnification of the same magnification and a resolution of 1.5 μm was used. In the exposure mask of FIG. 14A, the line and space widths are 0.5 μm and 1.0 μm, and the lines and spaces satisfy the above relationship. When exposure and development are performed using this exposure mask, a resist pattern having a thin region as shown in FIG. 14B and a substantially uniform thickness in the thin region is formed. I was able to.

  The resist pattern is formed on two conductive layers in which a second conductive layer is stacked on the first conductive layer. Here, TaN is used as the first conductive layer, and a tungsten film is used as the second conductive layer.

Next, the second conductive layer and the first conductive layer are etched by dry etching. Dry etching is performed while ashing the resist pattern. As the etching gas, CF ₄ , SF ₆ , Cl ₂ , and O ₂ are used. In order to improve the etching rate, a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) is used. Here, an example using an ICP etching apparatus is shown.

Thus, as shown in FIG. 14C, a conductive laminated pattern including the first conductive layer and the second conductive layer is formed. FIG. 14C shows an observation photograph from an oblique direction. By dry etching, the first conductive layer and the second conductive layer are etched and removed in the transmission part, that is, in the region where the resist pattern is not formed. In the light shielding portion, that is, the region where the resist pattern is thick, the first conductive layer and the second conductive layer remain without being etched because the resist pattern serves as a mask. In the semi-transmissive portion, that is, in the region where the resist pattern is thin, the second conductive layer is etched and removed, but the first conductive layer remains without being etched. As described above, both the side walls of the first conductive layer are exposed by etching, and further, the region that does not overlap the second conductive layer is exposed.

As described above, by using an exposure mask having a semi-transmissive portion that satisfies the above relationship, the exposure amount of the exposure light that has passed through the semi-transmissive portion on the exposed surface is substantially uniformized in the semi-transmissive portion. Accordingly, the resist pattern in the semi-transmissive portion can be made thin and the film thickness can be formed uniformly. The layer to be etched can be etched using the thin portion of the resist pattern. The portion where the resist pattern is thin can be formed to have a thinner film thickness compared to the portion where the thickness is thick. The pattern of the layer to be etched can be formed in a portion having a thin resist pattern in a shape different from that of the thick portion. By using this resist pattern, it is possible to accurately form gate electrodes, other electrodes, wirings, and the like having a desired pattern. When a gate electrode having a thick first region and a second region thinner than the first region is formed on the side of the first region using the exposure mask, By using the electrode as a mask for ion doping, a low concentration impurity region (L _ov region) overlapping with the gate electrode can be formed in a self-aligned manner on both sides or one side of the channel formation region.

In addition, this embodiment mode can be freely combined with the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, or the eighth embodiment. Can be combined.

The present invention reduces the number of photolithography steps (number of masks) by providing a photomask capable of forming a thin film thickness of the photoresist layer in the transflective portion and forming the film thickness uniformly. Improve productivity and reduce costs of semiconductor devices.
According to the present invention, various circuits can be formed on the same substrate, and an LDD region having an optimum width for each circuit can be formed in a self-aligned manner. Further, the width of the LDD region can be precisely controlled according to individual circuits. By optimizing the LDD region of the TFT of each circuit, it is possible to improve reliability, reduce power consumption, and drive at high speed.

  For example, TFTs having LDD regions with different widths on both sides of the channel formation region, TFTs having LDD regions of the same width on both sides of the channel formation region, TFTs without an LDD region, etc., are the same without increasing the number of steps. It can be formed on a substrate.

The top view of an exposure mask and the figure which shows light intensity distribution. (Embodiment 1) 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. (Embodiment 2) 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. (Embodiment 3) 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. (Embodiment 4) Sectional drawing of a light-emitting device. (Embodiment 5) The top view in a pixel part. (Embodiment 5) FIG. 6 is a diagram illustrating an equivalent circuit in a pixel portion. (Embodiment 5) Sectional drawing of a light-emitting device. (Embodiment 6) The figure which shows an example of a module. (Embodiment 7) FIG. 14 illustrates an example of an electronic device. (Embodiment 8) FIG. 14 illustrates an example of an electronic device. (Embodiment 8) Sectional drawing of exposure mask and sectional photograph of photoresist layer. Sectional drawing of exposure mask and sectional photograph of photoresist layer. Sectional drawing of exposure mask, sectional photograph of resist pattern, and observation photograph from oblique direction of conductive laminated pattern.

Explanation of symbols

101 substrate 102 having insulating surface first insulating film 103 semiconductor layer 104 second insulating film 105a first conductive layer 105b first conductive layer 106a second conductive layer 106b second conductive layer 107a resist pattern 107b resist pattern 109a low concentration impurity region 109b Low-concentration impurity region 110 High-concentration one-conductivity type impurity region 111 High-concentration one-conductivity-type impurity region 112 Third insulating film 113 Fourth insulating film 114 Source electrode 115 Drain electrode 202 Edge 203 of light-shielding portion P Line 204 Space 206 End portion 207 of light shielding portion P 207 line 208 space 212 rectangular pattern 213 space 214 light intensity distribution 301 substrate 302 first insulating film 303 semiconductor layer 304 second insulating film 305a first conductive layer 305b first conductive layer 306a second conductive layer 306b Second conductive layer 30 c Second conductive layer 306d Second conductive layer 306e Second conductive layer 307a Resist pattern 307b Resist pattern 307c Resist pattern 307d Resist pattern 400 Translucent substrate 401 Light shielding portion 402 Transflective portion 403a Non-exposed region 403b Exposed region 500 Substrate 502 Semiconductor Layer 503 semiconductor layer 504 gate insulating layer 505 first conductive film 506 second conductive film 508 insulating layer 520 first TFT portion 521 first gate electrode layer 522 second gate electrode layer 523 resist pattern 524a low concentration impurity Region 524b low concentration impurity region 525a high concentration impurity region 525b high concentration impurity region 526a low concentration impurity region 526b low concentration impurity region 529 resist pattern 530 second TFT portion 531 first gate electrode layer 532 second gate electrode Polar layer 533 Resist pattern 534a Low concentration impurity region 534b Low concentration impurity region 535a High concentration impurity region 535b High concentration impurity region 536a Low concentration impurity region 536b Low concentration impurity region 539 Resist pattern 540 Wiring portion 541 First wiring layer 542 Second Wiring layer 543 Resist pattern 549 Resist pattern 551 Light-shielding portion 552 Semi-transmissive portion 553 Light-shielding portion 554 Semi-transmissive portion 555 Light-shielding portion 610 Substrate having an insulating surface 611 Base insulating film 623 First electrode 624 Layer 625 containing an organic compound 625 Second Electrode 626 Protective layer 627 Filler 628 Sealant 629 Insulator 631 Anisotropic conductive film 632 FPC
633 Sealing substrate 636 n-channel TFT
637 p-channel TFT
638 n-channel TFT
639 p-channel TFT
680 Insulator peripheral edge 700 Cathode side power supply line 703R OLED emitting red light
703G OLED emitting green light
703B OLED emitting blue light
704 Source wiring 705 Gate wiring 706R Anode-side power supply line 706G Anode-side power supply line 706B Anode-side power supply line 710 Substrate having an insulating surface 714 Gate insulating film 715 Interlayer insulating film 718 Base insulating film 720 Second TFT portion 721 First conductive layer 722 Second conductive layer 725a Drain region 725b Source region 726a Third LDD region 726b Fourth LDD region 730 First TFT portion 731 First conductive layer 732 Second conductive layer 735a Drain region 735b Source region 736a First LDD Region 736b Second LDD region 740 Wiring portion and contact portion 741 First conductive layer 742 Second conductive layer 744 First conductive layer 745 Second conductive layer 750 Resist pattern 761 Third conductive layer 762 of connection wiring Third drain wiring Conductive layer 763 Source wiring Third conductive layer 764 Fourth conductive layer 765 of the source electrode Third conductive layer 766 of the connection electrode Fourth conductive layer 767 of the connection wiring Fourth conductive layer 768 of the drain wiring Fourth conductive layer 769 of the source wiring Third conductivity of the source electrode Layer 770 Fourth conductive layer 771 of connection electrode Oxide film 772 Electrode 773 Insulator 774 Layer containing organic compound 775 Electrode 781 Transflective portion 901 Main body (A)
902 Body (B)
903 Housing 904 Operation switches 905 Microphone 906 Speaker 907 Circuit board 908 Display panel (A)
909 Display panel (B)
910 Hinge 1201 Source side driving circuit 1202 Pixel portion 1203 Gate side driving circuit 1204 Sealing substrate 1205 Sealing material 1207 Connection region 1208 Terminal portion 1209 FPC
1210 Substrate 1301 Drive IC
1302 Pixel portion 1304 Sealing substrate 1305 Sealing material 1307 Connection region 1308 Terminal portion 1309 FPC
1310 Substrate 1901 Case 1902 Support base 1903 Display unit 1904 Speaker 1905 Video input terminal 1941 Passport 1942 Wireless IC tag 2101 Main unit 2102 Display unit 2104 Operation key 2106 Shutter 2201 Main unit 2202 Case 2203 Display unit 2204 Keyboard 2205 External connection port 2206 Pointing mouse 2401 body 2402 housing 2403 display part A
2404 Display B
2405 Recording medium reading unit 2406 Operation key 2407 Speaker unit

Claims (4)

Forming an insulating film on the semiconductor layer;
Forming a first conductive film on the insulating film;
Forming a second conductive film on the first conductive film;
Wherein on the second conductive film, using an exposure mask having a semi-transmissive portion, and the first region, said first region side to the first region having a small thickness the second region than in the Forming a resist pattern having
Wherein by etching said first conductive film and the second conductive film by using the resist pattern, below the first region, the second having the first conductive film and the second conductive film 3 and a pair of fourth regions having the first conductive film are formed below the second region, and a gate electrode is formed.
Removing the resist pattern;
An impurity element is implanted into the semiconductor layer using the gate electrode as a mask, and the source region and the drain region outside the gate electrode and the first conductive film in the pair of fourth regions are passed through the pair. and a first LDD region and the second LDD region is formed in the fourth region and the overlap region of,
In the exposure mask , the sum of the line width L of the light-shielding material and the space width S between the light-shielding materials in the semi-transmissive portion is set such that the resolution of the exposure apparatus is n and the projection magnification is 1 / m (m ≧ 1).
(N / 3) × meets m ≦ L + S ≦ (3n / 2) × conditional expression m, and the n, m, the relationship of L is, L <(2n / 3), wherein the Mitasuko a × m A method for manufacturing a semiconductor device. Forming an insulating film on the semiconductor layer;
Forming a first conductive film on the insulating film;
Forming a second conductive film on the first conductive film;
Wherein on the second conductive film, using an exposure mask having a semi-transmissive portion, and the first region, said first region side to the first region having a small thickness the second region than in the Forming a resist pattern having
Wherein by etching said first conductive film and the second conductive film by using the resist pattern, below the first region, the second having the first conductive film and the second conductive film 3 and a pair of fourth regions having the first conductive film are formed below the second region, and a gate electrode is formed.
Removing the resist pattern;
An impurity element is implanted into the semiconductor layer using the gate electrode as a mask, and the source region and the drain region outside the gate electrode and the first conductive film in the pair of fourth regions are passed through the pair. and a first LDD region and the second LDD region is formed in the fourth region and the overlap region of,
In the exposure mask , the sum of the line width L of the light-shielding material and the space width S between the light-shielding materials in the semi-transmissive portion is set such that the resolution of the exposure apparatus is n and the projection magnification is 1 / m (m ≧ 1).
(2n / 3) × meets m ≦ L + S ≦ (6n / 5) × conditional expression m, and the n, m, the relationship of L is, L <(2n / 3), wherein the Mitasuko a × m A method for manufacturing a semiconductor device. Forming an insulating film on the semiconductor layer;
Forming a first conductive film on the insulating film;
Forming a second conductive film on the first conductive film;
Using an exposure mask having a semi-transmissive portion on the second conductive film, a first region and a second region having a thickness smaller than that of the first region on a side portion of the first region And the first region forms a resist pattern having a shape at a position shifted from the center,
Wherein by etching said first conductive film and the second conductive film by using the resist pattern, below the first region, the second having the first conductive film and the second conductive film 3 and a pair of fourth regions having the first conductive film are formed below the second region, and a gate electrode is formed.
Removing the resist pattern;
An impurity element is implanted into the semiconductor layer using the gate electrode as a mask, and the source region and the drain region outside the gate electrode and the first conductive film in the pair of fourth regions are passed through the pair. and a first LDD region and the second LDD region is formed in the fourth region and the overlap region of,
The first LDD region is wider than the second LDD region,
In the exposure mask, the sum of the line width L of the light-shielding material and the space width S between the light-shielding materials in the semi-transmissive portion is set such that the resolution of the exposure apparatus is n and the projection magnification is 1 / m (m ≧ 1).
The condition of (n / 3) × m ≦ L + S ≦ (3n / 2) × m is satisfied, and the relationship between the n, m, and L satisfies L <(2n / 3) × m. A method for manufacturing a semiconductor device. Forming an insulating film on the semiconductor layer;
Forming a first conductive film on the insulating film;
Forming a second conductive film on the first conductive film;
Using an exposure mask having a semi-transmissive portion on the second conductive film, a first region and a second region having a thickness smaller than that of the first region on a side portion of the first region And the first region forms a resist pattern having a shape at a position shifted from the center,
Wherein by etching said first conductive film and the second conductive film by using the resist pattern, below the first region, the second having the first conductive film and the second conductive film 3 and a pair of fourth regions having the first conductive film are formed below the second region, and a gate electrode is formed.
Removing the resist pattern;
An impurity element is implanted into the semiconductor layer using the gate electrode as a mask, and the source region and the drain region outside the gate electrode and the first conductive film in the pair of fourth regions are passed through the pair. and a first LDD region and the second LDD region is formed in the fourth region and the overlap region of,
The first LDD region is wider than the second LDD region,
In the exposure mask, the sum of the line width L of the light-shielding material and the space width S between the light-shielding materials in the semi-transmissive portion is set such that the resolution of the exposure apparatus is n and the projection magnification is 1 / m (m ≧ 1).
The condition of (2n / 3) × m ≦ L + S ≦ (6n / 5) × m is satisfied, and the relationship of n, m, and L satisfies L <(2n / 3) × m. A method for manufacturing a semiconductor device.