JP2002217419A - Thin-film transistor substrate and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high wiring density TFT, formed by the use of a single photomask for solving the problem of low productivity and reduction in circuit density, due to misalignment of gates in normal manufacture of thin-film transistors, because a self-aligned N-type TFT and a P-type TFT are formed separately by processing their gate with two different photomasks. SOLUTION: A thin-film transistor substrate is formed through a manufacturing method, which comprises a first process of providing an opening the source and drain of a first conductivity-type TFT and forming a resist pattern, composed of a part that covers the source and drain of a second conductivity-type TFT and is thinner than the rest of the resist pattern, that covers the gate and a second process of reducing a resist pattern in thickness and forming the resist pattern with an opening located above the source and drain of the second conductivity-type TFT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate used for an active matrix type liquid crystal display device with a built-in circuit and a display device using an organic light emitting element,
The present invention relates to a thin film transistor substrate using low-temperature p-Si technology and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a so-called CMOS in which N-type and P-type TFTs are integrated on the same substrate by using low-temperature p-Si technology has been developed.
2. Description of the Related Art A liquid crystal display device capable of incorporating a driving circuit using a thin film transistor substrate is manufactured. Low temperature p-S
In a TFT using i, a so-called LDD (Lightly Doped) composed of a low-concentration N-type region is provided at the gate end of the N-type TFT to improve reliability and reduce off-state current.
Drain).

For forming an LDD, a method of forming the LDD in a self-aligned manner with respect to a gate is known in addition to a forming method using a resist mask covering the LDD. In the self-alignment method, an LDD having a smaller width than a mask alignment error is used.
Can be provided. A method for forming an LDD in a self-aligned manner by forming a gate in a shape recessed from a mask pattern is described in JP-A-11-163366.

In the production of an amorphous Si-TFT substrate using only an N-type amorphous Si-TFT, a first resist pattern having a step is formed using masks having different transmittances, and then a resist is formed. The number of masks is reduced by forming a second resist pattern by reducing the film thickness of the mask. A method of simplifying the manufacturing process using a stepped resist pattern is described in, for example, JP-A-2000-164584.

[0005]

In the conventional method, according to the method of forming an N-type TFT having a self-aligned LDD by retreating a gate, a P-type TFT having no LDD is used.
In order to make them different from the TFT of the type, the gate of the N-type TFT and the gate of the P-type TFT are processed using two different masks.

Therefore, a shift corresponding to a mask alignment error is formed in the conductive film pattern at the boundary between the N-type TFT and the P-type TFT. In order to absorb this shift, it is necessary to increase the width of the conductive film pattern at the boundary between the N-type and P-type TFTs, which causes a problem that the wiring density is reduced.

Further, since an area is required between the N-type TFT and the P-type TFT in consideration of a margin for a mask alignment error, a reduction in circuit density and an increase in circuit area have become problems. Was.

A first object of the present invention is to process a gate of an N-type TFT and a gate of a P-type TFT by using the same photomask,
An object of the present invention is to provide a thin film transistor substrate on which a high-density circuit is formed by forming D in a self-aligned manner (by adjusting its position).

Further, in the manufacture of a CMOS p-Si TFT, there is a problem that a doping mask is required because N-type and P-type transistors are separately formed, so that the number of steps is large and productivity is poor. Conventionally, to perform both P-type and N-type doping, at least two masks were required in addition to the processing of the gate.

On the other hand, for a so-called inverted staggered amorphous Si-TFT substrate, a method of forming a resist pattern having steps to simplify the process is known. However, regarding the doping process using two or more kinds of impurities peculiar to the method of forming a top gate type low temperature p-Si TFT, particularly a CMOS type thin film transistor substrate, what kind of resist pattern should be used for the manufacturing process It was not known that it could be simplified.

A second object of the present invention is to provide such a CMOS.
It is an object of the present invention to provide a method of manufacturing a thin film transistor substrate which reduces the number of masks used for doping a thin film transistor substrate, simplifies a manufacturing process, and improves productivity.

[0012]

The gist of the present invention for solving the above-mentioned object is as follows.

(1) A crystalline semiconductor film formed on a transparent insulating substrate; a gate insulating film formed on the semiconductor film; a gate formed of a conductive film formed on the gate insulating film; A top gate type TFT having a source and a drain doped with the semiconductor film is formed on both sides, and the TFT is a CMOS type thin film transistor substrate in which an N type and a P type are formed on the same substrate. In a conductive type TFT, a first region which is in contact with the gate between the gate and the source and the drain, is not covered with the same conductive film as the gate, and has a gate insulating film having substantially the same thickness as the lower portion of the gate. A gate insulating film in contact with the first region and substantially including a source or a drain, and a second region having a smaller thickness than the first region; The thickness of the gate insulating film on the gate and drain is less than or equal to the first region and larger than the second region, and connects the gates of the N-type and P-type TFTs and is the same conductive film pattern as the gate. Is on the thin film transistor substrate in contact with the second region only on the boundary between the first region and the second region.

(2) A CMOS type thin film transistor substrate in which P-type and N-type top gate type TFTs are formed on an insulating substrate is opened by opening the source and drain of the first conductive type TFT and forming the second conductive type TFT. Forming a first resist pattern in which the source and the drain of the TFT of the type are covered with a resist having a smaller film thickness than the resist covering the gate; and reducing the film thickness of the resist pattern to form a second conductive pattern. The present invention provides a method for manufacturing a thin film transistor substrate including a step of forming a second resist pattern in which a resist pattern in a source / drain region of a type TFT is opened and a gate is covered.

Further, a CMOS type thin film transistor substrate is formed by opening a resist on a source and a drain of an N-type TFT and forming a resist on a source and a drain of a P-type TFT with a film thickness smaller than that of a resist on a gate. Processing a conductive film of the same layer as the gate by using the coated first resist pattern; reducing the thickness of the first resist pattern; opening the source and drain of the P-type TFT; And a step of forming a gate of a P-type TFT by anisotropic etching using the second resist pattern as a mask.

(3) Between the source and the drain of the N-type TFT and the gate of the CMOS type thin-film transistor substrate, the source and the drain of the P-type TFT are in contact with the gate pattern, and the thickness of the gate insulating film is P-type. A first region which is equal to or more than the thickness of the upper gate insulating film, and a gate insulating film which is in contact with the first region and substantially includes the source / drain of the N-type TFT, has a smaller thickness than the first region. A second region is provided, and the width of the first region at the gate end of the N-type TFT is set to not more than １ ／ of the minimum line width of the gate of the TFT in the substrate, and between the N-type TFT and the P-type TFT. At the boundary between the first region and the second region, a step is formed in the conductive film pattern in the same layer as the gate, with a step not more than the width of the first region at the gate end of the N-type TFT.

Further, a CMOS type thin film transistor substrate in which an LDD which is a low concentration N type region is formed at the gate end of the N type TFT is opened on the source and drain of the first conductivity type TFT. , Second conductivity type TFT
Forming a first resist pattern in which the source and the drain are covered with a resist having a smaller film thickness than the resist covering the gate, and using the first resist pattern as a mask, performing isotropic etching. Forming the gate of the TFT of one conductivity type in a pattern recessed from the resist pattern, reducing the thickness of the first resist pattern, opening the source and drain of the TFT of the second conductivity type, and covering the gate Forming the formed second resist pattern, and using the second resist pattern as a mask, performing TF of the second conductivity type by anisotropic etching.
The manufacturing method includes a step of processing a T gate.

Further, there is a manufacturing method in which a conductive film forming a gate of a CMOS type thin film transistor substrate is a metal film, and wet etching is used for isotropic etching of the conductive film using the first resist pattern as a mask.

Also, a gate insulating film which is in contact with the gate between the gate and the source and the drain in the TFT of the first conductivity type and which is not covered with the same conductive film as the gate is provided on the CMOS type thin film transistor substrate. A first region having substantially the same thickness as the first region, and a second region having a smaller thickness than the first region in which the gate insulating film which is in contact with the first region and substantially includes the source or the drain is provided. The thickness of the gate insulating film on the source and drain of the second conductivity type TFT is equal to or less than the thickness of the first region and larger than the thickness of the second region; And forming the conductive film pattern in the same layer as the gate connecting the gates so as to be in contact with the second region only on the boundary between the first region and the second region.

[0020]

[Embodiment 1] FIGS. 1 to 6 show a first example of a method of manufacturing a thin film transistor substrate according to the present invention. The left figure is a plan view, and the right figure is a schematic view of the cross section.

As shown in FIG. 1, a 50-nm thick polysilicon film 3 is formed on a transparent insulating substrate 1 made of a glass substrate via a base film 2 made of SiO ₂ or a laminated film of SiN and SiO _2. Form.

The polysilicon film 3 is formed by photolithography.
Processed into islands by the _TwoGate consisting of
The edge film 4 is 100 nm, and the conductive film 5 made of Mo is 200 nm.
nm.

The polysilicon film 3 is formed by depositing an amorphous Si film by a plasma CVD method using silane, performing a dehydrogenation treatment by annealing, and then crystallizing by an excimer laser annealing method.

The amorphous Si film can be formed by a known method such as adding a metal serving as a catalyst to the amorphous Si film, crystallizing the film by thermal annealing, and then removing the metal.

The SiO ₂ film serving as the gate insulating film 4 is made of TEOS (tetra-ethoxysilane).
e) was formed by a CVD method. In addition, it can also be formed by a sputtering method using a SiO ₂ target.

The conductive film 5 serving as a gate is made of Mo.
In addition, W, Ta, Cr, Nb, Al, Ti, polysilicon and their alloys, or their laminated films can be used, and the formation thereof is performed by a known method such as sputtering using a metal target or plasma CVD. A method can be used.

After applying a positive resist on the conductive film 5,
Having an opening on the source and drain of the N-type TFT,
Using a photomask in which a translucent pattern with respect to ultraviolet light is formed on the source and the drain of the P-type TFT and the gate and the wiring are shielded from light, the resist in the opening 11 is completely exposed, and the resist corresponding to the translucent pattern is exposed. Is exposed under the exposure condition that is partially exposed.

This is developed, and an opening 11 is formed on a region to be a source and a drain of the N-type TFT, and the P-type TFT is formed.
Is thinner than the 2 μm-thick resist 12 covering the gate region by a thickness of 0.5 μm.
A resist pattern covered with a μm resist 13 was formed to obtain the structure shown in FIG.

The above resist pattern is formed by a P-type TF instead of using a photomask which is translucent to ultraviolet light.
In the source and drain regions of T, a light-shielding pattern and an opening pattern having a resolution equal to or less than the resolution of the exposure machine can be formed using a photomask formed in a linear, mesh, or isolated dot shape.

Next, using the first resist pattern thus formed, the conductive film 5 is anisotropically etched by dry etching using a fluorine-based gas, and is processed into a pattern substantially matching the resist pattern. And

Next, the resist is partially ashed.
The source and drain of the P-type TFT
Remove the resist on the top and on the gate of N-type TFT
Of the second resist pattern
To form an electrode 20. Next, using the conductive film 5 as a mask,
Phosphorus (P) dose 1 × 10 on silicon layer¹⁵/ Cm ^Two
Source and drain of N-type TFT using ion implantation
Injection was made into the in 33 to obtain the structure shown in FIG.

Further, using the second resist pattern 20, anisotropic etching is performed again to process the conductive film 5 having substantially the same shape as the resist pattern, thereby forming the gate 3 of the N-type TFT.
Gates 32 of 1 and P-type TFTs were formed, respectively, to obtain the structure shown in FIG.

At this time, the gate insulating film 4 in the region 52 not covered with the conductive film is also partially etched and thinned, and a thin portion 52 of the gate insulating film is formed.

Next, after removing the second resist pattern, a resist pattern 22 having an opening 21 in a P-type TFT region is formed by photolithography, and using this as a mask, boron (B) as a P-type impurity is formed. ) Is ion-implanted, and the polysilicon layer serving as the source and drain 34 of the P-type TFT is doped with P-type to obtain the structure shown in FIG.

After the resist pattern 22 is further removed, low concentration phosphorus (P) is ion-implanted using the gates 31 and 32 as a mask to form an LDD 35 in the polysilicon layer near the gate 31 of the N-type TFT. An N-type thin film transistor 41 having an LDD formed in a self-aligned manner with a gate as shown in FIG.
Was formed.

Thereafter, a known activation step is performed to form an interlayer insulating film, wiring, and a protective film, and a pixel electrode (not shown) for a liquid crystal display device. Can be formed.

In the thin film transistor substrate obtained by the process of the present invention, a thin region 52 of the gate insulating film formed at the time of anisotropic etching by the second resist pattern is formed on the source and the drain 33 of the N-type TFT. Have been.

A region between the source / drain 33 of the N-type TFT and the gate 31 covered with the first resist pattern and opened with the second resist pattern so as to be in contact with the thin region 52 of the gate insulating film. Correspondingly, a thick region 51 of the gate insulating film having the same thickness as the source and drain 34 of the P-type TFT 42 is formed.

The region 51 of the thick gate insulating film is formed in a self-aligned manner with the gate 31 due to the retreat during the ashing of the first resist pattern. The resist receding amount during ashing can be arbitrarily controlled with high accuracy by the ashing time, and it is easy to realize the receding amount less than half the minimum line width of the gate, which is limited by the resolution limit of the exposure machine. it can.

In the present embodiment, this width corresponds to the length of the LDD.
If the length is 1.5 μm or less, good TFT characteristics can be obtained.

Further, the gates of the N-type and P-type TFTs are formed in a pattern derived from the same photomask, and are not formed so as to be shifted from each other by more than the retreat amount at the time of resist ashing.

Accordingly, it is not necessary to make the conductive film pattern large in anticipation of a mask alignment error, and the wiring density can be improved. Furthermore, P-type and N-type TFTs
Since there is no alignment error, the TFTs can be arranged at a high density, the wiring density can be improved, and the circuit area can be reduced.

According to the present invention, the wiring density can be increased by 10% and the circuit area can be reduced by 20% as compared with the prior art.

Embodiment 2 FIGS. 7 to 12 show a second example of a method for manufacturing a thin film transistor substrate according to the present invention.

As in the first embodiment, a polysilicon film 3 as a semiconductor film is formed in an island shape on a transparent insulating substrate 1 made of glass with a base film 2 interposed therebetween, and a gate insulating film 4 is formed thereon.
And a conductive film 5 made of a MoW alloy.

An opening 11 is formed on the source and drain of the N-type transistor on the conductive film 5 serving as a gate.
A first resist pattern was formed in which the source and the drain of the type transistor were covered with a resist 13 having a smaller thickness than the resist 12 covering the region to be the gate.

Using the first resist pattern, wet etching is performed with an etchant containing cerium ammonium nitrate, and the conductive film 5 is isotropically etched to form a region 14 recessed by 1 μm from the resist, as shown in FIG. A structure was obtained.

The amount of recession of the conductive film 5 from the resist pattern can be arbitrarily controlled by adjusting the etching time.
The recess of 0.5 to 2 μm can be formed with high accuracy.

Further, it is also possible to use polysilicon for the conductive film 5 and perform isotropic etching by dry etching using a fluorine-based gas in addition to wet etching.

However, when a metal film is used for the conductive film 5 as in this embodiment, the dry etching generally uses SiO2.
However, there is a problem that the selectivity with respect to the gate insulating film 4 and the resist made of is small.

Therefore, if the etching time is lengthened, the gate insulating film 4 disappears and the exposed polysilicon film 3 is damaged, and the thin resist 13 covering the source and drain of the P-type TFT disappears. And the amount of retreat cannot be increased.

By using wet etching for etching the metal film, the gate insulating film and the resist can be processed without etching, and the amount of retreat of the gate can be increased. In addition, the wet etching of the metal film has an advantage that the etching time can be shortened because the etching rate is higher than the dry etching.

Thereafter, the resist is ashed, and the P-type T
A second resist pattern 20 having openings on the source and drain of the FT is formed. Using this second resist pattern 20 as a mask, phosphorus (P) is ion-implanted into the polysilicon layer serving as the source and drain 33 of the N-type TFT, and is doped to a high concentration of N-type to obtain the structure shown in FIG.

Further, the conductive film 5 is anisotropically etched,
The gate 32 and the wiring 6 of the P-type TFT are processed into substantially the same shape as the second resist pattern 20 to obtain the structure shown in FIG.

After removing the resist pattern 20, a resist pattern 22 having an opening 21 in the P-type TFT is formed using another photomask.
Using the gate 32 of the P-type TFT and the gate 32 of the P-type TFT as a mask, the source and drain 34 of the P-type TFT are doped with boron (B) at a high concentration to obtain the structure shown in FIG.

After the resist pattern 22 is removed, phosphorus (P) is ion-implanted at a low concentration on the entire surface, and L is applied to the gate end of the N-type TFT in a region covered with the second resist pattern.
A DD 35 was formed, and an N-type TFT 41 and a P-type TFT 42 were formed to have a structure shown in FIG.

Thereafter, a known activation step is performed to form a CMOS thin film transistor substrate having a self-aligned LDD.

Also in this embodiment, when the conductive film 5 is anisotropically etched by the second resist pattern 20, the gate insulating film on the source and drain of the N-type TFT is etched to form a thin film region 52. Is done.

A thick region 51 of a gate insulating film is formed in contact with this region 52 and around the gate 31 of the N-type TFT. The width of this region 51 is derived from the recession of the conductive film from the first resist pattern formed by isotropic etching and the second resist pattern formed by reducing the thickness of the first resist pattern. However, the gate is formed in a self-aligned manner, and can be easily formed with a width of half or less of the minimum resolution of the exposure device.

The gates of the N-type and P-type TFTs are formed in a pattern derived from the same photomask.
It is not formed so as to be shifted from each other by more than the difference between the recession amount of the conductive film in the isotropic etching and the recession amount of the resist. Therefore, there is no misalignment between the TFTs, the interval can be reduced, and the circuit area can be reduced.

Embodiment 3 FIGS. 13 to 17 show a third example of a method of manufacturing a thin film transistor substrate according to the present invention.

As in the first and second embodiments, as shown in FIG. 13, a region to be a gate is covered with a thick resist pattern 12, and an opening is formed on the source and the drain of the N-type TFT of the first conductivity type. Then, a first resist pattern is formed on the source and drain of a P-type TFT of the second conductivity type.

Using this as a mask, the conductive film 5 is isotropically etched, and the conductive film 5 is set back from the resist.
The structure shown in FIG.

Thereafter, the thickness of the resist is reduced by 0.5 μm as a whole by oxygen ashing, the resist on the P-type source and drain is removed, and only the resist on the gate and the wiring is left. Resist pattern 2
0 is formed. In addition to oxygen ashing, RIE
The resist film thickness can also be reduced by anisotropic etching using (Reactive Ion Etching).

Then, using the resist pattern 20 and the conductive film 5 as a mask, phosphorus (P), which is an N-type impurity, is applied to the source and drain 33 of the N-type TFT at a concentration of 1 × 10 ¹⁵ / P by an ion shower method using PH _3. Doping was performed at a high concentration at a dose of cm ² to form the structure shown in FIG.

In the ion shower method, the anisotropy of the implanted ions is weaker than in the ion implantation method, and the region 36 slightly inside the resist pattern is also doped.

Next, using the second resist pattern 20 as a mask, the conductive film 5 is anisotropically etched, and the gate 32 of the P-type TFT, the gate 31 of the N-type TFT, and the P-type TF
Wiring 6 connecting the gate of T was formed, and the structure shown in FIG. 16 was obtained.

The anisotropic etching of the MoW alloy can be performed, for example, by RIE using a fluorine-based gas.
In this case, the gate insulating film 4 on the source and drain 33 of the N-type TFT is also etched, and a region 52 with a reduced thickness is formed.

The gate insulating film 4 on the source and drain 34 of the P-type TFT is also etched at the time of overetching. However, since the etching time is short, it becomes thinner than the gate insulating film on the source and drain of the N-type TFT. Never.

The portion of the gate insulating film which is recessed from the resist of the gate of the N-type TFT is hardly etched due to the anisotropic etching, and remains almost the same thickness as the lower portion of the gate. Is formed around the gate insulating film.

Next, an acceleration voltage of 30 k
Boron (B) is implanted with V at a dose of 8 × 10 ¹⁴ / cm ² . Since only boron is implanted into the source and drain 34 of the P-type TFT, the TFT becomes P-type. Also, N-type TF
The T source and drain 33 are already doped with phosphorus (P) at a concentration of 1 × 10 ¹⁵ / cm ² higher than boron, and remain N-type even after boron implantation.

In addition, boron is not implanted into the polysilicon below the region 51 where the gate has receded from the resist of the N-type TFT.

The source and drain 34 of the N-type TFT have a region 36 into which an N-type impurity has been introduced slightly inside the resist edge during doping, and a second region during the anisotropic etching of the conductive film. Even if the resist pattern 20 is slightly recessed by etching and boron is also implanted into the region 36, the region is not inverted to the P type.

After the resist pattern 20 is removed, phosphorus is ion-implanted at an acceleration voltage of 70 kV and a dose of 1 × 1.
When the implantation is performed at 0 ¹³ / cm ² , the polysilicon of the thick region 51 of the gate insulating film in which the gate 31 of the N-type TFT is recessed from the resist is doped with a low concentration of N-type. The type TFT 42 can be formed.

In the same manner as in Examples 1 and 2, the steps after the known activation were performed to form a CMOS thin film transistor substrate having a self-aligned LDD.

In order to obtain an LDD 35 having a target length, the amount of recession of the conductive film 5 from the resist during isotropic etching using the first resist mask is determined by adjusting the target LD.
In addition to the DD length, the length may be the sum of the decrease in the resist film thickness during the formation of the second resist pattern and the length of phosphorus flowing into the resist due to the ion shower.

The thin film transistor substrate according to the present invention can be used for anisotropic etching using the second resist pattern.
The gate insulating film on the source and the drain of the first conductivity type N-type TFT is etched, and the film thickness is reduced.

However, the gate insulating film in the region where the gate has receded from the second resist pattern is not etched. Therefore, the first region 51 in which the gate insulating film has substantially the same thickness as the lower portion of the gate is formed in the second resist pattern 2.
The gate 31 is formed to have a width recessed from 0. In addition, a second resist pattern and a thin second region 52 of the gate insulating film bordering the conductive film not covered with the second resist pattern are formed.

The conductive film pattern in contact with the second region 52 is etched except for the region covered with the second resist pattern. Therefore, in the present embodiment, the second region 52 is a wiring that is a conductive film pattern only on the boundary 53 between the first region 51 and the second region 52 that was the boundary of the second resist pattern. 6 is formed.

In the figure, an example is shown in which an opening is formed on the source and the drain of the N-type TFT, and the source and the drain of the P-type TFT are manufactured using a resist pattern in which the resist is thinner than the resist covering the gate. However, conversely, a resist pattern can be formed in which the source and drain of the P-type TFT are opened, and the source and drain regions of the N-type TFT are covered with a thinner resist than the resist covering the gate. For example, it can be manufactured by the following procedure.

Using this resist pattern, a P-type TF
After the gate of T is isotropically etched, the resist is ashed to form a second resist pattern having openings on the source and drain of the N-type TFT.

Next, boron is doped at a high concentration by an ion shower, and the source and drain of the P-type TFT are formed using the gate as a mask. Further, after processing the gate film by anisotropic etching, phosphorus is implanted by an ion shower to form N-type sources and drains, and resist retreat by ashing and anisotropic etching of the conductive film are repeated.

Next, low-concentration phosphorus is ion-implanted,
Forming a self-aligned LDD with a P-type TFT.
Is formed.

Also in this step, the P type is changed to the first conductivity type,
When the mold is the second conductivity type, regions having similar film thicknesses are formed in the gate insulating film, and those having similar characteristics at the contact with the conductive film can be obtained.

[0085]

According to the present invention, the gate of a P-type TFT and the gate of an N-type TFT having a self-aligned LDD are
Both can be formed by one photomask. Therefore, the conductive film pattern in the same layer as the gate does not deviate more than the retreat amount from the resist pattern even at the boundary between the P-type and N-type TFTs. Density can be increased.

Further, an extra area corresponding to the alignment error between the P-type and N-type TFTs is not required, and the wiring density can be improved. Compared with the past, the wiring density increased by about 10%,
There is an effect that the circuit area can be reduced by 20%.

Further, according to the present invention, the gate processing and the doping process which conventionally required two or more photomasks can be completed with one photomask, so that the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a first example of a manufacturing process of a thin film transistor substrate of the present invention.

FIG. 2 is a schematic view showing an example of a manufacturing process that is continuous with FIG.

FIG. 3 is a schematic view showing an example of a manufacturing process that is continuous with FIG. 2;

FIG. 4 is a schematic view showing an example of a manufacturing process continued from FIG. 3;

FIG. 5 is a schematic view showing an example of a manufacturing process continued from FIG. 4;

FIG. 6 is a schematic view showing an example of a manufacturing process continuing from FIG. 5;

FIG. 7 is a schematic cross-sectional view showing a second example of the manufacturing process of the thin film transistor substrate of the present invention.

FIG. 8 is a schematic view showing an example of a manufacturing process continued from FIG. 7;

FIG. 9 is a schematic view showing an example of a manufacturing process continuing from FIG. 8;

FIG. 10 is a schematic view showing an example of a manufacturing process continuing from FIG. 9;

FIG. 11 is a schematic view showing an example of a manufacturing process continued from FIG. 10;

FIG. 12 is a schematic view showing an example of a manufacturing process continued from FIG. 11;

FIG. 13 is a schematic sectional view showing a third example of the manufacturing process of the thin film transistor substrate of the present invention.

FIG. 14 is a schematic view showing an example of a manufacturing process continuing from FIG. 13;

FIG. 15 is a schematic view showing an example of a manufacturing process continued from FIG. 14;

FIG. 16 is a schematic view showing an example of a manufacturing process continued from FIG. 15;

FIG. 17 is a schematic view showing an example of a manufacturing process continued from FIG. 16;

[Explanation of symbols]

DESCRIPTION OF REFERENCE NUMERALS 1: transparent insulating substrate, 2: base film, 3: polysilicon film,
4 gate insulating film, 5 conductive film, 6 wiring, 11 opening, 12 resist, 13 resist, 14 recessed region of conductive film, 20 resist pattern, 21 opening, 22 resist Pattern, 31 gate, 32 gate, 33 source and drain, 34 source and drain, 35 LDD, 36 N-type region, 41 N
Type TFT, 42: P-type TFT, 51: thick region of gate insulating film, 52: thin region of gate insulating film, 53: boundary line.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/30 338 H01L 27/08 331E 5G435 348 29/78 627C H01L 21/306 21/306 F 21/8238 27/08 321D 27/092 29/78 613A 27/08 331 616A F term (reference) 2H092 JA25 JA34 JA37 JA41 KA04 KA05 KA10 MA14 MA15 MA18 MA27 NA21 NA27 NA29 5C094 AA05 AA42 AA43 BA03 BA43 CA19 DA15 EA04 EA07 A08 5F GG02 5F048 AC04 BA16 BB09 BC06 5F110 AA04 AA16 BB02 BB04 CC02 DD02 DD13 DD14 DD17 EE03 EE04 EE06 EE09 EE14 EE44 EE45 FF02 FF12 FF28 FF29 GG02 GG13 GG25 GG28 GG45 HJ01 PP02 Q12 H02 BB15 CC09 HH12 HH14 KK05 KK09 KK10

Claims (6)

[Claims] 1. A gate comprising a crystalline semiconductor film formed on a transparent insulating substrate, a gate insulating film formed on the semiconductor film, a conductive film formed on the gate insulating film, and both sides of the gate. Forming a top gate type TFT having a source and a drain doped with the semiconductor film,
The TFT is a CMO in which N-type and P-type are formed on the same substrate.
An S-type thin film transistor substrate, wherein a TFT of a first conductivity type has a gate insulating film between a gate and a source and a drain which is in contact with the gate and not covered with a conductive film of the same layer as the gate, and A first region having substantially the same thickness, and a gate insulating film in contact with the first region and substantially including a source or a drain, having a second region with a smaller thickness than the first region; A gate connecting the gates of the N-type TFT and the P-type TFT, wherein the thickness of the gate insulating film on the source and the drain of the two-conductivity type TFT is equal to or smaller than the first region and larger than the second region. A thin film transistor substrate, wherein a conductive film pattern having the same layer as the above is configured to be in contact with the second region only on a boundary between the first region and the second region. 2. A gate comprising a crystalline semiconductor film formed on a transparent insulating substrate, a gate insulating film formed on the semiconductor film, a conductive film formed on the gate insulating film, and both sides of the gate. Forming a top gate type TFT having a source and a drain doped with the semiconductor film,
The TFT is a CM in which an N-type and a P-type are formed on the same substrate.
An OS type thin film transistor substrate, comprising: a source and a drain of an N type TFT;
In contact with the gate pattern, the thickness of the gate insulating film is P-type T
A first region having a thickness equal to or greater than the thickness of the gate insulating film on the source and drain of the FT;
A gate insulating film including a source and a drain of the FT has a second region in which the film thickness is smaller than the first region. The width of the first region at the gate end of the N-type TFT is equal to the substrate. And the conductive film pattern of the same layer as the gate is formed at the boundary between the first region and the second region between the N-type TFT and the P-type TFT. A thin film transistor substrate having a step difference equal to or less than the width of the first region at the gate end of the N-type TFT. 3. A gate made of a crystalline semiconductor film formed on a transparent insulating substrate, a gate insulating film formed on the semiconductor film, a conductive film formed on the gate insulating film, and both sides of the gate. Forming a top gate type TFT having a source and a drain doped with the semiconductor film,
The TFT is a CMO in which N-type and P-type are formed on the same substrate.
A method of manufacturing an S-type thin film transistor substrate, wherein an opening is formed on the source and the drain of the first conductivity type TFT, and the opening is formed on the source and the drain of the second conductivity type TFT.
Forming a first resist pattern covering with a resist having a smaller film thickness than the resist covering the gate; reducing the thickness of the resist pattern so as to open the resist pattern in the source / drain region of the second conductivity type TFT; And a step of forming a second resist pattern having a gate coated thereon. 4. A gate made of a crystalline semiconductor film formed on a transparent insulating substrate, a gate insulating film formed on the semiconductor film, a conductive film formed on the gate insulating film, and both sides of the gate. Forming a top gate type TFT having a source and a drain doped with the semiconductor film,
A method of manufacturing a CMOS type thin film transistor substrate in which an N-type TFT and a P-type TFT are formed on the same substrate, and a low-concentration N-type region LDD is formed at a gate end of the N-type TFT. Using a first resist pattern having openings on the source and drain of the N-type TFT and covering the source and drain of the P-type TFT with a resist having a thickness smaller than the thickness of the resist on the gate; Processing a conductive film of the same layer as the gate; and reducing the thickness of the first resist pattern to form a P-type TF.
Forming a second resist pattern having openings on the source and drain of T and covering the gate; and forming a gate of a P-type TFT by anisotropic etching using the second resist pattern as a mask. A method for producing a thin film transistor substrate, comprising: 5. A gate made of a crystalline semiconductor film formed on a transparent insulating substrate, a gate insulating film formed on the semiconductor film, a conductive film formed on the gate insulating film, and both sides of the gate. Forming a top gate type TFT having a source and a drain doped with the semiconductor film,
A method of manufacturing a CMOS type thin film transistor substrate in which N-type and P-type TFTs are formed on the same substrate, and an LDD which is a low-concentration N-type region is formed at a gate end of the N-type TFT. An opening is formed on the source and the drain of the TFT of one conductivity type, and on the source and the drain of the TFT of the second conductivity type,
Forming a first resist pattern covered with a resist having a smaller film thickness than the resist covering the gate; and using the first resist pattern as a mask, forming a gate of the first conductivity type TFT by isotropic etching. Forming a pattern recessed from the resist pattern, reducing the thickness of the first resist pattern, opening the source and drain of the second conductivity type TFT, and forming a second resist pattern covered with a gate. A method of manufacturing a thin film transistor substrate, comprising: a step of forming; and a step of processing a gate of a second conductivity type TFT by anisotropic etching using the second resist pattern as a mask. 6. A method of manufacturing a CMOS thin film transistor substrate, wherein the conductive film forming the gate of the TFT is a metal film, and the isotropic etching of the conductive film using the first resist pattern as a mask is performed by wet etching. The method for producing a thin film transistor substrate according to claim 5, wherein