KR20080004005A - Thin film transistor substrate manufacturing method - Google Patents

Abstract

A method of fabricating a thin film transistor substrate is provided to reduce a channel length between a source electrode and a drain electrode of a thin film transistor through a single slit mask having a notch. A gate pattern including a gate line and a gate electrode(20) is formed. A gate insulating layer(30), an active layer(40), an ohmic-contact layer(45) and a data metal layer are formed on the gate pattern. A channel of a thin film transistor and a data pattern including a source electrode(60), a drain electrode(70) and a data line(50) are formed at the data metal layer by using a single slit mask including a notch. A passivation layer and a pixel electrode(100) connected with the drain electrode are formed on the data pattern. The forming of the channel of the thin film transistor and the data pattern includes forming photoresist on the data metal layer, exposing the photoresist by using the single slit mask, and etching the data metal layer without a patterned photoresist pattern.

Description

The manufacturing method of a thin film transistor substrate {THIN FILM TRANSISTOR SUBSTRATE MANUFACTURING METHOD}

1 is a plan view illustrating a portion of a thin film transistor substrate formed by a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a cross section taken along line II ′ of the thin film transistor substrate illustrated in FIG. 1.

3A is a cross-sectional view illustrating a first mask process in the method of manufacturing the thin film transistor substrate illustrated in FIGS. 1 and 2 according to the first embodiment of the present invention.

3B is a cross-sectional view illustrating a second mask process in the method of manufacturing the thin film transistor substrate illustrated in FIGS. 1 and 2 according to the first embodiment of the present invention.

3C to 3E are diagrams for describing the second mask process of the present invention in detail.

3F is a cross-sectional view illustrating a third mask process in the method of manufacturing the thin film transistor substrate illustrated in FIGS. 1 and 2, according to the first embodiment of the present disclosure.

3G is a cross-sectional view illustrating a fourth mask process in the method of manufacturing the thin film transistor substrate illustrated in FIGS. 1 and 2, according to the first embodiment of the present disclosure.

4 is a diagram illustrating a single slit mask pattern according to an embodiment of the present invention.

5 is a plan view illustrating a portion of a thin film transistor substrate formed by a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view illustrating a cross section taken along line II-II ′ of the thin film transistor substrate illustrated in FIG. 5.

7A to 7D are diagrams for describing a third mask process of the present invention in detail.

<Short description of drawing symbols>

10 substrate 20 gate electrode

21: gate line 30: gate insulating film

40: active layer 45: ohmic contact layer

50: data line 60: source electrode

70: drain electrode 80: protective film

90 contact hole 100 pixel electrode

200: single slit mask 210: blocking area

220: slit region 230: transmission region

240: notch 330: amorphous silicon layer

340: impurity doped amorphous silicon layer 350: data metal layer

360, 400: photoresist

370: photoresist pattern 380: residual photoresist

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display device includes a liquid crystal panel formed of a color filter substrate and a thin film transistor substrate bonded with liquid crystals interposed therebetween, a panel driver for driving the liquid crystal panel, and a backlight unit for supplying light to the liquid crystal panel.

Here, the color filter substrate and the thin film transistor substrate of the liquid crystal panel are formed using a plurality of mask processes. One mask process includes a number of processes, such as a thin film deposition (coating) process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, an inspection process, and the like.

In particular, as the thin film transistor substrate includes a semiconductor process and requires a plurality of mask processes, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. Accordingly, efforts to reduce the number of mask processes of the thin film transistor substrate have been continued.

In addition, efforts have been made to reduce the manufacturing cost of the liquid crystal display by forming a panel driving unit integrated with the liquid crystal panel. In particular, since a thin film transistor must be integrated at a high density in order to manufacture a high-resolution liquid crystal panel, a mask pattern must be finely formed. The mask pattern for forming the source / drain electrodes of the thin film transistor uses a slit mask in which a plurality of slits are formed.

However, when the slit mask having a plurality of slits is used, the channel length between the source / drain electrodes becomes large and the on current between the source / drain electrodes decreases, resulting in a problem of deterioration of the thin film transistor characteristics.

Accordingly, a technical problem of the present invention is to reduce the channel length between the source electrode and the drain electrode of the thin film transistor using a notched single slit mask, and to reduce the pattern width of the source electrode and the drain electrode. To provide.

In order to solve the above technical problem, the present invention comprises the steps of forming a gate pattern including a gate line and a gate electrode, forming a gate insulating film, an active layer, an ohmic contact layer and a data metal layer on the gate pattern; Forming a data pattern including a source electrode, a drain electrode, and a data line and a channel of the thin film transistor using a single slit mask having a notch formed in the data metal layer, and connecting the passivation layer and the drain electrode on the data pattern. It provides a method of manufacturing a thin film transistor substrate comprising the step of forming a pixel electrode.

The forming of the data pattern and the channel of the thin film transistor may include forming a photoresist on the data metal layer, exposing the photoresist using the single slit mask, and forming the patterned photoresist pattern. Etching a data metal layer except for a.

The exposing the photoresist may further include forming a residual photoresist in the channel region of the thin film transistor through a notch formed in the single slit mask.

In the forming of the residual photoresist of the channel region of the thin film transistor, the notch may include a first blocking region for blocking a region corresponding to the drain electrode and a second blocking region for blocking a region corresponding to the source electrode. And adjusting the amount of residual photoresist according to the widths and depths of the notches formed in the first and second blocking regions, respectively.

And the width and depth of the notch is formed to 1 to 2㎛ further comprises adjusting the amount of the residual photoresist.

The forming of the passivation layer and the pixel electrode may include forming a passivation layer including a contact hole exposing the drain electrode with an organic or inorganic insulating material, and forming the passivation layer on the passivation layer via the contact hole. The method may further include forming a pixel electrode by forming the contact transparent conductive pattern.

Meanwhile, in the forming of the passivation layer and the pixel electrode, a passivation layer is formed on an entire area of the substrate using an organic or inorganic insulating material on the substrate on which the data pattern is formed, and a photoresist is patterned to etch the passivation layer. Forming a pixel electrode by etching the transparent conductive layer in a lift-off process after forming a transparent conductive layer on the substrate on which the resistor is patterned.

Other technical problems and features of the present invention in addition to the above technical problem will become apparent through the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 7D.

1 is a plan view illustrating a portion of a thin film transistor substrate formed by a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention, and FIG. 2 is a line II ′ of the thin film transistor substrate illustrated in FIG. 1. It is sectional drawing which shows the cross section cut along.

The method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention is manufactured by a four mask process.

3A is a cross-sectional view illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

In the first mask process, a gate pattern including the gate line 21 and the gate electrode 20 is formed on a transparent substrate 10 such as glass or plastic.

Specifically, the gate metal layer is formed on the substrate 10 by using a metal deposition method such as a sputtering method. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, or Al alloy is used, and the gate metal layer is formed in a form in which a single layer or a double layer of the metal material is laminated. do. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate pattern including the gate line 21 and the gate electrode 20.

3B is a cross-sectional view illustrating a second mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

A gate insulating film 30 is formed on the substrate 10 having the gate pattern formed thereon, and an active layer 40 and a source electrode 60 for forming a channel of the thin film transistor on the gate insulating film 30 by a second mask process. ) And a drain electrode 70 are formed, and a data line 50 connected to the source electrode 60 is formed. Here, an ohmic contact layer 45 is formed between the active layer 40, the source electrode 60, and the drain electrode 70. The data pattern including the active layer 40, the ohmic contact layer 45, the source electrode 60, the drain electrode, and the data line 50 is formed by one mask process using the single slit mask 200.

Referring to FIG. 3B, the gate insulating layer 30, the amorphous silicon layer 330, the impurity doped amorphous silicon layer 340, the source electrode 60, and the drain electrode 70 are formed on the substrate 10 on which the gate pattern is formed. ) And the data metal layer 350 including the data line 50 are sequentially formed. For example, the gate insulating layer 30, the amorphous silicon layer 330, and the impurity doped amorphous silicon layer 340 are formed by a Plasma Enhanced Chemical Vapor Deposion (PECVD) method, and the data metal layer 350 is formed by a sputtering method. do. The gate insulating layer 30 is formed of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), and the data metal layer 350 is formed of Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Metal materials such as Al alloys are formed in a stacked form of a single layer or a double layer or more.

After the photoresist 360 is applied on the data metal layer 350, the photoresist 360 is exposed and developed by a photolithography process using the single slit mask 200 to form the photoresist pattern 370.

Specifically, the blocking region 210 is positioned in the region where the active layer 40, the ohmic contact layer 45, and the data pattern are to be formed to block ultraviolet rays, so that the photoresist pattern 370 remains after development as illustrated in FIG. 3C. The slit region 220 is positioned in a region where a channel of the thin film transistor is to be formed to diffract ultraviolet rays, so that a residual photoresist pattern 380 thinner than the photoresist pattern 370 is left after development as illustrated in FIG. 3D. The transmissive region 230 transmits all ultraviolet rays so that the photoresist 360 is removed after development. Here, the source electrode 60 and the drain electrode 70 of the data metal layer 350 have a structure connected to each other.

Subsequently, by ashing the photoresist pattern 370 by an ashing process using an oxygen plasma or the like, the photoresist pattern 370 is thinned as shown in FIG. 3E, and the residual photoresist pattern 380 is removed. Subsequently, the data pattern exposed by the etching process using the ashed photoresist pattern 370 and the ohmic contact layer 45 below the same are removed, thereby separating the source electrode 60 and the drain electrode 70, thereby forming an active layer ( 40) is exposed. In the etching process using the photoresist pattern 370, the data metal layer 350 including the source electrode 60, the drain electrode 70, and the data line 50 is patterned, thereby as shown in FIG. 3B. The drain pattern and the semiconductor pattern below it are formed.

In this case, the photoresist pattern 370 is formed using the single slit mask 200.

4 is a plan view illustrating a single slit mask pattern according to an exemplary embodiment of the present invention.

The single slit mask 200 is divided into a blocking region 210, a slit region 220, and a transmission region 230. Referring to FIG. 4, a region in which a channel of the thin film transistor is formed, that is, the slit region 220 is formed with a single slit 220, and a blocking region in which the slit region 220 and the blocking region 210 are formed to face each other. Notches 240 are formed at the edges of 210. The notch 240 is formed in the first blocking region 210a for blocking the region where the drain electrode 70 is to be formed and the second blocking region 210b for blocking the region in which the source electrode 60 is to be formed. The notch 240 is alternately formed between the first notch 240a formed in the first blocking region 210a and the second notch 240b formed in the second blocking region 210b. In other words, the first notch 240a is formed by removing a part of the light blocking film of the first blocking region 210a, and the second notch 240b is alternately intersected with the first notch 240a to form the second blocking region 210b. ) Is formed by removing a part of the light blocking film. Therefore, the distance A between the first blocking region 210a and the second blocking region 210b is preferably formed to be 1 to 3 μm. If the distance A between the first blocking region 210a and the second blocking region 210b is formed within 1 μm, no channel is formed between the drain electrode 70 and the source electrode 60 when the thin film transistor is formed. Can be. Since the exposure width of the photoresist 360 formed on the data metal layer is reduced, the amount of the remaining photoresist 380 after exposure is large, so that the drain electrode 70 and the source electrode 60 are removed in the etching process because all of them are not removed in the ashing process. It is not separated. In addition, even when the drain electrode 70 and the source electrode 60 are separated, the pattern width of the drain electrode 70 and the source electrode 60 is too wide, so that the overlapping area between the gate electrode 20 and the gate electrode 20 increases, The parasitic storage between the drain electrode 70 or the source electrode 60 is increased to increase the size of the kickback voltage, thereby deteriorating operating characteristics of the thin film transistor.

On the other hand, when the distance A between the first blocking region 210a and the second blocking region 210b is 3 μm or more, the slit region 220 is widened so that the residual photoresist 380 is not formed. The channel length L between the drain electrode 70 and the source electrode 60 becomes too wide. Accordingly, there is a problem in that the amount of on current between the drain electrode 70 and the source electrode 60 is reduced, thereby lowering the charge rate margin.

In addition, the width B, in which the notch 240 is formed along the blocking region 210 surface, is preferably formed to have a width of 1 to 2 μm. When the notch width B is formed within 1 μm, the amount of residual photoresist increases, so that the pattern width of the drain electrode 70 and the source electrode 60 increases as described above in an etching process, thereby increasing parasitic storage. Problems arise. In addition, when the width B of the notch is formed to be 2 μm or more, a problem arises in that the channel length becomes too wide.

The depth C in which the notch 240 is recessed inwardly of the blocking region 210, that is, the depth C of the notch is preferably formed in a range of 1 to 2 μm. Here, when the notch depth C is formed within 1 μm, the amount of residual photoresist increases, so that the pattern width of the drain electrode 70 and the source electrode 60 increases in the subsequent etching process, thereby increasing parasitic storage. Is generated. In addition, when the notch depth C is formed to be 2 μm or more, a problem arises in that the channel length becomes too wide. Therefore, in order to prevent the above-mentioned problem, the width B and the depth C of the notch are formed to be 1 to 2 mu m.

3F is a cross-sectional view for describing a third mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

In the third mask process, the passivation layer 80 including the contact hole 90 is formed.

Specifically, the protective film 80 is formed on the gate insulating film 30 on which the data pattern is formed as shown in FIG. 3F by PECVD, spin coating, or spinless coating. As the protective film 80, an inorganic insulating material such as the gate insulating film 30 formed by a CVD or PECVD method is used. Alternatively, an organic insulating material such as an acrylic organic compound, BCB, PFCB, or the like formed by a method such as spin coating or spinless coating may be used. Alternatively, the inorganic insulating material and the organic insulating material may be formed by laminating a double layer. Subsequently, a photoresist is applied over the passivation layer 80, and then a photoresist pattern is formed in a region where the passivation layer 80 is to be formed. Next, a contact hole 90 is formed through the passivation layer 80 to expose the drain electrode 70 through an etching process using a photoresist pattern.

3E is a cross-sectional view for describing a fourth mask process in the method of manufacturing the thin film transistor substrate according to the embodiment of the present invention.

The pixel electrode 100 is formed by a fourth mask process.

Specifically, the transparent conductive film 100 is previously formed on the substrate 10 on which the protective film 80 is formed by a deposition method such as sputtering or the like. As the transparent conductive film 100, indium tin oxide, tin oxide, indium zinc oxide, or the like is used. The pixel electrode 100 is connected to the drain electrode 70 via the contact hole 90.

Meanwhile, the manufacturing method of the thin film transistor substrate according to the second embodiment of the present invention may be manufactured through three mask processes.

FIG. 5 is a plan view of a thin film transistor substrate for explaining a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 6 is cut along the line II-II ′ of the thin film transistor substrate illustrated in FIG. 5. 7A to 7D are cross-sectional views sequentially illustrating a third mask process of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

Here, the gate pattern, the active layer, the ohmic contact layer, and the data pattern are formed as shown in FIGS. 3A to 3E. The passivation layer 80 and the pixel electrode 100 are formed in one mask process. Next, the passivation layer 80 and the pixel electrode 100 are formed through the third mask process.

Specifically, as shown in FIG. 7A, the passivation layer 80 is formed on the gate insulating layer 30 on which the data pattern is formed by PECVD, spin coating, spinless coating, or the like. An inorganic insulating material or an organic insulating material is used as the passivation layer 80, and may be formed of a dual structure of an inorganic insulating material and an organic insulating material.

Subsequently, as shown in FIG. 7A, the photoresist 400 is applied on the passivation layer 80, and then exposed and developed by a photolithography process to form a photoresist pattern on the portion where the passivation layer 80 is to be formed. Next, as shown in FIG. 7B, the passivation layer 80 is patterned by an etching process using a photoresist pattern. When the passivation layer 80 is patterned, the gate insulating layer 30 in a region not overlapping with the data metal layer is also etched to expose the upper portion of the substrate 10.

Next, as shown in FIG. 7C, the transparent conductive film 100 is formed on the entire surface of the substrate 10 on which the photoresist pattern exists by a deposition method such as sputtering or the like.

Subsequently, the photoresist pattern and the transparent conductive film 100 thereon are removed together in a lift-off process to form a transparent conductive pattern including the pixel electrode 100 as illustrated in FIG. 7D. The pixel electrode 100 forms a boundary with the patterned passivation layer 80 and is laterally connected to the drain electrode 70.

As described above, in the method of manufacturing the thin film transistor substrate according to the present invention, a high-clean thin film transistor substrate may be manufactured using a single slit mask in which a notch is formed when forming a data pattern of the thin film transistor substrate.

In addition, it is possible to shorten the manufacturing process of the thin film transistor substrate by using a 3 mask or 4 mask process and to manufacture a high-clean thin film transistor substrate using a conventional exposure machine.

In addition to the thin film transistor formed in the pixel region of the liquid crystal panel, the thin film transistor included in the panel driver integrated in the liquid crystal panel may form a high density thin film transistor using a single slit mask.

The present invention described above will be capable of various substitutions, modifications and changes by those skilled in the art to which the present invention pertains. Therefore, the present invention should not be limited to the above-described embodiments and the accompanying drawings, and the rights thereof should be determined by the claims.

Claims (7)

Forming a gate pattern comprising a gate line and a gate electrode; Forming a gate insulating layer, an active layer, an ohmic contact layer, and a data metal layer on the gate pattern; Forming a channel of a data pattern and a thin film transistor including a source electrode, a drain electrode, and a data line using a single slit mask having a notch formed in the data metal layer; Forming a pixel electrode connected to the passivation layer and the drain electrode on the data pattern. The method of claim 1, Forming a channel of the data pattern and the thin film transistor is Forming a photoresist on the data metal layer; Exposing the photoresist using the single slit mask; And etching the data metal layer except for the patterned photoresist pattern. The method of claim 2, Exposing the photoresist And forming a residual photoresist in the channel region of the thin film transistor through the notch formed in the single slit mask. The method of claim 3, wherein Forming a residual photoresist in the channel region of the thin film transistor The notch may be alternately formed between the first blocking region blocking the region corresponding to the drain electrode and the second blocking region blocking the region corresponding to the source electrode, respectively. And adjusting the amount of residual photoresist in accordance with the width and depth. The method of claim 4, wherein Forming a width and depth of the notch of 1 to 2㎛ the method of manufacturing a thin film transistor substrate further comprising the step of adjusting the amount of the residual photoresist. The method according to any one of claims 1 to 5, Forming the passivation layer and the pixel electrode Forming a protective film including a contact hole exposing the drain electrode with an organic or inorganic insulating material; And forming a pixel electrode by forming a transparent conductive pattern in contact with the drain electrode via the contact hole on the passivation layer. The method according to any one of claims 1 to 5, Forming the passivation layer and the pixel electrode A protective film is formed on the entire region of the substrate on the substrate on which the data pattern is formed, the photoresist is patterned to etch the protective film, and the photoresist is patterned to form a transparent conductive film on the substrate. And forming a pixel electrode by etching the transparent conductive layer in a post-lift off process.

Images