WO2021179330A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2021179330A1
WO2021179330A1 PCT/CN2020/079369 CN2020079369W WO2021179330A1 WO 2021179330 A1 WO2021179330 A1 WO 2021179330A1 CN 2020079369 W CN2020079369 W CN 2020079369W WO 2021179330 A1 WO2021179330 A1 WO 2021179330A1
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WIPO (PCT)
Prior art keywords
electrode
layer
active layer
base substrate
inorganic passivation
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PCT/CN2020/079369
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English (en)
French (fr)
Inventor
贺家煜
宁策
李正亮
姚念琦
黄杰
刘雪
胡合合
Original Assignee
京东方科技集团股份有限公司
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Priority to CN202080000253.2A priority Critical patent/CN113728442A/zh
Priority to PCT/CN2020/079369 priority patent/WO2021179330A1/zh
Publication of WO2021179330A1 publication Critical patent/WO2021179330A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the main structure of the TFT-LCD is an array substrate and a color filter substrate arranged in a cell, and a liquid crystal molecular layer filled between the array substrate and the color filter substrate.
  • TFTs mainly include oxide semiconductor TFTs (referred to as oxide TFTs) and amorphous silicon TFTs according to different channel materials.
  • Oxide TFT uses an oxide semiconductor material as an active layer, which has good uniformity and is especially suitable for large-area display needs. It has gradually become the mainstream technology for large-size, high-quality, and low-power flat-panel display products.
  • an array substrate which includes:
  • the pixel electrode is arranged in the same layer as the active layer, the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the active layer do not overlap each other, and the material of the pixel electrode is a conductor Of the semiconductor material;
  • the first inorganic passivation layer is located on the side of the pixel electrode away from the base substrate;
  • the second inorganic passivation layer is located on a side of the first inorganic passivation layer away from the base substrate, and at least a part of the second inorganic passivation layer is in direct contact with the first inorganic passivation layer.
  • the first inorganic passivation layer has a hollow area
  • the second inorganic passivation layer covers the pixel electrode and is located at the hollow area.
  • the pixel electrode is in direct contact.
  • the transistor further includes: a gate located between the active layer and the base substrate, and a gate located away from the active layer.
  • the first pole and the second pole on one side of the base substrate;
  • the first inorganic passivation layer is located between the layer where the first electrode and the second electrode are located and the active layer;
  • the orthographic projection of the gate on the base substrate is located within the orthographic projection of the active layer
  • the orthographic projection of the first pole on the base substrate partially overlaps the orthographic projection of the first inorganic passivation layer, and the first pole includes a portion directly in contact with the first inorganic passivation layer , And the part directly in contact with the active layer;
  • the orthographic projection of the second pole on the base substrate partially overlaps the orthographic projection of the first inorganic passivation layer, and the second pole includes a portion directly in contact with the first inorganic passivation layer , The part directly in contact with the active layer, and the part directly in contact with the pixel electrode.
  • the orthographic projection of the gate on the base substrate directly contacts the first inorganic passivation layer.
  • the regions of the first pole, the second pole, and the active layer overlap each other, and the boundary of the gate is different from the boundary of the first pole or the second pole adjacent to the central region of the active layer.
  • the orthographic projection of the gates on the base substrate overlaps with the area of the first inorganic passivation layer that directly contacts the first pole and the second pole.
  • the first distance is twice the second distance.
  • the transistor further includes: a gate located between the active layer and the base substrate, and a gate located away from the active layer.
  • the first pole and the second pole on one side of the base substrate;
  • the first inorganic passivation layer is located between the layer where the first electrode and the second electrode are located and the second inorganic passivation layer, and is connected to the first electrode, the second electrode and the Active layer
  • the orthographic projection of the gate on the base substrate covers the orthographic projection of the active layer
  • the first electrode is in direct contact with the active layer
  • the second electrode is in direct contact with the active layer and the pixel electrode.
  • the transistor further includes: a first electrode and a second electrode located between the active layer and the base substrate, and The gate between the active layer and the first inorganic passivation layer;
  • the orthographic projection of the gate on the base substrate coincides with the orthographic projection of the active layer
  • the active layer covers the first electrode and the second electrode, and the bottom of the central area of the active layer is flush with the bottom of the first electrode and the second electrode;
  • the second electrode is directly connected to the pixel electrode.
  • the transistor further includes: a gate located between the active layer and the base substrate, and a gate located between the active layer and the base substrate.
  • the first inorganic passivation layer covers the first electrode, the second electrode, the active layer and the pixel electrode;
  • the orthographic projection of the gate on the base substrate covers the orthographic projection of the active layer
  • the first electrode is in direct contact with the active layer
  • the second electrode is in direct contact with the active layer and the pixel electrode.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, it further includes: a strip-shaped common electrode on the side of the second inorganic passivation layer away from the base substrate, and a gate electrode connected to the transistor. Common voltage lines set on the same floor;
  • the orthographic projection of the strip-shaped common electrode on the base substrate covers the orthographic projection of the pixel electrode, and the strip-shaped common electrode passes through each layer between the grid and the strip-shaped common electrode.
  • the via is electrically connected to the common voltage line.
  • embodiments of the present disclosure also provide a manufacturing method of an array substrate, which includes:
  • the step of forming a transistor includes:
  • a semiconductor material layer is formed on the base substrate, the semiconductor material layer includes a first part and a second part, the first part is used to form an active layer, the second part is used to form a pixel electrode, and the The orthographic projection of a part on the base substrate overlaps with the active layer, and the orthographic projection of the second part on the base substrate does not overlap with the active layer;
  • At least a part of the area of the second inorganic passivation layer is in direct contact with the first inorganic passivation layer.
  • a photoresist layer covering the active layer is formed, and using the photoresist layer as a mask, the second part contained in the semiconductor material layer is preliminarily conductive.
  • the forming the first inorganic passivation layer specifically includes:
  • the first inorganic passivation layer having a hollow area is formed at the position of the second part.
  • the conducting the second part to form the pixel electrode specifically includes:
  • the second part is conductive to form the pixel electrode.
  • FIG. 1, FIG. 2, FIG. 3, FIG. 4, and FIG. 5 are structural schematic diagrams of array substrates provided by embodiments of the disclosure, respectively;
  • FIG. 6, FIG. 7, FIG. 8, FIG. 9, and FIG. 10 are schematic structural diagrams of the array substrate shown in FIG. 1 during the manufacturing process;
  • FIG. 11, FIG. 12, FIG. 13, FIG. 14 and FIG. 15 are schematic structural diagrams of the array substrate shown in FIG. 2 during the manufacturing process;
  • FIG. 16, FIG. 17, and FIG. 18 are schematic diagrams of the structure of the array substrate shown in FIG. 3 during the manufacturing process
  • FIG. 19, FIG. 20, FIG. 21, FIG. 22, FIG. 23, and FIG. 24 are structural schematic diagrams of the array substrate shown in FIG. 4 during the manufacturing process;
  • FIG. 25 and FIG. 26 are schematic diagrams of the structure of the array substrate shown in FIG. 5 during the manufacturing process.
  • an 8-mask process (8mask) or more mask processes are generally used to realize the preparation of the array substrate of the oxide technology.
  • the 8mask process is used to form the gate electrode, the active layer, the source electrode and the drain electrode, the first inorganic passivation layer, the resin layer, the second inorganic passivation layer, the pixel electrode, and the common electrode, respectively.
  • oxide display products require a large number of masks, and the production cost is relatively high.
  • crosslinking reaction products, solvents, water, etc. are produced in the form of Outgas, which affects the stability of the transistor.
  • an array substrate as shown in FIGS. 1 to 5, including:
  • the transistor 102 is located on the base substrate 101, the transistor 102 includes an active layer 1021, and the material of the active layer 1021 is a semiconductor material;
  • the pixel electrode 103 is arranged on the same layer as the active layer 1021, the orthographic projection of the pixel electrode 103 on the base substrate 101 and the orthographic projection of the active layer 1021 do not overlap each other, and the material of the pixel electrode 103 is a conductive semiconductor material ;
  • the first inorganic passivation layer 104 is located on the side of the pixel electrode 103 away from the base substrate 101;
  • the second inorganic passivation layer 105 is located on the side of the first inorganic passivation layer 104 away from the base substrate 101, and at least a part of the second inorganic passivation layer 105 is in direct contact with the first inorganic passivation layer 104.
  • the thickness of the first inorganic passivation layer 104 and the second inorganic passivation layer 105 can be adjusted according to the actual product's requirements on the stability of the transistor 102, so that the first inorganic passivation
  • the layer 104 and the second inorganic passivation layer 105 have the functions of water blocking, hydrogen blocking and planarization of the resin layer in the related art, so there is no need to provide a resin layer, avoiding the crosslinking reaction products of the resin layer during the heating and curing process , Solvents, water, etc. are produced in the form of Outgas, and the number of masks is reduced.
  • the same semiconductor material layer is used, and the first part for forming the active layer 1021 and the second part for forming the pixel electrode 103 are formed by one patterning process, and then the second part of the semiconductor material layer is processed.
  • the corresponding semiconductor material layer can be used as the pixel electrode 103. This arrangement avoids the need to separately arrange the film layer of the pixel electrode 103, saves the cost of raw materials, and realizes a thin and light product design.
  • the mask for making the pixel electrode 103 is also saved.
  • the material of the first inorganic passivation layer 104 may be silicon oxide with a hydrogen barrier function, and the first inorganic passivation layer 104 made of silicon oxide is used. This can effectively avoid the problem that the channel region contained in the active layer 1021 is conductive due to the use of silicon nitride to make the first inorganic passivation layer 104 in the related art.
  • the material of the second inorganic passivation layer 105 may be silicon nitride with a water blocking function to prevent external water vapor from corroding the channel region of the active layer 1021.
  • the active layer 1021 may be formed of a metal oxide.
  • the metal oxide may be, but is not limited to, indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the first inorganic passivation layer 104 has a hollow area
  • the second inorganic passivation layer 105 covers the pixel electrode 103 and is hollowed out. The area is in direct contact with the pixel electrode 103.
  • the second inorganic passivation layer 105 is made of silicon nitride, since the second inorganic passivation layer 105 is in direct contact with the semiconductor material layer in the hollow area, hydrogen generated during the annealing process of silicon nitride is easy to The semiconductor material layer that enters the hollowed-out area is equivalent to another conduction treatment, which further improves the conductive characteristics of the pixel electrode 103.
  • the transistor 102 further includes: a first electrode 1022 and a second electrode located on the side of the active layer 1021 away from the base substrate 101 A diode 1023, and a gate 1024 located between the active layer 1021 and the base substrate 101;
  • the first inorganic passivation layer 104 is located between the layer where the first electrode 1022 and the second electrode 1023 are located and the active layer 1021;
  • the orthographic projection of the gate 1024 on the base substrate 101 is located within the orthographic projection of the active layer 1021;
  • the orthographic projection of the first pole 1022 on the base substrate 101 partially overlaps the orthographic projection of the first inorganic passivation layer 104.
  • the first pole 1022 includes a portion directly in contact with the first inorganic passivation layer 104 and a portion that is in direct contact with the active The part of layer 1021 that is in direct contact;
  • the orthographic projection of the second pole 1023 on the base substrate 101 partially overlaps the orthographic projection of the first inorganic passivation layer 104, and the second pole 1023 includes a portion directly in contact with the first inorganic passivation layer 104, and the active layer
  • the portion 1021 is in direct contact with the pixel electrode 103 and the portion is in direct contact with the pixel electrode 103.
  • the first inorganic passivation layer 104 can be used as an etching stop layer to prevent the formation of the first electrode 1022 and the second electrode 1023 from causing damage to the active layer 1021. Damage.
  • the first inorganic passivation layer 104 with a hollowed-out area can also be used as a mask, so that only the semiconductor material layer in the hollowed-out area can be conducted to realize the conductivity of the pixel electrode 103 and solve the problem of The problem of the contact resistance between the second electrode 1023 ensures a good electrical connection between the pixel electrode 103 and the second electrode 1023, and at the same time saves a mask for separately fabricating the pixel electrode 103 in the related art.
  • the first electrode 1022 and the second electrode 1023 of the transistor 102 are drain and source respectively, and their functions can be interchanged depending on the transistor type and the input signal, and no specific distinction is made here.
  • the first electrode 1022 is the source and the second electrode 1023 is the drain; when the transistor 102 is an N-type transistor, the first electrode 1022 is the drain and the second electrode 1023 is Source.
  • the first electrode 1022, the second electrode 1023, and the gate 1024 can be formed of molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, alloys and combinations thereof, or other suitable materials. This is not limited.
  • FIG. 2 there are two gates 1024, and the orthographic projection of the gates 1024 on the base substrate 101 and the area of the first inorganic passivation layer 104 that directly contact the first pole 1022 and the second pole 1023 are mutually Overlapping, there is a second distance L'B between the boundary of the gate 1024 away from the central area of the active layer 1021 and the boundary of the first electrode 1022 or the second electrode 1023 adjacent to the central area of the active layer 1021;
  • the first distance L B is twice or approximately twice the second distance L' B , where "approximately” means within an acceptable deviation range of the specific value determined by those skilled in the art, for example, “approximately” can mean Within one or more standard deviations, or within ⁇ 30%, ⁇ 20%, ⁇ 10%, ⁇ 5% of the stated value.
  • the hydrogen in the preparation process of the second inorganic passivation layer 105 may enter the active layer 1021 through the first inorganic passivation layer 104, and the first electrode 1022 above the first inorganic passivation layer 104 And the second electrode 1023 can better block hydrogen from entering the active layer 1021, therefore, the active layer 1021 (that is, the central area of the active layer 1021) located in the area between the first electrode 1022 and the second electrode 1023 may be conductive The active layer 1021 covered by the first pole 1022 and the second pole 1023 is still in a semiconductor state. Specifically, as shown in FIG.
  • the active layer 1021 L A conductive region may be in a state, the active layer 1021 L B region is still in the state of the semiconductor, i.e., the channel region is formed in the two L B
  • the area is symmetrically distributed with twin channels.
  • the carrier concentration in the L B region that is, the effective length of the channel L eff is 2L B.
  • the channel length of a single channel 2L B, L B is the length of the twin-channel, increasing the effective carrier concentration of the channel, to improve the mobility of the transistor and the operating current I on 102. Furthermore, as shown in FIG.
  • the active layer 1021 in the L'A region may be in a conductive state, while the active layer 1021 in the L' B region is still in a semiconductor state, that is, a
  • the two L' B regions are symmetrically distributed twin channels.
  • the carrier concentration in the L′ B region that is, the effective length of the channel L eff is 2L′ B.
  • the channel can be further increased carrier concentration, mobility and increase the operating current of the transistor 102 I on.
  • the transistor 102 includes: a gate 1024 located between the active layer 1021 and the base substrate 101, and a gate located on the active layer 1021 The first pole 1022 and the second pole 1023 on the side away from the base substrate 101;
  • the first inorganic passivation layer 104 is located between the layer where the first electrode 1022 and the second electrode 1023 are located and the second inorganic passivation layer 105, and is in direct contact with the first electrode 1022, the second electrode 1023 and the active layer 1021;
  • the orthographic projection of the gate 1024 on the base substrate 101 covers the orthographic projection of the active layer 1021;
  • the first electrode 1022 is in direct contact with the active layer 1021
  • the second electrode 1023 is in direct contact with the active layer 1021 and the pixel electrode 103.
  • the first inorganic passivation layer 104 is a mask, and the semiconductor material layer in the hollowed-out area is processed by ionization (Plasma) to realize the conductivity of the pixel electrode 103, and at the same time, it saves the mask for separately fabricating the pixel electrode 103 in the related art plate.
  • the transistor 102 includes a first electrode 1022 and a second electrode 1023 located between the active layer 1021 and the base substrate 101, and A gate 1024 located between the active layer 1021 and the first inorganic passivation layer 104;
  • the active layer 1021 covers the first electrode 1022 and the second electrode 1023, and the bottom of the central area of the active layer 1021 is flush with the bottom of the first electrode 1022 and the second electrode 1023;
  • the second electrode 1023 is directly connected to the pixel electrode 103.
  • the first inorganic passivation layer 104 with the hollowed-out area can be used as a mask to realize the conductive treatment of the semiconductor material layer in the hollowed-out area and ensure the conductivity of the pixel electrode 103. Therefore, The mask for separately manufacturing the pixel electrode 103 in the related art is saved. Moreover, since the pixel electrode 103 has better conductivity, the contact resistance between the pixel electrode 103 and the second electrode 1023 is small, which ensures a good electrical connection between the pixel electrode 103 and the second electrode 1023, and saves related technologies. The mask plate of the pixel electrode 103 is separately produced in.
  • the transistor 102 further includes a gate 1024 located between the active layer 1021 and the base substrate 101, and The first pole 1022 and the second pole 1023 between 1021 and the first inorganic passivation layer 104;
  • the first inorganic passivation layer 104 covers the first electrode 1022, the second electrode 1023, the active layer 1021 and the pixel electrode 103;
  • the orthographic projection of the gate 1024 on the base substrate 101 covers the orthographic projection of the active layer 1021;
  • the first electrode 1022 is in direct contact with the active layer 1021
  • the second electrode 1023 is in direct contact with the active layer 1021 and the pixel electrode 104.
  • the patterns of the first inorganic passivation layer 104 and the second inorganic passivation layer 105 are the same. Therefore, in the actual production process, the first inorganic thin film layer and the second inorganic thin film layer can be deposited sequentially, and the same A patterning process is performed on a mask to form a via pattern penetrating the first inorganic passivation layer 104 and the second inorganic passivation layer 105. In this way, a mask can be saved.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIGS. 1 to 5, it further includes: a strip-shaped common electrode 106 on the side of the second inorganic passivation layer 105 away from the base substrate 101, And a common voltage line 107 provided on the same layer as the gate 1024 of the transistor 102;
  • the orthographic projection of the strip-shaped common electrode 106 on the base substrate 101 covers the orthographic projection of the pixel electrode 103, and the strip-shaped common electrode 106 passes through the via holes and common voltage lines that penetrate the layers between the gate 1024 and the strip-shaped common electrode 106. 107 electrical connection.
  • “same layer arrangement” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to one mask.
  • a patterning process may include multiple exposure, display or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses. Therefore, the gate 1024 and the common voltage line 107 are arranged in the same layer, which can reduce the masking process, improve the production efficiency, and realize a light and thin design.
  • FIG. 1 to FIG. A gate line (not shown in the figure) is provided, and a data line (not shown in the figure) is provided in the same layer as the first pole 1022 and the second pole 1023.
  • the arrangement and manufacturing method of the gate insulating layer 108, the gate lines and the data lines are the same as those in the related art, and are not limited here.
  • the embodiments of the present disclosure provide a manufacturing method of an array substrate. Since the principle of the manufacturing method to solve the problem is similar to the principle of the above-mentioned array substrate, the implementation of the manufacturing method provided by the embodiment of the present disclosure is Reference can be made to the implementation of the above-mentioned array substrate provided by the embodiments of the present disclosure, and the repetition is not repeated here.
  • a manufacturing method of an array substrate provided by an embodiment of the present disclosure includes:
  • the steps of forming a transistor include:
  • a semiconductor material layer is formed on the base substrate.
  • the semiconductor material layer includes a first part and a second part.
  • the first part is used to form the active layer, and the second part is used to form the pixel electrode.
  • the orthographic projection of the first part on the base substrate is the same as The active layers overlap each other, and the orthographic projection of the second part on the base substrate does not overlap with the active layer;
  • At least a part of the second inorganic passivation layer is in direct contact with the first inorganic passivation layer.
  • a photoresist layer covering the active layer is formed, and the photoresist layer is used as a mask to conduct preliminary conductorization of the second part contained in the semiconductor material layer.
  • the semiconductor material layer is made of oxides such as IGZO
  • oxides such as IGZO
  • the second part of the semiconductor material layer used to make the pixel electrode is preliminarily conductive, which can greatly reduce the amount of oxygen. , To achieve conductivity for the second part of the pixel electrode.
  • the oxygen of the silicon oxide will enter the semiconducting material layer after preliminary conduction, resulting in a deconducting effect and affecting the conductivity of the pixel electrode.
  • the hollow area of the first inorganic passivation layer is formed, so that the first inorganic passivation layer can be used as a mask to realize the secondary conductorization of the pixel electrode and solve the problem of silicon oxide.
  • forming the first inorganic passivation layer can be specifically implemented in the following manner:
  • a first inorganic passivation layer with a hollow area is formed at the position of the second part.
  • conducting the second part to form the pixel electrode may specifically include:
  • the second part contained in the semiconductor material layer is conductorized to form a pixel electrode.
  • the patterning process involved in forming each layer structure may not only include deposition, photoresist coating, mask masking, exposure, development, etching, Part or all of the process, such as photoresist stripping, may also include other processes, and the details are subject to the pattern formed in the actual manufacturing process, which is not limited here.
  • a post-baking process may also be included after development and before etching.
  • the deposition process can be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a physical vapor deposition method, which is not limited here;
  • the mask used in the mask process can be a half-tone mask (Half Tone Mask). ), Single Slit Mask or Gray Tone Mask, which is not limited here;
  • the etching can be dry etching or wet etching, which is not limited here.
  • the manufacturing process of the array substrate shown in FIG. 1 is as follows:
  • the gate 1024 and the common voltage line 107 are patterned once on the base substrate 101, as shown in FIG. 6;
  • the gate insulating layer 108 and the semiconductor material layer are sequentially deposited, and the semiconductor material layer is patterned to obtain the first part for forming the active layer 1021 and the second part for forming the pixel electrode 103, and the second part is on the substrate
  • the orthographic projection on the substrate 101 and the orthographic projection of the active layer 1021 do not overlap each other, as shown in FIG. 7;
  • the first inorganic passivation layer 104 is formed by a patterning process.
  • the first inorganic passivation layer 104 has a hollow area at the second part of the semiconductor material layer.
  • the first inorganic passivation layer 104 is used as a mask to achieve alignment
  • the semiconductor material layer contains the conductive processing for forming the second part of the pixel electrode 103 to ensure the conductivity of the pixel electrode 103. So far, the production of the pixel electrode 103 is completed, as shown in FIG. 8;
  • the first electrode 1022 and the second electrode 1023 are formed through a patterning process, and the second electrode 1023 is directly connected to the pixel electrode 103, so far, the fabrication of the transistor 102 is completed, as shown in FIG. 9;
  • a strip-shaped common electrode 106 electrically connected to the common voltage line 107 is formed at the via hole, and the orthographic projection of the strip-shaped common electrode 106 on the base substrate 101 covers the orthographic projection of the pixel electrode 103, as shown in FIG. 1.
  • the manufacturing process of the array substrate shown in FIG. 2 is as follows:
  • the two gates 1024 and the common voltage line 107 are patterned at one time on the base substrate 101, as shown in FIG. 11;
  • the gate insulating layer 108 and the semiconductor material layer are sequentially deposited, and the semiconductor material layer is patterned to obtain the first part for forming the active layer 1021 and the second part for forming the pixel electrode 103.
  • the second part is on the substrate.
  • the orthographic projection on the substrate 101 and the orthographic projection of the active layer 1021 do not overlap each other, as shown in FIG. 12;
  • the first inorganic passivation layer 104 is formed by a patterning process.
  • the first inorganic passivation layer 104 has a hollow area at the second part of the semiconductor material layer.
  • the first inorganic passivation layer 104 is used as a mask to achieve Conducting the second part of the semiconductor material layer used to form the pixel electrode 103 is processed to ensure the conductivity of the pixel electrode 103. So far, the manufacture of the pixel electrode 103 is completed, as shown in FIG. 13;
  • the first electrode 1022 and the second electrode 1023 are formed through a patterning process, and the second electrode 1023 is directly connected to the pixel electrode 103. So far, the fabrication of the transistor 102 is completed, as shown in FIG. 14;
  • a strip-shaped common electrode 106 electrically connected to the common voltage line 107 is formed at the via hole, and the orthographic projection of the strip-shaped common electrode 106 on the base substrate 101 covers the orthographic projection of the pixel electrode 103, as shown in FIG. 2.
  • the manufacturing process of the array substrate shown in FIG. 3 is as follows:
  • the gate 1024 and the common voltage line 107 are patterned once on the base substrate 101, as shown in FIG. 6;
  • the gate insulating layer 108 and the semiconductor material layer are sequentially deposited, and the semiconductor material layer is patterned to obtain a first part for forming the active layer 1021 and a second part for forming the pixel electrode 103, the second part being on the substrate
  • the orthographic projection on the substrate 101 and the orthographic projection of the active layer 1021 do not overlap each other, as shown in FIG. 7;
  • the first electrode 1022 and the second electrode 1023 are formed by a patterning process, and the second electrode 1023 is directly connected to the pixel electrode 103, so far, the fabrication of the transistor 102 is completed, as shown in FIG. 16;
  • the first inorganic passivation layer 104 is formed by a patterning process.
  • the first inorganic passivation layer 104 has a hollow area at the second part of the semiconductor material layer.
  • the first inorganic passivation layer 104 is used as a mask to achieve alignment
  • the semiconductor material layer contains the conductive processing for forming the second part of the pixel electrode 103 to ensure the conductivity of the pixel electrode 103. So far, the manufacture of the pixel electrode 103 is completed, as shown in FIG. 17;
  • a strip-shaped common electrode 106 electrically connected to the common voltage line 107 is formed at the via hole, and the orthographic projection of the strip-shaped common electrode 106 on the base substrate 101 covers the orthographic projection of the pixel electrode 103, as shown in FIG. 3.
  • the manufacturing process of the array substrate shown in FIG. 4 is as follows:
  • the first pole 1022 and the second pole 1023 are patterned once on the base substrate 101, as shown in FIG. 19;
  • a layer of semiconductor material is deposited and patterned to obtain a first part for forming the active layer 1021 and a second part for forming the pixel electrode 103.
  • the orthographic projection of the second part on the base substrate 101 is obtained Do not overlap with the orthographic projection of the active layer 1021, as shown in FIG. 20;
  • the photoresist layer 109 at the position of the active layer 1021 is formed by a patterning process, and the photoresist layer 109 is used as a mask to conduct preliminary conductors on the second part of the semiconductor material layer used to form the pixel electrode 103 Chemical treatment to realize the conductivity of the pixel electrode 103, as shown in FIG. 21;
  • the gate 1024 and the common voltage line 107 are formed through a patterning process, so far, the fabrication of the transistor 102 is completed, as shown in FIG. 22;
  • the first inorganic passivation layer 104 is formed by a patterning process.
  • the first inorganic passivation layer 104 has a hollow area at the second part of the semiconductor material layer.
  • the first inorganic passivation layer 104 is used as a mask to achieve
  • the second part of the semiconductor material layer used to form the pixel electrode 103 is reconducted to avoid the deconducting effect of the first inorganic passivation layer 104 and to ensure the conductivity of the pixel electrode 103. So far, the pixel electrode is completed.
  • the production of 103 as shown in Figure 23;
  • a strip-shaped common electrode 106 electrically connected to the common voltage line 107 is formed at the via hole, and the orthographic projection of the strip-shaped common electrode 106 on the base substrate 101 covers the orthographic projection of the pixel electrode 103, as shown in FIG. 4.
  • the manufacturing process of the array substrate shown in FIG. 5 is as follows:
  • the gate 1024 and the common voltage line 107 are patterned once on the base substrate 101, as shown in FIG. 6;
  • the gate insulating layer 108 and the semiconductor material layer are sequentially deposited, and the semiconductor material layer is patterned to obtain the first part for forming the active layer 1021 and the second part for forming the pixel electrode 103, and the second part is on the substrate
  • the orthographic projection on the substrate 101 and the orthographic projection of the active layer 1021 do not overlap each other, as shown in FIG. 7;
  • the photoresist layer 109 at the position of the active layer 1021 is formed by a patterning process, and the photoresist layer 109 is used as a mask to conduct a conductive process on the second part of the semiconductor material layer for forming the pixel electrode 103 ,
  • the conductivity of the pixel electrode 103 is realized, so far, the manufacture of the pixel electrode 103 is completed, as shown in FIG. 25;
  • the first electrode 1022 and the second electrode 1023 are formed by a patterning process, and the second electrode 1023 is directly connected to the pixel electrode 103, so far, the fabrication of the transistor 102 is completed, as shown in FIG. 16;
  • the first inorganic thin film layer used to make the first inorganic passivation layer 104 and the second inorganic thin film layer used to make the second inorganic passivation layer 105 are sequentially deposited, and formed at the position of the common voltage line 107 through a patterning process.
  • the via holes of the first inorganic passivation layer 104 and the second inorganic passivation layer 105 are as shown in FIG. 26;
  • the strip-shaped common electrode 106 electrically connected to the common voltage line 107 is formed at the via hole, and the orthographic projection of the strip-shaped common electrode 106 on the base substrate 101 covers the orthographic projection of the pixel electrode 103, as shown in FIG. 5.
  • the thickness of the first inorganic passivation layer and the second inorganic passivation layer can be adjusted according to the requirements of the actual product on the stability of the transistor, so that the first inorganic passivation layer
  • the second inorganic passivation layer and the second inorganic passivation layer have the functions of water blocking, hydrogen blocking and planarization of the resin layer in the related art, so there is no need to provide a resin layer, avoiding the crosslinking reaction products and products of the resin layer during the heating and curing process. Solvents, water, etc. are produced in the form of Outgas, and the number of masks is reduced.
  • the same semiconductor material layer is used, and the first part for forming the active layer and the second part for forming the pixel electrode are formed through a patterning process, and then the second part contained in the semiconductor material layer is conducted. Therefore, the corresponding semiconductor material layer can be used as a pixel electrode.
  • This arrangement avoids the need to separately arrange the film layer of the pixel electrode, saves the cost of raw materials, and realizes a thin and light product design.
  • the mask for making the pixel electrode is also saved.

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Abstract

一种阵列基板及其制作方法，包括：衬底基板（101）；晶体管（102），位于衬底基板（101）之上，晶体管（102）包括有源层（1021），有源层（1021）的材料为半导体材料；像素电极（103），与有源层（1021）同层设置，像素电极（103）在衬底基板（101）上的正投影与有源层（1021）的正投影互不交叠，且像素电极（103）的材料为导体化的半导体材料；第一无机钝化层（104），位于像素电极（103）背离衬底基板（101）的一侧；第二无机钝化层（105），位于第一无机钝化层（104）背离衬底基板（101）的一侧，第二无机钝化层（105）的至少部分区域与第一无机钝化层（104）直接接触。

Description

阵列基板及其制作方法 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有体积小、功耗低、无辐射等特点，在当前的平板显示器市场中占据了主导地位。TFT-LCD的主体结构是对盒设置的阵列基板和彩膜基板，以及填充在阵列基板和彩膜基板之间的液晶分子层。相关技术中，根据沟道材料的不同，TFT主要有氧化物半导体TFT(简称氧化物TFT)和非晶硅TFT两种。氧化物TFT使用氧化物半导体材料作为有源层，其具有良好的均一性，尤其适用于大面积显示的需求，已经逐渐成为大尺寸、高画质、低功耗平板显示产品的主流技术。
发明内容
本公开实施例提供了一种阵列基板，其中，包括：
衬底基板；
晶体管，位于所述衬底基板之上，所述晶体管包括有源层，所述有源层的材料为半导体材料；
像素电极，与所述有源层同层设置，所述像素电极在所述衬底基板上的正投影与所述有源层的正投影互不交叠，且所述像素电极的材料为导体化的所述半导体材料；
第一无机钝化层，位于所述像素电极背离所述衬底基板的一侧；
第二无机钝化层，位于所述第一无机钝化层背离所述衬底基板的一侧，所述第二无机钝化层的至少部分区域与所述第一无机钝化层直接接触。
可选地，在本公开实施例提供的上述阵列基板中，所述第一无机钝化层 具有镂空区域，所述第二无机钝化层覆盖所述像素电极且在所述镂空区域处与所述像素电极直接接触。
可选地，在本公开实施例提供的上述阵列基板中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的栅极，以及位于所述有源层背离所述衬底基板一侧的第一极和第二极；
所述第一无机钝化层位于所述第一极和所述第二极所在层与所述有源层之间；
所述栅极在所述衬底基板上的正投影位于所述有源层的正投影内；
所述第一极在所述衬底基板上的正投影与所述第一无机钝化层的正投影部分交叠，所述第一极包括与所述第一无机钝化层直接接触的部分、以及与所述有源层直接接触的部分；
所述第二极在所述衬底基板上的正投影与所述第一无机钝化层的正投影部分交叠，所述第二极包括与所述第一无机钝化层直接接触的部分、与所述有源层直接接触的部分、以及与所述像素电极直接接触的部分。
可选地，在本公开实施例提供的上述阵列基板中，所述栅极为一个，所述栅极在所述衬底基板上的正投影与所述第一无机钝化层中直接接触所述第一极、所述第二极和所述有源层的区域相互重合，所述栅极的边界与所述第一极或所述第二极临近所述有源层的中心区域的边界之间具有第一距离；
或者，所述栅极为两个，所述栅极在所述衬底基板上的正投影与所述第一无机钝化层中直接接触所述第一极和所述第二极的区域相互重合，所述栅极远离所述有源层的中心区域的边界与所述第一极或所述第二极临近所述有源层的中心区域的边界之间具有第二距离；
所述第一距离是所述第二距离的二倍。
可选地，在本公开实施例提供的上述阵列基板中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的栅极，以及位于所述有源层背离所述衬底基板一侧的第一极和第二极；
所述第一无机钝化层位于所述第一极和所述第二极所在层与所述第二无 机钝化层之间，并与所述第一极、所述第二极和所述有源层；
所述栅极在所述衬底基板上的正投影覆盖所述有源层的正投影；
所述第一极与所述有源层直接接触，所述第二极与所述有源层和所述像素电极直接接触。
可选地，在本公开实施例提供的上述阵列基板中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的第一极和第二极，以及位于所述有源层与所述第一无机钝化层之间的栅极；
所述栅极在所述衬底基板上的正投影与所述有源层的正投影相互重合；
所述有源层覆盖所述第一极和所述第二极，且所述有源层的中心区域的底部与所述第一极和所述第二极的底部平齐；
所述第二极与所述像素电极直接相连。
可选地，在本公开实施例提供的上述阵列基板中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的栅极，以及位于所述有源层与所述第一无机钝化层之间的第一极和第二极；
所述第一无机钝化层覆盖所述第一极、所述第二极、所述有源层和所述像素电极；
所述栅极在所述衬底基板上的正投影覆盖所述有源层的正投影；
所述第一极与所述有源层直接接触，所述第二极与所述有源层和所述像素电极直接接触。
可选地，在本公开实施例提供的上述阵列基板中，还包括：位于所述第二无机钝化层背离所述衬底基板一侧的条状公共电极，以及与所述晶体管的栅极同层设置的公共电压线；
所述条状公共电极在所述衬底基板上的正投影覆盖所述像素电极的正投影，且所述条状公共电极通过贯穿所述栅极与所述条状公共电极之间各层的过孔与所述公共电压线电连接。
基于同一发明构思，本公开实施例还提供了一种阵列基板的制作方法，其中，包括：
提供一衬底基板；
所述衬底基板上形成晶体管、第一无机钝化层和第二无机钝化层；
其中，所述形成晶体管的步骤包括：
在所述衬底基板上形成半导体材料层，所述半导体材料层包括第一部分和第二部分，所述第一部分用于形成有源层，所述第二部分用于形成像素电极，所述第一部分在所述衬底基板上的正投影与所述有源层相互重合，所述第二部分在所述衬底基板上的正投影与所述有源层互不交叠；
对所述第二部分进行导体化，形成所述像素电极；
所述第二无机钝化层的至少部分区域与所述第一无机钝化层直接接触。
可选地，在本公开实施例提供的上述制作方法中，在所述衬底基板上形成半导体材料层之后，且在所述对所述第二部分进行导体化，形成所述像素电极之前，还包括：
形成覆盖所述有源层的光刻胶层，并以所述光刻胶层为掩膜板，对所述半导体材料层所含所述第二部分进行初步导体化处理。
可选地，在本公开实施例提供的上述制作方法中，所述形成所述第一无机钝化层，具体包括：
形成在所述第二部分的位置具有镂空区域的所述第一无机钝化层。
可选地，在本公开实施例提供的上述制作方法中，所述对所述第二部分进行导体化，形成所述像素电极，具体包括：
以具有镂空区域的所述第一无机钝化层为掩膜板，对所述第二部分进行导体化，形成所述像素电极。
附图说明
图1、图2、图3、图4和图5分别为本公开实施例提供的阵列基板的结构示意图；
图6、图7、图8、图9和图10分别为图1所示阵列基板制作过程中的结构示意图；
图11、图12、图13、图14和图15分别为图2所示阵列基板制作过程中的结构示意图；
图16、图17和图18分别为图3所示阵列基板制作过程中的结构示意图；
图19、图20、图21、图22、图23和图24分别为图4所示阵列基板制作过程中的结构示意图；
图25和图26分别为图5所示阵列基板制作过程中的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。附图中各膜层的厚度和形状不反映真实比例，目的只是示意说明本公开内容。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
相关技术中，一般采用8道掩膜工艺(8mask)或者更多mask的工艺实现氧化物技术的阵列基板的制备。具体地，8mask工艺分别用于形成栅极、有源层、源极和漏极、第一无机钝化层、树脂层、第二无机钝化层、像素电极和公共电极。可见，相关技术中氧化物显示产品需要的掩膜板数量较多，生产成本较高。另外，在树脂层的加热固化过程中会有交联反应生成物、溶剂、 水等以Outgas形式产出，影响晶体管稳定性。
针对相关技术中存在的上述问题，本公开实施例提供了一种阵列基板，如图1至图5所示，包括：
衬底基板101；
晶体管102，位于衬底基板101之上，晶体管102包括有源层1021，有源层1021的材料为半导体材料；
像素电极103，与有源层1021同层设置，像素电极103在衬底基板101上的正投影与有源层1021的正投影互不交叠，且像素电极103的材料为导体化的半导体材料；
第一无机钝化层104，位于像素电极103背离衬底基板101的一侧；
第二无机钝化层105，位于第一无机钝化层104背离衬底基板101的一侧，第二无机钝化层105的至少部分区域与第一无机钝化层104直接接触。
在本公开实施例提供的上述阵列基板中，可根据实际产品对晶体管102稳定性的要求，来调节第一无机钝化层104和第二无机钝化层105的厚度，使得第一无机钝化层104和第二无机钝化层105兼具相关技术中树脂层的阻水、阻氢和平坦化的功能，从而无需设置树脂层，规避了树脂层在加热固化过程中的交联反应生成物、溶剂、水等以Outgas形式产出，且减少了掩膜板数量。另外，在本公开中采用同一半导体材料层，通过一次构图工艺形成了用于形成有源层1021的第一部分和用于形成像素电极103的第二部分，之后对半导体材料层的第二部分进行导体化，相应的半导体材料层即可作为像素电极103。如此设置，避免了单独设置像素电极103的膜层，节省了原料成本，实现了产品轻薄化设计。在一些实施例中，还节省了制作像素电极103的掩膜板。
可选地，在本公开实施例提供的上述阵列基板中，第一无机钝化层104的材料可以为具备阻氢功能的氧化硅，并且，采用氧化硅材质的第一无机钝化层104，可有效避免相关技术中采用氮化硅制作第一无机钝化层104导致有源层1021所含沟道区被导体化的问题。第二无机钝化层105的材料可以为具 备阻水功能的氮化硅，防止外界水汽对有源层1021沟道区的侵蚀。此外，有源层1021可以由金属氧化物形成，可选地，金属氧化物可以但不限于铟镓锌氧化物(IGZO)。IGZO材质的有源层1021有着较低的关态电流，有利于降低噪声。
可选地，在本公开实施例提供的上述阵列基板中，如图1至图4所示，第一无机钝化层104具有镂空区域，第二无机钝化层105覆盖像素电极103且在镂空区域处与像素电极103直接接触。
具体地，通过在第一无机钝化层104设置镂空区域，利于离子(Plasma)对镂空区域的半导体材料层进行导体化处理，获得像素电极103。并且，在第二无机钝化层105为氮化硅材质的情况下，由于第二无机钝化层105与镂空区域的半导体材料层直接接触，因此在氮化硅退火处理过程中产生的氢容易进入镂空区域的半导体材料层，相当于又进行了一次导体化处理，进一步提升了像素电极103的导电特性。
可选地，在本公开实施例提供的上述阵列基板中，如图1和图2所示，晶体管102，还包括：位于有源层1021背离衬底基板101一侧的第一极1022和第二极1023，以及位于有源层1021与衬底基板101之间的栅极1024；
第一无机钝化层104位于第一极1022和第二极1023所在层与有源层1021之间；
栅极1024在衬底基板101上的正投影位于有源层1021的正投影内；
第一极1022在衬底基板101上的正投影与第一无机钝化层104的正投影部分交叠，第一极1022包括与第一无机钝化层104直接接触的部分、以及与有源层1021直接接触的部分；
第二极1023在衬底基板101上的正投影与第一无机钝化层104的正投影部分交叠，第二极1023包括与第一无机钝化层104直接接触的部分、与有源层1021直接接触的部分、以及与像素电极103直接接触的部分。
在图1和图2所示的阵列基板中，第一无机钝化层104可以作为刻蚀阻挡层，防止刻蚀形成第一极1022和第二极1023的过程中，对有源层1021造 成的损伤。另外，还可采用具有镂空区域的第一无机钝化层104作为掩膜板，使得仅可以对镂空区域的半导体材料层进行导体化处理，实现像素电极103的导电性能，解决了像素电极103与第二极1023之间的接触电阻问题，保证了像素电极103与第二极1023的良好电连接，同时还节省了相关技术中单独制作像素电极103的掩膜板。
具体地，在本公开中，晶体管102的第一极1022和第二极1023分别为漏极和源极，根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。一般地，当晶体管102为P型晶体管时，第一极1022为源极，第二极1023为漏极；当晶体管102为N型晶体管时，第一极1022为漏极，第二极1023为源极。具体地，可由钼、铝、银、铜、钛、铂、钨、钽、氮化钽、其合金及其组合或其它合适的材料形成第一极1022、第二极1023和栅极1024，在此不做限定。
可选地，在本公开实施例提供的上述阵列基板中，如图1所示，栅极1024为一个，栅极1024在衬底基板101上的正投影与第一无机钝化层104中直接接触第一极1022、第二极1023和有源层1021的区域相互重合，栅极1024的边界与第一极1022或第二极1023临近有源层1021的中心区域的边界之间具有第一距离L B；
或者，如图2所示，栅极1024为两个，栅极1024在衬底基板101上的正投影与第一无机钝化层104中直接接触第一极1022和第二极1023的区域相互重合，栅极1024远离有源层1021的中心区域的边界与第一极1022或第二极1023临近有源层1021的中心区域的边界之间具有第二距离L’ B；
第一距离L B是第二距离L’ B的二倍或近似两倍，这里的“近似”指在本领域技术人员确定的具体值的可接受的偏差范围内，例如“近似”能意味着在一个或更多个标准偏差内，或者在所述及的值的±30％、±20％、±10％、±5％之内。
可以理解的是，第二无机钝化层105的制备过程中的氢存在经第一无机钝化层104进入有源层1021的可能性，而第一无机钝化层104上方的第一极 1022和第二极1023可较好地阻挡氢进入有源层1021，因此，位于第一极1022和第二极1023之间区域的有源层1021(即有源层1021的中心区域)可能被导体化，而被第一极1022和第二极1023覆盖的有源层1021则仍处于半导体状态。具体地，如图1所示，L A区域的有源层1021可能处于导体状态，L B区域的有源层1021则仍处于半导体状态，也就是说，沟道区形成了在两个L B区域呈对称分布的双胞胎沟道。在实际工作过程中，真正影响迁移率的为L B区域的载流子浓度，即沟道的有效长度L eff为2L B。相较于常规技术中沟道长度为2L B的单一沟道，长度为L B的双胞胎沟道，有效增加了沟道载流子浓度，提高了晶体管102的迁移率和工作电流I on。再者，如图2所示，L’ A区域的有源层1021可能处于导体状态，L’ B区域的有源层1021则仍处于半导体状态，也就是说，通过设置双栅极形成了在两个L’ B区域呈对称分布的双胞胎沟道。在实际工作过程中，真正影响迁移率的为L’ B区域的载流子浓度，即沟道的有效长度L eff为2L’ B。相较于图1所示沟道有效长度为2L B的双胞胎沟道，可进一步增加沟道载流子浓度，提高晶体管102的迁移率和工作电流I on。
可选地，在本公开实施例提供的上述阵列基板中，如图3所示，晶体管102，包括：位于有源层1021与衬底基板101之间的栅极1024，以及位于有源层1021背离衬底基板101一侧的第一极1022和第二极1023；
第一无机钝化层104位于第一极1022和第二极1023所在层与第二无机钝化层105之间，并与第一极1022、第二极1023和有源层1021直接接触；
栅极1024在衬底基板101上的正投影覆盖有源层1021的正投影；
第一极1022与有源层1021直接接触，第二极1023与有源层1021和像素电极103直接接触。
在图3所示结构的阵列基板中，在制备覆盖晶体管102且在像素电极103的位置具有镂空区域的第一无机钝化层104之后，且在制备第二无机钝化层105之前，以第一无机钝化层104为掩膜板，通过离子(Plasma)对镂空区域的半导体材料层进行导体化处理，实现像素电极103的导电性能，同时节省了相关技术中单独制作像素电极103的掩膜板。
可选地，在本公开实施例提供的上述阵列基板中，如图4所示，晶体管102包括：位于有源层1021与衬底基板101之间的第一极1022和第二极1023，以及位于有源层1021与第一无机钝化层104之间的栅极1024；
栅极1024在衬底基板101上的正投影与有源层1021的正投影相互重合；
有源层1021覆盖第一极1022和第二极1023，且有源层1021的中心区域的底部与第一极1022和第二极1023的底部平齐；
第二极1023与像素电极103直接相连。
针对图4所示结构的阵列基板，具有镂空区域的第一无机钝化层104可作为掩膜板，实现对镂空区域的半导体材料层的导体化处理，保证了像素电极103的导电性能，因此节省了相关技术中单独制作像素电极103的掩膜板。并且，由于像素电极103的导电性能较好，因此像素电极103与第二极1023之间的接触电阻较小，保证了像素电极103与第二极1023的良好电连接，同时还节省了相关技术中单独制作像素电极103的掩膜板。
可选地，在本公开实施例提供的上述阵列基板中，如图5所示，晶体管102，还包括：位于有源层1021与衬底基板101之间的栅极1024，以及位于有源层1021与第一无机钝化层104之间的第一极1022和第二极1023；
第一无机钝化层104覆盖第一极1022、第二极1023、有源层1021和像素电极103；
栅极1024在衬底基板101上的正投影覆盖有源层1021的正投影；
第一极1022与有源层1021直接接触，第二极1023与有源层1021和像素电极104直接接触。
由图5可见，第一无机钝化层104和第二无机钝化层105的图案一致，因此，在实际制作过程中，可依次沉积第一无机薄膜层和第二无机薄膜层，并采用同一个掩膜板进行一次构图工艺来形成贯穿第一无机钝化层104和第二无机钝化层105的过孔图案。如此，则可节省一掩膜板。
可选地，在本公开实施例提供的上述阵列基板中，如图1至图5所示，还包括：位于第二无机钝化层105背离衬底基板101一侧的条状公共电极106， 以及与晶体管102的栅极1024同层设置的公共电压线107；
条状公共电极106在衬底基板101上的正投影覆盖像素电极103的正投影，且条状公共电极106通过贯穿栅极1024与条状公共电极106之间各层的过孔与公共电压线107电连接。
需要说明的是，在本公开中，“同层设置”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板。根据特定图形的不同，一次构图工艺可能包括多次曝光、显或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。因此，栅极1024与公共电压线107同层设置，可减少掩膜工艺，提高生产效率，实现轻薄化设计。
一般地，在本公开实施例提供的上述阵列基板中，如图1至图5所示，还可以包括位于栅极1024与有源层1021之间的栅绝缘层108，与栅极1024同层设置的栅线(图中未示出)，以及与第一极1022、第二极1023同层设置的数据线(图中未示出)。其中，栅绝缘层108、栅线和数据线的设置方式和制作方法与相关技术相同，在此不做限定。
基于同一发明构思，本公开实施例提供了一种阵列基板的制作方法，由于该制作方法解决问题的原理与上述阵列基板解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见本公开实施例提供的上述阵列基板的实施，重复之处不再赘述。
具体地，本公开实施例提供的一种阵列基板的制作方法，包括：
提供一衬底基板；
在衬底基板上形成晶体管、第一无机钝化层和第二无机钝化层；
其中，形成晶体管的步骤包括：
在衬底基板上形成半导体材料层，半导体材料层包括第一部分和第二部分，第一部分用于形成有源层，第二部分用于形成像素电极，第一部分在衬底基板上的正投影与有源层相互重合，第二部分在衬底基板上的正投影与有 源层互不交叠；
对第二部分进行导体化，形成像素电极；
第二无机钝化层的至少部分区域与第一无机钝化层直接接触。
可选地，在本公开实施例提供的上述制作方法中，在执行步骤在衬底基板上形成半导体材料层之后，且在执行步骤对第二部分进行导体化，形成像素电极之前，还可以执行以下步骤：
形成覆盖有源层的光刻胶层，并以光刻胶层为掩膜板，对半导体材料层所含第二部分进行初步导体化。
当半导体材料层由IGZO等氧化物制作时，在半导体材料层中存在较多的氧，对半导体材料层所含用于制作像素电极的第二部分进行初步导体化，可以使氧的数量大大减少，实现用于制作像素电极的第二部分的导电性。后续沉积材料为氧化硅的第一无机钝化层的过程中，氧化硅的氧会进入初步导体化后的半导体材料层，产生去导体化效应，影响像素电极的导电性。基于此，通过去除像素电极上方的氧化硅，形成第一无机钝化层的镂空区域，从而可以第一无机钝化层为掩膜板，实现对像素电极的二次导体化，解决氧化硅造成的去导体化问题，提升像素电极的导电性。
可选地，在本公开实施例提供的上述制作方法中，形成第一无机钝化层，具体可以通过以下方式进行实现：
形成在第二部分的位置具有镂空区域的第一无机钝化层。
可选地，在本公开实施例提供的上述制作方法中，对第二部分进行导体化，形成所述像素电极，具体可以包括：
以具有镂空区域的第一无机钝化层为掩膜板，对该半导体材料层所含第二部分进行导体化，形成像素电极。
需要说明的是，在本发明实施例提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如， 在显影之后和刻蚀之前还可以包括后烘工艺。
其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
为更好地理解本公开实施例提供的上述制作方法，以下将对图1至图5所示的阵列基板的制作过程进行详细描述。
具体地，图1所示阵列基板的制作过程如下：
在衬底基板101上一次构图形成栅极1024和公共电压线107，如图6所示；
依次沉积栅绝缘层108和半导体材料层，并对该半导体材料层进行构图，获得用于形成有源层1021的第一部分、以及用于形成像素电极103的第二部分，第二部分在衬底基板101上的正投影与有源层1021的正投影互不交叠，如图7所示；
通过构图工艺形成第一无机钝化层104，该第一无机钝化层104在上述半导体材料层的第二部分位置处具有镂空区域，以第一无机钝化层104为掩膜板，实现对半导体材料层所含用于形成像素电极103的第二部分的导体化处理，保证像素电极103的导电性，至此完成了像素电极103的制作，如图8所示；
通过构图工艺形成第一极1022和第二极1023，第二极1023与像素电极103直接相连，至此完成了晶体管102的制作，如图9所示；
沉积用于制作第二无机钝化层105的薄膜材料层，并在公共电压线107的位置形成贯穿第一无机钝化层104、第二无机钝化层105和栅绝缘层108的过孔，如图10所示；
形成在过孔处与公共电压线107电连接的条状公共电极106，该条状公共电极106在衬底基板101上的正投影覆盖像素电极103的正投影，如图1所 示。
至此，完成了图1所示阵列基板的制作。
具体地，图2所示阵列基板的制作过程如下：
在衬底基板101上一次构图形成两个栅极1024和公共电压线107，如图11所示；
依次沉积栅绝缘层108和半导体材料层，并对该半导体材料层进行构图，获得用于形成有源层1021的第一部分，以及用于形成像素电极103的第二部分，第二部分在衬底基板101上的正投影与有源层1021的正投影互不交叠，如图12所示；
通过构图工艺形成在第一无机钝化层104，该第一无机钝化层104在上述半导体材料层的第二部分位置处具有镂空区域，以第一无机钝化层104为掩膜板，实现对半导体材料层所含用于形成像素电极103的第二部分的导体化处理，保证像素电极103的导电性，至此完成了像素电极103的制作，如图13所示；
通过构图工艺形成第一极1022和第二极1023，第二极1023与像素电极103直接相连，至此完成了晶体管102的制作，如图14所示；
沉积用于制作第二无机钝化层105的薄膜材料层，并在公共电压线107的位置形成贯穿第一无机钝化层104、第二无机钝化层105和栅绝缘层108的过孔，如图15所示；
形成在过孔处与公共电压线107电连接的条状公共电极106，该条状公共电极106在衬底基板101上的正投影覆盖像素电极103的正投影，如图2所示。
至此，完成了图2所示阵列基板的制作。
具体地，图3所示阵列基板的制作过程如下：
在衬底基板101上一次构图形成栅极1024和公共电压线107，如图6所示；
依次沉积栅绝缘层108和半导体材料层，并对该半导体材料层进行构图， 获得用于形成有源层1021的第一部分、以及用于形成像素电极103的第二部分，第二部分在衬底基板101上的正投影与有源层1021的正投影互不交叠，如图7所示；
通过构图工艺形成第一极1022和第二极1023，第二极1023与像素电极103直接相连，至此完成了晶体管102的制作，如图16所示；
通过构图工艺形成第一无机钝化层104，该第一无机钝化层104在上述半导体材料层的第二部分位置处具有镂空区域，以第一无机钝化层104为掩膜板，实现对半导体材料层所含用于形成像素电极103的第二部分的导体化处理，保证像素电极103的导电性，至此完成了像素电极103的制作，如图17所示；
沉积用于制作第二无机钝化层105的薄膜材料层，并在公共电压线107的位置形成贯穿第一无机钝化层104、第二无机钝化层105和栅绝缘层108的过孔，如图18所示；
形成在过孔处与公共电压线107电连接的条状公共电极106，该条状公共电极106在衬底基板101上的正投影覆盖像素电极103的正投影，如图3所示。
至此，完成了图3所示阵列基板的制作。
具体地，图4所示阵列基板的制作过程如下：
在衬底基板101上一次构图形成第一极1022和第二极1023，如图19所示；
沉积半导体材料层，并对该半导体材料层进行构图，获得用于形成有源层1021的第一部分、以及用于形成像素电极103的第二部分，第二部分在衬底基板101上的正投影与有源层1021的正投影互不交叠，如图20所示；
通过构图工艺形成在有源层1021位置处的光刻胶层109，并以光刻胶层109为掩膜板，对半导体材料层所含用于形成像素电极103的第二分部进行初步导体化处理，实现像素电极103的导电性，如图21所示；
通过构图工艺形成栅极1024和公共电压线107，至此完成了晶体管102 的制作，如图22所示；
通过构图工艺形成第一无机钝化层104，该第一无机钝化层104在上述半导体材料层的第二部分位置处具有镂空区域的，以第一无机钝化层104为掩膜板，实现对半导体材料层所含用于形成像素电极103的第二部分的再次导体化处理，以避免第一无机钝化层104的去导体化作用，保证像素电极103的导电性，至此完成了像素电极103的制作，如图23所示；
沉积用于制作第二无机钝化层105的薄膜材料层，并在公共电压线107的位置形成贯穿第一无机钝化层104和第二无机钝化层105的过孔，如图24所示；
形成在过孔处与公共电压线107电连接的条状公共电极106，该条状公共电极106在衬底基板101上的正投影覆盖像素电极103的正投影，如图4所示。
至此，完成了图4所示阵列基板的制作。
具体地，图5所示阵列基板的制作过程如下：
在衬底基板101上一次构图形成栅极1024和公共电压线107，如图6所示；
依次沉积栅绝缘层108和半导体材料层，并对该半导体材料层进行构图，获得用于形成有源层1021的第一部分、以及用于形成像素电极103的第二部分，第二部分在衬底基板101上的正投影与有源层1021的正投影互不交叠，如图7所示；
通过构图工艺形成在有源层1021位置处的光刻胶层109，并以光刻胶层109为掩膜板，对半导体材料层所含用于形成像素电极103的第二部分进行导体化处理，实现像素电极103的导电性，至此完成了像素电极103的制作，如图25所示；
通过构图工艺形成第一极1022和第二极1023，第二极1023与像素电极103直接相连，至此完成了晶体管102的制作，如图16所示；
依次沉积用于制作第一无机钝化层104的第一无机薄膜层和用于制作第 二无机钝化层105的第二无机薄膜层，并通过一次构图工艺形成在公共电压线107的位置贯穿第一无机钝化层104和第二无机钝化层105的过孔，如图26所示；
形成在过孔处与公共电压线107电连接的条状公共电极106，条状公共电极106在衬底基板101上的正投影覆盖像素电极103的正投影，如图5所示。
至此，完成了图5所示阵列基板的制作。
在本公开实施例提供的上述阵列基板及其制作方法中，可根据实际产品对晶体管稳定性的要求，来调节第一无机钝化层和第二无机钝化层的厚度，使得第一无机钝化层和第二无机钝化层兼具相关技术中树脂层的阻水、阻氢和平坦化的功能，从而无需设置树脂层，规避了树脂层在加热固化过程中的交联反应生成物、溶剂、水等以Outgas形式产出，且减少了掩膜板数量。另外，在本公开中采用同一半导体材料层，通过一次构图工艺形成了用于形成有源层的第一部分和用于形成像素电极的第二部分，之后对半导体材料层所含第二部分进行导体化，相应的半导体材料层即可作为像素电极。如此设置，避免了单独设置像素电极的膜层，节省了原料成本，实现了产品轻薄化设计。在一些实施例中，还节省了制作像素电极的掩膜板。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    晶体管，位于所述衬底基板之上，所述晶体管包括有源层，所述有源层的材料为半导体材料；
    像素电极，与所述有源层同层设置，所述像素电极在所述衬底基板上的正投影与所述有源层的正投影互不交叠，且所述像素电极的材料为导体化的所述半导体材料；
    第一无机钝化层，位于所述像素电极背离所述衬底基板的一侧；
    第二无机钝化层，位于所述第一无机钝化层背离所述衬底基板的一侧，所述第二无机钝化层的至少部分区域与所述第一无机钝化层直接接触。
  2. 如权利要求1所述的阵列基板，其中，所述第一无机钝化层具有镂空区域，所述第二无机钝化层覆盖所述像素电极且在所述镂空区域处与所述像素电极直接接触。
  3. 如权利要求2所述的阵列基板，其中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的栅极，以及位于所述有源层背离所述衬底基板一侧的第一极和第二极；
    所述第一无机钝化层位于所述第一极和所述第二极所在层与所述有源层之间；
    所述栅极在所述衬底基板上的正投影位于所述有源层的正投影内；
    所述第一极在所述衬底基板上的正投影与所述第一无机钝化层的正投影部分交叠，所述第一极包括与所述第一无机钝化层直接接触的部分、以及与所述有源层直接接触的部分；
    所述第二极在所述衬底基板上的正投影与所述第一无机钝化层的正投影部分交叠，所述第二极包括与所述第一无机钝化层直接接触的部分、与所述有源层直接接触的部分、以及与所述像素电极直接接触的部分。
  4. 如权利要求3所述的阵列基板，其中，所述栅极为一个，所述栅极在所述衬底基板上的正投影与所述第一无机钝化层中直接接触所述第一极、所述第二极和所述有源层的区域相互重合，所述栅极的边界与所述第一极或所述第二极临近所述有源层的中心区域的边界之间具有第一距离；
    或者，所述栅极为两个，所述栅极在所述衬底基板上的正投影与所述第一无机钝化层中直接接触所述第一极和所述第二极的区域相互重合，所述栅极远离所述有源层的中心区域的边界与所述第一极或所述第二极临近所述有源层的中心区域的边界之间具有第二距离；
    所述第一距离是所述第二距离的二倍。
  5. 如权利要求2所述的阵列基板，其中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的栅极，以及位于所述有源层背离所述衬底基板一侧的第一极和第二极；
    所述第一无机钝化层位于所述第一极和所述第二极所在层与所述第二无机钝化层之间，并与所述第一极、所述第二极和所述有源层；
    所述栅极在所述衬底基板上的正投影覆盖所述有源层的正投影；
    所述第一极与所述有源层直接接触，所述第二极与所述有源层和所述像素电极直接接触。
  6. 如权利要求2所述的阵列基板，其中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的第一极和第二极，以及位于所述有源层与所述第一无机钝化层之间的栅极；
    所述栅极在所述衬底基板上的正投影与所述有源层的正投影相互重合；
    所述有源层覆盖所述第一极和所述第二极，且所述有源层的中心区域的底部与所述第一极和所述第二极的底部平齐；
    所述第二极与所述像素电极直接相连。
  7. 如权利要求1所述的阵列基板，其中，所述晶体管，还包括：位于所述有源层与所述衬底基板之间的栅极，以及位于所述有源层与所述第一无机钝化层之间的第一极和第二极；
    所述第一无机钝化层覆盖所述第一极、所述第二极、所述有源层和所述像素电极；
    所述栅极在所述衬底基板上的正投影覆盖所述有源层的正投影；
    所述第一极与所述有源层直接接触，所述第二极与所述有源层和所述像素电极直接接触。
  8. 如权利要求1-7任一项所述的阵列基板，其中，还包括：位于所述第二无机钝化层背离所述衬底基板一侧的条状公共电极，以及与所述晶体管的栅极同层设置的公共电压线；
    所述条状公共电极在所述衬底基板上的正投影覆盖所述像素电极的正投影，且所述条状公共电极通过贯穿所述栅极与所述条状公共电极之间各层的过孔与所述公共电压线电连接。
  9. 一种阵列基板的制作方法，其中，包括：
    提供一衬底基板；
    所述衬底基板上形成晶体管、第一无机钝化层和第二无机钝化层；
    其中，所述形成晶体管的步骤包括：
    在所述衬底基板上形成半导体材料层，所述半导体材料层包括第一部分和第二部分，所述第一部分用于形成有源层，所述第二部分用于形成像素电极，所述第一部分在所述衬底基板上的正投影与所述有源层相互重合，所述第二部分在所述衬底基板上的正投影与所述有源层互不交叠；
    对所述第二部分进行导体化，形成所述像素电极；
    所述第二无机钝化层的至少部分区域与所述第一无机钝化层直接接触。
  10. 如权利要求9所述的制作方法，其中，在所述衬底基板上形成半导体材料层之后，且在所述对所述第二部分进行导体化，形成所述像素电极之前，还包括：
    形成覆盖所述有源层的光刻胶层，并以所述光刻胶层为掩膜板，对所述半导体材料层所含所述第二部分进行初步导体化。
  11. 如权利要求9或10所述的制作方法，其中，所述形成所述第一无机 钝化层，具体包括：
    形成在所述第二部分的位置具有镂空区域的所述第一无机钝化层。
  12. 如权利要求11所述的制作方法，其中，所述对所述第二部分进行导体化，形成所述像素电极，具体包括：
    以具有镂空区域的所述第一无机钝化层为掩膜板，对所述第二部分进行导体化，形成所述像素电极。
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