WO2018035973A1 - 阵列基板、液晶显示面板以及制造方法 - Google Patents

阵列基板、液晶显示面板以及制造方法 Download PDF

Info

Publication number
WO2018035973A1
WO2018035973A1 PCT/CN2016/104606 CN2016104606W WO2018035973A1 WO 2018035973 A1 WO2018035973 A1 WO 2018035973A1 CN 2016104606 W CN2016104606 W CN 2016104606W WO 2018035973 A1 WO2018035973 A1 WO 2018035973A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
pattern
contact hole
drain
oxide semiconductor
Prior art date
Application number
PCT/CN2016/104606
Other languages
English (en)
French (fr)
Inventor
谢应涛
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/322,253 priority Critical patent/US10114259B2/en
Publication of WO2018035973A1 publication Critical patent/WO2018035973A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/06—Materials and properties dopant
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate, a liquid crystal display panel, and a manufacturing method.
  • Oxide semiconductor TFTs have advantages such as high mobility and large-area production, and are gradually becoming a strong competitor for next-generation display technologies.
  • oxide semiconductor TFTs are sensitive to light and require additional light shielding layers to reduce the effect of illumination on device performance stability.
  • an additional mask step is required to increase the light shielding layer, and therefore, the entire device generally requires eight mask steps.
  • the technical problem to be solved by the present invention is to provide an array substrate, a liquid crystal display panel, and a manufacturing method, which can reduce the number of three masks and reduce the production cost.
  • an array substrate including:
  • the data line layer and the light shielding layer are located in the same layer, and are respectively formed on the substrate at intervals, and the materials of the light shielding layer and the data line layer are both metal materials;
  • a first insulating layer covering the substrate, the data line layer and the light shielding layer
  • a source layer, a drain layer, an oxide semiconductor material layer, and a common electrode layer are respectively formed on the first insulating layer, wherein the source layer and the drain layer are in close proximity to and located in the oxide semiconductor
  • the common electrode layer is spaced apart from the drain layer at both ends of the material layer, and the source layer, the drain layer, and the common electrode layer are formed by doping the oxide semiconductor material.
  • the oxide semiconductor material layer can completely avoid the influence of light under the shielding effect of the light shielding layer;
  • An insulating interconnection layer covering the first insulating layer, the source layer, the gate layer, the drain layer, and the common electrode layer, and forming a through-hole in the interconnect layer a first contact hole, a second contact hole, and a third contact hole of the interconnect layer, one end of the first contact hole extending through the first insulating layer and connected to the data line layer, the second contact One end of the hole is connected to the source layer, and one end of the third contact hole is connected to the drain layer, wherein materials filled in the first contact hole, the second contact hole and the third contact hole are transparent Electrode material;
  • a transparent electrode material layer and a pixel electrode layer respectively formed on the interconnect layer the materials of which are transparent electrode materials, wherein the transparent electrode material layer and the other end of the first contact hole and the The other ends of the second contact holes are connected such that the source layer is electrically connected to the data line layer through the second contact hole, the transparent electrode material layer and the first contact hole,
  • the pixel electrode layer is connected to the other end of the third contact hole to achieve an electrical connection between the pixel electrode layer and the drain layer.
  • the common electrode layer is divided into a plurality.
  • the common electrode layer is a whole.
  • the doping treatment is H 2 , Ar or NH 3 plasma treatment.
  • a liquid crystal display panel including:
  • the data line layer and the light shielding layer are located in the same layer, and are respectively formed on the substrate at intervals, and the materials of the light shielding layer and the data line layer are both metal materials;
  • a first insulating layer covering the substrate, the data line layer and the light shielding layer
  • a source layer, a drain layer, an oxide semiconductor material layer, and a common electrode layer are respectively formed on the first insulating layer, wherein the source layer and the drain layer are in close proximity to and located in the oxide semiconductor
  • the common electrode layer is spaced apart from the drain layer at both ends of the material layer, and the source layer, the drain layer, and the common electrode layer are formed by doping the oxide semiconductor material.
  • the oxide semiconductor material layer can completely avoid the influence of light under the shielding effect of the light shielding layer;
  • An insulating interconnection layer covering the first insulating layer, the source layer, the gate layer, the drain layer, and the common electrode layer, and forming a through-hole in the interconnect layer a first contact hole, a second contact hole, and a third contact hole of the interconnect layer, one end of the first contact hole extending through the first insulating layer and connected to the data line layer, the second contact One end of the hole is connected to the source layer, and one end of the third contact hole is connected to the drain layer, wherein materials filled in the first contact hole, the second contact hole and the third contact hole are transparent Electrode material;
  • a transparent electrode material layer and a pixel electrode layer respectively formed on the interconnect layer the materials of which are transparent electrode materials, wherein the transparent electrode material layer and the other end of the first contact hole and the The other ends of the second contact holes are connected such that the source layer is electrically connected to the data line layer through the second contact hole, the transparent electrode material layer and the first contact hole, a pixel electrode layer is connected to the other end of the third contact hole to achieve an electrical connection between the pixel electrode layer and the drain layer;
  • the liquid crystal layer is interposed between the first substrate and the second substrate.
  • the common electrode layer is divided into a plurality.
  • the common electrode layer is a monolith.
  • the doping treatment is H 2 , Ar or NH 3 plasma treatment.
  • another technical solution adopted by the present invention is to provide a method for manufacturing an array substrate, comprising: exposing and developing a metal material deposited on a substrate by using a first photomask at a time, respectively obtaining The same layer and spaced data line pattern and light shielding layer pattern;
  • the common electrode pattern Doping the source pattern, the drain pattern, and the common electrode pattern that are not protected by the second insulating layer pattern and the gate pattern, such that the source pattern and the drain pattern And a material of the common electrode pattern is changed from the oxide semiconductor material to a conductor material, and the source pattern and the drain pattern are in close proximity and located at both ends of the oxide semiconductor material layer pattern, the common The electrode pattern is spaced apart from the drain pattern;
  • the interconnecting layer is exposed and developed, and a first contact hole, a second contact hole and a third contact hole penetrating through the interconnect layer are respectively formed in the interconnect layer, and one end of the first contact hole extends and penetrates the first
  • An insulating layer pattern is connected to the data line pattern, one end of the second contact hole is connected to the source pattern, and one end of the third contact hole is connected to the drain pattern;
  • a transparent electrode material layer on the interconnect layer Forming a transparent electrode material layer on the interconnect layer, and filling the transparent electrode material with the first contact hole, the second contact hole, and the third contact hole, and using the fifth mask to directly face the transparent electrode
  • the material layer is subjected to exposure and development to obtain a transparent electrode material layer pattern and a pixel electrode pattern, respectively, and the transparent electrode material layer pattern is respectively connected to the other end of the first contact hole and the other end of the second contact hole, thereby
  • the source pattern is electrically connected to the data line pattern through the second contact hole, the transparent electrode material layer pattern, and the first contact hole, the pixel electrode pattern and the third contact hole Connecting the other end to achieve an electrical connection between the pixel electrode pattern and the drain pattern;
  • the common electrode pattern is divided into a plurality of parts; or, the common electrode pattern is one whole piece.
  • the doping treatment is H 2 , Ar or NH 3 plasma treatment.
  • the invention has the beneficial effects that the present invention is different in the prior art, and the data layer and the light shielding layer are designed in the same layer, and the source layer, the drain layer, the oxide semiconductor material layer and the common electrode layer are further disposed.
  • the source layer, the drain layer, and the common electrode layer are formed in the same layer, and the source layer, the drain layer, and the common electrode layer are formed by doping the oxide semiconductor material to improve the conductivity thereof.
  • the material can be electrically conductive. In this way, the process of reducing the total of three masks can be reduced compared with the prior art, and only five mask processes are required, which greatly reduces the number of masks in the process, thereby greatly reducing the production cost.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • FIG. 3 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • FIG. 4 is a flow chart showing an embodiment of a method for fabricating an array substrate of the present invention.
  • FIG. 5 is a schematic view showing a preparation process of the array substrate of the present invention.
  • Fig. 6 is a schematic view showing another preparation process of the method for fabricating the array substrate of the present invention.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of two embodiments of an array substrate according to the present invention.
  • the array substrate includes: a substrate 1, a data line layer 2 and a light shielding layer 3, a first insulating layer 4, and a source.
  • the data line layer 2 and the light shielding layer 3 are located in the same layer, and are respectively formed on the substrate 1 at intervals.
  • the materials of the light shielding layer 3 and the data line layer 2 are all metal materials; that is, and the prior art.
  • the difference is that the data line layer 2 and the light shielding layer 3 are designed in the same layer in this application, and in this way, the process of reducing the mask can be reduced compared with the prior art.
  • the first insulating layer 4 covers the substrate 1, the data line layer 2 and the light shielding layer 3; the first insulating layer serves as a buffer layer, and the material thereof is an insulating material, for example, may be a SiOx film.
  • the source layer 5, the drain layer 6, the oxide semiconductor material layer 7, and the common electrode layer 8, respectively, are formed on the first insulating layer 4, wherein the source layer 5 and the drain layer 6 are in close proximity to and located in the oxide semiconductor material. At both ends of the layer 7, the common electrode layer 8 and the drain layer 6 are spaced apart, and the source layer 5, the drain layer 6 and the common electrode layer 8 are formed by doping the oxide semiconductor material, and the oxide semiconductor material layer is formed. 7 Under the shielding effect of the light shielding layer 3, the influence of light can be completely avoided; that is, the source layer 5, the drain layer 6, the oxide semiconductor material layer 7, and the common electrode layer 8 are designed in the same layer.
  • the source layer 5, the drain layer 6, and the common electrode layer 8 since the materials of the source layer 5, the drain layer 6, and the common electrode layer 8 must be capable of conducting, in the present application, the source layer 5, the drain layer 6 and the common are formed by doping the oxide semiconductor material. Electrode layer 8.
  • the material of the source layer 5, the drain layer 6, and the common electrode layer 8 can be electrically conductive by converting the oxide semiconductor material into a conductor material of the doped oxide by doping treatment and improving the conductivity thereof. In a way, the process of reducing the reticle can be reduced compared to the prior art.
  • the basic principle of the oxide semiconductor material being turned into a conductor material after doping treatment may be: taking out oxygen atoms in the oxide semiconductor material, causing the oxygen atoms to react with other substances, thereby making the oxide
  • the semiconductor material becomes a conductor material by being trapped of oxygen atoms.
  • the manner of doping treatment includes, but is not limited to, plasma, UV illumination, metal oxidation, and the like.
  • the material of the interconnect layer 28 is SiNx
  • H 2 can take off oxygen atoms in the oxide semiconductor material and react by releasing hydrogen H 2 , thereby causing the oxide semiconductor material to become Conductor material.
  • the second insulating layer 9 is overlaid on the oxide semiconductor material layer 7; the material of the insulating layer is an insulating material, for example, may be a SiOx film.
  • the gate layer 10 is formed on the second insulating layer 9, the material of which is a metal material.
  • the insulating interconnection layer 11 covers the first insulating layer 4, the source layer 5, the gate layer 10, the drain layer 6, and the common electrode layer 8.
  • the first contact hole 111, the second contact hole 112, and the third contact hole 113 are formed in the interconnect layer 11, and the first end 1111 of the first contact hole 111 extends through the first insulating layer 4, and the data
  • the wire layer 2 is connected, one end 1121 of the second contact hole 112 is connected to the source layer 5, and one end 1131 of the third contact hole 113 is connected to the drain layer 6, wherein the first contact hole 111, the second contact hole 112, and the third
  • the material filled in the contact hole 113 is a transparent electrode material.
  • the transparent electrode material layer 12 and the pixel electrode layer 13 are respectively formed on the interconnect layer 11 with a material of a transparent electrode material, wherein the transparent electrode material layer 12 and the other end 1112 and the second of the first contact hole 111 are respectively The other end 1122 of the contact hole 112 is connected, so that the source layer 5 is electrically connected to the data line layer 2 through the second contact hole 112, the transparent electrode material layer 12 and the first contact hole 111, and the pixel electrode layer 13 and the third layer
  • the other end 1132 of the contact hole 113 is connected to realize an electrical connection between the pixel electrode layer 13 and the drain layer 6.
  • the source layer 5, the drain layer 6, the oxide semiconductor material layer 7, and the common electrode layer 8 are designed in the same layer, and
  • the source layer 5, the drain layer 6, and the common electrode layer 8 are formed by doping the oxide semiconductor material to improve the conductivity thereof to realize the source layer 5, the drain layer 6, and the common electrode layer 8.
  • the material can be electrically conductive. In this way, the process of reducing the total of three masks can be reduced compared with the prior art, and only five mask processes are required, which greatly reduces the number of masks in the process, thereby greatly reducing the production cost.
  • the common electrode layer 8 is divided into a plurality, as shown in FIG.
  • the common electrode layer 8 is a monolith, as shown in FIG.
  • the liquid crystal display panel 200 includes a first substrate 101, a second substrate 102 opposite to the first substrate 101, and a first substrate 101.
  • the liquid crystal layer 103 is disposed between the second substrate 102 and the second substrate 102.
  • the second substrate 102 is any one of the array substrates. For details of related content, refer to the above array substrate. Let me repeat.
  • the present invention also provides a method for fabricating an array substrate, the method comprising:
  • Step S101 Exposing and developing the metal material deposited on the substrate by using the first photomask to obtain the data line pattern and the light shielding layer pattern in the same layer and spaced apart, respectively.
  • FIG. 5 is a schematic diagram of a preparation process of the array substrate of the present invention
  • FIG. 6 is a schematic diagram of another preparation process of the method for fabricating the array substrate of the present invention.
  • step 1 a layer of metal material is first deposited on the substrate 1, and the data line pattern 2 and the light shield pattern 3 can be simultaneously constructed by a standard photolithography process using the first mask.
  • the deposition of the metal material on the substrate is performed based on a physical vapor deposition (PVD) method.
  • PVD physical vapor deposition
  • Step S102 sequentially forming a first insulating layer and an oxide semiconductor material layer over the data line pattern and the light shielding layer pattern, and performing the oxide semiconductor material layer deposited on the first insulating layer at one time by using the second photomask. Exposure development is performed to obtain a source pattern, a drain pattern, an oxide semiconductor material layer pattern, and a common electrode pattern, respectively, wherein the oxide semiconductor material layer pattern can be completely prevented from being affected by light under the light shielding effect of the light shielding layer pattern.
  • the first insulating layer covers the substrate, the data line pattern and the light shielding layer pattern, and the first insulating layer serves as a buffer layer, and the material thereof is an insulating material, for example, may be a SiOx film.
  • the step can be deposited by chemical vapor deposition (CVD).
  • an oxide semiconductor material is covered on the first insulating layer, and a desired source pattern, a drain pattern, and an oxide semiconductor material layer pattern are formed by a standard photolithography process using a second mask. And a common electrode pattern.
  • the material of the source pattern, the drain pattern, and the common electrode pattern is still an oxide semiconductor material. It is necessary to convert to a conductor material by the doping treatment of the following steps.
  • depositing a layer of oxide semiconductor material can be deposited by PVD and then annealed in air, followed by standard photolithography processes to form the desired pattern described above.
  • a first insulating layer 4 and an oxide semiconductor material layer are sequentially formed on the data line pattern 2 and the light shielding layer pattern 3, and the first time is deposited on the first layer by using the second photomask.
  • the oxide semiconductor material layer on the insulating layer 4 is subjected to exposure and development to obtain a source pattern 5, a drain pattern 6, an oxide semiconductor material layer pattern 7, and a common electrode pattern 8, respectively.
  • the oxide semiconductor material layer pattern is located directly above the light shielding layer pattern, and under the light shielding effect of the light shielding layer pattern, the oxide semiconductor material layer pattern can completely avoid the influence of light.
  • Step S103 sequentially forming a second insulating layer and a gate layer over the source pattern, the drain pattern, the oxide semiconductor material layer pattern, and the common electrode pattern, and using the third mask to directly pair the second insulating layer and the gate
  • the electrode layer is subjected to exposure development to obtain a second insulating layer pattern and a gate pattern, respectively, and the second insulating layer pattern and the gate pattern are over the oxide semiconductor material layer pattern.
  • the second insulating layer covers the source pattern, the drain pattern, the oxide semiconductor material layer pattern, and the common electrode pattern, and the material thereof is an insulating material, for example, may be a SiOx film. In one embodiment, this step can be deposited by CVD.
  • a metal material on the second insulating layer as a gate layer for example, can be deposited by a PVD method, and the second insulating layer and the gate layer are exposed and developed at a time by using a third mask.
  • Step S104 Doping the source pattern, the drain pattern, and the common electrode pattern that are not protected by the second insulating layer pattern and the gate pattern, so that the source pattern, the drain pattern, and the material of the common electrode pattern are made of oxide
  • the semiconductor material becomes a conductor material, and the source pattern and the drain pattern are adjacent to each other and located at both ends of the oxide semiconductor material layer pattern, and the common electrode pattern is spaced apart from the drain pattern.
  • the basic principle of the oxide semiconductor material being turned into a conductor material after doping treatment may be: taking out oxygen atoms in the oxide semiconductor material, causing the oxygen atoms to react with other substances, thereby making the oxide
  • the semiconductor material becomes a conductor material by being trapped of oxygen atoms.
  • the manner of doping treatment here includes, but is not limited to, plasma, UV illumination, metal oxidation, and the like.
  • the material of the interconnect layer 28 is SiNx
  • H 2 can take off oxygen atoms in the oxide semiconductor material and react by releasing hydrogen H 2 , thereby causing the oxide semiconductor material to become Conductor material. That is to say, when the interconnection layer 28 is deposited, the source pattern, the drain pattern, and the common electrode pattern which are not protected by the second insulating layer pattern and the gate pattern are also doped at the same time.
  • step S104 It can be omitted and proceeds directly to step S105.
  • the second insulating layer pattern and the gate pattern are over the oxide semiconductor material layer pattern, and the oxide semiconductor material layer pattern can be protected, while the unprotected source pattern 5, the drain pattern 6 and the common electrode pattern 8 are exposed In addition, their materials are still oxide semiconductor materials.
  • the unprotected oxide semiconductor materials are doped, for example, by H 2 , Ar or NH 3 plasma treatment to increase the conductivity. Drain electrode and common electrode.
  • step 3 the material of the second insulating layer 9 and the material of the gate layer 10 are respectively deposited, and the channel oxide semiconductor material layer pattern 7 is formed by a self-alignment technique by using a third photomask. Then, the source 5, the drain 6, and the common electrode 8 are formed by plasma treatment.
  • Step S105 forming an insulating interconnection layer over the first insulating layer pattern, the source pattern, the gate pattern, the drain pattern, and the common electrode pattern, and performing exposure and development on the interconnection layer at a time by using the fourth photomask.
  • An insulating interlayer layer is overlying the first insulating layer pattern, the source pattern, the gate pattern, the drain pattern, and the common electrode pattern, and the material may be SiOx or SiNx and any order therebetween The combination.
  • the interconnect layer can be deposited by CVD.
  • a contact hole is opened to the interconnect layer by a standard photolithography process, and a first contact hole, a second contact hole, and a third contact hole are respectively obtained through the interconnect layer, and the first contact hole One end extends and penetrates through the first insulating layer pattern, and is connected to the data line pattern.
  • One end of the second contact hole is connected to the source pattern, and one end of the third contact hole is connected to the drain pattern.
  • Step S106 forming a transparent electrode material layer on the interconnection layer, and filling the transparent electrode material with the first contact hole, the second contact hole, and the third contact hole, and exposing and developing the transparent electrode material layer by using the fifth photomask at one time.
  • the material layer pattern and the first contact hole are electrically connected to the data line pattern, and the pixel electrode pattern is connected to the other end of the third contact hole to achieve an electrical connection between the pixel electrode pattern and the drain pattern.
  • a transparent electrode material on the interconnect layer such as an ITO film layer
  • the transparent electrode material also permeating and filling the first contact hole, the second contact hole and the third contact hole, and the data line is connected to the source electrode through the contact hole
  • the pixel electrode is interconnected with the drain electrode, and is patterned by a standard photolithography process using a fifth photomask to obtain a transparent electrode material layer pattern and a pixel electrode pattern.
  • the common electrode pattern is divided into a plurality, as shown in FIG. 6.
  • the common electrode pattern is a whole block, as shown in FIG.
  • the ILD layer 11 is deposited, and three contacts are formed by a photolithography process.
  • the holes 111, 112, 113 are then deposited with a transparent electrode material and patterned to form a transparent electrode material layer pattern 12 and a pixel electrode pattern 13.
  • the data line and the light shielding layer are designed in the same layer, and the source, the drain, the oxide semiconductor material and the common electrode are designed in the same layer, and the source, the drain and the common electrode are oxidized by the opposite side.
  • the material semiconductor material is formed by doping treatment, and the conductivity thereof is improved to realize the material of the source, the drain, and the common electrode. In this way, the process of reducing the three masks can be reduced compared with the prior art. It takes five mask processes to greatly reduce the number of masks in the process, which in turn greatly reduces production costs.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板、液晶显示面板以及制造方法，该阵列基板包括：将数据线层（2）和遮光层（3）设计在同一层，而且，将源极层（5）、漏极层（6）、氧化物半导体材料层（7）以及公共电极层（8）设计在同一层中，且源极层（5）、漏极层（6）以及公共电极层（8）是通过对氧化物半导体材料经过掺杂处理而形成，提高其导电率的方式来实现源极层（5）、漏极层（6）、公共电极层（8）的材料能够导电。通过上述方式，能够极大地减少制程中的光罩数目，进而使得生产成本大大降低。

Description

阵列基板、液晶显示面板以及制造方法 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板、液晶显示面板以及制造方法。
【背景技术】
氧化物半导体TFT(Oxide semiconductor TFT)具有高迁移率、大面积生产等优势，正逐渐成为下一代显示技术的有力竞争者。
但是，氧化物半导体TFT对光照较为敏感，需要增加额外的遮光层进而降低光照对器件性能稳定性的影响。现有技术中，氧化物半导体TFT液晶显示面板的制造过程中，为增加遮光层需要另外的光罩步骤，因此，整个器件一般需要8道光罩步骤。
上述制造工艺，由于光罩数目增加，花费较多，导致其生产成本上升，且制程比较繁琐。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板、液晶显示面板以及制造方法，能够减少3道光罩数目，降低生产成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括：
基板；
数据线层和遮光层，位于同一层中，且分别间隔地形成在所述基板上，所述遮光层和所述数据线层的材料均为金属材料；
第一绝缘层，覆盖在所述基板、所述数据线层和所述遮光层上；
源极层、漏极层、氧化物半导体材料层以及公共电极层，分别形成在所述第一绝缘层上，其中，所述源极层和所述漏极层紧邻并位于所述氧化物半导体材料层的两端，所述公共电极层与所述漏极层间隔设置，所述源极层、所述漏极层以及所述公共电极层通过对氧化物半导体材料经过掺杂处理而形成，所述氧化物半导体材料层在所述遮光层的遮光作用下，能够完全避免受到光线的影响；
第二绝缘层，覆盖在所述氧化物半导体材料层上；
栅极层，形成在所述第二绝缘层上，其材料为金属材料；
绝缘的互联层，覆盖在所述第一绝缘层、所述源极层、所述栅极层、所述漏极层以及所述公共电极层上，且在所述互联层中分别形成贯穿所述互联层的第一接触孔、第二接触孔以及第三接触孔，所述第一接触孔的一端延伸并贯穿所述第一绝缘层，与所述数据线层连接，所述第二接触孔的一端与所述源极层连接，所述第三接触孔的一端与所述漏极层连接，其中所述第一接触孔、第二接触孔以及第三接触孔中填充的材料为透明电极材料；
透明电极材料层和像素电极层，其分别间隔形成在所述互联层上，其材料均为透明电极材料，其中，所述透明电极材料层分别与所述第一接触孔的另一端和所述第二接触孔的另一端相连，从而使所述源极层通过所述第二接触孔、所述透明电极材料层和所述第一接触孔而电性连接至所述数据线层，所述像素电极层与所述第三接触孔的另一端相连，以实现所述像素电极层与所述漏极层之间的电性连接。
其中，所述公共电极层分成多个。
其中，所述公共电极层是一个整体。
其中，所述掺杂处理为H2、Ar或NH3等离子处理。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示面板，包括：
第一基板，
第二基板，与所述第一基板相对设置，其包括：
基板；
数据线层和遮光层，位于同一层中，且分别间隔地形成在所述基板上，所述遮光层和所述数据线层的材料均为金属材料；
第一绝缘层，覆盖在所述基板、所述数据线层和所述遮光层上；
源极层、漏极层、氧化物半导体材料层以及公共电极层，分别形成在所述第一绝缘层上，其中，所述源极层和所述漏极层紧邻并位于所述氧化物半导体材料层的两端，所述公共电极层与所述漏极层间隔设置，所述源极层、所述漏极层以及所述公共电极层通过对氧化物半导体材料经过掺杂处理而形成，所述氧化物半导体材料层在所述遮光层的遮光作用下，能够完全避免受到光线的影响；
第二绝缘层，覆盖在所述氧化物半导体材料层上；
栅极层，形成在所述第二绝缘层上，其材料为金属材料；
绝缘的互联层，覆盖在所述第一绝缘层、所述源极层、所述栅极层、所述漏极层以及所述公共电极层上，且在所述互联层中分别形成贯穿所述互联层的第一接触孔、第二接触孔以及第三接触孔，所述第一接触孔的一端延伸并贯穿所述第一绝缘层，与所述数据线层连接，所述第二接触孔的一端与所述源极层连接，所述第三接触孔的一端与所述漏极层连接，其中所述第一接触孔、第二接触孔以及第三接触孔中填充的材料为透明电极材料；
透明电极材料层和像素电极层，其分别间隔形成在所述互联层上，其材料均为透明电极材料，其中，所述透明电极材料层分别与所述第一接触孔的另一端和所述第二接触孔的另一端相连，从而使所述源极层通过所述第二接触孔、所述透明电极材料层和所述第一接触孔而电性连接至所述数据线层，所述像素电极层与所述第三接触孔的另一端相连，以实现所述像素电极层与所述漏极层之间的电性连接；
液晶层，夹设在所述第一基板和所述第二基板之间。
其中，所述公共电极层分成多个。
其中，所述公共电极层是一个整块。
其中，所述掺杂处理为H2、Ar或NH3等离子处理。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板的制造方法，包括：利用第一次光罩一次性对沉积在基板上的金属材料进行曝光显影，分别得到位于同一层且间隔的数据线图案和遮光层图案；
在所述数据线图案和遮光层图案之上依次形成第一绝缘层、氧化物半导体材料层，利用第二次光罩一次性对沉积在所述第一绝缘层之上的氧化物半导体材料层进行曝光显影，分别得到源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案，其中，所述氧化物半导体材料层图案在所述遮光层图案的遮光作用下，能够完全避免受到光线的影响；
在所述源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案之上依次形成第二绝缘层和栅极层，利用第三次光罩一次性对所述第二绝缘层和栅极层进行曝光显影，分别得到第二绝缘层图案和栅极图案，所述第二绝缘层图案和栅极图案位于所述氧化物半导体材料层图案之上；
对未被所述第二绝缘层图案和栅极图案保护的所述源极图案、所述漏极图案以及所述公共电极图案进行掺杂处理，使得所述源极图案、所述漏极图案以及所述公共电极图案的材料由所述氧化物半导体材料变为导体材料，且所述源极图案和所述漏极图案紧邻并位于所述氧化物半导体材料层图案的两端，所述公共电极图案与所述漏极图案间隔设置；
在所述第一绝缘层图案、所述源极图案、所述栅极图案、所述漏极图案以及所述公共电极图案之上形成绝缘的互联层，利用第四次光罩一次性对所述互联层进行曝光显影，在所述互联层中分别形成贯穿所述互联层的第一接触孔、第二接触孔以及第三接触孔，所述第一接触孔的一端延伸并贯穿所述第一绝缘层图案，与所述数据线图案连接，所述第二接触孔的一端与所述源极图案连接，所述第三接触孔的一端与所述漏极图案连接；
在所述互联层上形成透明电极材料层，且使所述透明电极材料充满所述第一接触孔、第二接触孔以及第三接触孔，利用第五次光罩一次性对所述透明电极材料层进行曝光显影，分别获得透明电极材料层图案和像素电极图案，所述透明电极材料层图案分别与所述第一接触孔的另一端和所述第二接触孔的另一端相连，从而使所述源极图案通过所述第二接触孔、所述透明电极材料层图案和所述第一接触孔而电性连接至所述数据线图案，所述像素电极图案与所述第三接触孔的另一端相连，以实现所述像素电极图案与所述漏极图案之间的电性连接；
其中，所述公共电极图案分成多个；或者，所述公共电极图案是一个整块。
其中，所述掺杂处理是H2、Ar或NH3等离子处理。
本发明的有益效果是：区别于现有技术的情况，本发明由于将数据线层和遮光层设计在同一层，而且，将源极层、漏极层、氧化物半导体材料层以及公共电极层设计在同一层中，且源极层、漏极层以及公共电极层通过对氧化物半导体材料经过掺杂处理而形成，提高其导电率的方式来实现源极层、漏极层、公共电极层的材料能够导电，通过这种方式，能够比现有技术总共减少三道光罩的过程，只需要5道光罩过程即可，极大地减少制程中的光罩数目，进而使得生产成本大大降低。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是本发明阵列基板另一实施方式的结构示意图；
图3是本发明液晶显示面板一实施方式的结构示意图；
图4是本发明阵列基板的制造方法一实施方式的流程图；
图5是本发明阵列基板的制造方法一制备流程示意图；
图6是本发明阵列基板的制造方法另一制备流程示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
参阅图1和图2，图1和图2是本发明阵列基板两个实施方式的结构示意图，该阵列基板包括：基板1，数据线层2和遮光层3，第一绝缘层4，源极层5、漏极层6、氧化物半导体材料层7以及公共电极层8，第二绝缘层9，栅极层10，互联层11，透明电极材料层12和像素电极层13。
其中，数据线层2和遮光层3，位于同一层中，且分别间隔地形成在基板1上，遮光层3和数据线层2的材料均为金属材料；也即是说，和现有技术不同的是，本申请中将数据线层2和遮光层3设计在同一层，通过这种方式，能够比现有技术减少一道光罩的过程。
第一绝缘层4覆盖在基板1、数据线层2和遮光层3上；该第一绝缘层作为缓冲层，其材料是绝缘材料，例如，可以是SiOx薄膜。
源极层5、漏极层6、氧化物半导体材料层7以及公共电极层8，分别形成在第一绝缘层4上，其中，源极层5和漏极层6紧邻并位于氧化物半导体材料层7的两端，公共电极层8与漏极层6间隔设置，源极层5、漏极层6以及公共电极层8通过对氧化物半导体材料经过掺杂处理而形成，氧化物半导体材料层7在遮光层3的遮光作用下，能够完全避免受到光线的影响；也即是说，源极层5、漏极层6、氧化物半导体材料层7以及公共电极层8设计在同一层中，且由于源极层5、漏极层6、公共电极层8的材料必须要能够导电，本申请中，通过对氧化物半导体材料经过掺杂处理而形成源极层5、漏极层6以及公共电极层8。其中通过掺杂处理将氧化物半导体材料转变为掺杂氧化物的导体材料，提高其导电率的方式来实现源极层5、漏极层6、公共电极层8的材料能够导电，通过这种方式，可以比现有技术减少二道光罩的过程。在一实施方式中，氧化物半导体材料经过掺杂处理后变成导体材料的基本原理可以是：将氧化物半导体材料中的氧原子夺取出来，使氧原子与其他物质发生反应，从而使得氧化物半导体 材料由于被夺取氧原子而变为导体材料。此处掺杂处理的方式包括但不限于：等离子体(plasma)、UV光照、金属氧化等方式。当然，如果互联层28的材料是SiNx，在沉积互联层28时，由于释放出氢气H2，H2可以夺取氧化物半导体材料中的氧原子，并发生反应，从而使氧化物半导体材料变成导体材料。
第二绝缘层9覆盖在氧化物半导体材料层7上；该绝缘层的材料是绝缘材料，例如，可以是SiOx薄膜。
栅极层10形成在第二绝缘层9上，其材料为金属材料。
绝缘的互联层11覆盖在第一绝缘层4、源极层5、栅极层10、漏极层6以及公共电极层8上。且在互联层11中分别形成贯穿互联层11的第一接触孔111、第二接触孔112以及第三接触孔113，第一接触孔111的一端1111延伸并贯穿第一绝缘层4，与数据线层2连接，第二接触孔112的一端1121与源极层5连接，第三接触孔113的一端1131与漏极层6连接，其中第一接触孔111、第二接触孔112以及第三接触孔113中填充的材料为透明电极材料。
透明电极材料层12和像素电极层13，其分别间隔形成在互联层11上，其材料均为透明电极材料，其中，透明电极材料层12分别与第一接触孔111的另一端1112和第二接触孔112的另一端1122相连，从而使源极层5通过第二接触孔112、透明电极材料层12和第一接触孔111而电性连接至数据线层2，像素电极层13与第三接触孔113的另一端1132相连，以实现像素电极层13与漏极层6之间的电性连接。
本发明实施方式由于将数据线层2和遮光层3设计在同一层，而且，将源极层5、漏极层6、氧化物半导体材料层7以及公共电极层8设计在同一层中，且源极层5、漏极层6以及公共电极层8通过对氧化物半导体材料经过掺杂处理而形成，提高其导电率的方式来实现源极层5、漏极层6、公共电极层8的材料能够导电，通过这种方式，能够比现有技术总共减少三道光罩的过程，只需要5道光罩过程即可，极大地减少制程中的光罩数目，进而使得生产成本大大降低。
在一实施方式中，公共电极层8分成多个，如图2所示。
在另一实施方式中，公共电极层8是一个整块，如图1所示。
参见图3，图3是本发明液晶显示面板一实施方式的结构示意图，该液晶显示面板200包括：第一基板101、与第一基板101相对设置第二基板102以及夹设在第一基板101和第二基板102之间的液晶层103，其中，第二基板102为上述阵列基板中的任意一种，相关内容的详细说明请参见上述阵列基板，在此不 再赘叙。
参见图4，本发明还提供一种阵列基板的制造方法，该方法包括：
步骤S101：利用第一次光罩一次性对沉积在基板上的金属材料进行曝光显影，分别得到位于同一层且间隔的数据线图案和遮光层图案。
参见图5和图6，图5是本发明阵列基板的制造方法一制备流程示意图，图6是本发明阵列基板的制造方法另一制备流程示意图。步骤1，首先在基板1上沉积一层金属材料，利用第一次光罩，通过标准的光刻工艺，即可同时构建数据线图案2和遮光层(light shield)图案3。
在一实施方式中，在基板上沉积金属材料时，是基于物理气相沉积(Physical Vapor Deposition，简写PVD)方法进行的。
由于将数据线线图案和遮光层图案设计在同一层，通过这种方式，能够比现有技术减少一道光罩的过程。
步骤S102：在数据线图案和遮光层图案之上依次形成第一绝缘层、氧化物半导体材料层，利用第二次光罩一次性对沉积在第一绝缘层之上的氧化物半导体材料层进行曝光显影，分别得到源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案，其中，氧化物半导体材料层图案在遮光层图案的遮光作用下，能够完全避免受到光线的影响。
第一绝缘层覆盖在基板、数据线图案和遮光层图案之上，第一绝缘层作为缓冲层，其材料是绝缘材料，例如，可以是SiOx薄膜。在一实施方式中，该步骤可以通过化学气相沉积(Chemical Vapor Deposition，简写CVD)的方法进行沉积。
然后在第一绝缘层之上覆盖一层氧化物半导体材料，利用第二次光罩，通过标准的光刻工艺，即可形成所需的源极图案、漏极图案、氧化物半导体材料层图案及公共电极图案。当然，该步骤后，源极图案、漏极图案、及公共电极图案的材料依然还是氧化物半导体材料。需要经过下面步骤的掺杂处理转变为导体材料。在一实施方式中，沉积一层氧化物半导体材料可以通过PVD的方法进行沉积，然后在空气中退火，接着通过标准的光刻工艺形成所需的上述图案。
参见图5和图6，步骤2中，在数据线图案2和遮光层图案3之上依次形成第一绝缘层4、氧化物半导体材料层，利用第二次光罩一次性对沉积在第一绝缘层4之上的氧化物半导体材料层进行曝光显影，分别得到源极图案5、漏极图案6、氧化物半导体材料层图案7以及公共电极图案8。
其中，氧化物半导体材料层图案正好位于遮光层图案的垂直上方，且在遮光层图案的遮光作用下，氧化物半导体材料层图案能够完全避免受到光线的影响。
步骤S103：在源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案之上依次形成第二绝缘层和栅极层，利用第三次光罩一次性对第二绝缘层和栅极层进行曝光显影，分别得到第二绝缘层图案和栅极图案，第二绝缘层图案和栅极图案位于氧化物半导体材料层图案之上。
第二绝缘层覆盖在源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案之上，其材料是绝缘材料，例如，可以是SiOx薄膜。在一实施方式中，该步骤可以通过CVD的方法进行沉积。
然后在第二绝缘层之上再沉积一层金属材料，作为栅极层，例如，可以通过PVD的方法进行沉积，利用第三次光罩一次性对第二绝缘层和栅极层进行曝光显影，通过干蚀刻(dry etch)或者湿蚀刻(wet etch)等方式刻蚀未被光刻胶保护的栅极金属及其下的第二绝缘层，得到第二绝缘层图案和栅极图案，其中，第二绝缘层图案和栅极图案位于氧化物半导体材料层图案之上。
步骤S104：对未被第二绝缘层图案和栅极图案保护的源极图案、漏极图案以及公共电极图案进行掺杂处理，使得源极图案、漏极图案以及公共电极图案的材料由氧化物半导体材料变为导体材料，且源极图案和漏极图案紧邻并位于氧化物半导体材料层图案的两端，公共电极图案与漏极图案间隔设置。在一实施方式中，氧化物半导体材料经过掺杂处理后变成导体材料的基本原理可以是：将氧化物半导体材料中的氧原子夺取出来，使氧原子与其他物质发生反应，从而使得氧化物半导体材料由于被夺取氧原子而变为导体材料。此处掺杂处理的方式包括但不限于：等离子体(plasma)、UV光照、金属氧化等方式。当然，如果互联层28的材料是SiNx，在沉积互联层28时，由于释放出氢气H2，H2可以夺取氧化物半导体材料中的氧原子，并发生反应，从而使氧化物半导体材料变成导体材料。也即是说，在沉积互联层28时，也是同时在对未被第二绝缘层图案和栅极图案保护的源极图案、漏极图案以及公共电极图案进行掺杂处理，此时，步骤S104可以省略，直接进入步骤S105。
第二绝缘层图案和栅极图案位于氧化物半导体材料层图案之上，可以对氧化物半导体材料层图案进行保护，而未受保护的源极图案5、漏极图案6以及公共电极图案8裸露在外，它们的材料依然还是氧化物半导体材料，此时，对未 被保护的这些氧化物半导体材料进行掺杂处理，例如，进行H2、Ar或NH3等离子处理，使其导电率提高形成源漏电极和公共电极。
参见图5和图6，步骤3中，分别沉积第二绝缘层9的材料和栅极层10的材料，利用第三次光罩，通过自对准技术形成沟道氧化物半导体材料层图案7，然后通过等离子处理，形成源极5、漏极6以及公共电极8。
步骤S105：在第一绝缘层图案、源极图案、栅极图案、漏极图案以及公共电极图案之上形成绝缘的互联层，利用第四次光罩一次性对互联层进行曝光显影，在互联层中分别形成贯穿互联层的第一接触孔、第二接触孔以及第三接触孔，第一接触孔的一端延伸并贯穿第一绝缘层图案，与数据线图案连接，第二接触孔的一端与源极图案连接，第三接触孔的一端与漏极图案连接。
绝缘的互联层(interlayer deposition，简写ILD)覆盖在第一绝缘层图案、源极图案、栅极图案、漏极图案以及公共电极图案之上，其材料可为SiOx或SiNx及其两者任意顺序的组合。互联层可以采用CVD方法进行沉积。利用第四次光罩，基于标准的光刻工艺，对互联层开接触孔(contact hole)，分别获得贯穿互联层的第一接触孔、第二接触孔以及第三接触孔，第一接触孔的一端延伸并贯穿第一绝缘层图案，与数据线图案连接，第二接触孔的一端与源极图案连接，第三接触孔的一端与漏极图案连接。
步骤S106：在互联层上形成透明电极材料层，且使透明电极材料充满第一接触孔、第二接触孔以及第三接触孔，利用第五次光罩一次性对透明电极材料层进行曝光显影，分别获得透明电极材料层图案和像素电极图案，透明电极材料层图案分别与第一接触孔的另一端和第二接触孔的另一端相连，从而使源极图案通过第二接触孔、透明电极材料层图案和第一接触孔而电性连接至数据线图案，像素电极图案与第三接触孔的另一端相连，以实现像素电极图案与漏极图案之间的电性连接。
在互联层上沉积一层透明电极材料，例如ITO膜层，透明电极材料也渗透并充满第一接触孔、第二接触孔以及第三接触孔，通过接触孔实现数据线与源电极互联，以及像素电极与漏电极互联，并利用第五次光罩，通过标准光刻工艺进行图形化制备得到透明电极材料层图案和像素电极图案。
其中，公共电极图案分成多个，如图6所示。
其中，公共电极图案是一个整块，如图5所示。
参见图5和图6，步骤4中，沉积ILD层11，通过光刻工艺形成三个接触 孔111、112、113，接着沉积透明电极材料并图案化形成透明电极材料层图案12和像素电极图案13。
本发明实施方式由于将数据线和遮光层设计在同一层，而且，将源极、漏极、氧化物半导体材料以及公共电极设计在同一层中，且源极、漏极以及公共电极通过对氧化物半导体材料经过掺杂处理而形成，提高其导电率的方式来实现源极、漏极、公共电极的材料能够导电，通过这种方式，能够比现有技术总共减少三道光罩的过程，只需要5道光罩过程即可，极大地减少制程中的光罩数目，进而使得生产成本大大降低。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种阵列基板的制造方法，其中，所述方法包括：
    利用第一次光罩一次性对沉积在基板上的金属材料进行曝光显影，分别得到位于同一层且间隔的数据线图案和遮光层图案；
    在所述数据线图案和遮光层图案之上依次形成第一绝缘层、氧化物半导体材料层，利用第二次光罩一次性对沉积在所述第一绝缘层之上的氧化物半导体材料层进行曝光显影，分别得到源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案，其中，所述氧化物半导体材料层图案在所述遮光层图案的遮光作用下，能够完全避免受到光线的影响；
    在所述源极图案、漏极图案、氧化物半导体材料层图案以及公共电极图案之上依次形成第二绝缘层和栅极层，利用第三次光罩一次性对所述第二绝缘层和栅极层进行曝光显影，分别得到第二绝缘层图案和栅极图案，所述第二绝缘层图案和栅极图案位于所述氧化物半导体材料层图案之上；
    对未被所述第二绝缘层图案和栅极图案保护的所述源极图案、所述漏极图案以及所述公共电极图案进行掺杂处理，使得所述源极图案、所述漏极图案以及所述公共电极图案的材料由所述氧化物半导体材料变为导体材料，且所述源极图案和所述漏极图案紧邻并位于所述氧化物半导体材料层图案的两端，所述公共电极图案与所述漏极图案间隔设置；
    在所述第一绝缘层图案、所述源极图案、所述栅极图案、所述漏极图案以及所述公共电极图案之上形成绝缘的互联层，利用第四次光罩一次性对所述互联层进行曝光显影，在所述互联层中分别形成贯穿所述互联层的第一接触孔、第二接触孔以及第三接触孔，所述第一接触孔的一端延伸并贯穿所述第一绝缘层图案，与所述数据线图案连接，所述第二接触孔的一端与所述源极图案连接，所述第三接触孔的一端与所述漏极图案连接；
    在所述互联层上形成透明电极材料层，且使所述透明电极材料充满所述第一接触孔、第二接触孔以及第三接触孔，利用第五次光罩一次性对所述透明电极材料层进行曝光显影，分别获得透明电极材料层图案和像素电极图案，所述透明电极材料层图案分别与所述第一接触孔的另一端和所述第二接触孔的另一端相连，从而使所述源极图案通过所述第二接触孔、所述透明电极材料层图案和所述第一接触孔而电性连接至所述数据线图案，所述像素电极图案与所述第 三接触孔的另一端相连，以实现所述像素电极图案与所述漏极图案之间的电性连接；
    其中，所述公共电极图案分成多个，或者所述公共电极图案是一个整块。
  2. 根据权利要求1所述的方法，其中，所述掺杂处理为H2、Ar或NH3等离子处理。
  3. 一种阵列基板，其中，包括：
    基板；
    数据线层和遮光层，位于同一层中，且分别间隔地形成在所述基板上，所述遮光层和所述数据线层的材料均为金属材料；
    第一绝缘层，覆盖在所述基板、所述数据线层和所述遮光层上；
    源极层、漏极层、氧化物半导体材料层以及公共电极层，分别形成在所述第一绝缘层上，其中，所述源极层和所述漏极层紧邻并位于所述氧化物半导体材料层的两端，所述公共电极层与所述漏极层间隔设置，所述源极层、所述漏极层以及所述公共电极层通过对氧化物半导体材料经过掺杂处理而形成，所述氧化物半导体材料层在所述遮光层的遮光作用下，能够完全避免受到光线的影响；
    第二绝缘层，覆盖在所述氧化物半导体材料层上；
    栅极层，形成在所述第二绝缘层上，其材料为金属材料；
    绝缘的互联层，覆盖在所述第一绝缘层、所述源极层、所述栅极层、所述漏极层以及所述公共电极层上，且在所述互联层中分别形成贯穿所述互联层的第一接触孔、第二接触孔以及第三接触孔，所述第一接触孔的一端延伸并贯穿所述第一绝缘层，与所述数据线层连接，所述第二接触孔的一端与所述源极层连接，所述第三接触孔的一端与所述漏极层连接，其中所述第一接触孔、第二接触孔以及第三接触孔中填充的材料为透明电极材料；
    透明电极材料层和像素电极层，其分别间隔形成在所述互联层上，其材料均为透明电极材料，其中，所述透明电极材料层分别与所述第一接触孔的另一端和所述第二接触孔的另一端相连，从而使所述源极层通过所述第二接触孔、所述透明电极材料层和所述第一接触孔而电性连接至所述数据线层，所述像素电极层与所述第三接触孔的另一端相连，以实现所述像素电极层与所述漏极层之间的电性连接。
  4. 根据权利要求3所述的阵列基板，其中，所述公共电极层分成多个。
  5. 根据权利要求3所述的阵列基板，其中，所述公共电极层是一个整块。
  6. 根据权利要求3所述的阵列基板，其中，所述掺杂处理为H2、Ar或NH3等离子处理。
  7. 一种液晶显示面板，其中，包括：
    第一基板，
    第二基板，与所述第一基板相对设置，其包括：
    基板；
    数据线层和遮光层，位于同一层中，且分别间隔地形成在所述基板上，所述遮光层和所述数据线层的材料均为金属材料；
    第一绝缘层，覆盖在所述基板、所述数据线层和所述遮光层上；
    源极层、漏极层、氧化物半导体材料层以及公共电极层，分别形成在所述第一绝缘层上，其中，所述源极层和所述漏极层紧邻并位于所述氧化物半导体材料层的两端，所述公共电极层与所述漏极层间隔设置，所述源极层、所述漏极层以及所述公共电极层通过对氧化物半导体材料经过掺杂处理而形成，所述氧化物半导体材料层在所述遮光层的遮光作用下，能够完全避免受到光线的影响；
    第二绝缘层，覆盖在所述氧化物半导体材料层上；
    栅极层，形成在所述第二绝缘层上，其材料为金属材料；
    绝缘的互联层，覆盖在所述第一绝缘层、所述源极层、所述栅极层、所述漏极层以及所述公共电极层上，且在所述互联层中分别形成贯穿所述互联层的第一接触孔、第二接触孔以及第三接触孔，所述第一接触孔的一端延伸并贯穿所述第一绝缘层，与所述数据线层连接，所述第二接触孔的一端与所述源极层连接，所述第三接触孔的一端与所述漏极层连接，其中所述第一接触孔、第二接触孔以及第三接触孔中填充的材料为透明电极材料；
    透明电极材料层和像素电极层，其分别间隔形成在所述互联层上，其材料均为透明电极材料，其中，所述透明电极材料层分别与所述第一接触孔的另一端和所述第二接触孔的另一端相连，从而使所述源极层通过所述第二接触孔、所述透明电极材料层和所述第一接触孔而电性连接至所述数据线层，所述像素电极层与所述第三接触孔的另一端相连，以实现所述像素电极层与所述漏极层之间的电性连接；
    液晶层，夹设在所述第一基板和所述第二基板之间。
  8. 根据权利要求7所述的液晶显示面板，其中，所述公共电极层分成多个。
  9. 根据权利要求7所述的液晶显示面板，其中，所述公共电极层是一个整块。
  10. 根据权利要求7所述的液晶显示面板，其中，所述掺杂处理为H2、Ar或NH3等离子处理。
PCT/CN2016/104606 2016-08-26 2016-11-04 阵列基板、液晶显示面板以及制造方法 WO2018035973A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/322,253 US10114259B2 (en) 2016-08-26 2016-11-04 Array substrate, liquid crystal display panel and manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610742677.1 2016-08-26
CN201610742677.1A CN106371253A (zh) 2016-08-26 2016-08-26 阵列基板、液晶显示面板以及制造方法

Publications (1)

Publication Number Publication Date
WO2018035973A1 true WO2018035973A1 (zh) 2018-03-01

Family

ID=57903996

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/104606 WO2018035973A1 (zh) 2016-08-26 2016-11-04 阵列基板、液晶显示面板以及制造方法

Country Status (3)

Country Link
US (1) US10114259B2 (zh)
CN (1) CN106371253A (zh)
WO (1) WO2018035973A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711086B (zh) * 2016-12-23 2019-08-20 深圳市华星光电技术有限公司 阵列基板、阵列基板制造方法及液晶显示屏
CN107565049B (zh) * 2017-08-25 2019-11-01 京东方科技集团股份有限公司 Amoled显示面板及其制备方法
KR102457997B1 (ko) * 2017-12-29 2022-10-21 엘지디스플레이 주식회사 전계 발광 표시장치
US10825838B2 (en) 2018-03-29 2020-11-03 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and its manufacturing method and display device
CN108461507A (zh) * 2018-03-29 2018-08-28 武汉华星光电技术有限公司 一种阵列基板及其制备方法、显示器
CN108511465A (zh) * 2018-04-28 2018-09-07 武汉华星光电技术有限公司 内嵌式触控阵列基板、显示面板及制造方法
US10453872B1 (en) 2018-05-03 2019-10-22 Wuhan China Star Optoelectronics Semiconductor Display Technologiy Co., Ltd. Array substrate and manufacturing method thereof
CN108598091B (zh) * 2018-05-03 2020-03-17 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制作方法
CN108873527A (zh) * 2018-07-25 2018-11-23 Oppo（重庆）智能科技有限公司 阵列基板、液晶显示面板、装置及制备阵列基板的方法
CN110931509B (zh) * 2019-11-25 2022-12-06 Tcl华星光电技术有限公司 阵列基板及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101997025A (zh) * 2009-08-25 2011-03-30 三星移动显示器株式会社 有机发光二极管显示器及其制造方法
CN202796954U (zh) * 2012-07-27 2013-03-13 北京京东方光电科技有限公司 一种平板阵列基板及传感器
KR20140017854A (ko) * 2012-08-01 2014-02-12 엘지디스플레이 주식회사 유기전기발광 표시장치용 어레이 기판 및 그 제조 방법
CN103700628A (zh) * 2013-12-26 2014-04-02 京东方科技集团股份有限公司 阵列基板制作方法、阵列基板及显示装置
CN203950283U (zh) * 2014-05-20 2014-11-19 京东方科技集团股份有限公司 一种触摸显示面板和显示装置
CN104393000A (zh) * 2014-10-20 2015-03-04 上海天马微电子有限公司 一种阵列基板及其制作方法、显示装置
CN105097948A (zh) * 2015-08-14 2015-11-25 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制作方法、显示面板和装置
CN105720012A (zh) * 2016-02-18 2016-06-29 深圳市华星光电技术有限公司 双栅极tft阵列基板及制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6245602B1 (en) * 1999-11-18 2001-06-12 Xerox Corporation Top gate self-aligned polysilicon TFT and a method for its production
TW554538B (en) * 2002-05-29 2003-09-21 Toppoly Optoelectronics Corp TFT planar display panel structure and process for producing same
JP2004343018A (ja) * 2003-03-20 2004-12-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2009194348A (ja) * 2008-02-15 2009-08-27 Akito Hara 半導体製造方法
CN102184966B (zh) * 2011-04-15 2013-02-13 福州华映视讯有限公司 晶体管数组基板
TWI508171B (zh) * 2013-02-05 2015-11-11 Ind Tech Res Inst 半導體元件結構及其製造方法
CN103268891B (zh) * 2013-03-28 2016-08-10 北京京东方光电科技有限公司 一种薄膜晶体管、非晶硅平板探测基板及制备方法
KR102169861B1 (ko) * 2013-11-07 2020-10-26 엘지디스플레이 주식회사 어레이기판 및 이의 제조방법
CN104332477B (zh) * 2014-11-14 2017-05-17 京东方科技集团股份有限公司 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
CN105226015B (zh) * 2015-09-28 2018-03-13 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101997025A (zh) * 2009-08-25 2011-03-30 三星移动显示器株式会社 有机发光二极管显示器及其制造方法
CN202796954U (zh) * 2012-07-27 2013-03-13 北京京东方光电科技有限公司 一种平板阵列基板及传感器
KR20140017854A (ko) * 2012-08-01 2014-02-12 엘지디스플레이 주식회사 유기전기발광 표시장치용 어레이 기판 및 그 제조 방법
CN103700628A (zh) * 2013-12-26 2014-04-02 京东方科技集团股份有限公司 阵列基板制作方法、阵列基板及显示装置
CN203950283U (zh) * 2014-05-20 2014-11-19 京东方科技集团股份有限公司 一种触摸显示面板和显示装置
CN104393000A (zh) * 2014-10-20 2015-03-04 上海天马微电子有限公司 一种阵列基板及其制作方法、显示装置
CN105097948A (zh) * 2015-08-14 2015-11-25 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制作方法、显示面板和装置
CN105720012A (zh) * 2016-02-18 2016-06-29 深圳市华星光电技术有限公司 双栅极tft阵列基板及制作方法

Also Published As

Publication number Publication date
US20180217458A1 (en) 2018-08-02
CN106371253A (zh) 2017-02-01
US10114259B2 (en) 2018-10-30

Similar Documents

Publication Publication Date Title
WO2018035973A1 (zh) 阵列基板、液晶显示面板以及制造方法
JP6129312B2 (ja) アレイ基板の製造方法、アレイ基板及び表示装置
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
JP4368200B2 (ja) 薄膜トランジスタ基板及びその製造方法
US9455324B2 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
WO2014127579A1 (zh) 薄膜晶体管阵列基板、制造方法及显示装置
US7799619B2 (en) Thin film transistor array substrate and fabricating method thereof
WO2017008497A1 (zh) 氧化物薄膜晶体管的制备方法
KR20120042029A (ko) 표시 장치 및 그 제조 방법
TW201622158A (zh) 薄膜電晶體以及其製作方法
WO2017133145A1 (zh) 金属氧化物薄膜晶体管及其制造方法
WO2013127201A1 (zh) 阵列基板和其制造方法以及显示装置
WO2018205886A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
WO2014146358A1 (zh) 阵列基板、阵列基板的制造方法及显示装置
TWI333279B (en) Method for manufacturing an array substrate
WO2018149027A1 (zh) 一种薄膜晶体管及其制备方法
WO2018006446A1 (zh) 薄膜晶体管阵列基板及其制造方法
WO2013181915A1 (zh) Tft阵列基板及其制造方法和显示装置
WO2019100465A1 (zh) 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
WO2019029007A1 (zh) 一种tft基板的制备方法、tft基板以及oled显示面板
WO2016026176A1 (zh) Tft基板的制作方法及其结构
CN101488479A (zh) 薄膜晶体管阵列基板及其制造方法
CN111048524A (zh) 阵列基板及制备方法、显示面板
WO2021026990A1 (zh) 一种阵列基板及其制作方法
KR102224457B1 (ko) 표시장치와 그 제조 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15322253

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16913993

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16913993

Country of ref document: EP

Kind code of ref document: A1