WO2017210995A1 - 金属氧化物薄膜晶体管及其制备方法 - Google Patents

金属氧化物薄膜晶体管及其制备方法 Download PDF

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WO2017210995A1
WO2017210995A1 PCT/CN2016/094684 CN2016094684W WO2017210995A1 WO 2017210995 A1 WO2017210995 A1 WO 2017210995A1 CN 2016094684 W CN2016094684 W CN 2016094684W WO 2017210995 A1 WO2017210995 A1 WO 2017210995A1
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semiconductor active
patterned
active layer
layer
electrode
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PCT/CN2016/094684
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English (en)
French (fr)
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刘洋
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深圳市华星光电技术有限公司
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Priority to US15/300,045 priority Critical patent/US10290743B2/en
Publication of WO2017210995A1 publication Critical patent/WO2017210995A1/zh

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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Definitions

  • the invention relates to the field of wafer manufacturing and display technology, in particular to a metal oxide thin film transistor and a preparation method thereof.
  • the high mobility thin film transistor includes a polysilicon thin film transistor and a metal oxide thin film transistor.
  • the polysilicon thin film transistor has a high mobility, the uniformity is poor and the manufacturing process is complicated, so the cost is high and the yield is low;
  • metal oxide thin film transistors have high mobility and good uniformity and relatively low process cost, so they are considered to be key technologies in next-generation flat panel displays.
  • thin film transistor devices are required to have shorter channels because short channel devices have a larger aspect ratio, which allows thin film transistors to have larger switching currents.
  • the channel length L of the thin film transistor device is directly limited by the photolithography process, and is to be realized. Short channel devices have greater difficulty.
  • the present invention aims to provide a novel metal oxide thin film transistor and a method for fabricating the same, which solves the problem that the thin film transistor is difficult to realize short channel and improve the performance of the thin film transistor in the prior art.
  • the present invention includes two aspects.
  • the present invention provides a metal oxide thin film transistor including: a substrate; a source electrode, a barrier layer, and a drain electrode sequentially formed on the substrate; and the drain electrode is formed on the drain electrode a semiconductor active layer on a side surface of the source electrode, wherein the semiconductor active layer is in contact with the drain electrode and the source electrode, respectively.
  • the source electrode, the barrier layer, and the drain electrode are each a trapezoidal structure having an upper surface length smaller than a lower surface length, and The length of the lower surface of the barrier layer is the same as the length of the upper surface of the source electrode, and the length of the lower surface of the drain electrode is the same as the length of the upper surface of the barrier layer.
  • the source electrode, the barrier layer, and the drain electrode are each a trapezoidal structure having an upper surface length smaller than a length of a lower surface.
  • the lower surface of the barrier layer has the same length as the upper surface of the source electrode, the drain electrode is formed on the left and right sides of the upper surface of the barrier layer, and the drain electrode located on the left side of the barrier layer is located at the barrier The drain electrodes on the right side of the layer are interconnected.
  • the source electrode, the barrier layer, and the drain electrode are each a trapezoidal structure having an upper surface length smaller than a length of a lower surface.
  • the length of the lower surface of the drain electrode is the same as the length of the upper surface of the barrier layer, and the length of the lower surface of the barrier layer is smaller than the length of the upper surface of the source electrode, so that the source electrode portion is exposed outside the coverage of the barrier layer.
  • the left side and the right side of the source electrode are respectively protruded from the lower surface of the barrier layer, so that the left side and the right side of the source electrode are respectively exposed outside the coverage of the barrier layer.
  • the semiconductor active layer is a patterned semiconductor active layer, and the patterned semiconductor active layer includes a left side and a side of the left side of the drain electrode A first patterned semiconductor active layer on a left side of the source electrode, and a second patterned semiconductor active layer on the right side and simultaneously contacting the right side of the drain electrode and the right side of the source electrode.
  • the barrier layer is one of an insulating layer or a semiconductor barrier layer.
  • the material of the insulating layer is selected from one or a combination of SiNx or SiOx.
  • the material of the semiconductor barrier layer is selected from a combination of one or more of a ZnO-based, In 2 O 3 -based, and SnO 2 -based material.
  • the semiconductor barrier layer in the present invention is a semiconductor high resistance layer, that is, a semiconductor layer having a relatively high resistance value.
  • GI is further formed with a gate electrode insulating layer formed on the semiconductor active layer.
  • Gate electrode is further provided] Further, a gate electrode is further formed on the gate electrode insulating layer.
  • the gate electrode is a patterned gate electrode.
  • the patterned gate electrodes are respectively located on the left side surface and the right side surface of the gate electrode insulating layer, and the patterned gate electrodes on the left side surface are correspondingly disposed on the first pattern.
  • the patterned gate electrode on the right side surface is correspondingly disposed above the second patterned semiconductor active layer, and the patterned gate on the left side The electrodes are interconnected with the patterned gate electrode on the right side.
  • PV is further set
  • a passivation layer is formed on the patterned gate electrode.
  • the material selected for the drain electrode is a composite material of one or more of Al, Mo, Cu or Ag.
  • the material selected from the source electrode is a composite material of one or more of Al, Mo, Cu or Ag.
  • the material selected for the semiconductor active layer is a combination of one or more of a ZnO-based, In 2 O 3 -based, and SnO 2 -based material.
  • the material selected for the gate electrode insulating layer is one of SiNx, SiOx or a combination of two.
  • the gate electrode is made of a composite material of one or more of Al, Mo, Cu or Ag.
  • the passivation layer is made of a material of one or a combination of SiNx and SiOx.
  • the present invention also provides a method for fabricating the above metal oxide thin film transistor, comprising the steps of:
  • the bulk active layer is in contact with the drain electrode and the source electrode, respectively.
  • sequentially forming a source electrode, a barrier layer, and a drain electrode on the substrate is to form a first metal layer on the substrate, Forming a barrier layer on the first metal layer, forming a second metal layer on the barrier layer, performing photolithography on the second metal layer, the barrier layer, and the first metal layer to make the first metal A layer forms the source electrode, and the second metal layer forms the drain electrode.
  • photolithography is performed on the second metal layer, the barrier layer, and the first metal layer by using a halftone mask and/or a grayscale mask.
  • a photoresist is coated on the first metal layer, and after exposure and development, a photolithographic pattern is formed, and after etching and stripping the photoresist, the source electrode and the drain electrode are formed.
  • the source electrode, the barrier layer, and the drain electrode are each a trapezoidal structure having an upper surface length smaller than a length of a lower surface.
  • the length of the lower surface of the barrier layer is the same as the length of the upper surface of the source electrode, and the length of the lower surface of the drain electrode is the same as the length of the upper surface of the barrier layer.
  • the source electrode, the barrier layer, and the drain electrode are both a trapezoidal structure having a surface length smaller than a length of the lower surface, the lower surface length of the barrier layer being the same as the upper surface of the source electrode, the drain electrode being formed on the left and right sides of the upper surface of the barrier layer, and located at the barrier The drain electrode on the left side of the layer is interconnected with the drain electrode on the right side of the barrier layer.
  • the source electrode, the barrier layer, and the drain electrode are both a trapezoidal structure having a surface length smaller than a length of the lower surface, the length of the lower surface of the drain electrode being the same as the length of the upper surface of the barrier layer, the length of the lower surface of the barrier layer being smaller than the length of the upper surface of the source electrode, exposing the source electrode portion Outside the coverage of the barrier layer.
  • the left side and the right side of the source electrode are respectively protruded from the lower surface of the barrier layer, so that the left side and the right side of the source electrode are respectively exposed outside the coverage of the barrier layer.
  • the preparation method of the present invention in the Forming a semiconductor active layer on a side surface of the drain electrode and the source electrode is performing photolithography on the semiconductor active layer to obtain a patterned semiconductor active layer, wherein the patterned semiconductor active layer includes a left side and Simultaneously contacting the left side of the drain electrode and the first patterned semiconductor active layer on the left side of the source electrode, and on the right side while simultaneously contacting the right side of the drain electrode and the right side of the source electrode A second patterned semiconductor active layer.
  • the barrier layer is one of an insulating layer or a semiconductor barrier layer.
  • the material of the insulating layer is selected from one or a combination of SiNx or SiOx.
  • the material of the semiconductor barrier layer is selected from a combination of one or more of a ZnO-based, In 2 O 3 -based, and SnO 2 -based material.
  • the semiconductor barrier layer in the present invention is a semiconductor high resistance layer, that is, a semiconductor layer having a relatively high resistance value.
  • the method further includes the step of forming a gate electrode insulating layer on the semiconductor active layer.
  • the method further includes the step of forming a gate electrode on the gate electrode insulating layer.
  • forming a gate electrode on the gate electrode insulating layer is to deposit a third metal layer on the gate electrode insulating layer, and photolithography is performed on the third metal layer to obtain a pattern The gate electrode.
  • the patterned gate electrodes are respectively located on the left side surface and the right side surface of the gate electrode insulating layer, and the patterned gate electrodes on the left side surface are correspondingly disposed at the same time.
  • the patterned gate electrode on the right side surface is simultaneously disposed above the second patterned semiconductor active layer and located on the left side
  • the patterned gate electrode is interconnected with the patterned gate electrode on the right side.
  • the method further includes the step of forming a passivation layer on the patterned gate electrode.
  • the material selected for the drain electrode is a composite material of one or more of Al, Mo, Cu or Ag.
  • the material selected from the source electrode is a composite material of one or more of Al, Mo, Cu or Ag.
  • the material selected for the semiconductor active layer is a combination of one or more of a ZnO-based, In 2 O 3 -based, and SnO 2 -based material.
  • the material selected for the gate electrode insulating layer is one of SiNx, SiOx or a combination of two.
  • the gate electrode is made of a composite material of one or more of Al, Mo, Cu or Ag.
  • the passivation layer is made of a material of one or a combination of SiNx and SiOx.
  • a gate electrode, a gate insulating layer, a semiconductor active layer, and the like are sequentially formed on a substrate, and a source electrode and a drain electrode are respectively formed on both sides of the semiconductor active layer.
  • the channel length of the thin film transistor is limited by the accuracy of the photolithography process, and it is difficult to achieve a shorter channel length.
  • a novel metal oxide thin film transistor and a method for fabricating the same are provided. First, a source electrode and a drain electrode are formed on a substrate, and a barrier layer is disposed between the two to distinguish the respective structures, thereby making the source The electrode, the drain electrode, and the barrier layer are parallel to the substrate and the film layers are also parallel to each other.
  • the semiconductor active layers are respectively formed on the left and right sides of the drain electrode, and are also formed on the left and right sides of the source electrode, thereby further forming a structure such as a gate electrode insulating layer and a gate electrode. That is, the source/drain electrodes are arranged parallel to the substrate, and the semiconductor active layer is respectively in contact with the source electrode and the drain electrode in a substantially vertical or stepped manner, thereby obtaining a thin film transistor structure parallel to the substrate of the conventional semiconductor active layer. Distinct different thin film transistors.
  • the channel length is no longer directly determined by the photolithography process, but is determined by the length of the side where the source electrode and the drain electrode are respectively in contact with the semiconductor active layer, since it is no longer limited.
  • a thin film transistor having a shorter channel can be obtained, thereby improving device performance such as an on-state current of the thin film transistor, so that it can meet the requirements of higher performance display.
  • the metal oxide thin film transistor of the present invention it is also possible to increase the source electrode at the base
  • the length of the board enables the source electrode to fully exert the function of the light shielding layer to reduce the influence of backlight illumination on the characteristics of the thin film transistor device, thereby further improving the performance of the thin film transistor.
  • the drain electrode in the metal oxide thin film transistor of the present invention, it is also possible to reduce leakage by designing the drain electrode to be respectively located on the left and right sides of the barrier layer and the left and right sides are in communication in the planar structure of the thin film transistor.
  • the overlap between the pole and the gate electrode reduces parasitic capacitance and improves the performance of the thin film transistor.
  • FIG. 1 is a schematic view showing the structure of a metal oxide thin film transistor of the prior art.
  • FIGS. 2A to 2F are process flowcharts of a method for fabricating a metal oxide thin film transistor according to a first embodiment of the present invention (a metal oxide thin film transistor is a cross section).
  • Fig. 2G is a perspective view showing the planar structure of a metal oxide thin film transistor in the first embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view showing a metal oxide thin film transistor according to Embodiment 1 of the present invention.
  • FIG. 4A is a schematic cross-sectional view showing a metal oxide thin film transistor according to a second embodiment of the present invention.
  • Fig. 4B is a perspective view showing the planar structure of a metal oxide thin film transistor in the second embodiment of the present invention.
  • Fig. 5 is a cross-sectional view showing the structure of a metal oxide thin film transistor according to a third embodiment of the present invention.
  • This embodiment provides a method for preparing a metal oxide thin film transistor, including the following steps:
  • a substrate 1 is prepared, and a first metal layer 21, a barrier layer 22, and a second metal layer 23 are sequentially deposited on the substrate 1 by a sputtering method, wherein the first metal layer and the second metal layer are both
  • the metal Mo and the barrier layer are made of SiOx material.
  • the barrier layer may be either an insulating layer or a semiconductor layer having a high resistance value, a semiconductor high resistance layer.
  • a SiNx material may also be used; when the barrier layer is a semiconductor high resistance layer, a transparent oxide semiconductor material such as a ZnO-based, SnO 2 -based or In 2 O 3 -based material may be used.
  • the first metal layer and the second metal layer in this embodiment may also be made of other metal materials, for example, metal materials such as Al, Cu, and Ag.
  • photolithography is performed on the first metal layer, the barrier layer, and the second metal layer, specifically, a photoresist (not shown) is coated on the second metal layer 23, and a halftone mask is used. Exposure and development are performed to form a first metal layer 21, a barrier layer 22, and a second metal layer 23 to form a photolithographic pattern, and then the first metal layer, the barrier layer, and the second metal layer outside the photoresist protection range are engraved. The etch is then stripped so that the first metal layer forms the source electrode 24 and the second metal layer forms the drain electrode 25.
  • the cross-sectional structure of the metal oxide thin film transistor ie, the structure shown in FIG.
  • a film layer respectively parallel to the substrate 1 - the source electrode 24 and the barrier layer 22 are formed.
  • the drain electrode 25 is continuous and complete film layers, and the lengths of the film layers are gradually reduced from the lower surface to the upper surface, respectively, so that the three are in the metal oxide film.
  • a trapezoidal shape having a short length and a long length is formed in the cross-sectional structure of the transistor.
  • the lower surface of the barrier layer 22 just covers the upper surface of the source electrode 24, and the lower surface of the drain electrode 25 just covers the upper surface of the barrier layer 22.
  • a ZnO-based material is deposited as a semiconductor active layer by a sputtering method on the exposed surface of the substrate 1, the source electrode 24, the barrier layer 22, and the drain electrode 25, and photolithography is performed thereon, specifically
  • the photoresist is coated on the semiconductor active layer, exposed and developed to form a photolithographic pattern, and then etched and stripped to form a patterned semiconductor active layer 3.
  • the patterned semiconductor active layer 3 includes a first patterned semiconductor active layer 31 on the left side and simultaneously contacting the left side of the drain electrode 25 and the left side of the source electrode 24, and the drain electrode on the right side while being in contact with the drain electrode 25 a right side of the second patterned semiconductor active layer 32 on the right side of the source electrode 24. Further, the patterned semiconductor active layer 3 is also in contact with the left and right sides of the barrier layer 22, respectively.
  • the semiconductor active layer may also be a transparent oxide semiconductor material such as a SnO 2 group or an In 2 O 3 group.
  • the patterned semiconductor active layer is in contact with the left and right sides of the source electrode and the drain electrode, respectively. Therefore, the channel is formed on the left and right sides of the source electrode and the drain electrode, that is, the channel length of the thin film transistor of the embodiment mainly depends on the lengths of the source electrode and the drain electrode on the left and right sides, and is no longer Due to the limitation of the photolithography process conditions, the thin film transistor of the present embodiment can realize a short channel structure.
  • SiOx is then deposited as a gate electrode insulating layer 4 by a sputtering method on the exposed surface of the substrate 1, the patterned semiconductor active layer 3, and the drain electrode 25.
  • the gate electrode insulating layer may also be an insulator material such as SiNx or Al 2 O 3 .
  • a metal Mo is deposited as a third metal layer by a sputtering method on the gate electrode insulating layer 4, and photolithography is performed on the third metal layer, specifically: coating light on the third metal layer.
  • the film is exposed and exposed to form a photolithographic pattern, and then etched and stripped to form a patterned gate electrode 5.
  • the gate electrodes 5 are respectively located on the left and right sides of the gate electrode insulating layer 4; however, as shown in FIG.
  • the gate electrode on the left side and the gate electrode on the right side are in communication with the planar structure of the metal oxide thin film transistor. It can be understood that, in order to clearly show the connection characteristics of the gate electrode in the planar structure of the metal oxide thin film transistor, only a part of the main structure of the metal oxide thin film transistor is shown in FIG. 2G, including the source electrode, the drain electrode, and the blocking. A layer, a patterned semiconductor active layer, and a gate electrode.
  • a SiNx material is then deposited as a passivation layer 6 by a sputtering method on the exposed surface of the gate electrode insulating layer 4 and the gate electrode 5.
  • one of vapor deposition and sol-gel methods may also be used in depositing and forming the first metal layer, the second metal layer, the third metal layer, and the semiconductor active layer.
  • a chemical vapor deposition method may also be employed in depositing a gate electrode insulating layer, a passivation layer, and a barrier layer.
  • the present embodiment further provides a metal oxide thin film transistor obtained by the above preparation method.
  • the metal oxide thin film transistor includes a substrate 1, a source electrode 24, a barrier layer 22, which are sequentially formed on the substrate 1,
  • the drain electrode 25 is formed on the left and right sides of the source electrode 24 and the drain electrode 25, respectively, and is formed on the exposed surface of the substrate 1, the patterned semiconductor active layer 3, and the drain electrode 25.
  • a gate electrode insulating layer 4 formed on the left and right gate electrodes 5 of the gate electrode insulating layer 4, and a gate electrode on the left side and a gate electrode on the right side are connected in a plane of the metal oxide thin film transistor of.
  • the source electrode and the drain electrode are both disposed on the substrate in a planar structure parallel to the substrate, and the patterned semiconductor active layer is disposed on the left and right sides of the source electrode and the drain electrode in a substantially vertical or stepped manner.
  • the lengths of the sides of the source and drain electrodes on both sides determine the channel length of the thin film transistor.
  • This structure does not need to be limited by the photolithography process, and belongs to a novel metal oxide thin film transistor structure, which can realize the short channel structure of the metal oxide thin film transistor.
  • the materials used in the respective film layer structures of the metal oxide thin film transistor are the materials described in the above preparation methods, and are not described herein again.
  • the difference between this embodiment and the preparation method of the first embodiment is that, as shown in FIG. 4A, after the first metal layer, the barrier layer and the second metal layer are photolithographically, the cross-sectional structure of the metal oxide thin film transistor is used.
  • the drain electrodes 25 formed after photolithography are respectively located on the left and right sides of the upper surface of the barrier layer 22, exposing the intermediate portion of the upper surface of the barrier layer 22, but at the same time, as shown in FIG. 4B, from the plane of the metal oxide thin film transistor In the top view of the structure, the drain electrode on the left side is connected to the drain electrode on the right side.
  • FIG. 4B only a part of the main structure of the metal oxide thin film transistor is shown in FIG. 4B, including the source electrode, the drain electrode, and the barrier.
  • a layer, a patterned semiconductor active layer, and a gate electrode is shown in FIG. 4B, including the source electrode, the drain electrode, and the barrier.
  • the metal oxide thin film transistor obtained by the preparation method of the present embodiment has a continuous structure from the planar structure of the metal oxide thin film transistor, but the leakage electrode is respectively viewed from the cross-sectional structure of the metal oxide thin film transistor. Located on the left and right sides of the upper surface of the barrier layer, this structural design reduces the overlap between the gate electrode and the drain electrode, thereby reducing parasitic capacitance and improving the performance of the thin film transistor.
  • the difference between the embodiment and the preparation method of the first embodiment is that when the first metal layer, the barrier layer and the second metal layer are photolithographically, the gray scale mask is used for exposure and development, and finally, as shown in FIG. 5 .
  • the lower surface of the barrier layer 22 covers only a portion of the source electrode, and the length of the upper surface of the source electrode 24 formed after photolithography is greater than the length of the lower surface of the barrier layer 22, that is, the source electrode.
  • the left side and the right side of the 24 are respectively protruded from the barrier layer 22 and the drain electrode 25, and are exposed outside the range covered by the barrier layer 22 and the drain electrode 25.
  • the source electrode since the length of the source electrode on the substrate is increased, the source electrode can fully exert the function of the light shielding layer. This reduces the influence of backlight illumination on the characteristics of the thin film transistor device and further improves the performance of the thin film transistor.
  • the metal oxide thin film transistor may further include other conventional functional structures, which will not be repeatedly described in the present invention.

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Abstract

一种金属氧化物薄膜晶体管及其制备方法，薄膜晶体管包括基板（1），依次形成于基板上的源电极（24）、阻挡层（22）、漏电极（25），形成于漏电极、源电极的侧面上的半导体有源层（3），半导体有源层与漏电极、源电极相接触。源、漏电极平行于基板设置，半导体有源层则以大致垂直或阶梯覆盖的方式分别与源电极、漏电极相接触，沟道长度不由光刻工艺直接决定，而是由源电极、漏电极分别与半导体有源层相接触的侧面的长度决定，因此可制得具有短沟道的薄膜晶体管。

Description

金属氧化物薄膜晶体管及其制备方法 技术领域
本发明涉及晶圆制造领域及显示技术领域，具体是一种金属氧化物薄膜晶体管及其制备方法。
背景技术
近年来随着液晶显示器尺寸的不断增大，驱动电路的频率不断提高，现有的非晶硅薄膜晶体管迁移率已经很难满足要求，故具有更高迁移率的薄膜晶体管成为相关企业和研发人员的关注热点。高迁移率的薄膜晶体管包括多晶硅薄膜晶体管和金属氧化物薄膜晶体管，其中多晶硅薄膜晶体管虽然具有较高的迁移率，但是其均一性较差、制作工艺较为复杂，故而成本较高、产量较低；相比较而言，金属氧化物薄膜晶体管在兼有高迁移率的同时，还具有良好的均一性、相对较低的工艺成本，因此被认为是下一代平板显示中的关键技术。
随着显示器性能的提高，要求薄膜晶体管器件具有更短的沟道，这是因为短沟道器件具有较大的宽长比，可以使得薄膜晶体管具有较大的开关电流。然而，如图1所示，为传统的金属氧化物薄膜晶体管结构，在传统的金属氧化物薄膜晶体管的制备过程中，薄膜晶体管器件的沟道长度L直接受到光刻工艺的限制，要想实现短沟道器件具有较大难度。
发明内容
为克服现有技术的不足，本发明的目的在于提供一种新型的金属氧化物薄膜晶体管及其制备方法，以解决现有技术中薄膜晶体管难以实现短沟道、提高薄膜晶体管性能的问题。
本发明包括两个方面，第一个方面，本发明提供一种金属氧化物薄膜晶体管，包括：基板；依次形成于所述基板上的源电极、阻挡层、漏电极；形成于所述漏电极侧面上、所述源电极侧面上的半导体有源层，所述半导体有源层分别与所述漏电极、所述源电极相接触。
【源漏电极1】进一步地，在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，且所述阻挡层下表面长度与所述源电极上表面长度相同，所述漏电极下表面长度与所述阻挡层上表面长度相同。
【源漏电极2】进一步地，在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，所述阻挡层下表面长度与所述源电极上表面相同，所述漏电极形成于所述阻挡层上表面的左侧和右侧，且位于所述阻挡层左侧的漏电极与位于所述阻挡层右侧的漏电极是互连的。
【源漏电极3】进一步地，在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，所述漏电极下表面长度与所述阻挡层上表面长度相同，所述阻挡层下表面长度小于所述源电极上表面长度，使所述源电极部分暴露在所述阻挡层的覆盖范围之外。
进一步地，所述源电极的左侧和右侧分别凸出于所述阻挡层下表面设置，使所述源电极的左侧和右侧分别暴露在所述阻挡层的覆盖范围之外。
【半导体层-图形化】进一步地，所述半导体有源层为图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
【阻挡层】可选地，所述阻挡层为绝缘层或半导体阻挡层中的一种。
可选地，所述绝缘层的材料选用SiNx或SiOx中的一种或两种的结合。
可选地，所述半导体阻挡层的材料选用ZnO基、In2O3基、SnO2基材料中的一种或几种的结合。可以理解的是，本发明中的半导体阻挡层为半导体高阻层，即具有较高电阻值的半导体层。
【还设GI】进一步地，在所述半导体有源层上还形成有栅电极绝缘层。
【还设栅电极】进一步地，在所述栅电极绝缘层上还形成有栅电极。
进一步地，所述栅电极为图形化的栅电极。
进一步地，所述图形化的栅电极分别位于所述栅电极绝缘层的左侧面和右侧面上，位于左侧面上的所述图形化的栅电极同时对应设置在所述第一图形化的半导体有源层上方，位于右侧面上的所述图形化的栅电极同时对应设置在所述第二图形化的半导体有源层上方，且位于左侧面的所述图形化的栅电极与位于右侧面的所述图形化的栅电极是互连的。
【还设PV】进一步地，在所述图形化的栅电极上形成有钝化层。
可选地，所述漏电极选用的材料为Al、Mo、Cu或Ag中的一种或几种的复合材料。
可选地，所述源电极选用的材料为Al、Mo、Cu或Ag中的一种或几种的复合材料。
可选地，所述半导体有源层选用的材料为ZnO基、In2O3基、SnO2基材料中的一种或几种的结合。
可选地，所述栅电极绝缘层选用的材料为SiNx、SiOx中的一种或两种的结合。
可选地，所述栅电极采用的材料为Al、Mo、Cu或Ag中的一种或几种的复合材料。
可选地，所述钝化层采用的材料为SiNx、SiOx中的一种或两种的结合。
第二个方面，本发明还提供一种上述金属氧化物薄膜晶体管的制备方法，包括以下步骤：
准备一基板；
依次在所述基板上形成源电极、阻挡层、漏电极；
在所述漏电极侧面上、所述源电极侧面上形成半导体有源层，使所述半导 体有源层分别与所述漏电极、所述源电极相接触。
【源漏极-具体】进一步地，在本发明所述的制备方法中，依次在所述基板上形成源电极、阻挡层、漏电极是在所述基板上形成第一金属层，在所述第一金属层上形成阻挡层，在所述阻挡层上形成第二金属层，对所述第二金属层、所述阻挡层、所述第一金属层进行光刻，使所述第一金属层形成所述源电极，所述第二金属层形成所述漏电极。
【半色调或灰阶光刻】进一步地，对所述第二金属层、所述阻挡层、所述第一金属层进行光刻是利用半色调掩膜版和/或灰阶掩膜版，在所述第一金属层上涂布光阻，并进行曝光、显影后形成光刻图形，再经过刻蚀、剥离光阻后，形成所述源电极和所述漏电极。
【源漏电极结构1】进一步地，在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，且所述阻挡层下表面长度与所述源电极上表面长度相同，所述漏电极下表面长度与所述阻挡层上表面长度相同。
【源漏电极结构2】进一步地，在本发明所述的制备方法中，在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，所述阻挡层下表面长度与所述源电极上表面相同，所述漏电极形成于所述阻挡层上表面的左侧和右侧，且位于所述阻挡层左侧的漏电极与位于所述阻挡层右侧的漏电极是互连的。
【源漏电极结构3】进一步地，在本发明所述的制备方法中，在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，所述漏电极下表面长度与所述阻挡层上表面长度相同，所述阻挡层下表面长度小于所述源电极上表面长度，使所述源电极部分暴露在所述阻挡层的覆盖范围之外。
进一步地，所述源电极的左侧和右侧分别凸出于所述阻挡层下表面设置，使所述源电极的左侧和右侧分别暴露在所述阻挡层的覆盖范围之外。
【半导体有源层-具体】进一步地，在本发明所述的制备方法中，在所述 漏电极、所述源电极的侧面上形成半导体有源层是对所述半导体有源层进行光刻，得到图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
【阻挡层】可选地，所述阻挡层为绝缘层或半导体阻挡层中的一种。
可选地，所述绝缘层的材料选用SiNx或SiOx中的一种或两种的结合。
可选地，所述半导体阻挡层的材料选用ZnO基、In2O3基、SnO2基材料中的一种或几种的结合。可以理解的是，本发明中的半导体阻挡层为半导体高阻层，即具有较高电阻值的半导体层。
【栅绝缘层】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述半导体有源层上形成栅电极绝缘层。
【栅电极】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述栅电极绝缘层上形成栅电极。
【栅电极-具体光刻】进一步地，在所述栅电极绝缘层上形成栅电极是在所述栅电极绝缘层上沉积第三金属层，对所述第三金属层进行光刻，得到图形化的栅电极。
【栅电极-具体】进一步地，所述图形化的栅电极分别位于所述栅电极绝缘层的左侧面和右侧面上，位于左侧面上的所述图形化的栅电极同时对应设置在所述第一图形化的半导体有源层上方，位于右侧面上的所述图形化的栅电极同时对应设置在所述第二图形化的半导体有源层上方，且位于左侧面的所述图形化的栅电极与位于右侧面的所述图形化的栅电极是互连的。
【钝化层】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述图形化的栅电极上形成钝化层。
【材料】可选地，所述漏电极选用的材料为Al、Mo、Cu或Ag中的一种或几种的复合材料。
可选地，所述源电极选用的材料为Al、Mo、Cu或Ag中的一种或几种的复合材料。
可选地，所述半导体有源层选用的材料为ZnO基、In2O3基、SnO2基材料中的一种或几种的结合。
可选地，所述栅电极绝缘层选用的材料为SiNx、SiOx中的一种或两种的结合。
可选地，所述栅电极采用的材料为Al、Mo、Cu或Ag中的一种或几种的复合材料。
可选地，所述钝化层采用的材料为SiNx、SiOx中的一种或两种的结合。
与现有技术相比，本发明的有益效果如下：
在常规金属氧化物薄膜晶体管结构中，通常是在基板上依次形成栅极、栅极绝缘层、半导体有源层等结构，在半导体有源层两侧分别形成源电极和漏电极，这种结构中薄膜晶体管的沟道长度受限于光刻工艺的精度等问题，难以实现较短的沟道长度。而在本发明中，提供了一种新型的金属氧化物薄膜晶体管及其制备方法，首先在基板上形成源电极和漏电极，并在二者之间设置阻挡层以区分各自结构，从而使得源电极、漏电极、阻挡层平行于基板且各膜层之间也互相平行。然后再使半导体有源层分别形成于漏电极的左右两侧，同时也形成于源电极的左右两侧，进而再形成栅电极绝缘层和栅电极等结构。即：源漏电极平行于基板设置，半导体有源层则以大致垂直或阶梯覆盖的方式分别与源电极、漏电极相接触，从而得到一种与以往半导体有源层平行于基板的薄膜晶体管结构截然不同的薄膜晶体管。
在本发明的金属氧化物薄膜晶体管中，沟道长度不再由光刻工艺直接决定，而是由源电极、漏电极分别与半导体有源层相接触的侧面的长度决定，由于不再受限于复杂的光刻工艺，故而能够制得具有较短沟道的薄膜晶体管，从而提高薄膜晶体管的开态电流等器件性能，使其能够满足更高性能的显示其要求。
此外，在本发明的金属氧化物薄膜晶体管中，还可以通过增加源电极在基 板上的长度，使源电极充分发挥遮光层的作用，以减少背光光照对薄膜晶体管器件特性的影响，进一步提升薄膜晶体管性能。
最后，在本发明的金属氧化物薄膜晶体管中，还可以通过将漏电极设计为分别位于阻挡层左右两侧且该左右两侧在薄膜晶体管的平面结构中相连通的结构，好处在于可以减少漏电极与栅电极之间的重叠部分，从而减少寄生电容，提高薄膜晶体管的性能。
附图说明
图1是现有技术的金属氧化物薄膜晶体管的结构示意图。
图2A至图2F是本发明实施例一中金属氧化物薄膜晶体管的制备方法的工艺流程图(金属氧化物薄膜晶体管为剖面)。
图2G是本发明实施例一中金属氧化物薄膜晶体管的平面结构透视图。
图3是本发明实施例一中金属氧化物薄膜晶体管的剖面结构示意图。
图4A是本发明实施例二中金属氧化物薄膜晶体管的剖面结构示意图。
图4B是本发明实施例二中金属氧化物薄膜晶体管的平面结构透视图。
图5是本发明实施例三中金属氧化物薄膜晶体管的剖面结构示意图。
具体实施方式
实施例一
本实施例提供一种金属氧化物薄膜晶体管的制备方法，包括以下步骤：
如图2A所示，准备一基板1，通过溅射方法依次在基板1上沉积形成第一金属层21、阻挡层22、第二金属层23，其中第一金属层和第二金属层均采用金属Mo，阻挡层采用SiOx材料。在本实施例中，阻挡层既可以是绝缘层，也可以是电阻值较高的半导体层——半导体高阻层。当阻挡层为绝缘层时，还可以采用SiNx材料；当阻挡层为半导体高阻层时，可以采用ZnO基、SnO2基或者In2O3基等透明氧化物半导体材料。本实施例中的第一金属层、第二金属层也可采用其它金属材料，例如采用Al、Cu、Ag等金属材料。
如图2B所示，对上述第一金属层、阻挡层、第二金属层进行光刻，具体为：在第二金属层23上涂布光阻(图未示)，利用半色调掩膜版进行曝光、显影以使第一金属层21、阻挡层22、第二金属层23形成光刻图形，再对处于光阻保护范围之外的第一金属层、阻挡层、第二金属层进行刻蚀，然后剥离光阻，使第一金属层形成源电极24，第二金属层形成漏电极25。在本实施例中，从金属氧化物薄膜晶体管的剖面结构来看(即图2B所示结构)，经过光刻后，形成了分别平行于基板1的膜层——源电极24、阻挡层22、漏电极25。在本实施例中，源电极24、阻挡层22、漏电极25均为连续、完整的膜层，且各膜层的长度分别由下表面至上表面逐渐减小，使三者在金属氧化物薄膜晶体管的剖面结构中形成上短下长的梯形。其中，阻挡层22下表面刚好覆盖源电极24上表面，漏电极25下表面刚好覆盖阻挡层22上表面。可以理解的是，在本实施例的制备方法中，还可以利用灰阶掩膜版对上述第一金属层、阻挡层、第二金属层进行曝光，最终也可得到具有光刻图形的源电极和漏电极。
如图2C所示，接着在基板1、源电极24、阻挡层22、漏电极25暴露在外的表面上通过溅射方法沉积ZnO基材料作为半导体有源层，并对其进行光刻，具体为：在半导体有源层上涂布光阻，并进行曝光、显影以形成光刻图形，再经过刻蚀、剥离光阻，形成图形化的半导体有源层3。该图形化的半导体有源层3包括位于左侧且同时接触漏电极25左侧边和源电极24左侧边的第一图形化的半导体有源层31，以及位于右侧且同时接触漏电极25右侧边和源电极24右侧边的第二图形化的半导体有源层32。此外，该图形化的半导体有源层3也分别与阻挡层22的左侧边和右侧边相接触。可以理解的是，该半导体有源层还可以采用SnO2基以及In2O3基等透明氧化物半导体材料。
在本实施例中，从金属氧化物薄膜晶体管的剖面结构来看(即图2C所示结构)，图形化的半导体有源层是从源电极、漏电极的左右两侧面分别与二者相接触的，因此沟道是在源电极、漏电极的左右两侧面上形成的，即本实施例的薄膜晶体管的沟道长度主要取决于源电极、漏电极在左右两侧面上的长度，而不再受限于光刻工艺条件，故本实施例的薄膜晶体管可以实现短沟道结构。
如图2D所示，接着在基板1、图形化的半导体有源层3、漏电极25暴露在外的表面上通过溅射方法沉积SiOx作为栅电极绝缘层4。该栅电极绝缘层还可以采用SiNx、Al2O3等绝缘体材料。
如图2E所示，接着在栅电极绝缘层4上通过溅射方法沉积金属Mo作为第三金属层，并对该第三金属层进行光刻，具体为：在第三金属层上涂布光阻，并进行曝光、显影以形成光刻图形，再经过刻蚀、剥离光阻，形成图形化的栅电极5。从金属氧化物薄膜晶体管的剖面结构来看(即图2E所示结构)，该栅电极5分别位于栅电极绝缘层4的左右两侧；然而如图2G所示，从金属氧化物薄膜晶体管的平面结构透视图来看，位于左侧的栅电极与位于右侧的栅电极在金属氧化物薄膜晶体管的平面结构上是相连通的。可以理解的是，为了清楚显示栅电极在金属氧化物薄膜晶体管的平面结构中的连通特性，在图2G中仅示出了金属氧化物薄膜晶体管的部分主要结构，包括源电极、漏电极、阻挡层、图形化的半导体有源层以及栅电极。
如图2F所示，接着在栅电极绝缘层4、栅电极5暴露在外的表面上通过溅射方法沉积SiNx材料作为钝化层6。
可以理解的是，本实施例的制备方法中在沉积形成第一金属层、第二金属层、第三金属层、半导体有源层时还可以采用蒸镀、溶胶凝胶方法中的一种。本实施例的制备方法中在沉积形成栅电极绝缘层、钝化层、阻挡层时还可以采用化学气相沉积方法。
本实施例还提供一种采用上述制备方法得到的金属氧化物薄膜晶体管，如图3所示，该金属氧化物薄膜晶体管包括基板1，依次形成于基板1上的源电极24、阻挡层22、漏电极25，分别形成于源电极24、漏电极25的左右两侧面上图形化的半导体有源层3，形成于基板1、图形化的半导体有源层3、漏电极25暴露在外的表面上的栅电极绝缘层4，形成于栅电极绝缘层4的左右两侧的栅电极5，且位于左侧的栅电极与位于右侧的栅电极在该金属氧化物薄膜晶体管的平面上是相连通的。在本实施例中，源电极和漏电极均以平行于基板的平面结构设置在基板上，而图形化的半导体有源层则以大致垂直或者阶梯覆盖的方式设置在源电极、漏电极的左右两侧，即源电极和漏电极的侧面长度决定了薄膜晶体管的沟道长度。这种结构无需受限于光刻工艺，属于一种新型的金属氧化物薄膜晶体管结构，可实现金属氧化物薄膜晶体管的短沟道结构。
在本实施例中，金属氧化物薄膜晶体管的各膜层结构所采用的材料即为上述制备方法中记载的材料，此处不再赘述。
实施例二
本实施例与实施例一制备方法的不同之处仅在于，如图4A所示，对第一金属层、阻挡层、第二金属层进行光刻后，从金属氧化物薄膜晶体管的剖面结构来看，使光刻后形成的漏电极25分别位于阻挡层22上表面的左右两侧，使阻挡层22上表面的中间部分暴露，但同时如图4B所示，从金属氧化物薄膜晶体管的平面结构俯视图来看，位于左侧的漏电极与位于右侧的漏电极是相连的。可以理解的是，为了清楚显示漏电极在金属氧化物薄膜晶体管的平面结构中的连通特性，在图4B中仅示出了金属氧化物薄膜晶体管的部分主要结构，包括源电极、漏电极、阻挡层、图形化的半导体有源层以及栅电极。
通过本实施例制备方法得到的金属氧化物薄膜晶体管，虽然从金属氧化物薄膜晶体管的平面结构来看，漏电极是连续的结构，但是从金属氧化物薄膜晶体管的剖面结构来看，漏电极分别位于阻挡层上表面的左侧和右侧，这种结构设计使得栅电极与漏电极之间的重叠部分有所减少，从而减少了寄生电容，提高了薄膜晶体管的性能。
实施例三
本实施例与实施例一制备方法的不同之处仅在于，对第一金属层、阻挡层、第二金属层进行光刻时，是利用灰阶掩膜版进行曝光、显影，最终如图5所示，从金属氧化物薄膜晶体管的剖面结构来看，阻挡层22下表面仅覆盖了部分源电极，光刻后形成的源电极24上表面长度大于阻挡层22下表面长度，即：源电极24的左侧和右侧分别凸出于阻挡层22、漏电极25设置，暴露在阻挡层22、漏电极25覆盖的范围之外。
通过本实施例制备方法得到的金属氧化物薄膜晶体管，从金属氧化物薄膜晶体管的剖面结构来看，由于源电极在基板上的长度有所增加，使得源电极可充分发挥遮光层的作用，由此来减少背光光照对薄膜晶体管器件特性的影响，进一步提升薄膜晶体管性能。
以上仅对金属氧化物薄膜晶体管的主体结构进行了说明，该金属氧化物薄膜晶体管还可以包括其它常规的功能结构，在本发明中不再一一赘述。
以上所述为本发明的具体实施方式，其目的是为了清楚说明本发明而作的举例，并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (18)

  1. 一种金属氧化物薄膜晶体管，其中，所述金属氧化物薄膜晶体管包括：基板；依次形成于所述基板上的源电极、阻挡层、漏电极；形成于所述漏电极、所述源电极的侧面上的半导体有源层，所述半导体有源层分别与所述漏电极、所述源电极相接触。
  2. 如权利要求1所述的金属氧化物薄膜晶体管，其中：在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，且所述阻挡层下表面长度与所述源电极上表面长度相同，所述漏电极下表面长度与所述阻挡层上表面长度相同。
  3. 如权利要求1所述的金属氧化物薄膜晶体管，其中：所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，所述阻挡层下表面长度与所述源电极上表面相同，所述漏电极形成于所述阻挡层上表面的左侧和右侧，且位于所述阻挡层左侧的漏电极与位于所述阻挡层右侧的漏电极是互连的。
  4. 如权利要求1所述的金属氧化物薄膜晶体管，其中：在所述金属氧化物薄膜晶体管的剖面结构中，所述源电极、所述阻挡层、所述漏电极均为上表面长度小于下表面长度的梯形结构，所述漏电极下表面长度与所述阻挡层上表面长度相同，所述阻挡层下表面长度小于所述源电极上表面长度，使所述源电极部分暴露在所述阻挡层的覆盖范围之外。
  5. 如权利要求1所述的金属氧化物薄膜晶体管，其中：所述半导体有源层为图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
  6. 如权利要求2所述的金属氧化物薄膜晶体管，其中：所述半导体有源层为图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以 及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
  7. 如权利要求3所述的金属氧化物薄膜晶体管，其中：所述半导体有源层为图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
  8. 如权利要求4所述的金属氧化物薄膜晶体管，其中：所述半导体有源层为图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
  9. 如权利要求5所述的金属氧化物薄膜晶体管，其中：在所述半导体有源层上还形成有栅电极绝缘层，在所述栅电极绝缘层上还形成有图形化的栅电极，所述图形化的栅电极分别位于所述栅电极绝缘层的左侧面和右侧面上，位于左侧面上的所述图形化的栅电极同时对应设置在所述第一图形化的半导体有源层上方，位于右侧面上的所述图形化的栅电极同时对应设置在所述第二图形化的半导体有源层上方，且位于左侧面的所述图形化的栅电极与位于右侧面的所述图形化的栅电极是互连的。
  10. 如权利要求6所述的金属氧化物薄膜晶体管，其中：在所述半导体有源层上还形成有栅电极绝缘层，在所述栅电极绝缘层上还形成有图形化的栅电极，所述图形化的栅电极分别位于所述栅电极绝缘层的左侧面和右侧面上，位于左侧面上的所述图形化的栅电极同时对应设置在所述第一图形化的半导体有源层上方，位于右侧面上的所述图形化的栅电极同时对应设置在所述第二图形化的半导体有源层上方，且位于左侧面的所述图形化的栅电极与位于右侧面的所述图形化的栅电极是互连的。
  11. 如权利要求7所述的金属氧化物薄膜晶体管，其中：在所述半导体有源层上还形成有栅电极绝缘层，在所述栅电极绝缘层上还形成有图形化的栅电极，所述图形化的栅电极分别位于所述栅电极绝缘层的左侧面和右侧面上， 位于左侧面上的所述图形化的栅电极同时对应设置在所述第一图形化的半导体有源层上方，位于右侧面上的所述图形化的栅电极同时对应设置在所述第二图形化的半导体有源层上方，且位于左侧面的所述图形化的栅电极与位于右侧面的所述图形化的栅电极是互连的。
  12. 如权利要求8所述的金属氧化物薄膜晶体管，其中：在所述半导体有源层上还形成有栅电极绝缘层，在所述栅电极绝缘层上还形成有图形化的栅电极，所述图形化的栅电极分别位于所述栅电极绝缘层的左侧面和右侧面上，位于左侧面上的所述图形化的栅电极同时对应设置在所述第一图形化的半导体有源层上方，位于右侧面上的所述图形化的栅电极同时对应设置在所述第二图形化的半导体有源层上方，且位于左侧面的所述图形化的栅电极与位于右侧面的所述图形化的栅电极是互连的。
  13. 一种金属氧化物薄膜晶体管的制备方法，其中，包括以下步骤：准备一基板；依次在所述基板上形成源电极、阻挡层、漏电极；在所述漏电极、所述源电极的侧面上形成半导体有源层，使所述半导体有源层分别与所述漏电极、所述源电极相接触。
  14. 如权利要求13所述的制备方法，其中：依次在所述基板上形成源电极、阻挡层、漏电极是在所述基板上形成第一金属层，在所述第一金属层上形成阻挡层，在所述阻挡层上形成第二金属层，对所述第二金属层、所述阻挡层、所述第一金属层进行光刻，使所述第一金属层形成所述源电极，所述第二金属层形成所述漏电极。
  15. 如权利要求14所述的制备方法，其中：对所述第二金属层、所述阻挡层、所述第一金属层进行光刻是利用半色调掩膜版和/或灰阶掩膜版，在所述第一金属层上涂布光阻，并进行曝光、显影后形成光刻图形，再经过刻蚀、剥离光阻后，形成所述源电极和所述漏电极。
  16. 如权利要求13所述的制备方法，其中：在所述漏电极、所述源电极的侧面上形成半导体有源层是对所述半导体有源层进行光刻，得到图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
  17. 如权利要求14所述的制备方法，其中：在所述漏电极、所述源电极的侧面上形成半导体有源层是对所述半导体有源层进行光刻，得到图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
  18. 如权利要求15所述的制备方法，其中：在所述漏电极、所述源电极的侧面上形成半导体有源层是对所述半导体有源层进行光刻，得到图形化的半导体有源层，所述图形化的半导体有源层包括位于左侧且同时接触所述漏电极左侧边和所述源电极左侧边的第一图形化的半导体有源层，以及位于右侧且同时接触所述漏电极右侧边和所述源电极右侧边的第二图形化的半导体有源层。
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