WO2014005348A1 - 一种阵列基板的制作方法、阵列基板和液晶显示装置 - Google Patents
一种阵列基板的制作方法、阵列基板和液晶显示装置 Download PDFInfo
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- WO2014005348A1 WO2014005348A1 PCT/CN2012/078573 CN2012078573W WO2014005348A1 WO 2014005348 A1 WO2014005348 A1 WO 2014005348A1 CN 2012078573 W CN2012078573 W CN 2012078573W WO 2014005348 A1 WO2014005348 A1 WO 2014005348A1
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- Prior art keywords
- layer
- array substrate
- photoresist
- tft
- active layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000084 colloidal system Substances 0.000 claims description 4
- 238000004380 ashing Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 35
- 238000005530 etching Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Definitions
- the present invention relates to the field of display, and more particularly to a method of fabricating an array substrate, an array substrate, and a liquid crystal display device.
- TFT-LCD Thin Film Transistor Liquid Crystal Dsiplay
- the TFT-LCD is formed by the combination of the array substrate and the color filter substrate.
- the array substrate is currently manufactured by a 5 mask or 4 mask process.
- Each reticle mask manufacturing process needs to undergo several steps such as cleaning, drying, film formation, photolithography, etc., because there are many processes in the process technology in the prior art, there is inevitably a long process time, good Low rate, high cost and other issues.
- the technical problem to be solved by the present invention is to provide a method for fabricating an array substrate having a small process flow, low cost, and high yield, an array substrate, and a liquid crystal display device.
- a method for fabricating an array substrate comprising the steps of:
- A using a first mask process, forming a scan line and a gate of the TFT on the surface of the substrate;
- the n+a-Si film layer covering the undoped active layer is left to form a doped active layer, and then a transparent conductive layer is formed on the drain surface of the TFT.
- step E using the undoped active layer as a mask, etching the n+a-Si film layer other than the undoped active layer covering portion to form a doped active layer, and then using the first A three-mask process forms a transparent conductive layer on the surface of the TFT.
- This is a specific fabrication process for doping the active layer.
- a pattern of a transparent conductive layer is formed on the surface of the array substrate by using a mask process, and then n+a-Si other than the covered portion of the undoped active layer is removed by exposure, development, and etching.
- the material, the retained n+a-Si material forms a doped active layer; then a layer of transparent conductive colloid is laid, and the remaining photoresist and its surface-coated conductive colloid are stripped to form the transparent conductive layer.
- a transparent conductive layer is formed on the source and drain surfaces of the TFT by a mask process.
- a transparent conductive layer is also laid on the source to protect the source.
- the transparent conductive layer on the source can be formed synchronously with the transparent conductive layer on the drain without additional processing.
- the method includes the following steps:
- A2 coating a first photoresist on the first metal layer, and then exposing and developing, forming a pattern of scan lines of the array substrate and gates of the TFTs, that is, forming a first photoresist;
- the step B includes:
- B2 coating a second photoresist on the n+a-Si film layer, forming a second photoresist by exposure and development, and forming a second photoresist in the upper region of the gate, the gap is divided into the bottom first a square notch, and a second square notch at the opening; the second square notch width is greater than the width of the first square notch; B3, using the second photoresist as a cover, etching away the n+a-Si film material at the first square notch; B4, after the n+a-Si film material at the first square notch is removed, continuing etching a second metal layer exposed to form a source, a drain, and a data line of the array substrate; and a first square gap is formed between the cut n+a-Si film layer and the second metal layer a conductive channel of equal width;
- the step C includes:
- the step E includes:
- a transparent conductive layer is formed on the source and drain surfaces of the TFT by a mask process.
- the surface of the source is also covered with a transparent conductive layer, which can protect the source.
- the transparent conductive layer on the source can be formed synchronously with the transparent conductive layer on the drain without additional processing.
- An array substrate includes a TFT structure, the TFT structure includes a gate, an insulating layer, a metal layer, a doped active layer, and a conductive channel in a region above the gate.
- the conductive channel cuts the doped active layer and the metal layer, the cut metal layer is divided into a source and a drain, and the drain surface is covered with a transparent conductive layer, the doped active layer surface and the conductive trench
- the track is covered with an undoped active layer.
- the source surface is also covered with a transparent conductive layer.
- a transparent conductive layer is also laid on the source to protect the source.
- the transparent conductive layer on the source can be formed synchronously with the transparent conductive layer on the drain without additional processing.
- the TFT structure is axisymmetric with respect to a center line of the conductive channel.
- the symmetrical structure allows for a tubular design that reduces design costs.
- the doped active layer is made of an n+a-Si material; and the undoped active layer is made of an a-Si material. This is a specific material for doping the active layer and the undoped active layer.
- a liquid crystal display device comprising the above array substrate.
- the invention adopts a structure in which a doped active layer, an undoped active layer is above, and a source and a drain are located below, and a source, a drain and a doped active layer can be simultaneously formed by a mask process.
- the photoresist is etched to reduce the thickness of the photoresist, so that the doped active layer at a higher position at both ends of the conductive channel leaks out.
- the a-Si material is laid and the conductive layer is conductive.
- the doped active layers at both ends of the channel are connected, and finally the photoresist is completely stripped, and the a-Si material of the conductive channel region remains to form an undoped active layer, so that only one mask process is needed in the present invention.
- the invention can simultaneously form a source, a drain and a doped active layer and an undoped active layer, a mask process of adding a TFT gate, and a transparent conductive layer of the TFT pixel electrode also requires a mask process, the present invention Only three mask processes are required to make the entire array substrate. Compared with the existing four-way and five-mask process, the process time is reduced, the manufacturing cost is reduced, and the step of the process is also beneficial to improve the yield.
- FIG. 2 is a schematic diagram of a step b of the embodiment of the present invention
- FIG. 3 is a schematic diagram of a step c of the embodiment of the present invention
- Figure 5 is a schematic diagram of a step e of the embodiment of the present invention
- Figure 6 is a schematic view of step f of the embodiment of the present invention
- Figure 7 is a schematic view of a step g of the embodiment of the present invention
- Figure 8 is a schematic diagram of step h of the embodiment of the present invention.
- FIG. 9 is a schematic diagram of a step i of the embodiment of the present invention.
- Figure 10 is a schematic diagram of step j of the embodiment of the present invention.
- Figure 11 is a schematic view showing a step k of the embodiment of the present invention.
- Figure 12 is a schematic view of step 1 of the embodiment of the present invention.
- Figure 13 is a schematic view of a step m of the embodiment of the present invention.
- Figure 14 is a schematic view of a step n of the embodiment of the present invention.
- Figure 15 is a schematic overall view of the array substrate of the present invention.
- 100 a first metal layer; 110, a gate; 210, a first photoresist; 220, a second photoresist; 230, a third photoresist; 300, an insulating layer; 400, a second metal layer; Drain; 420, source; 510, doped active layer; 520, undoped active layer; 600, transparent conductive layer; 700, conductive channel; 810 scan line; 820, data line.
- the invention discloses a liquid crystal display device, which comprises an array substrate. As shown in FIG. 15, the array substrate is provided with a vertical and horizontal scanning line 810 and a data line 820, and a thin film transistor (TFT). The source of the TFT is connected to the data line, the gate is connected to the scan line, and the drain is connected to the TFT. The pixel electrode is connected.
- TFT thin film transistor
- the TFT structure of the present invention includes, in order from the bottom, a gate 110, an insulating layer 300, a metal layer, and a doped active layer 510, and a conductive channel 700 is disposed in a region above the gate. Cutting the doped active layer and the metal layer, the cut metal layer is divided into a source 420 and a drain 410, and the source and drain surfaces are covered with a transparent conductive layer 600, the doped active layer surface and the conductive trench The track is covered with an undoped active layer 520.
- the doped active layer is made of an n+a-Si material; the undoped active layer is made of an a-Si material.
- each TFT structure is axisymmetric about its conductive channel centerline.
- the transparent conductive layer forms the pixel electrode of the TFT, so the transparent conductive layer only covers the drain It is feasible, but the transparent conductive layer is also laid on the source, which can protect the source. In addition, the transparent conductive layer on the source can be formed synchronously with the transparent conductive layer on the drain without additional process. Therefore, the impact on costs is also small.
- the present invention also discloses a method of fabricating the above array substrate, and the present invention will be further described below in conjunction with the accompanying drawings and preferred embodiments.
- the first photoresist is coated on the first metal layer, and then the pattern of the scan lines of the array substrate and the gate of the TFT is formed by exposure and development, that is, the first light is formed.
- an insulating layer (SiNx material), a second metal layer 400, and an n+a-Si film layer are sequentially deposited on the substrate;
- a second photoresist is coated on the n+a-Si film layer, and a second photoresist is formed by exposure and development, and the second photoresist forms a "T" in the upper region of the gate.
- a shaped notch the notch being divided into a first square notch at the bottom, and a second square notch at the opening; the second square notch width being greater than the width of the first square notch;
- the exposed second metal layer is continued to be etched to form the source and drain of the TFT and the data line of the array substrate.
- a conductive channel 700 is formed between the cut n+ a-Si film layer and the second metal layer, which is equal to the first square notch;
- the second photoresist is ashed, the thickness of the photoresist is thinned, and the first square notch disappears.
- the n+a-Si film covered at both ends of the first square notch is covered.
- the layer is exposed; i, as shown in FIG. 9, depositing an a-Si film layer on the substrate, the a-Si film layer covering the exposed n+ a-Si film layer and the surface of the conductive channel;
- the second photoresist is stripped, the a-Si film layer covering the photoresist surface is removed together, and the remaining a-Si film layer forms the undoped active layer 520;
- a third photoresist is used, and then a third photoresist 230 is formed in the region where the undoped active layer is located by exposure and development;
- a transparent conductive layer 600 (such as ITO) is deposited on the substrate, and the transparent conductive layer is respectively connected to the source and drain of the TFT;
- the entire process requires only three mask mask processes to produce the entire array substrate. Compared with the existing four-channel and five-mask process, the process time is reduced and the process time is reduced. The manufacturing cost and the step of the process are also beneficial to improve the yield.
- the third photoresist can cover one side of the entire source region. After the transparent conductive layer is deposited and the third photoresist is stripped, the transparent conductive layer is not present in the source portion, and the transparent conductive layer is formed only in the drain portion.
- step k The difference between this embodiment and the first embodiment starts from step k.
- the third photoresist is used in the first embodiment, and then the area where the undoped active layer is left is exposed and developed.
- ITO transparent conductive layer
- the third photoresist can cover one side of the entire source region, and after subsequently depositing the transparent conductive layer and stripping the third photoresist, the source The transparent portion is not present in the pole portion, and the transparent conductive layer is formed only in the drain portion. It is to be understood that the specific embodiments of the invention are limited only by the description. It will be apparent to those skilled in the art that the present invention can be made without departing from the spirit and scope of the invention.
Abstract
一种阵列基板的制作方法、阵列基板和液晶显示装置,该方法包括步骤:A、采用第一道掩模制程,在基材表面形成扫描线(810)和TFT的闸极(110);B、采用第二道掩模制程,形成阵列基板的数据线(820)、TFT的源极(420)和漏极(410)、及位于源极(420)和漏极(410)之间的导电沟道(700);C、对第二道掩模制程形成的光阻进行灰化处理,然后在阵列基板表面铺设一层a—Si膜层;D、剥离光阻,在惨杂有源层(510)的表面形成非惨杂有源层(520);E、采用第三道掩模制程,在TFT的漏极(410)表面形成透明导电层(600)。由于只需要三道掩模制程就能制作出整个阵列基板,减少了制程时间,降低了制造成本,步骤的简化也有利于提升良品率。
Description
一种阵列基板的制作方法、 阵列基板和液晶显示装置
【技术领域】
本发明涉及显示领域, 更具体的说, 涉及一种阵列基板的制作方法、 阵列 基板和液晶显示装置。
【背景技术】
在平板显示装置中, 薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Dsiplay, 筒称 TFT-LCD )具有体积小、 功耗低、 制造成本相对较低和无 辐射等特点, 在当前的平板显示器市场中占据了主导地位。 TFT-LCD是由阵列 基板和彩膜基板对合形成的,其中阵列基板目前较主流是采用 5次掩模(5 mask ) 或 4次掩模 ( 4 mask )工艺制造。 每一道光罩掩模制造工艺中都需要经历清洗、 干燥、 成膜、 光刻等几个步骤, 因现在有技术中制程工艺中的流程较多, 不可 避免的存在着制程时间较长, 良率较低、 成本高等问题。
【发明内容】
本发明所要解决的技术问题是提供一种工艺流程少、 低成本、 高良品率的 阵列基板的制作方法、 阵列基板和液晶显示装置。
本发明的目的是通过以下技术方案来实现的:
一种阵列基板的制作方法, 包括步骤:
A、 采用第一道掩膜制程, 在基材表面形成扫描线和 TFT的闸极;
B、 在基材上依次铺设绝缘层、 第二金属层和 n+a-Si膜层, 然后通过采用第 二道掩膜制程, 形成阵列基板的扫描线数据线、 TFT 的源极和漏极、 及位于源 极和漏极之间的导电沟道;
C、 对第二道掩膜制程形成的光阻进行灰化处理, 曝露出导电沟道两端的 n+a-Si膜层, 然后在阵列基板表面铺设一层 a-Si膜层, 形成的 a-Si膜层跟导电 沟道两端的 n+a-Si膜层可靠电连接;
D、 剥离光阻, 将覆盖在光阻表面的 a-Si材料一并去除, 剩余的 a-Si膜层 形成非掺杂有源层;
E、 采用第三道掩膜制程, 保留非掺杂有源层覆盖部分的 n+a-Si膜层, 形成 掺杂有源层, 然后在 TFT的漏极表面形成透明导电层。
优选的, 所述步骤 E中, 以非掺杂有源层为掩体, 蚀刻掉非掺杂有源层覆 盖部分以外的 n+a-Si膜层,形成掺杂有源层,然后再利用第三道掩膜制程在 TFT 表面形成透明导电层。 此为一种掺杂有源层的具体制作工艺。
优选的, 所述步骤 E中, 先采用掩膜制程在阵列基板表面形成透明导电层 的图案, 然后通过曝光、 显影、 蚀刻的方式去除非掺杂有源层覆盖部分以外的 n+a-Si材料, 保留的 n+a-Si材料形成掺杂有源层; 然后铺设一层透明导电胶体, 剥离剩余的光刻胶及其表面覆盖的导电胶体, 形成所述透明导电层。 此为另一 种掺杂有源层的具体制作工艺。
优选的, 所述步骤 E中, 利用掩膜制程在 TFT的源极和漏极表面同步形成 透明导电层。 源极上也铺设透明导电层, 对源极来说可以起到保护作用, 另外 源极上的透明导电层可以跟漏极上的透明导电层同步形成, 无须额外增加制程。
优选的, 所述步骤 A中, 包括步骤:
Al、 在基材上沉积第一金属层;
A2、 在第一金属层上涂布第一道光刻胶, 然后通过曝光、 显影, 做出阵列 基板的扫描线和 TFT的闸极的图案, 即形成第一道光阻;
A3、 对第一金属层进行蚀刻, 然后剥离第一道光阻, 形成阵列基板的扫描 线和 TFT的闸极;
所述步骤 B包括:
Bl、 依次在基板上沉积绝缘层、 第二金属层和 n+a-Si膜层;
B2、 在 n+a-Si膜层上涂布第二道光刻胶, 通过曝光、 显影, 形成第二道光 阻, 第二道光阻在闸极上方区域形成缺口, 缺口分为底部的第一方形缺口, 以 及位于开口处的第二方形缺口; 第二方形缺口宽度大于第一方形缺口的宽度;
B3、 以第二道光阻为掩体, 蚀刻掉第一方形缺口处的 n+a-Si膜层材料; B4、 第一方形缺口处的 n+a-Si膜层材料掉以后, 继续蚀刻暴露出来的第二 金属层, 形成 TFT的源极、 漏极以及阵列基板的数据线; 同时, 切断的 n+a-Si 膜层和第二金属层之间也形成了跟第一方形缺口等宽的导电沟道;
所述步骤 C包括:
Cl、 对第二道光阻进行灰化处理, 使其厚度减薄, 将第一方形缺口两端覆 盖下的 n+a-Si膜层暴露出来;
C2、 在基材上沉积 a-Si膜层, a-Si膜层覆盖暴露的 n+a-Si膜层和导电沟道 的表面;
所述步骤 E包括:
El、 以非掺杂有源层为掩体, 蚀刻掉非掺杂有源层覆盖区域以外的 n+a-Si 膜层材料, 残留的 n+a-Si膜层形成掺杂的有源层;
E2、 采用第三道光刻胶, 然后通过曝光、 显影, 在非掺杂有源层所在的区 域形成第三道光阻;
E3、在基材上沉积透明导电层,透明导电层覆盖在 TFT的源极和漏极表面;
E4、 剥离第三道光阻, 连同第三道光阻表面的透明导电层一并去除, 形成 TFT的像素电极。
此为一种具体的阵列基板的制作方法。
优选的, 所述步骤 E中, 利用掩膜制程在 TFT的源极和漏极表面同步形成 透明导电层。 源极表面也覆盖透明导电层, 可以对源极起到保护作用, 另外源 极上的透明导电层可以跟漏极上的透明导电层同步形成, 无须额外增加制程。
一种阵列基板, 包括一种 TFT结构, 所述 TFT结构从底部算起, 依次包括 闸极、 绝缘层、 金属层、 掺杂有源层, 所述闸极上方区域设有导电沟道, 所述 导电沟道切断所述掺杂有源层和金属层, 切断的金属层分为源极和漏极, 所述 漏极表面覆盖有透明导电层, 所述掺杂有源层表面及导电沟道内覆盖有非掺杂 有源层。
优选的, 所述源极表面也覆盖有透明导电层。 源极上也铺设透明导电层, 对源极来说可以起到保护作用, 另外源极上的透明导电层可以跟漏极上的透明 导电层同步形成, 无须额外增加制程。
优选的, 所述 TFT结构关于导电沟道中心线轴对称。 采用对称结构可以筒 化设计, 降低设计成本。
优选的, 所述掺杂有源层采用 n+a-Si材料; 所述非掺杂有源层采用 a-Si材 料。 此为一种具体的掺杂有源层和非掺杂有源层的材料。
一种液晶显示装置, 包括上述的一种阵列基板。
本发明采用有掺杂有源层、 非掺杂有源层在上方, 而源极、 漏极位于下方 的结构, 采用一道掩膜制程就能同时形成源极、 漏极和掺杂有源层, 而通过光 刻胶的灰化, 将光刻胶厚度减薄, 这样位于导电沟道两端位置较高的掺杂有源 层就暴漏出来, 此时再铺设 a-Si材料, 将导电沟道两端的掺杂有源层连接起来, 最后将光刻胶全部剥离, 导电沟道区域的 a-Si材料保留, 形成非掺杂有源层, 因此采用本发明只需要一道掩膜制程就能同时形成源极、 漏极和掺杂有源层和 非掺杂有源层, 加上 TFT闸极的一道掩膜制程, 以及 TFT像素电极的透明导电 层也需要一道掩膜制程, 本发明只需要三道掩膜制程就能制作出整个阵列基板, 相比现有的四道、 五道掩膜制程, 减少了制程时间, 降低了制造成本, 步骤的 筒化也有利于提升良品率。
【附图说明】
图 1是本发明实施例一步骤 a示意图
图 2是本发明实施例一步骤 b示意图
图 3是本发明实施例一步骤 c示意图
图 4是本发明实施例一步骤 d示意图
图 5是本发明实施例一步骤 e示意图
图 6是本发明实施例一步骤 f示意图
图 7是本发明实施例一步骤 g示意图;
图 8是本发明实施例一步骤 h示意图;
图 9是本发明实施例一步骤 i示意图;
图 10是本发明实施例一步骤 j示意图;
图 11是本发明实施例一步骤 k示意图;
图 12是本发明实施例一步骤 1示意图;
图 13是本发明实施例一步骤 m示意图;
图 14是本发明实施例一步骤 n示意图;
图 15是本发明阵列基板整体示意图;
其中: 100、 第一金属层; 110、 闸极; 210、 第一道光阻; 220、 第二道光 阻; 230、 第三道光阻; 300、 绝缘层; 400、 第二金属层; 410、 漏极; 420、 源 极; 510、 掺杂有源层; 520、 非掺杂有源层; 600、 透明导电层; 700、 导电沟 道; 810扫描线; 820、 数据线。
【具体实施方式】
本发明公开了一种液晶显示装置, 液晶显示装置包括一种阵列基板。 如图 15所示, 阵列基板上设有纵横交错的扫描线 810和数据线 820, 以及薄膜晶体 管(TFT ), TFT的源极跟数据线连接, 闸极跟扫描线连接, 漏极跟 TFT的像素 电极连接。
如图 14所示, 本发明的 TFT结构从底部算起, 依次包括闸极 110、 绝缘层 300、 金属层、 掺杂有源层 510, 闸极上方区域设有导电沟道 700, 导电沟道切 断所述掺杂有源层和金属层, 切断的金属层分为源极 420和漏极 410, 源极和漏 极表面覆盖有透明导电层 600,所述掺杂有源层表面及导电沟道内覆盖有非掺杂 有源层 520。 掺杂有源层采用 n+a-Si材料; 非掺杂有源层采用 a-Si材料。 本发 明中, 每个 TFT结构关于其导电沟道中心线轴对称。
当然, 透明导电层形成 TFT的像素电极, 因此透明导电层仅覆盖漏极也是
可行的, 只不过源极上也铺设透明导电层, 对源极来说可以起到保护作用, 另 外源极上的透明导电层可以跟漏极上的透明导电层同步形成, 无须额外增加制 程, 因此对成本的影响也很小。
本发明还公开了上述阵列基板的制造方法, 下面结合附图和较佳的实施例 对本发明作进一步说明。
实施例一
此为最佳实施方式, 包括步骤:
a、 如图 1所述, 在洗净、 干燥后的基材上沉积第一金属层 100;
b、 如图 2所示, 在第一金属层上涂布第一道光刻胶, 然后通过曝光、 显影, 做出阵列基板的扫描线和 TFT的闸极的图案, 即形成第一道光阻 210;
c、 如图 3所示, 对第一金属层进行蚀刻, 然后剥离第一道光阻, 形成阵列 基板的扫描线和 TFT的闸极;
d、 如图 4所示, 依次在基板上沉积绝缘层( SiNx材质)、 第二金属层 400 和 n+a-Si膜层;
e、 如图 5所示, 在 n+a-Si膜层上涂布第二道光刻胶, 通过曝光、 显影, 形 成第二道光阻, 第二道光阻在闸极上方区域形成一个 "T" 形缺口, 缺口分为底 部的第一方形缺口, 以及位于开口处的第二方形缺口; 第二方形缺口宽度大于 第一方形缺口的宽度;
f、如图 6所示,以第二道光阻 220为掩体,蚀刻掉第一方形缺口处的 n+a-Si 膜层材料;
g、 如图 7所示, 第一方形缺口处的 n+a-Si膜层材料掉以后, 继续蚀刻暴露 出来的第二金属层, 形成 TFT的源极、 漏极以及阵列基板的数据线; 同时, 切 断的 n+a-Si膜层和第二金属层之间也形成了跟第一方形缺口等宽的导电沟道 700;
h、 如图 8所示, 对第二道光阻进行灰化处理, 光阻的厚度减薄, 第一方形 缺口消失, 此时第一方形缺口两端覆盖下的 n+a-Si膜层暴露出来;
i、 如图 9所示, 在基材上沉积 a-Si膜层, a-Si膜层覆盖暴露的 n+a-Si膜层 和导电沟道的表面;
j、如图 10所示,剥离第二道光阻,将覆盖在光阻表面的 a-Si膜层一并去除, 残留的 a-Si膜层形成非掺杂有源层 520;
k、 如图 11 所示, 以非掺杂有源层为掩体, 蚀刻掉非掺杂有源层覆盖区域 以外的 n+a-Si膜层材料, 残留的 n+a-Si膜层形成掺杂的有源层 510;
1、 如图 12所示, 采用第三道光刻胶, 然后通过曝光、 显影, 在非掺杂有源 层所在的区域形成第三道光阻 230;
m、 如图 13所示, 在基材上沉积透明导电层 600 (如 ITO ), 透明导电层分 别 3艮 TFT的源极和漏极连接;
n、 如图 14所示, 剥离第三道光阻, 连同第三道光阻表面的透明导电层一 并去除, 形成 TFT的像素电极;
至此, 整个阵列基板的必要部件全部形成, 整个制程只需要采用三道光罩 掩膜工艺就能制作出整个阵列基板, 相比现有的四道、 五道掩膜制程, 减少了 制程时间, 降低了制造成本, 步骤的筒化也有利于提升良品率。
当然, 第三道光阻可以覆盖整个源极区域的一侧, 后续沉积透明导电层并 剥离第三道光阻以后, 源极部分就不存在透明导电层, 而仅在漏极部分形成透 明导电层。
实施方式二
本实施方式跟实施方式一的区别从步骤 k开始, 形成非掺杂有源层以后, 本实施方式先采用第三道光刻胶, 然后通过曝光、 显影, 保留非掺杂有源层所 在区域的第三道光阻, 以第三道光阻为掩体, 蚀刻掉暴漏的 n+a-Si膜层, 残留 的 n+a-Si膜层形成掺杂的有源层; 最后, 在基材上沉积透明导电层(如 ITO ), 透明导电层分别跟 TFT的源极和漏极连接, 然后剥离第三道光阻, 连同第三道 光阻表面的透明导电层一并去除, 形成 TFT的像素电极。 当然, 第三道光阻可 以覆盖整个源极区域的一侧, 后续沉积透明导电层并剥离第三道光阻以后, 源
极部分就不存在透明导电层, 而仅在漏极部分形成透明导电层。 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通 技术人员来说, 在不脱离本发明构思的前提下, 还可以做出若干筒单推演或替 换, 都应当视为属于本发明的保护范围。
Claims
1、 一种阵列基板的制作方法, 包括步骤:
A、 采用第一道掩膜制程, 在基材表面形成扫描线和 TFT的闸极;
B、 在基材上依次铺设绝缘层、 第二金属层和 n+a-Si膜层, 然后通过采用第 二道掩膜制程, 形成阵列基板的扫描线数据线、 TFT 的源极和漏极、 及位于源 极和漏极之间的导电沟道;
C、 对第二道掩膜制程形成的光阻进行灰化处理, 曝露出导电沟道两端的 n+a-Si膜层, 然后在阵列基板表面铺设一层 a-Si膜层, 形成的 a-Si膜层跟导电 沟道两端的 n+a-Si膜层可靠电连接;
D、 剥离光阻, 将覆盖在光阻表面的 a-Si材料一并去除, 剩余的 a-Si膜层 形成非掺杂有源层;
E、 采用第三道掩膜制程, 保留非掺杂有源层覆盖部分的 n+a-Si膜层, 形成 掺杂有源层, 然后在 TFT的漏极表面形成透明导电层。
2、 如权利要求 1所述的一种阵列基板的制作方法, 其中, 所述步骤 E中, 利用掩膜制程在 TFT的源极和漏极表面同步形成透明导电层。
3、 如权利要求 1所述的一种阵列基板的制作方法, 其中, 所述步骤 E中, 以非掺杂有源层为掩体, 蚀刻掉非掺杂有源层覆盖部分以外的 n+a-Si膜层, 形 成掺杂有源层, 然后再利用第三道掩膜制程在 TFT表面形成透明导电层。
4、 如权利要求 3所述的一种阵列基板的制作方法, 其中, 所述步骤 E中, 利用掩膜制程在 TFT的源极和漏极表面同步形成透明导电层。
5、 如权利要求 1所述的一种阵列基板的制作方法, 其中, 所述步骤 E中, 先采用掩膜制程在阵列基板表面形成透明导电层的图案, 然后通过曝光、 显影、 蚀刻的方式去除非掺杂有源层覆盖部分以外的 n+a-Si材料, 保留的 n+a-Si材料 形成掺杂有源层; 然后铺设一层透明导电胶体, 剥离剩余的光刻胶及其表面覆 盖的导电胶体, 形成所述透明导电层。
6、 如权利要求 5所述的一种阵列基板的制作方法, 其中, 所述步骤 E中, 利用掩膜制程在 TFT的源极和漏极表面同步形成透明导电层。
7、 如权利要求 1所述的一种阵列基板的制作方法, 其中, 所述步骤 A中, 包括步骤:
Al、 在基材上沉积第一金属层;
A2、 在第一金属层上涂布第一道光刻胶, 然后通过曝光、 显影, 做出阵列 基板的扫描线和 TFT的闸极的图案, 即形成第一道光阻;
A3、 对第一金属层进行蚀刻, 然后剥离第一道光阻, 形成阵列基板的扫描 线和 TFT的闸极;
所述步骤 B包括:
Bl、 依次在基板上沉积绝缘层、 第二金属层和 n+a-Si膜层;
B2、 在 n+a-Si膜层上涂布第二道光刻胶, 通过曝光、 显影, 形成第二道光 阻, 第二道光阻在闸极上方区域形成缺口, 缺口分为底部的第一方形缺口, 以 及位于开口处的第二方形缺口; 第二方形缺口宽度大于第一方形缺口的宽度; B3、 以第二道光阻为掩体, 蚀刻掉第一方形缺口处的 n+a-Si膜层材料; B4、 第一方形缺口处的 n+a-Si膜层材料掉以后, 继续蚀刻暴露出来的第二 金属层, 形成 TFT的源极、 漏极以及阵列基板的数据线; 同时, 切断的 n+a-Si 膜层和第二金属层之间也形成了跟第一方形缺口等宽的导电沟道;
所述步骤 C包括:
Cl、 对第二道光阻进行灰化处理, 使其厚度减薄, 将第一方形缺口两端覆 盖下的 n+a-Si膜层暴露出来;
C2、 在基材上沉积 a-Si膜层, a-Si膜层覆盖暴露的 n+a-Si膜层和导电沟道 的表面;
所述步骤 E包括:
El、 以非掺杂有源层为掩体, 蚀刻掉非掺杂有源层覆盖区域以外的 n+a-Si 膜层材料, 残留的 n+a-Si膜层形成掺杂的有源层;
E2、 采用第三道光刻胶, 然后通过曝光、 显影, 在非掺杂有源层所在的区 域形成第三道光阻;
E3、在基材上沉积透明导电层,透明导电层覆盖在 TFT的源极和漏极表面; E4、 剥离第三道光阻, 连同第三道光阻表面的透明导电层一并去除, 形成 TFT的像素电极。
8、 如权利要求 7所述的一种阵列基板的制作方法, 其中, 所述步骤 E中, 利用掩膜制程在 TFT的源极和漏极表面同步形成透明导电层。
9、 一种阵列基板, 包括一种 TFT结构, 所述 TFT结构从底部算起, 依次 包括闸极、 绝缘层、 金属层、 掺杂有源层, 所述闸极上方区域设有导电沟道, 所述导电沟道切断所述掺杂有源层和金属层, 切断的金属层分为源极和漏极, 所述漏极表面覆盖有透明导电层, 所述掺杂有源层表面及导电沟道内覆盖有非 掺杂有源层。
10、 如权利要求 9所述的一种阵列基板, 其中, 所述源极表面也覆盖有透 明导电层。
11、 如权利要求 10所述的一种阵列基板, 其中, 所述 TFT结构关于导电沟 道中心线轴对称。
12、如权利要求 9所述的一种阵列基板, 其中, 所述掺杂有源层采用 n+a-Si 材料; 所述非掺杂有源层采用 a-Si材料。
13、 一种液晶显示装置, 包括一种阵列基板, 所述阵列基板包括一种 TFT 结构, 所述 TFT结构从底部算起, 依次包括闸极、 绝缘层、 金属层、 掺杂有源 层, 所述闸极上方区域设有导电沟道, 所述导电沟道切断所述掺杂有源层和金 属层, 切断的金属层分为源极和漏极, 所述漏极表面覆盖有透明导电层, 所述 掺杂有源层表面及导电沟道内覆盖有非掺杂有源层。
14、 如权利要求 13所述的一种液晶显示装置, 其中, 所述源极表面也覆盖 有透明导电层。
15、 如权利要求 14所述的一种液晶显示装置, 其中, 所述 TFT结构关于导
电沟道中心线轴对称。
16、 如权利要求 13所述的一种液晶显示装置, 其中, 所述掺杂有源层采用 n+a-Si材料; 所述非掺杂有源层采用 a-Si材料。
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