WO2020024345A1 - Tft 阵列基板的制造方法及 tft 阵列基板 - Google Patents

Tft 阵列基板的制造方法及 tft 阵列基板 Download PDF

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Publication number
WO2020024345A1
WO2020024345A1 PCT/CN2018/101840 CN2018101840W WO2020024345A1 WO 2020024345 A1 WO2020024345 A1 WO 2020024345A1 CN 2018101840 W CN2018101840 W CN 2018101840W WO 2020024345 A1 WO2020024345 A1 WO 2020024345A1
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layer
photoresist
photoresist block
tft array
array substrate
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PCT/CN2018/101840
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English (en)
French (fr)
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朱茂霞
徐洪远
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深圳市华星光电技术有限公司
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Priority to US16/308,631 priority Critical patent/US20200035709A1/en
Publication of WO2020024345A1 publication Critical patent/WO2020024345A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer

Definitions

  • the present invention relates to the field of flat panel display technology, and particularly to a method for manufacturing a TFT array substrate and a TFT array substrate.
  • a TFT Thin Film Transistor
  • a commonly used TFT is a three-terminal device. Generally, an active layer is prepared on a glass substrate, and a source and a drain are connected to the two ends of the TFT. The voltage between the source and the drain is used to control the current between the source and the drain. .
  • the more commonly used methods for preparing TFTs on glass substrates are back channel etch type and etch stop type. Etch barrier type requires an additional layer of etch barrier. Generally, 5 masks are used, which will increase the manufacturing cost, and it is no longer a mainstream process.
  • the back-channel etch type only needs 4 photomasks to make a TFT, which can greatly save preparation costs and improve production efficiency.
  • back-channel etched structures are used as the main method for TFT fabrication in the factory.
  • the channels in the back channel etch type active layer are etched by dry etching gas, which further causes semiconductors.
  • the electrical properties of the back channel deteriorate, which further affects the use effect of the TFT array substrate.
  • the channels in the back-channel etch-type active layer are caused to be dry-etched by the gas. Etching further deteriorates the electrical properties of the TFT array substrate.
  • the invention provides a method for manufacturing a TFT array substrate.
  • the method includes:
  • S10 Provide a substrate, prepare a gate on a surface of the substrate, and deposit a gate insulating layer and a semiconductor thin film on the gate and the substrate;
  • the part of the first photoresist block and the part of the second photoresist block are peeled off to form a source and a drain.
  • the S20 further includes:
  • the exposed photoresist layer is removed to form a first photoresist block and a second photoresist block spaced apart from each other.
  • the photomask is a half-tone mask or a gray-tone mask.
  • the gas used in the ashing treatment in S40 is oxygen, and the ashing time is between 20 seconds and 100 seconds.
  • the thickness of the first photoresist block is greater than the thickness of the second photoresist block.
  • the thickness of the part of the first photoresist block is smaller than the thickness of the first photoresist block, and the thickness of the part of the second photoresist block is less than the thickness of the second photoresist block.
  • the active layer in the lateral etching structure is retracted.
  • a material of the ohmic contact layer is amorphous silicon doped with phosphorus, and a material of the metal layer is copper.
  • the thickness of the active layer is 30-50 nm, and the thickness of the source-drain metal layer is 450-500 nm.
  • the invention also provides a TFT array substrate, including:
  • a gate insulating layer located on the surface of the substrate and covering the gate
  • An active layer is located on the surface of the gate insulating layer.
  • the active layer is a channel structure with the same shape as the gate.
  • the active layer includes a channel, a source doped region, and a drain doped region. Miscellaneous area
  • An ohmic contact layer located in the source doped region and the drain doped region;
  • the passivation layer is located on the surface of the gate insulating layer and completely covers the active layer and the source and drain metal layer.
  • a material of the ohmic contact layer is amorphous silicon doped with phosphorus, and a material of the metal layer is copper.
  • the thickness of the active layer is 30-50 nm, and the thickness of the source-drain metal layer is 450-500 nm.
  • the TFT array substrate manufacturing method and the TFT array substrate provided by the present invention form photoresist layers with different thicknesses on the back channel of the TFT array substrate, and use an exfoliation process to form an ohmic contact layer and a source and drain metal layer, thereby avoiding the first
  • the back channel is etched when the source and drain metal layers are formed by the second dry etching to further protect the back channel of the active layer.
  • FIG. 1 is a flowchart of a manufacturing method of a TFT array substrate according to the present invention.
  • 1A-1G are schematic diagrams of a manufacturing method of the TFT array substrate shown in FIG. 1.
  • FIG. 2 is a schematic structural diagram of a TFT array substrate according to the present invention.
  • the back-channel etch-type four-channel photomask patterning process technology Because the back-channel etch-type semiconductor back channel is subjected to two dry etching processes, the active layer back channel is damaged.
  • the dry etching gas etching further causes the technical problem of the electrical deterioration of the semiconductor back channel. This embodiment can solve this defect.
  • the present invention provides a method for preparing a TFT array substrate.
  • the method includes:
  • a substrate 101 is provided.
  • a gate 102 is prepared on a surface of the substrate 101, and a gate insulating layer 103 and a semiconductor thin film 104 are deposited on the gate 102 and the substrate 101.
  • the S10 further includes:
  • the substrate 101 is a glass substrate; firstly, the substrate 101 is cleaned with a cleaning solution such as pure water or hot sulfuric acid, and a metal thin film is formed on the substrate 101 by a sputtering method, and a photolithography process is performed by a mask A gate conductor structure is defined to make the gate 102; and the material of the gate 102 is Mo / AlNd.
  • a cleaning solution such as pure water or hot sulfuric acid
  • a metal thin film is formed on the substrate 101 by a sputtering method, and a photolithography process is performed by a mask
  • a gate conductor structure is defined to make the gate 102; and the material of the gate 102 is Mo / AlNd.
  • a gate insulating layer 103 and a semiconductor thin film 104 are sequentially deposited on the gate 102 by a vapor deposition method; a material of the gate insulating layer 103 is a silicon nitride compound, and a thickness of the gate insulating layer 103 is 300 nm; the material of the semiconductor thin film 104 is amorphous silicon, and the thickness of the semiconductor thin film 104 is 40 nm, as shown in FIG. 1A.
  • Block 106 coating a photoresist layer on the semiconductor thin film 104, performing grayscale exposure on the photoresist layer, patterning the photoresist layer, and forming a first photoresist block 105 and a second photoresist spaced apart from each other. Block 106.
  • the S20 further includes:
  • a photoresist layer is coated on the surface of the semiconductor thin film 104 by a coating process, and the photoresist layer is exposed from bottom to top through a substrate through a photomask to form first photoresist blocks spaced apart from each other.
  • 105 and second photoresist block 106 wherein the photomask is a half-tone mask or a gray-tone mask, which utilizes a part of the light transmittance of the grating, so that the first part of the photoresist layer can be formed without exposure.
  • Thick photoresist the second part of the photoresist layer is semi-exposed to form a thin photoresist, and the photoresist in other areas is completely exposed and developed and removed.
  • the thickness of the first photoresist block 105 is greater than the thickness of the second photoresist block 106, as shown in FIG. 1B.
  • the semiconductor thin film 104 not covered by the first photoresist block 105 and the second photoresist block 106 is removed by an etching process to form an active layer 107.
  • the S30 further includes:
  • the semiconductor thin film 104 is etched for the first time by using the first photoresist block 105 and the second photoresist block 106 as masks through an etching process, and then the semiconductor thin film 104 is defined into a shape and shape.
  • the gate 102 has the same channel structure, and the semiconductor thin film 104 not covered by the first photoresist block 105 and the second photoresist block 106 is removed to form an active layer 107.
  • the active layer 107 includes a channel, a source doped region, and a drain doped region, as shown in FIG. 1C.
  • the first photoresist block 105 and the second photoresist block 106 are subjected to ashing treatment, and a part of the first photoresist block and a part of the second photoresist block 108 are retained.
  • the part of the first photoresist block includes A first sub-block 109 and a second sub-block 110 spaced from each other.
  • the S40 further includes:
  • a part of the first photoresist block and a part of the second photoresist block 108 are obtained.
  • the part of the first photoresist block includes a first sub-block 109 and a second sub-block 110 spaced apart from each other.
  • the first sub-block 109 is located on a channel surface of the active layer 107
  • the second sub-block 110 is located in a drain doped region of the active layer 107
  • a part of the second photoresist block 108 is located at a via hole on the active layer 107, as shown in FIG. 1D.
  • the S50 further includes:
  • An ohmic contact layer film 111 and a metal layer 112 are sequentially deposited on the active layer 107, the gate insulating layer 103, the part of the first photoresist block, and the part of the second photoresist block 108.
  • the ohmic contact layer film 111 and the metal layer 112 are disconnected at edges of the part of the first photoresist block and the part of the second photoresist block 108.
  • the S60 further includes:
  • An ohmic contact layer film 111 and a metal layer 112 are sequentially deposited on the active layer 107, the gate insulating layer 103, the part of the first photoresist block and the part of the second photoresist block 108, and the ohmic contact A layer film 111 is located in the source doped region and the drain doped region, the ohmic contact layer film 111 and the metal layer 112 are in the part of the first photoresist block and the part of the second photoresist The edges of the block 108 are broken.
  • the specific operation can be as follows: a vapor deposition method is used to deposit phosphorus-doped amorphous silicon to form the ohmic contact layer film 111, and then a metal film 112 is deposited on the ohmic contact layer film 111 by a sputtering method; In the lateral etching structure, the ohmic contact layer film 111 and the metal layer 112 are disconnected at edges of the part of the first photoresist block and the part of the second photoresist block 108; The surface of the photoresist block and the part of the second photoresist block 108 covers the ohmic contact layer film 111 and the metal layer 112; because the channel of the active layer 107 has the first sub-block 109, Secondary etching is avoided; the material of the metal layer 112 is metal copper; the thickness of the metal layer 112 is 500 nm, as shown in FIG. 1F.
  • the part of the first photoresist block and the part of the second photoresist block 108 are peeled off to form a source and a drain.
  • the S70 further includes:
  • an array substrate using a back channel etching type TFT element can be obtained, as shown in FIG. 2: a gate electrode 202 of a metal thin film is provided on a glass substrate 201, and the gate electrode 202 A gate insulating layer 203 of silicon nitride and an active layer 204 of amorphous silicon are respectively provided thereon. Above the active layer 204, there are provided ohmic contacts that are cut off and expose the channel insulation protection layer to be exposed. Layer 205 and source-drain metal layer 206, the ohmic contact layer 205 and the source-drain metal layer 206 are completely embedded in the source doped region and the drain doped region in the active Layer 204 surface.
  • a passivation layer 207 made of silicon nitride is also provided on the surface of the source and drain metal layer 206, and an ITO (indium tin oxide) layer is formed on the passivation layer 207 to form an ITO (indium tin oxide) pixel. Electrode 208.
  • the manufacturing method of the TFT array substrate and the TFT array substrate provided by the present invention form photoresist layers with different thicknesses on the back channel of the TFT array substrate, and form an ohmic contact layer and source / drain metal using a lift-off process. Layer, thereby avoiding etching of the back channel when the second dry etching forms the source and drain metal layers, and further protecting the back channel of the active layer.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Thin Film Transistor (AREA)

Abstract

一种TFT阵列基板的制造方法，所述方法包括：提供基板（101），在所述基板（101）表面依次制备栅极（102）、栅极绝缘层（103）以及半导体薄膜（104）；在所述半导体薄膜（104）上涂布光阻层，使所述光阻层图案化；在所述基板（101）表面依次制备欧姆接触层（111）以及金属层（112）；剥离所述光阻层，形成源漏极。一种使用上述TFT阵列基板的制作方法制成的TFT阵列基板。

Description

TFT阵列基板的制造方法及TFT阵列基板 技术领域
本发明涉及属于平板显示技术领域，尤其涉及TFT阵列基板的制造方法及TFT阵列基板。
 背景技术
目前在TFT-LCD中，TFT（Thin Film Transistor，薄膜晶体管）的功能相当于一个开关管。常用的TFT是三端器件，一般在玻璃基板上制备有源层，在其两端有与之相连的源极和漏极，利用施加在栅极上的电压来控制源、漏电极间的电流。在玻璃基板上制备TFT，较常用的方法是背沟道刻蚀型和刻蚀阻挡型。刻蚀阻挡型因为要多加一层刻蚀阻挡层，一般采用5道光罩，会增加制备成本，目前已经不作为主流工艺。而背沟道刻蚀型只需要4道光罩即可做出TFT，可以大大节省制备成本及提高了生产效率。目前厂内均把背沟道刻蚀型结构作为TFT制备的主要方法。但是，目前的4道光罩构图工艺技术中在第二次干刻蚀形成源漏极时，会致使背沟道刻蚀型的有源层中的沟道被干蚀气体蚀刻，进一步会使半导体背沟道的电性恶化，更进一步影响TFT阵列基板的使用效果。
综上所述，现有的背沟道刻蚀型4道光罩构图工艺技术中，由于在第二次干刻蚀形成源漏极时，会致使背沟道刻蚀型的有源层中的沟道被干蚀气体蚀刻，进一步导致了TFT阵列基板的电性恶化的技术问题。
 技术问题
现有的背沟道刻蚀型4道光罩构图工艺技术中，在第二次干刻蚀形成源漏极时，会致使背沟道刻蚀型的有源层中的沟道被干蚀气体蚀刻，进一步导致了TFT阵列基板的电性恶化。
 技术解决方案
本发明提供一种一种TFT阵列基板的制造方法，所述方法包括：
S10，提供基板，在所述基板表面制备栅极，并在所述栅极及所述基板上沉积栅绝缘层和半导体薄膜；
S20，在所述半导体薄膜上涂布光阻层，对所述光阻层进行灰阶曝光，使所述光阻层图案化，形成相互间隔的第一光阻块和第二光阻块；
S30，通过蚀刻制程移除未被所述第一光阻块和所述第二光阻块覆盖的半导体薄膜，形成有源层；
S40，对所述第一光阻块和所述第二光阻块进行灰化处理，保留部分第一光阻块和部分第二光阻块，所述部分第一光阻块包括相互间隔的第一子块和第二子块；
S50，对所述有源层进行刻蚀，使所述有源层与所述部分第一光阻块形成侧向刻蚀结构；
S60，在所述有源层、所述栅绝缘层、所述部分第一光阻块和所述部分第二光阻块上依次沉积欧姆接触层薄膜和金属层，所述欧姆接触层薄膜和所述金属层在所述部分第一光阻块和所述部分第二光阻块的边缘断开；
S70，剥离所述部分第一光阻块和所述部分第二光阻块，形成源漏极。
根据本发明一优选实施例，所述S20还包括：
S201，使用涂布工艺在所述半导体薄膜的表面涂布光阻层；
S202，通过光罩透过所述基板由下而上对所述光阻层进行灰阶曝光，形成厚度不同的所述光阻层；
S203，去除经过曝光的所述光阻层，形成相互间隔的第一光阻块和第二光阻块。
根据本发明一优选实施例，所述光罩为半色调掩模或灰色调掩模。
根据本发明一优选实施例，所述S40中的灰化处理使用的气体为氧气，灰化时间为20秒到100秒之间。
根据本发明一优选实施例，所述第一光阻块的厚度大于所述第二光阻块的厚度。
根据本发明一优选实施例，所述部分第一光阻块的厚度小于所述第一光阻块的厚度，所述部分第二光阻块的厚度小于所述第二光阻块的厚度。
根据本发明一优选实施例，所述侧向刻蚀结构中所述有源层内缩。
根据本发明一优选实施例，所述欧姆接触层的材料为掺杂有磷的非晶硅，所述金属层的材料为铜。
根据本发明一优选实施例，所述有源层的厚度为30~50纳米，所述源漏极金属层的厚度为450~500纳米。
本发明还提供一种TFT阵列基板，包括：
基板；
栅极，位于所述基板表面；
栅极绝缘层，位于所述基板表面并覆盖所述栅极；
有源层，位于所述栅极绝缘层表面，所述有源层为一形状与所述栅极相同的一通道结构，所述有源层包括沟道、源极掺杂区以及漏极掺杂区；
欧姆接触层，位于所述源极掺杂区以及所述漏极掺杂区；
源漏极金属层，位于所述欧姆接触层表面；
钝化层，位于所述栅极绝缘层的表面并完全覆盖所述有源层以及所述源漏极金属层。
根据本发明一优选实施例，所述欧姆接触层的材料为掺杂有磷的非晶硅，所述金属层的材料为铜。
根据本发明一优选实施例，所述有源层的厚度为30~50纳米，所述源漏极金属层的厚度为450~500纳米。
 有益效果
本发明所提供的TFT阵列基板的制造方法及TFT阵列基板，在TFT阵列基板背沟道上形成不同厚度的光阻层，并采用剥离工艺形成欧姆接触层以及源漏极金属层，从而避免了第二次干刻蚀形成源漏极金属层时对背沟道刻蚀，进一步实现了对有源层背沟道的保护。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明TFT阵列基板的制造方法流程图。
图1A-1G为图1所述TFT阵列基板的制造方法示意图。
图2为本发明TFT阵列基板结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的背沟道刻蚀型4道光罩构图工艺技术中，由于背沟道刻蚀型的半导体背沟道会经过两道干法刻蚀工艺，致使有源层背沟道被干蚀气体蚀刻，进一步导致了半导体背沟道的电性恶化的技术问题，本实施例能够解决该缺陷。
如图1所示，本发明提供一种TFT阵列基板制备方法流程，所述方法包括：
S10，提供基板101，在所述基板101表面制备栅极102，并在所述栅极102及所述基板101上沉积栅绝缘层103和半导体薄膜104。
具体的，所述S10还包括：
所述基板101为玻璃基板；首先使用纯水或热硫酸等清洗液将所述基板101洗净，采用溅射法在所述基板101上形成一层金属薄膜，以一道光罩微影蚀刻制程来定义出栅极导体结构用于制作所述栅极102；所述栅极102材料选用Mo/AlNd。然后再用气相沉积法方式在所述栅极102上依次沉积栅极绝缘层103和半导体薄膜104；所述栅极绝缘层103材料为氮化硅化合物，所述栅极绝缘层103的厚度为300nm；所述半导体薄膜104的材料为非晶硅，所述半导体薄膜104的厚度为40nm，如图1A所示。
S20 ，在所述半导体薄膜104上涂布光阻层，对所述光阻层进行灰阶曝光，使所述光阻层图案化，形成相互间隔的第一光阻块105和第二光阻块106。
具体的，所述S20还包括：
首先使用涂布工艺在所述半导体薄膜104的表面涂布光阻层，通过光罩透过所述基板101由下而上对所述光阻层进行曝光，形成相互间隔的第一光阻块105和第二光阻块106；其中，所述光罩为半色调掩模或灰色调掩模，其利用了光栅的部分透光性，可以使所述光阻层的第一部分不曝光形成较厚的光阻，所述光阻层的第二部分半曝光形成较薄的光阻，其他区域的光阻被完全曝光而被显影去掉。所述第一光阻块105的厚度大于所述第二光阻块106的厚度，如图1B所示。
S30 ，通过蚀刻制程移除未被所述第一光阻块105和所述第二光阻块106覆盖的半导体薄膜104，形成有源层107。
具体的，所述S30还包括：
通过蚀刻制程以所述第一光阻块105和所述第二光阻块106为掩膜对所述半导体薄膜104进行第一次刻蚀，进而将所述半导体薄膜104定义出一形状与所述栅极102相同的一通道结构，移除未被所述第一光阻块105和所述第二光阻块106覆盖的半导体薄膜104，形成有源层107。其中，所述有源层107包括包括沟道、源极掺杂区以及漏极掺杂区，如图1C所示。
S40，对所述第一光阻块105和所述第二光阻块106进行灰化处理，保留部分第一光阻块和部分第二光阻块108，所述部分第一光阻块包括相互间隔的第一子块109和第二子块110。
具体的，所述S40还包括：
对所述第一光阻块105和所述第二光阻块106进行灰化处理，使所述第一光阻块105和所述第二光阻块106中较薄的消失，较厚的变薄；所述灰化过程中使用的气体为O 2，灰化时间为20s~100s；所述灰化气体可以使用O 2，灰化时间为40s。经过灰化处理后，得到部分第一光阻块和部分第二光阻块108，所述部分第一光阻块包括相互间隔的第一子块109和第二子块110。其中，所述第一子块109位于所述有源层107的沟道表面，所述第二子块110位于所述有源层107的漏极掺杂区，所述部分第二光阻块108位于所述有源层107上的过孔处，如图1D所示。
S50，对所述有源层107进行刻蚀，使所述有源层107与所述部分第一光阻块形成侧向刻蚀结构。
具体的，所述S50还包括：
采用各向同性气体以所述部分第一光阻块为掩膜对所述有源层107进行刻蚀，使所述有源层107与所述部分第一光阻块产生边缘线宽差异，形成侧向刻蚀结构；所述侧向刻蚀结构中所述有源层107内缩，所述部分第一光阻块在所述TFT阵列基板所对应的平面上的投影覆盖所述有源层107在所述TFT阵列基板所对应的平面上的投影，如图1E所示。
S60，在所述有源层107、所述栅绝缘层103、所述部分第一光阻块和所述部分第二光阻块108上依次沉积欧姆接触层薄膜111和金属层112，所述欧姆接触层薄膜111和所述金属层112在所述部分第一光阻块和所述部分第二光阻块108的边缘断开。
具体的，所述S60还包括：
在所述有源层107、所述栅绝缘层103、所述部分第一光阻块和所述部分第二光阻块108上依次沉积欧姆接触层薄膜111和金属层112，所述欧姆接触层薄膜111位于所述源极掺杂区以及所述漏极掺杂区，所述欧姆接触层薄膜111和所述金属层112在所述部分第一光阻块和所述部分第二光阻块108的边缘断开。可具体操作如下：使用气相沉积法沉积掺杂磷的非晶硅形成所述欧姆接触层薄膜111，再用溅射法在所述欧姆接触层薄膜111上沉积一层金属膜112；因为存在所述侧向刻蚀结构，所述欧姆接触层薄膜111与所述金属层112会在所述部分第一光阻块和所述部分第二光阻块108的边缘断开；所述部分第一光阻块和所述部分第二光阻块108的表面覆盖了所述欧姆接触层薄膜111与所述金属层112；所述有源层107的沟道因为存在所述第一子块109，避免了二次刻蚀；所述金属层112的材料为金属铜；所述金属层112的厚度为500nm，如图1F所示。
S70，剥离所述部分第一光阻块和所述部分第二光阻块108，形成源漏极。
具体的，所述S70还包括：
首先用光阻剥离液去除所述部分第一光阻块和所述部分第二光阻块108，这样，所述部分第一光阻块和所述部分第二光阻块108DE 表面上的所述欧姆接触层薄膜111与所述金属层112一起被去除，所述金属层112形成源漏极，如图1G所示。
根据上述的制作方法，可得到一种采用背沟道刻蚀型的TFT元件的阵列基板，如图2中所示：玻璃基板201上设有金属薄膜的栅极202，在所述栅极202之上分别设有氮化硅的栅极绝缘层203和非晶硅的有源层204，在所述有源层204之上，设有切断的、使沟道绝缘保护层裸露出来的欧姆接触层205和源漏极金属层206，所述欧姆接触层205和所述源漏极金属层206在所述源极掺杂区和所述漏极掺杂区完整的嵌合在所述有源层204表面。所述源漏极金属层206表面上还设有氮化硅为材料的钝化层207,所述钝化层207上还设有ITO（氧化铟锡）层，形成ITO（氧化铟锡）像素电极208。
本发明的有益效果：本发明所提供的TFT阵列基板的制造方法及TFT阵列基板，在TFT阵列基板背沟道上形成不同厚度的光阻层，并采用剥离工艺形成欧姆接触层以及源漏极金属层，从而避免了第二次干刻蚀形成源漏极金属层时对背沟道刻蚀，进一步实现了对有源层背沟道的保护。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种TFT阵列基板的制造方法，其中，所述方法包括：
    S10，提供基板，在所述基板表面制备栅极，并在所述栅极及所述基板上沉积栅绝缘层和半导体薄膜；
    S20，在所述半导体薄膜上涂布光阻层，对所述光阻层进行灰阶曝光，使所述光阻层图案化，形成相互间隔的第一光阻块和第二光阻块；
    S30，通过蚀刻制程移除未被所述第一光阻块和所述第二光阻块覆盖的半导体薄膜，形成有源层；
    S40，对所述第一光阻块和所述第二光阻块进行灰化处理，保留部分第一光阻块和部分第二光阻块，所述部分第一光阻块包括相互间隔的第一子块和第二子块；
    S50，对所述有源层进行刻蚀，使所述有源层与所述部分第一光阻块形成侧向刻蚀结构；
    S60，在所述有源层、所述栅绝缘层、所述部分第一光阻块和所述部分第二光阻块上依次沉积欧姆接触层薄膜和金属层，所述欧姆接触层薄膜和所述金属层在所述部分第一光阻块和所述部分第二光阻块的边缘断开；
    S70，剥离所述部分第一光阻块和所述部分第二光阻块，形成源漏极。
  2. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述S20还包括：
    S201，使用涂布工艺在所述半导体薄膜的表面涂布光阻层；
    S202，通过光罩透过所述基板由下而上对所述光阻层进行灰阶曝光，形成厚度不同的所述光阻层；
    S203，去除经过曝光的所述光阻层，形成相互间隔的第一光阻块和第二光阻块。
  3. 根据权利要求2所述的TFT阵列基板的制造方法，其中，所述光罩为半色调掩模或灰色调掩模。
  4. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述S40中的灰化处理使用的气体为氧气，灰化时间为20秒到100秒之间。
  5. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述第一光阻块的厚度大于所述第二光阻块的厚度。
  6. 根据权利要求5所述的TFT阵列基板的制造方法，其中，所述部分第一光阻块的厚度小于所述第一光阻块的厚度，所述部分第二光阻块的厚度小于所述第二光阻块的厚度。
  7. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述侧向刻蚀结构中所述有源层内缩。
  8. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述欧姆接触层的材料为掺杂有磷的非晶硅，所述金属层的材料为铜。
  9. 根据权利要求1所述的TFT阵列基板的制造方法，其中，所述有源层的厚度为30~50纳米，所述金属层的厚度为450~500纳米。
  10. 一种TFT阵列基板，其中，包括：
    基板；
    栅极，位于所述基板表面；
    栅极绝缘层，位于所述基板表面并覆盖所述栅极；
    有源层，位于所述栅极绝缘层表面，所述有源层为一形状与所述栅极相同的一通道结构，所述有源层包括沟道、源极掺杂区以及漏极掺杂区；
    欧姆接触层，位于所述源极掺杂区以及所述漏极掺杂区；
    源漏极金属层，位于所述欧姆接触层表面；
    钝化层，位于所述栅极绝缘层的表面并完全覆盖所述有源层以及所述源漏极金属层。
  11. 根据权利要求10所述的TFT阵列基板，其中，所述欧姆接触层的材料为掺杂有磷的非晶硅，所述金属层的材料为铜。
  12. 根据权利要求10所述的TFT阵列基板，其中，所述有源层的厚度为30~50纳米，所述金属层的厚度为450~500纳米。
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