WO2013044796A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2013044796A1
WO2013044796A1 PCT/CN2012/081997 CN2012081997W WO2013044796A1 WO 2013044796 A1 WO2013044796 A1 WO 2013044796A1 CN 2012081997 W CN2012081997 W CN 2012081997W WO 2013044796 A1 WO2013044796 A1 WO 2013044796A1
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Prior art keywords
photoresist
layer
region
semi
depositing
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PCT/CN2012/081997
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English (en)
French (fr)
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宁策
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京东方科技集团股份有限公司
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Priority to US13/703,112 priority Critical patent/US9178046B2/en
Publication of WO2013044796A1 publication Critical patent/WO2013044796A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the array substrate and its manufacturing process determine product performance, yield and price.
  • the manufacturing process of TFT-LCD array substrate is gradually simplified. The seven mask process from the beginning has been developed to four based on slit lithography. Sub Mask ( 4 Mask ) process.
  • the fabrication of the array substrate by using the four mask processes mainly includes the following steps: Step S11, forming a gate electrode and a gate line on the substrate; Step S12, depositing an insulating layer on the gate electrode and the gate line; Step S13 Depositing an active layer on the insulating layer; Step S14, depositing a source/drain electrode layer on the active layer; Step S15, depositing a PVX protective layer on the source/drain electrode layer, and forming a via hole on the protective layer; Step S16, Finally, an ITO conductive layer is formed on the protective layer.
  • Step S11 Forming the gate electrode and the gate line by one mask process makes the subsequent process complicated, and the performance of the fabricated array substrate is difficult to be ensured.
  • the thickness of the insulating layer in the prior art is 400 nm, which is thicker, resulting in a longer charging time of the TFT; the thickness of the protective layer is 250 nm, which is thinner, resulting in a capacitance between the data line and the gate line. Larger, it is easy to generate parasitic capacitance (Cgs), which causes crosstalk between the source and drain electrodes and the gate, which affects the display quality.
  • Cgs parasitic capacitance
  • Embodiments of the present invention can simplify the fabrication process of the array substrate, reduce cost, and ensure better performance.
  • An aspect of an embodiment of the present invention provides a method for fabricating an array substrate, including the following steps.
  • Step S1 continuously depositing a gate electrode metal layer, an insulating layer and an active layer on the substrate, and forming a gate electrode, a gate line and an active layer pattern by a first mask process;
  • Step S2 after completing step SI Depositing a protective layer on the substrate, and forming a via hole in the protective layer by a second masking process; and step S3, sequentially depositing the pixel electrode layer and the source/drain electrode metal on the substrate completing step S2 Layers, and source and drain electrodes, pixel electrodes, and data lines are formed by a third mask process.
  • an array substrate fabricated according to the above method for fabricating an array substrate, comprising: a substrate; a gate electrode formed on the substrate; an insulating layer formed on the gate electrode; a source layer formed on the insulating layer; a protective layer formed on the substrate, wherein a via hole is formed; a pixel electrode formed on the protective layer and the active layer, and passing through the via hole and the The active layer is electrically connected; and the source and drain electrodes are formed on the pixel electrode.
  • FIG. 1A is a schematic view showing a process of fabricating an array substrate according to Embodiment 1 of the present invention. detailed description
  • Embodiment 1 of the present invention provides a method for fabricating an array substrate, which simplifies the manufacturing process of the array substrate, reduces the cost, and ensures better performance of the fabricated array substrate.
  • an array substrate is manufactured using a three-mask process.
  • the method for manufacturing an array substrate according to the first embodiment of the present invention includes the following steps: Step S1, continuously depositing a gate electrode metal layer, an insulating layer and an active layer on a substrate, and forming a gate electrode and a gate line through a first mask process And active layer graphics; Step S2, depositing a protective layer on the substrate on which the step S1 is completed, and forming a via hole in the protective layer by a second masking process;
  • Step S3 depositing a pixel electrode layer and a source/drain electrode metal layer on the substrate completing the step S2, and forming a pixel electrode, a source/drain electrode and a data line through a third mask process.
  • step S1 An example of the step S1 is as follows.
  • a gate electrode metal layer on the substrate depositing SiNx or SiOx as an insulating layer on the gate electrode metal layer, depositing an a-Si layer on the insulating layer as an active layer; and then coating the active layer a layer of photoresist; ⁇ exposing the photoresist with a halftone or gray tone mask to form a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist
  • the fully-retained area of the engraved glue corresponds to the area where the active layer pattern is located, the semi-reserved area of the photoresist corresponds to the area where the gate electrode and the gate line are located, and the completely removed area of the photoresist corresponds to the remaining area; after the development process, the photoresist is completely retained
  • the thickness of the photoresist in the region is not changed, the photoresist in the completely removed region of the photoresist is completely removed, and the
  • step S2 An example of the step S2 is as follows.
  • step S3 An example of the step S3 is as follows
  • a pixel electrode layer on the substrate on which step S2 is completed depositing a source/drain electrode metal layer on the pixel electrode layer; applying a layer of photoresist on the source/drain electrode metal layer; and using halftone or gray tone
  • the mask exposes the photoresist to form a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to the source drain electrode and the data line
  • the semi-reserved area of the photoresist corresponds to the area where the pixel electrode is located, and the completely removed area of the photoresist corresponds to the remaining area; after the development process, the thickness of the photoresist in the completely remaining area of the photoresist does not change, and the photoresist is completely removed.
  • the photoresist in the region is completely removed, and the photoresist is semi-reserved.
  • the layer and the pixel electrode layer are removed to form a source/drain electrode and a data line; the photoresist is ashed to remove the photoresist in the semi-reserved region of the photoresist; and the pixel electrode is formed by wet etching; finally, the remaining portion is stripped Photoresist.
  • the insulating layer has a thickness of 200 nm to 400 nm
  • the protective layer has a thickness of 250 ⁇ to 400 ⁇ .
  • the method for fabricating the array substrate of the first embodiment of the present invention includes the following steps;
  • Step S21 continuously depositing a gate electrode metal layer 11, an insulating layer 2, and an active layer 3 on the substrate 7, and forming a gate electrode 1, a gate line, and an active layer pattern by a first mask process;
  • a gate electrode metal layer 11 having a thickness between 200 nm and 400 nm is deposited on the substrate 7 by a magnetron sputtering process for forming the gate electrode 1 for forming the gate electrode 1.
  • the metal may be selected from a metal such as Mo, Cu, or A1; then a layer of SiNx or SiOx having a thickness of between 200 nm and 400 nm is deposited on the gate electrode metal layer 11 by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the gate electrode 1, the gate line and the active layer pattern are then formed by using a first mask process: applying a layer of photoresist on the active layer 3; using a halftone or gray tone mask Exposing the photoresist to form a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to the region where the active layer pattern is located, the light
  • the semi-reserved area of the engraved glue corresponds to the area where the gate electrode 1 and the gate line are located, and the completely removed area of the photoresist corresponds to the remaining area; after the development process, the thickness of the photoresist in the completely remaining area of the photoresist does not change, and the photoresist is completely removed.
  • the photoresist in the region is completely removed, and the thickness of the photoresist in the semi-reserved region of the photoresist is thinned; the active layer 3 is etched by wet etching, and then the insulating layer is dry etched. Etching, and then etching the gate electrode metal layer 11 by wet etching to form the gate electrode 1 and the gate line; then, by the ashing process, the photoresist of the semi-reserved region of the photoresist is completely removed ( Photoresist, PR ) Then, the wet etching process for forming the active layer pattern; and finally, the remaining photoresist is stripped.
  • Step S22 depositing a protective layer 4 on the substrate 7 completing step S21, and forming a via hole 8 in the protective layer 4 by a second mask process;
  • SiNx or SiOx having a thickness of between 250 nm and 400 nm is deposited as a protective layer 4 by PECVD on the substrate 7 on which step S21 is completed; as shown in FIG.
  • a via 8 is formed on the layer 3 to connect the active layer 3 to the source and drain electrode 6 formed later, and to form the TFT channel 9; after the via 8 is formed, doping is formed on the exposed active layer 3.
  • An (n+) contact layer (not shown) of n-type amorphous silicon, so that the active layer 3 and the source-drain electrodes 6 formed later can form an ohmic contact.
  • Step S23 depositing the pixel electrode layer 51 and the source/drain electrode metal layer 61 on the substrate 7 completing the step S22, and forming the source/drain electrode 6, the data line and the pixel electrode 5 through a third mask process;
  • Le shows that an ITO layer 51 having a thickness of between 40 nm and 100 nm is deposited by a magnetron sputtering process on the substrate 7 on which step S22 is completed, for forming the pixel electrode 5, and continuing to deposit source and drain with a thickness between 200 nm and 400 nm.
  • the electrode metal layer 61 is for forming the source and drain electrodes 6.
  • the source/drain electrode 6, the data line and the pixel electrode 5 are formed by a third mask process: a layer of photoresist is applied on the source/drain electrode metal layer 61; ⁇ is masked with halftone or gray
  • the template exposes the photoresist to form a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to the source drain electrode 6 and the data line
  • the photoresist semi-reserved region corresponds to the region where the pixel electrode 5 is located, and the photoresist completely removed region corresponds to the remaining region; after the development process, the photoresist thickness of the photoresist completely reserved region does not change, and the photoresist is completely
  • the photoresist in the removed region is completely removed, the photoresist ITO layer 51 in the semi-reserved region of the photoresist is removed, and the source and drain
  • the embodiment of the present invention saves a mask process by depositing a gate electrode metal layer, an insulating layer and an active layer together and performing photolithography, and can realize the fabrication of the array substrate by only three mask processes, thereby reducing the production cost.
  • the thickness of the insulating layer 2 the charging current Ion when the TFT is opened can be increased, thereby shortening the charging time, and the embodiment of the present invention can reduce the capacitance between the data line and the gate line by increasing the thickness of the protective layer 4, Eliminate the purpose of parasitic capacitance, avoid crosstalk, and ensure the display of shield.
  • a method of fabricating an array substrate according to embodiment 2 of the present invention includes the following steps:
  • Step S1 continuously depositing a gate electrode metal layer, an insulating layer and an active layer on the substrate, and forming a gate electrode, a gate line and an active layer pattern by a first mask process;
  • Step S2 depositing a protective layer on the substrate completing step S1, and forming a via hole in the protective layer by a second mask process;
  • Step S3 depositing a pixel electrode layer and a source/drain electrode metal layer on the substrate completing the step S2, and forming a pixel electrode, a source/drain electrode and a data line through a third mask process.
  • step S1 An example of the step S1 is as follows:
  • a gate electrode metal layer on the substrate depositing SiNx or SiOx as an insulating layer on the gate electrode metal layer, depositing a metal oxide layer as an active layer on the insulating layer; and then coating the active layer a layer of photoresist; ⁇ exposing the photoresist with a halftone or gray tone mask to form a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist
  • the fully-retained area of the engraved glue corresponds to the area where the active layer pattern is located, the semi-reserved area of the photoresist corresponds to the area where the gate electrode and the gate line are located, and the completely removed area of the photoresist corresponds to the remaining area; after the development process, the photoresist is completely retained
  • the thickness of the photoresist in the region is not changed, the photoresist in the completely removed region of the photoresist is completely removed, and the thickness of
  • the metal oxide comprises: an oxidized word, an indium oxide, a gallium, and a mixture thereof.
  • step S2 is as follows:
  • a SiNx or SiOx is deposited as a protective layer on the substrate on which the step S1 is completed, and a via hole is formed on the active layer by a second mask process.
  • step S3 An example of the step S3 is as follows:
  • a pixel electrode layer on the substrate on which step S2 is completed depositing a source/drain electrode metal layer on the pixel electrode layer, and applying a layer of photoresist on the source/drain electrode metal layer; using halftone or gray tone
  • the mask exposes the photoresist to form a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to the source drain electrode and the data line
  • the photoresist semi-reserved area corresponds to the area where the pixel electrode is located, and the photoresist completely removed area corresponds to the remaining area; after the development process, the photoresist completely retains the area of the photoresist
  • the thickness is not changed, the photoresist in the completely removed region of the photoresist is completely removed, the photoresist semi-retained layer and the pixel electrode layer are removed, and the source and drain electrodes and the data lines are formed;
  • the insulating layer has a thickness of 200 nm to 400 nm
  • the protective layer has a thickness of 250 ⁇ to 400 ⁇ .
  • the method for fabricating the array substrate of the second embodiment of the present invention includes the following steps;
  • Step S31 continuously depositing a gate electrode metal layer 11, an insulating layer 2 and an active layer 3 on the substrate 7, and forming a gate electrode 1, a gate line and an active layer pattern by a first masking process;
  • a gate electrode metal layer 11 having a thickness of between 200 nm and 400 nm is deposited on the substrate 7 by a magnetron sputtering process for forming the gate electrode 1, and a metal such as Mo, Cu, or A1 may be selected; and then PECVD is used.
  • a gate electrode 1, a gate line and an active layer pattern by using a first mask process: applying a layer of photoresist on the active layer; and exposing the photoresist with a halftone or gray tone mask,
  • the photoresist is formed into a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to a region where the active layer pattern is located, and the photoresist semi-reserved region corresponds to In the region where the gate electrode 1 and the gate line are located, the photoresist completely removed region corresponds to the remaining region; after the development process, the photoresist thickness in the completely remaining region of the photoresist is not changed, and the photoresist in the completely removed region of the photoresist is completely removed.
  • the thickness of the photoresist in the semi-reserved region of the photoresist is thinned; first etching the active layer 3 and the insulating layer 2 by dry etching; then performing wet etching to form the gate electrode 1 and the gate line; The photoresist is subjected to ashing treatment, and an active layer pattern is formed by dry etching.
  • Step S32 depositing a protective layer 4 on the substrate 7 of the step S31, and forming a via 8 by a second masking process;
  • Step S33 depositing a pixel electrode layer 51 and a source/drain electrode metal layer 61 on the substrate 7 that completes step S32, and forming a source/drain electrode 6, a data line, and a pixel electrode 5 through a third mask process; specifically, in completion On the substrate 7 of step S32, an ITO layer 51 having a thickness of between 40 nm and 100 nm is deposited by a magnetron sputtering process for forming the pixel electrode 5, and the source/drain electrode metal layer 61 having a thickness of between 200 nm and 400 nm is continuously deposited.
  • the source and drain electrodes 6 are formed.
  • the photoresist is formed into a photoresist completely removed region, a photoresist completely reserved region, and a photoresist semi-reserved region, wherein the photoresist completely reserved region corresponds to the source and drain electrode 6 and the data line region, the photoresist
  • the semi-reserved area corresponds to the area where the pixel electrode 5 is located, and the photoresist completely removed area corresponds to the remaining area; after the development process, the photoresist thickness of the photoresist completely reserved area does not change, and the photoresist completely removes the area of the photoresist After being completely removed, the thickness of the photoresist in the semi-reserved region of the photoresist is thinned; except; the
  • the embodiment of the present invention saves a mask process by depositing a gate electrode metal layer, an insulating layer and an active layer together and performing photolithography, and can realize the fabrication of the array substrate by only three mask processes, thereby reducing the production cost.
  • the thickness of the insulating layer 2 the charging current Ion when the TFT is opened can be increased, thereby shortening the charging time, and the embodiment of the present invention can reduce the capacitance between the data line and the gate line by increasing the thickness of the protective layer 4, Eliminate the purpose of parasitic capacitance, avoid crosstalk, and ensure the display of shield.
  • FIG. 3 is a schematic structural diagram of an array substrate according to Embodiment 3 of the present invention.
  • the array substrate of the third embodiment is fabricated by the method in the foregoing embodiment, and includes:
  • the via 8 in the protective layer 4 is connected to the active layer 3.
  • the embodiment of the present invention passes the gate electrode, the insulating layer and the active layer.
  • Depositing and performing photolithography together saves one mask process, and the fabrication of the array substrate can be realized by only three mask processes, which reduces the production cost; further, by reducing the thickness of the insulating layer, the charging current of the TFT is increased, The charging time is shortened, the capacitance between the data line and the gate line is reduced by increasing the thickness of the protective layer, the parasitic capacitance is effectively eliminated, the display quality is ensured, and the performance of the array substrate is optimized.

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Abstract

一种阵列基板及其制作方法，其中阵列基板的制作方法包括以下步骤：步骤S1、在基板（7）上连续沉积栅电极金属层（11），绝缘层（2）和有源层（3），并通过第一次掩模工艺形成栅电极（1）、栅线和有源层图形；步骤S2、在完成步骤S1的基板（7）上沉积保护层（4），并通过第二次掩模工艺在保护层（4）上形成过孔；步骤S3、在完成步骤S2的基板（7）上沉积像素电极层（51）和源漏电极金属层（61），并通过第三次掩模工艺形成像素电极（5）、源漏电极（6）和数据线。

Description

阵列基板及其制作方法 技术领域
本发明的实施例涉及一种阵列基板及其制作方法。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD ) 由于具有体积小、 功耗低以及无辐射等特点， 在当前的平板显示 器领域占据了主导地位。 对于 TFT-LCD 来说， 阵列基板及其制造工艺决定 了产品性能、 成品率和价格。 为了有效地降低 TFT-LCD 的生产成本、 提高 成品率， TFT-LCD阵列基板的制造工艺逐步进行简化，从开始的七次掩模（7 Mask )工艺已经发展到基于狭缝光刻技术的四次掩模 ( 4 Mask )工艺。
现有技术中釆用四次掩模工艺进行阵列基板的制作主要包括以下步骤： 步骤 Sll、 在基板上形成栅电极和栅线； 步骤 S12、 在栅电极和栅线上沉积 绝缘层； 步骤 S13、 在绝缘层上沉积有源层； 步骤 S14、 在有源层上沉积源 漏电极层； 步骤 S15、 在源漏电极层上沉积 PVX保护层， 并在保护层上形成 过孔； 步骤 S16、 最后在保护层上形成 ITO导电层。 其中栅电极的形成、 源 漏电极层、 过孔和氧化铟锡（Indium-Tin Oxide, ITO )导电层的形成均需要 掩模工艺， 因此现有技术中阵列基板的制作共需要四次掩模工艺。 步骤 S11 利用一次掩模工艺形成栅电极和栅线使得后面的工艺复杂， 并且制作的阵列 基板的性能很难得到保证。 另一方面， 现有技术中绝缘层的厚度为 400nm, 这个厚度较厚， 导致 TFT的充电时间较长； 保护层的厚度为 250nm, 这个厚 度较薄， 导致数据线与栅线之间的电容较大， 容易产生寄生电容（Cgs ), 导 致源漏电极和栅极之间发生串扰现象， 影响显示品质。 发明内容
本发明的实施例可以简化阵列基板的制作工艺， 减低成本， 并保证其更 好的性能。
本发明实施例的一个方面提供了一种阵列基板的制作方法， 包括以下步 骤： 步骤 Sl、 在基板上连续沉积栅电极金属层， 绝缘层和有源层， 并通过第 一次掩模工艺形成栅电极、 栅线和有源层图形； 步骤 S2、 在完成步骤 SI的 所述基板上沉积保护层， 并通过第二次掩模工艺在所述保护层中形成过孔； 以及步骤 S3、 在完成步骤 S2的所述基板上顺次沉积像素电极层和源漏电极 金属层， 并通过第三次掩模工艺形成源漏电极、 像素电极和数据线。
本发明实施例的另一个方面提供了一种根据以上阵列基板的制作方法制 作的阵列基板， 包括： 基板； 栅电极， 形成于所述基板上； 绝缘层， 形成于 所述栅电极上； 有源层， 形成于所述绝缘层上； 保护层， 形成于所述基板上， 其中形成有过孔； 像素电极， 形成于所述保护层和有源层上， 且通过所述过 孔与所述有源层电连接； 以及源漏电极， 形成于所述像素电极上。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 la-图 If是本发明实施例一的阵列基板的制作过程示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一
本发明的实施例一提供了阵列基板的制造方法， 其简化了阵列基板的制 作工艺， 减低了成本， 并保证了所制作的阵列基板具有更好的性能。
作为示例， 根据本发明实施例一的阵列基板的制造方法釆用三次掩模工 艺制造阵列基板。根据本发明实施例一的阵列基板的制造方法包括以下步骤： 步骤 Sl、 在基板上连续沉积栅电极金属层、 绝缘层和有源层， 并通过第 一次掩模工艺形成栅电极、 栅线和有源层图形； 步骤 S2、 在完成步骤 SI的所述基板上沉积保护层， 并通过第二次掩模 工艺在所述保护层中形成过孔；
步骤 S3、 在完成步骤 S2的所述基板上沉积像素电极层和源漏电极金属 层， 并通过第三次掩模工艺形成像素电极、 源漏电极和数据线。
所述步骤 S1的一个示例如下所述。
在基板上沉积栅电极金属层， 在所述栅电极金属层上沉积 SiNx或 SiOx 作为绝缘层， 在所述绝缘层上沉积 a-Si层作为有源层； 然后， 在有源层上涂 敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻胶进行曝光， 使光刻胶形 成光刻胶完全去除区域、 光刻胶完全保留区域和光刻胶半保留区域， 其中光 刻胶完全保留区域对应于有源层图形所在区域， 光刻胶半保留区域对应于栅 电极和栅线所在区域， 光刻胶完全去除区域对应于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶完全去除区域的光刻胶 被完全去除，光刻胶半保留区域的光刻胶厚度变薄；釆用湿法刻蚀对所述 a-Si 层进行刻蚀， 釆用干法刻蚀对所述绝缘层进行刻蚀， 再釆用湿法刻蚀对栅电 极金属层进行刻蚀， 得到栅电极和栅线； 然后， 通过灰化工艺， 完全去除掉 光刻胶半保留区域的光刻胶； 然后釆用湿法刻蚀形成有源层图形； 最后， 剥 离剩余的光刻胶。
所述步骤 S2的一个示例如下所述。
在完成步骤 S1的所述基板上沉积 SiNx或 SiOx作为保护层， 利用第二 次掩模工艺在所述有源层上形成过孔， 在暴露的所述有源层上形成掺杂 n型 非晶硅的接触层。
所述步骤 S3的一个示例如下所述
在完成步骤 S2 的所述基板上沉积像素电极层， 在所述像素电极层上沉 积源漏电极金属层； 在源漏电极金属层上涂敷一层光刻胶； 釆用半色调或灰 色调掩模板对光刻胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶 完全保留区域和光刻胶半保留区域， 其中光刻胶完全保留区域对应于源漏电 极和数据线所在区域， 光刻胶半保留区域对应于像素电极所在区域， 光刻胶 完全去除区域对应于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶 厚度没有变化， 光刻胶完全去除区域的光刻胶被完全去除， 光刻胶半保留区 层以及像素电极层去除， 形成源漏电极和数据线； 将光刻胶灰化， 去除掉光 刻胶半保留区域的光刻胶； 釆用湿法刻蚀形成像素电极； 最后， 剥离剩余的 光刻胶。
其中， 所述绝缘层的厚度为 200nm-400nm , 所述保护层的厚度为 250匪-400匪。
下面结合图 la-lf,对本发明实施例一的阵列基板的制造方法进行详细说 明。
本发明实施例一的阵列基板的制作方法包括以下步骤；
步骤 S21、在基板 7上连续沉积栅电极金属层 11、 绝缘层 2和有源层 3 , 并通过第一次掩模工艺形成栅电极 1、 栅线和有源层图形；
具体地， 如图 la所示， 在基板 7上利用磁控溅射工艺沉积一层厚度在 200nm-400nm之间的栅电极金属层 11 , 用于形成栅电极 1 , 用于形成栅电极 1的金属可以选用 Mo, Cu, A1等金属； 然后利用等离子体增强化学气相沉 积法 （ Plasma Enhanced Chemical Vapor Deposition , PECVD ) 在栅电极金属 层 11上沉积一层厚度在 200nm-400nm之间的 SiNx或 SiOx作为绝缘层 2 , 然后在绝缘层 2上沉积厚度在 100nm-200nm之间的有源层 3 , 有源层 3的材 料选用 a-Si;
如图 lb所示， 然后利用第一次掩模工艺形成栅电极 1、栅线和有源层图 形： 在有源层 3上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻胶进 行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区域和光刻胶 半保留区域， 其中光刻胶完全保留区域对应于有源层图形所在区域， 光刻胶 半保留区域对应于栅电极 1和栅线所在区域， 光刻胶完全去除区域对应于剩 余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶 完全去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 先釆用湿法刻蚀对有源层 3进行刻蚀，再釆用干法刻蚀对绝缘层 2进行刻蚀， 再釆用湿法刻蚀对栅电极金属层 11进行刻蚀， 形成栅电极 1和栅线； 然后， 通过灰化工艺， 完全去除掉光刻胶半保留区域的光刻胶（Photoresist, PR )； 然后， 利用湿法刻蚀工艺形成有源层图形； 最后， 剥离剩余的光刻胶。
步骤 S22、 在完成步骤 S21的基板 7上沉积保护层 4, 并通过第二次掩 模工艺在保护层 4中形成过孔 8; 如图 lc 所示， 在完成步骤 S21 的基板 7 上用 PECVD 沉积厚度在 250nm-400nm之间的 SiNx或 SiOx作为保护层 4; 如图 Id所示， 利用第二 次掩模工艺， 在有源层 3上形成过孔 8, 以便使有源层 3连接到稍后形成的 源漏电极 6, 并形成 TFT沟道 9; 在形成过孔 8后， 在暴露的有源层 3上形 成掺杂 n型非晶硅的 （ n+ )接触层（未示出） ， 以便有源层 3和稍后形成的 源漏电极 6能够形成欧姆接触。
步骤 S23、在完成步骤 S22的基板 7上沉积像素电极层 51和源漏电极金 属层 61 , 并通过第三次掩模工艺形成源漏电极 6、 数据线和像素电极 5; 具体地，如图 le所示，在完成步骤 S22的基板 7上用磁控溅射工艺沉积 厚度为 40nm-100nm之间的 ITO层 51 , 用于形成像素电极 5, 继续沉积厚度 在 200nm-400nm之间的源漏电极金属层 61 , 用于形成源漏电极 6。
如图 If所示， 利用第三次掩模工艺形成源漏电极 6、 数据线和像素电极 5: 在源漏电极金属层 61上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对 光刻胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区域 和光刻胶半保留区域， 其中光刻胶完全保留区域对应于源漏电极 6和数据线 所在区域， 光刻胶半保留区域对应于像素电极 5所在区域， 光刻胶完全去除 区域对应于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有 变化， 光刻胶完全去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻 ITO层 51去除， 形成源漏电极 6和数据线； 将光刻胶灰化， 去除掉光刻胶半 保留区域的光刻胶； 釆用湿法刻蚀形成像素电极 5; 最后， 剥离剩余的光刻 胶。
本发明的实施例通过将栅电极金属层、 绝缘层和有源层一起沉积并进行 光刻， 节省了一次掩模工艺， 仅通过三次掩模工艺就能够实现阵列基板的制 作， 降低了生产成本； 通过减少绝缘层 2的厚度， 能够增加 TFT打开时的充 电电流 Ion, 从而缩短充电时间， 本发明的实施例通过增加保护层 4的厚度， 能够减少数据线与栅线之间的电容， 达到消除寄生电容的目的， 避免串扰现 象发生， 保证显示品盾。
实施例二
根据本发明实施例二的阵列基板的制造方法釆用三次掩模工艺制造阵列 基板。 根据本发明实施例二的阵列基板的制造方法包括以下步骤：
步骤 Sl、 在基板上连续沉积栅电极金属层、 绝缘层和有源层， 并通过第 一次掩模工艺形成栅电极、 栅线和有源层图形；
步骤 S2、 在完成步骤 S1的所述基板上沉积保护层， 并通过第二次掩模 工艺在所述保护层中形成过孔；
步骤 S3、 在完成步骤 S2的所述基板上沉积像素电极层和源漏电极金属 层， 并通过第三次掩模工艺形成像素电极、 源漏电极和数据线。
其中， 所述步骤 S1的一个示例如下所述：
在基板上沉积栅电极金属层， 在所述栅电极金属层上沉积 SiNx或 SiOx 作为绝缘层， 在所述绝缘层上沉积金属氧化物层作为有源层； 然后， 在有源 层上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻胶进行曝光， 使光 刻胶形成光刻胶完全去除区域、 光刻胶完全保留区域和光刻胶半保留区域， 其中光刻胶完全保留区域对应于有源层图形所在区域， 光刻胶半保留区域对 应于栅电极和栅线所在区域， 光刻胶完全去除区域对应于剩余区域； 显影处 理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶完全去除区域的 光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 釆用干法刻蚀对 所述金属氧化物层及绝缘层进行刻蚀， 再釆用湿法刻蚀对栅电极金属层进行 刻蚀， 得到栅电极和栅线； 然后， 通过灰化工艺， 完全去除掉光刻胶半保留 区域的光刻胶； 釆用干法刻蚀形成有源层图形； 最后， 剥离剩余的光刻胶。
其中， 所述金属氧化物包括： 氧化辞、 氧化铟辞镓及其混合物。
进一步地， 所述步骤 S2的一个示例如下所述：
在完成步骤 S1的所述基板上沉积 SiNx或 SiOx作为保护层， 利用第二 次掩模工艺在所述有源层上形成过孔。
所述步骤 S3的一个示例如下所述：
在完成步骤 S2 的所述基板上沉积像素电极层， 在所述像素电极层上沉 积源漏电极金属层， 在源漏电极金属层上涂敷一层光刻胶； 釆用半色调或灰 色调掩模板对光刻胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶 完全保留区域和光刻胶半保留区域， 其中光刻胶完全保留区域对应于源漏电 极和数据线所在区域， 光刻胶半保留区域对应于像素电极所在区域， 光刻胶 完全去除区域对应于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶 厚度没有变化， 光刻胶完全去除区域的光刻胶被完全去除， 光刻胶半保留区 层以及像素电极层去除， 形成源漏电极和数据线； 将光刻胶灰化， 去除掉光 刻胶半保留区域的光刻胶； 釆用湿法刻蚀形成像素电极； 最后， 剥离剩余的 光刻胶。
其中， 所述绝缘层的厚度为 200nm-400nm , 所述保护层的厚度为 250匪-400匪。
下面对本发明实施例二的阵列基板的制造方法进行详细说明。
本发明实施例二的阵列基板的制作方法包括以下步骤；
步骤 S31、在基板 7上连续沉积栅电极金属层 11 , 绝缘层 2和有源层 3 , 并通过第一次掩模工艺形成栅电极 1、 栅线和有源层图形；
具体地，在基板 7上利用磁控溅射工艺沉积一层厚度在 200nm-400nm之 间的栅电极金属层 11 , 用于形成栅电极 1 , 可以选用 Mo、 Cu、 A1等金属； 然后利用 PECVD沉积一层厚度在 200nm-400nm之间的 SiNx或 SiOx作为绝 缘层 2, 和 30nm-50nm的金属氧化物层作为有源层 3 , 该金属氧化物层的材 料可以为 ZnO、 氧化铟辞镓（IGZO )、 氧化铟和氧化辞掺杂的混合物及其他 金属氧化物等。
然后利用第一次掩模工艺形成栅电极 1、 栅线和有源层图形： 在有源层 上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻胶进行曝光， 使光刻 胶形成光刻胶完全去除区域、 光刻胶完全保留区域和光刻胶半保留区域， 其 中光刻胶完全保留区域对应于有源层图形所在区域， 光刻胶半保留区域对应 于栅电极 1和栅线所在区域， 光刻胶完全去除区域对应于剩余区域； 显影处 理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶完全去除区域的 光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 先釆用干法刻蚀 对有源层 3和绝缘层 2进行刻蚀； 再进行湿刻形成栅电极 1和栅线； 然后对 光刻胶进行灰化处理， 利用干法刻蚀形成有源层图形。
步骤 S32、 在完成步骤 S31的基板 7上沉积保护层 4, 并通过第二次掩 模工艺形成过孔 8;
在完成步骤 S31的基板 7上用 PECVD沉积厚度在 250nm-400nm之间的 SiNx或 SiOx作为保护层 4; 利用第二次掩模工艺， 在有源层 3上形成过孔， 以便有源层 3连接源漏电极 6, 形成 TFT沟道 9。
步骤 S33、 在完成步骤 S32的基板 7上沉积像素电极层 51和源漏电 极金属层 61 , 并通过第三次掩模工艺形成源漏电极 6、数据线和像素电极 5; 具体地， 在完成步骤 S32 的基板 7 上用磁控溅射工艺沉积厚度在 40nm-100nm之间的 ITO 层 51 , 用于形成像素电极 5 , 继续沉积厚度在 200nm-400nm之间的源漏电极金属层 61 , 用于形成源漏电极 6。
利用第三次掩模工艺形成源漏电极 6,数据线和像素电极 5:在源漏电极 金属层 61 上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻胶进行曝 光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区域和光刻胶半保 留区域， 其中光刻胶完全保留区域对应于源漏电极 6和数据线所在区域， 光 刻胶半保留区域对应于像素电极 5所在区域， 光刻胶完全去除区域对应于剩 余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶 完全去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 除； 釆用湿法刻蚀形成像素电极 5; 最后， 剥离剩余的光刻胶。
本发明的实施例通过将栅电极金属层、 绝缘层和有源层一起沉积并进行 光刻， 节省了一次掩模工艺， 仅通过三次掩模工艺就能够实现阵列基板的制 作， 降低了生产成本； 通过减少绝缘层 2的厚度， 能够增加 TFT打开时的充 电电流 Ion, 从而缩短充电时间， 本发明的实施例通过增加保护层 4的厚度， 能够减少数据线与栅线之间的电容， 达到消除寄生电容的目的， 避免串扰现 象发生， 保证显示品盾。
实施例三
如图 If所示， 为本发明实施例三的阵列基板的结构示意图， 本实施例三 的阵列基板由上述实施例中的方法制作， 其包括：
基板 7, 形成于基板 7上的栅电极 1 , 形成于栅电极 1上的绝缘层 2, 形 成于绝缘层 2上的有源层 3,形成于具有栅电极 1的基板 7上的保护层 4,形 成于保护层 4和有源层 3上的像素电极 5, 以及形成于像素电极 5上的源漏 电极 6, 其中像素电极 5及源漏电极 6的在沟道区上的一端通过形成于保护 层 4中的过孔 8连接到有源层 3。
由以上实施例可以看出， 本发明实施例通过将栅电极、 绝缘层和有源层 一起沉积并进行光刻， 节省了一次掩模工艺， 仅通过三次掩模工艺就能够实 现阵列基板的制作， 降低了生产成本； 进一步地， 通过减少绝缘层的厚度， 增加了 TFT的充电电流， 缩短了充电时间， 通过增加保护层的厚度， 减少了 数据线和栅线之间的电容， 有效消除了寄生电容， 保证了显示品质， 优化了 阵列基板的性能。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明技术原理的前提下， 还可以做出若干改进 和变型， 这些改进和变型也应视为本发明的保护范围。

Claims

权利要求书
1、 一种阵列基板的制作方法， 包括以下步骤：
步骤 Sl、 在基板上连续沉积栅电极金属层， 绝缘层和有源层， 并通过第 一次掩模工艺形成栅电极、 栅线和有源层图形；
步骤 S2、 在完成步骤 S1的所述基板上沉积保护层， 并通过第二次掩模 工艺在所述保护层中形成过孔； 以及
步骤 S3、 在完成步骤 S2的所述基板上顺次沉积像素电极层和源漏电极 金属层， 并通过第三次掩模工艺形成源漏电极、 像素电极和数据线。
2、 如权利要求 1所述的阵列基板的制作方法， 其中所述步骤 S1包括： 在基板上沉积所述栅电极金属层， 在所述栅电极金属层上沉积 SiNx或 SiOx作为所述绝缘层， 在所述绝缘层上沉积 a-Si层作为有源层；
然后， 在所述有源层上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对 光刻胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区域 和光刻胶半保留区域，其中光刻胶完全保留区域对应于有源层图形所在区域， 光刻胶半保留区域对应于栅电极和栅线所在区域， 光刻胶完全去除区域对应 于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光 刻胶完全去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变 薄；
釆用湿法刻蚀对有源层进行刻蚀， 再釆用干法刻蚀对绝缘层进行刻蚀， 再釆用湿法刻蚀对栅电极金属层进行刻蚀， 得到栅电极和栅线；
然后， 通过灰化工艺， 完全去除掉光刻胶半保留区域的光刻胶， 利用湿 法刻蚀工艺形成有源层图形；
最后， 剥离剩余的光刻胶。
3、 如权利要求 1所述的阵列基板的制作方法， 其中所述步骤 S2包括： 在完成步骤 S1的所述基板上沉积 SiNx或 SiOx作为保护层， 利用第二 次掩模工艺在所述有源层上形成过孔， 在暴露的所述有源层上形成掺杂 n型 非晶硅的接触层。
4、 如权利要求 1所述的阵列基板的制作方法， 其中所述步骤 S3包括： 在完成步骤 S2 的所述基板上沉积像素电极层， 在所述像素电极层上沉 积源漏电极金属层；
在所述源漏电极金属层上涂敷一层光刻胶； 釆用半色调或灰色调掩模板 对光刻胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区 域和光刻胶半保留区域， 其中光刻胶完全保留区域对应于源漏电极和数据线 所在区域， 光刻胶半保留区域对应于像素电极所在区域， 光刻胶完全去除区 域对应于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变 化， 光刻胶完全去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶 厚度变薄； 去除， 形成源漏电极和数据线；
将光刻胶灰化， 去除掉光刻胶半保留区域的光刻胶， 釆用湿法刻蚀形成 像素电极；
最后， 剥离剩余的光刻胶。
5、 如权利要求 1所述的阵列基板的制作方法， 其中所述步骤 S1包括： 在基板上沉积栅电极金属层， 在所述栅电极金属层上沉积 SiNx或 SiOx 作为所述绝缘层， 在所述绝缘层上沉积金属氧化物层作为有源层；
然后， 在有源层上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻 胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区域和光 刻胶半保留区域， 其中光刻胶完全保留区域对应于有源层图形所在区域， 光 刻胶半保留区域对应于栅电极和栅线所在区域， 光刻胶完全去除区域对应于 剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻 胶完全去除区域的光刻胶被完全去除，光刻胶半保留区域的光刻胶厚度变薄； 然后釆用干法刻蚀对所述金属氧化物层和所述绝缘层， 再釆用湿法刻蚀 对所述栅电极金属层进行刻蚀， 得到栅电极和栅线图形；
然后， 通过灰化工艺， 完全去除掉光刻胶半保留区域的光刻胶， 最后釆 用干法刻蚀形成有源层图形；
最后， 剥离剩余的光刻胶。
6、如权利要求 5所述的阵列基板的制作方法，其中所述金属氧化物包括： 氧化辞、 氧化铟辞镓或其混合物。
7、 如权利要求 5所述的阵列基板的制作方法， 其中 所述步骤 S2包括： 在完成步骤 SI的所述基板上沉积 SiNx或 SiOx作为保护层， 利用第二 次掩模工艺在所述有源层上形成过孔。
8、 如权利要求 5所述的阵列基板的制作方法， 其中所述步骤 S3包括： 在完成步骤 S2 的所述基板上沉积像素电极层， 在所述像素电极层上沉 积源漏电极金属层；
在所述源漏电极金属层上涂敷一层光刻胶； 釆用半色调或灰色调掩模板 对光刻胶进行曝光， 使光刻胶形成光刻胶完全去除区域、 光刻胶完全保留区 域和光刻胶半保留区域， 其中光刻胶完全保留区域对应于源漏电极和数据线 所在区域， 光刻胶半保留区域对应于像素电极所在区域， 光刻胶完全去除区 域对应于剩余区域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变 化， 光刻胶完全去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶 厚度变薄； 去除， 形成源漏电极和数据线；
将光刻胶灰化， 去除掉光刻胶半保留区域的光刻胶， 釆用湿法刻蚀形成 像素电极；
最后， 剥离剩余的光刻胶。
9、如权利要求 1所述的阵列基板的制作方法，其中所述绝缘层的厚度为 200nm-400nm, 所述保护层的厚度为 250nm-400nm。
10、 如权利要求 1所述的方法制作的阵列基板， 包括：
基板；
栅电极， 形成于所述基板上；
绝缘层， 形成于所述栅电极上；
有源层， 形成于所述绝缘层上；
保护层， 形成于所述基板上， 其中形成有过孔；
像素电极， 形成于所述保护层和有源层上， 且通过所述过孔与所述有源 层电连接； 以及
源漏电极， 形成于所述像素电极上。
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