WO2016004692A1 - 阵列基板制备方法 - Google Patents

阵列基板制备方法 Download PDF

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Publication number
WO2016004692A1
WO2016004692A1 PCT/CN2014/088589 CN2014088589W WO2016004692A1 WO 2016004692 A1 WO2016004692 A1 WO 2016004692A1 CN 2014088589 W CN2014088589 W CN 2014088589W WO 2016004692 A1 WO2016004692 A1 WO 2016004692A1
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Prior art keywords
photoresist
source
array substrate
layer
forming
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PCT/CN2014/088589
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English (en)
French (fr)
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王凯
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US14/767,132 priority Critical patent/US9825069B2/en
Priority to EP14882131.7A priority patent/EP3168865A4/en
Publication of WO2016004692A1 publication Critical patent/WO2016004692A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate.
  • the mobility of an amorphous silicon thin film transistor is generally about 0.5 cmW ⁇ S, and when the size of a liquid crystal display exceeds 80 inch (inch) and the driving frequency is 120 Hz, the mobility of a TFT used for a liquid crystal display is required to be 1 cm W ⁇ s or more. Therefore, the mobility of the amorphous silicon TFT is obviously difficult to satisfy.
  • the high mobility thin film transistor includes a polysilicon thin film transistor and a metal oxide thin film transistor. However, the uniformity of the polysilicon thin film transistor in the preparation process is poor, and the preparation process is complicated. Indium Gallium Zinc Oxide Thin Film Transistor (IGZO-TFT) has high mobility, uniformity, transparency, and simple fabrication process, which can better meet large-size liquid crystal displays and active organic electro-optics. The need for luminescence.
  • the structure of the metal oxide IGZO-TFT mainly has three types: an etch barrier type, a back channel etch type, and a coplanar type.
  • the etch barrier metal oxide IGZO-TFT is simple in fabrication process.
  • the etch barrier layer on the metal oxide IGZO can protect the metal oxide IGZO layer from being damaged when the source/drain metal electrode is formed, thereby improving the performance of the metal oxide IGZO-TFT.
  • this process requires an additional photolithography process to form an etch barrier, which increases the fabrication process of the metal oxide IGZO-TFT.
  • the etching process of the etch-blocking TFT requires an etch barrier layer, a masking process applied to the layer is required accordingly, which complicates the entire production process, increases product cost, and reduces the productivity of the factory and the product. Rate, the final product has lower benefits.
  • At least one embodiment of the present invention provides a method for fabricating an array substrate, which can simplify the production process of the etch barrier TFT, reduce production cost, and improve product yield and product efficiency.
  • At least one embodiment of the present invention provides a method for fabricating an array substrate, comprising: forming a thin film crystal An active layer of the body tube, wherein a portion of the photoresist above the active layer corresponding to a position corresponding to a channel region between the source and drain electrodes of the thin film transistor is retained; a source/drain metal layer is formed, and Further, source and drain electrodes are formed; a portion of the thickness of the channel region between the source and drain electrodes is stripped.
  • forming the active layer includes forming a semiconductor film, coating a photoresist on the semiconductor film, and patterning the semiconductor film using a halftone mask.
  • a photoresist complete removal region corresponds to the channel region between the source and drain electrodes to be formed, and the photoresist portion reserved region is formed in the region above the active layer covered by the source and drain electrodes, the photoresist
  • the completely removed region is a region other than the active layer region; the semiconductor film in the photoresist completely removed region is removed by an etching process; the photoresist in the resist portion of the photoresist is removed, and the photoresist is completely retained in the reserved region Thickness of photoresist.
  • forming the source/drain electrode includes: forming a source/drain metal layer on a substrate on which the active layer is formed, and patterning a source/drain metal layer to form a source/drain electrode and A channel region between the source and drain electrodes is then removed, and the portion of the thickness of the photoresist corresponding to the location of the channel region is removed.
  • the method of fabricating further includes forming a gate and a gate insulating layer prior to forming the active layer.
  • the preparation method further includes forming a pixel electrode and a passivation layer after forming the source and drain electrodes.
  • Figure 1 is a process flow diagram of an embodiment of the present invention
  • FIG. 2 is a schematic view of a substrate after a gate mask process is performed in an embodiment of the invention
  • FIG. 3 is a schematic view of a substrate after performing an IGZO semi-transparent mask process in an embodiment of the invention
  • FIG. 4 is a schematic diagram of a substrate after performing a source/drain data line mask process according to an embodiment of the invention
  • FIG. 5 is a schematic diagram of a substrate after performing a pixel electrode mask process according to an embodiment of the invention.
  • FIG. 6 is a schematic view showing a substrate after a protective layer mask process in an embodiment of the present invention.
  • Figure 7 is a schematic view of a substrate after performing a common electrode mask process in an embodiment of the present invention.
  • 1 substrate; 2: gate; 3: gate line signal loading region; 4: gate insulating layer; 5: active layer; 6: source-drain electrode; 7: pixel electrode; 8: passivation layer; Electrode; 10: data line signal loading area; 11: photoresist.
  • At least one embodiment of the present invention provides an improved method for fabricating an array substrate.
  • An array substrate includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in an array, each of the pixel units including a thin film transistor as a switching element And a pixel electrode and a common electrode for controlling the arrangement of the liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • a portion of the thickness of the photoresist corresponding to the location of the channel region between the source and drain electrodes of the thin film transistor is retained; Then, a source/drain metal layer is formed to further form a source/drain electrode; next, a portion of the thickness of the channel region between the source and drain electrodes is stripped.
  • the above technical solution is a fabrication process for fabricating an etch barrier metal oxide TFT using, for example, a semi-transmissive mask (halftone mask or gray tone mask) technique.
  • a semi-transmissive mask halftone mask or gray tone mask
  • a semiconductor film is formed, a part of the photoresist is left at the TFT channel by a semi-transparent mask process, thereby avoiding the source-drain electrode etching process.
  • Destruction of the metal oxide layer; the photoresist is further stripped off during the subsequent stripping process, which can replace the conventional etch barrier layer, thereby eliminating the filming and masking process of the etch barrier layer.
  • At least one embodiment of the present invention uses a six-mask process to fabricate an array substrate, which is described below.
  • the gate (and the gate line) is formed, and the step mainly includes a gate film forming process and a mask process.
  • a gate metal layer is formed on a substrate 1 such as glass or plastic by a sputtering process, and the gate metal layer may be Cr, Mo, Al, or Cu or the like (gate metal layer film formation (Gate film formation)); Then, using a gate mask, a first mask process is performed, wherein the gate 2 (gate mask) is formed by a single exposure, development, and wet etching process, that is, as shown in the figure. 2 shows the substrate structure.
  • the gate line signal loading region 3 can also be formed in the same layer as the gate 2.
  • a gate insulating layer (GI film forming) is formed, and this step mainly includes a gate insulating layer film forming process.
  • the thickness is formed by a plasma enhanced chemical vapor deposition (PECVD) process to form a SiO 2 insulating film as the gate insulating layer 4 for protecting the gate electrode 2.
  • PECVD plasma enhanced chemical vapor deposition
  • the active layer is formed, and the step mainly includes, for example, an IGZO film forming process and an IGZO Half Tone Mask process.
  • a semiconductor film is formed by a sputtering process, and the semiconductor film is made of IGZO metal oxide such as ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO. Then, a second masking process is performed, The thickness is coated with a photoresist, and then the semiconductor film is patterned using a halftone mask. In the patterning process of the semiconductor film, after the photoresist is exposed and developed, a photoresist complete removal region, a photoresist partial retention region, and a photoresist complete retention region are formed.
  • the photoresist completely reserved area corresponds to the channel region between the source and drain electrodes to be formed, and the photoresist partially reserved region is formed in the active layer 5 over the region covered by the source and drain electrodes, and the photoresist completely removed region is The area corresponding to the area outside the active layer 5. Then, the semiconductor film in the photoresist completely removed region is removed by an etching process. Next, for example, the photoresist of the resist portion and the photoresist completely reserved region is irradiated with ultraviolet light of a certain light intensity, so that the photoresist in the remaining portion of the photoresist is completely denatured and developed and removed. The glue is completely reserved, and a half thickness of the photoresist 11 is retained. As shown in FIG. 3, the active layer 5 is completed.
  • This step mainly includes an S/D film forming process and an S/D mask process.
  • the thickness of the source/Drain (S/D) metal layer is formed on the substrate by a sputtering process. Then, a third masking process is performed to form a layer of photoresist on the S/D metal layer, and the photoresist is exposed and developed by the source/drain electrode mask to make the light corresponding to the region where the source and drain electrodes are to be formed. The photoresist is retained, and the photoresist in other regions is completely removed, and the source and drain electrodes are formed by an etching process.
  • the channel region between the source electrode and the drain electrode is obtained, but the channel region still retains a portion of the photoresist reserved in the step of forming the active layer 5, and the photoresist over the source and drain electrodes is The remaining half of the thickness of the photoresist 11 above the source layer 5 is subjected to a lift-off process to form a source-drain electrode 6 as shown in FIG.
  • the data line signal loading region 10 can also be formed.
  • the step mainly includes, for example, a first ITO film forming process and a first ITO mask process.
  • first press The thickness is formed on the substrate on which the source/drain electrode 6 is formed by a sputtering process, and the transparent electrode layer can be formed using, for example, ITO or IZO; then a fourth mask process is performed to form a photoresist on the transparent electrode layer. After the photoresist is exposed and developed by using the pixel electrode mask, an etching process is performed to obtain a patterned transparent electrode layer, and then the photoresist is stripped. As shown in FIG. 5, the pixel electrode 7 is completed. .
  • a passivation layer is formed, and the step mainly includes a PVX (passivation layer) film formation process and a PVX mask process.
  • the thickness of the passivation layer is formed on the substrate on which the pixel electrode 7 is formed by a chemical vapor deposition (CVD) process.
  • the passivation layer material may be, for example, a single layer film formed of SiOx, or SiOx and SiNx. Composite film formed by composite.
  • a fifth masking process is performed, a photoresist is formed on the protective film layer, and the photoresist is exposed and developed using a passivation mask, and an etching process is performed to obtain a patterned passivation layer.
  • the photoresist is stripped, as shown in FIG. 6, and the passivation layer 8 is completed.
  • the step of preparing the corresponding array substrate may further include the following steps of forming the common electrode.
  • the step includes, for example, mainly a second ITO film forming process and a second ITO mask process.
  • first press The thickness forms a transparent electrode layer on the substrate on which the passivation layer 8 is formed, and the transparent electrode layer is formed using, for example, ITO or IZO; then a sixth mask process is performed to form a photoresist on the transparent electrode layer, using a common electrode mask The film is exposed and developed by the photoresist, and after etching, a patterned transparent electrode layer is obtained, and the photoresist is stripped. As shown in FIG. 7, the common electrode 9 is completed.
  • the mask process is not required, and the other six steps are performed in six mask processes.
  • the step of forming the active layer is an IGZO halftone mask process on the TFT array substrate; when the active layer is formed, a part of the photoresist is retained at the TFT channel by using a halftone mask process, and the source is used
  • the drain electrode layer functions as an etch barrier layer to protect the IGZO metal oxide forming the active layer from being etched away, and is removed in the subsequent stripping process, without adding an etch barrier layer, and also saving
  • the masking process of this layer is made, the whole production process is simplified, the product cost is reduced, the production capacity of the factory and the yield of the product are improved, and the efficiency of the product is finally improved.
  • the above preparation method corresponds to the array substrate structure in which the common electrode is located above the pixel electrode.
  • the formation process of the active layer and the subsequent step of forming the source and drain electrodes can adopt the same process as described above. The difference is only that the common electrode is formed before or after the pixel electrode, and the preparation process of the entire array substrate will not be described herein.
  • the embodiment of the present invention can avoid the destruction of the metal oxide layer in the process of forming the source and drain metal electrodes, as compared with the case of using the specially formed etch barrier layer. Glow discharge, plasma and dry etching process during the formation of the etch barrier layer damage to the metal oxide layer, stress residual and defect state increase, the production method does not increase the production process, no need to carry out Equipment transformation can be corresponding.

Abstract

一种阵列基板制备方法，包括：形成薄膜晶体管的有源层(5)，其中保留有源层(5)上方所述薄膜晶体管的源漏电极(6)之间沟道区所对应位置的部分厚度的光刻胶(11)；形成源漏金属层，并进一步形成源漏电极(6)；将源漏电极(6)之间沟道区的部分厚度的光刻胶(11)剥离。该阵列基板制备方法在源漏电极刻蚀工艺中能够避免对金属氧化物层的破坏，并且降低生产成本，简化工艺，提高产品良率和产品效益。

Description

阵列基板制备方法 技术领域
本发明的实施例涉及一种阵列基板制备方法。
背景技术
近年来液晶显示器尺寸的不断增大，显示驱动电路的频率不断提高。非晶硅薄膜晶体管(TFT)的迁移率一般在0.5cmW·S左右，而液晶显示器尺寸超过80吋(inch)且驱动频率为120Hz时，需要液晶显示器使用的TFT的迁移率为1cmW·S以上，因此非晶硅TFT的迁移率显然很难满足。高迁移率的薄膜晶体管包括多晶硅薄膜晶体管和金属氧化物薄膜晶体管。但是，多晶硅薄膜晶体管在制备过程中的均一性差，且制备工艺复杂。铟镓锌氧化物薄膜场晶体管(Indium Gallium Zinc Oxide Thin Film Transistor，IGZO-TFT)迁移率高、均一性好、透明、制作工艺简单，可以更好地满足大尺寸液晶显示器和有源有机电致发光的需求。
目前金属氧化物IGZO-TFT的结构主要有刻蚀阻挡型、背沟道刻蚀型和共面型三种类型。
刻蚀阻挡型金属氧化物IGZO-TFT制作工艺简单。金属氧化物IGZO上的刻蚀阻挡层，可以在形成源漏金属电极时保护金属氧化物IGZO层不被破坏，从而提高金属氧化物IGZO-TFT的性能。但是，该工艺需要一次额外的光刻工艺形成刻蚀阻挡层，增加了金属氧化物IGZO-TFT的制作工艺流程。
因刻蚀阻挡型的TFT的制备工艺需要刻蚀阻挡层，也相应地需要应用于该层的掩膜工艺，从而使得整个生产工序变的复杂，增加产品成本，降低工厂的产能及产品的良率，最终产品的效益较低。
发明内容
本发明至少一实施例提供一种阵列基板制备方法，其能够简化刻蚀阻挡型TFT的生产工序，降低生产成本，提高产品良率和产品效益。
本发明至少一实施例提供了一种阵列基板制备方法，包括：形成薄膜晶 体管的有源层，其中，保留所述有源层上方对应于所述薄膜晶体管的源漏电极之间的沟道区所对应位置的部分厚度的光刻胶；形成源漏金属层，并进一步形成源漏电极；将源漏电极之间沟道区的部分厚度的光刻胶剥离。
在本发明至少一实施例中，例如，形成所述有源层包括：形成一层半导体膜，在半导体膜上涂布光刻胶，采用半色调掩膜版，对半导体膜进行图案化。
在本发明至少一实施例中，例如，在对所述半导体膜的图案化过程中，在对所述光刻胶曝光、显影之后，形成光刻胶完全去除区、光刻胶部分保留区和光刻胶完全保留区，光刻胶完全保留区对应待形成的源漏电极之间的沟道区，光刻胶部分保留区为形成有源层上方被源漏电极覆盖的区域，光刻胶完全去除区为有源层区域以外所对应的区域；将光刻胶完全去除区的半导体膜通过刻蚀工艺去除；去除光刻胶部分保留区的光刻胶，光刻胶完全保留区保留部分厚度的光刻胶。
在本发明至少一实施例中，例如，形成所述源漏电极包括：在形成所述有源层的基板上形成源漏金属层，并对源漏金属层进行图案化以形成源漏电极和源漏电极之间的沟道区，然后将沟道区位置对应的所述部分厚度的光刻胶去除。
在本发明至少一实施例中，例如，制备方法还包括在形成有源层之前形成栅极和栅绝缘层。
在本发明至少一实施例中，例如，制备方法还包括形成源漏电极之后形成像素电极和钝化层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1：本发明一实施例的工艺流程图；
图2：本发明一实施例中进行完栅极掩膜工艺后基板示意图；
图3：本发明一实施例中进行IGZO半透掩膜工艺后基板示意图；
图4：本发明一实施例中进行源/漏数据线掩膜工艺后基板示意图；
图5：本发明一实施例中进行像素电极掩膜工艺后基板示意图；
图6：本发明一实施例中进行保护层掩膜工艺后基板示意图；
图7：本发明一实施例中进行公共电极掩膜工艺后基板示意图。
附图符号说明：
1：衬底；2：栅极；3：栅线信号加载区；4：栅绝缘层；5：有源层；6：源漏电极；7：像素电极；8：钝化层；9：公共电极；10：数据线信号加载区；11：光刻胶。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了简化刻蚀阻挡型TFT的生产工序，降低其生产成本，提高产品良率和产品效益，本发明至少一实施例提供了一种改进的阵列基板制备方法。
本发明至少一实施例的阵列基板包括多条栅线和多条数据线，这些栅线和数据线彼此交叉由此限定了排列为阵列的像素单元，每个像素单元包括作为开关元件的薄膜晶体管和用于控制液晶的排列的像素电极和公共电极。例如，每个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成，源极与相应的数据线电连接或一体形成，漏极与相应的像素电极电连接或一体形成。下面的描述主要针对单个或多个像素单元进行，但是其他像素单元可以相同地形成。
在本发明实施例的制备方法之中，在薄膜晶体管的有源层的形成过程中，保留有源层上方薄膜晶体管的源漏电极之间沟道区所对应位置的部分厚度的光刻胶；然后形成源漏金属层，进一步形成源漏电极；接下来将源漏电极之间沟道区的部分厚度的光刻胶剥离。
上述技术方案为利用例如半透掩膜(半色调掩模或灰色调掩模)技术制作刻蚀阻挡型金属氧化物TFT的制作工艺。在形成半导体膜时，采用半透掩膜工艺在TFT沟道处保留部分的光刻胶，从而在源漏电极刻蚀工艺中避免对 金属氧化物层的破坏；该光刻胶在之后的剥离过程中再被剥离掉，其可代替传统的刻蚀阻挡层，从而可以省掉刻蚀阻挡层的成膜及掩膜工艺，由此降低生产成本，简化工艺，提高产品良率和产品效益。
如图1所示，本发明至少一实施例采用6道掩膜工艺制作阵列基板的方法，该方法描述如下。
形成栅极(以及栅线)，该步骤主要包括栅极成膜工艺和掩膜工艺。
首先，在例如玻璃或塑料的衬底1上通过溅射工艺形成一层栅金属层，栅金属层可采用Cr、Mo、Al、或Cu等(栅金属层成膜(Gate成膜))；然后，采用栅极掩膜版，进行第一次掩膜工艺，其中，通过一次曝光、显影和湿法刻蚀工艺形成栅极2(栅金属层掩模工艺(Gate Mask))，即如图2所示的基板结构。
另外，还可以与栅极2同层形成栅线信号加载区3。
形成栅绝缘层(GI成膜)，该步骤主要包括栅绝缘层成膜工艺。
例如，栅极2完成之后，按
Figure PCTCN2014088589-appb-000001
的厚度通过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺形成一层SiO2绝缘薄膜作为栅绝缘层4，用来保护栅极2。
形成有源层，该步骤例如主要包括IGZO成膜工艺及IGZO半色调掩膜(Half Tone Mask)工艺。
例如，在上述已形成的栅绝缘层4上面，通过溅射工艺形成一层半导体膜，半导体膜选用ZnO、InZnO、ZnSnO、GaInZnO、或ZrInZnO等IGZO金属氧化物。然后，进行第二次掩膜工艺，按
Figure PCTCN2014088589-appb-000002
的厚度涂布光刻胶，后采用半色调掩膜版，对半导体膜进行图案化。在对半导体膜的图案化过程中，在对光刻胶曝光、显影之后，形成光刻胶完全去除区、光刻胶部分保留区和光刻胶完全保留区。光刻胶完全保留区对应待形成的源、漏电极之间的沟道区，光刻胶部分保留区为形成有源层5上方被源、漏电极覆盖的区域，光刻胶完全去除区为有源层5区域以外所对应的区域。然后，光刻胶完全去除区的半导体膜通过刻蚀工艺去除。接下来，例如，采用一定光强的紫外线照射光刻胶部分保留区和光刻胶完全保留区的光刻胶，使得光刻胶部分保留区的光刻胶完全变性并显影去除，此时光刻胶完全保留区，保留一半厚度的光刻胶11，如图3所示，有源层5完成。
形成源漏电极，该步骤主要包括S/D成膜工艺及S/D掩膜(Mask)工艺。
例如，有源层5形成之后，按
Figure PCTCN2014088589-appb-000003
的厚度通过溅射工艺在基板上形成源/漏(Source/Drain，S/D)金属层。然后进行第三次掩膜工艺，在S/D金属层上形成一层光刻胶，利用源漏电极掩膜板对光刻胶曝光、显影，使得待形成源漏电极的区域所对应的光刻胶保留，其他区域的光刻胶完全去除，通过刻蚀工艺形成源漏电极。此时，得到源电极和漏电极之间的沟道区，但是沟道区域仍保留有在有源层5形成步骤中预留的部分光刻胶，将源漏电极上方的光刻胶及有源层5上方剩余的一半厚度的光刻胶11一起做剥离处理，形成如图4所示的源漏电极6。
另外，例如，在形成源漏电极6的同层，还可以形成数据线信号加载区10。
形成像素电极，该步骤例如主要包括第一ITO成膜工艺及第一ITO掩膜(Mask)工艺。
例如，首先按
Figure PCTCN2014088589-appb-000004
的厚度在形成了源漏电极6的基板上通过溅射工艺形成透明电极层，透明电极层可采用例如ITO或IZO形成；然后进行第四次掩膜工艺，在透明电极层上形成光刻胶，使用像素电极掩膜板，对光刻胶进行曝光、显影，进行刻蚀工艺后，得到图案化了的透明电极层，然后将光刻胶做剥离，如图5所示，像素电极7完成。
形成钝化层，该步骤主要包括PVX(钝化层)成膜工艺及PVX掩膜工艺。
例如，首先按
Figure PCTCN2014088589-appb-000005
的厚度采用化学气相沉积(Chemical Vapor Deposition,CVD)工艺在形成了像素电极7的基板上形成一层钝化层材料，钝化层材料例如可采用SiOx所形成的单层膜，或者SiOx及SiNx复合形成的复合膜。然后进行第五次掩膜工艺，在保护膜层上形成光刻胶，使用钝化层掩膜板，对光刻胶进行曝光、显影，进行刻蚀工艺后，得到图案化了的钝化层，将光刻胶做剥离，如图6所示，钝化层8完成。
如果公共电极布置在阵列基板上，并且公共电极位于像素电极上方，则对应的阵列基板的制备方法中还可以包括以下形成公共电极的步骤。
形成公共电极，该步骤例如主要包括第二ITO成膜工艺及第二ITO掩膜(Mask)工艺。
例如，首先按
Figure PCTCN2014088589-appb-000006
的厚度在形成了钝化层8的基板上形成透明电极层，透明电极层采用例如ITO或IZO形成；然后进行第六次掩膜工艺，在透明电极层上形成光刻胶，使用公共电极掩膜板，对光刻胶进行曝光、显影，进行刻蚀工艺后，得到图案化了的透明电极层，将光刻胶做剥离，如图7所示，公共电极9完成。
上述过程中，除了形成栅绝缘层的步骤不需要进行掩膜工艺外，其它六个步骤进行了六道掩膜工艺。形成有源层的步骤，为用于TFT阵列基板上的IGZO半色调掩膜工艺；在形成有源层时，采用半色调掩膜工艺在TFT沟道处保留部分的光刻胶，在进行源漏电极层制作时起到刻蚀阻挡层的作用，保护形成有源层的IGZO金属氧化物不被刻蚀掉，在之后的剥离过程中再去除，不需要增加刻蚀阻挡层，同时也省去了该层的掩膜工艺，使得整个生产工序变的简单化，降低产品成本，提高工厂的产能及产品的良率，最终提高产品的效益。
上述制备方法对应公共电极位于像素电极上方的阵列基板结构，对于公共电极位于像素电极下方的阵列基板结构，有源层的形成步骤及接下来的源漏电极形成步骤均可采用上述同样的工艺，不同的地方仅在于公共电极相对像素电极形成在前或在后，整个阵列基板的制备过程在此不再赘述。
由上述实施例可以看出，本发明实施例与采用特别形成的刻蚀阻挡层的方案相比，在避免在形成源漏极金属电极工艺中对金属氧化物层的破坏的同时，还可以避免在刻蚀阻挡层形成过程中的辉光放电，等离子体以及干刻的制成工艺对金属氧化物层的损伤，应力残留和缺陷态的增加，该制作方法不增加制作的流程，不需进行设备改造即可对应。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年7月11日递交的中国专利申请第201410331516.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种阵列基板制备方法，包括：
    形成薄膜晶体管的有源层，其中，保留所述有源层上方对应于所述薄膜晶体管的源漏电极之间的沟道区所对应位置的部分厚度的光刻胶；
    形成源漏金属层，并进一步形成源漏电极；
    将源漏电极之间沟道区的部分厚度的光刻胶剥离。
  2. 如权利要求1所述的阵列基板制备方法，其中，形成所述有源层包括：
    形成一层半导体膜，在半导体膜上涂布光刻胶，采用半色调掩膜版，对半导体膜进行图案化。
  3. 如权利要求2所述的阵列基板制备方法，其中，在对所述半导体膜的图案化过程中，在对所述光刻胶曝光、显影之后，形成光刻胶完全去除区、光刻胶部分保留区和光刻胶完全保留区，光刻胶完全保留区对应待形成的源漏电极之间的沟道区，光刻胶部分保留区为形成有源层上方被源漏电极覆盖的区域，光刻胶完全去除区为有源层区域以外所对应的区域；
    将光刻胶完全去除区的半导体膜通过刻蚀工艺去除；
    去除光刻胶部分保留区的光刻胶，光刻胶完全保留区保留部分厚度的光刻胶。
  4. 如权利要求1-3任一所述的阵列基板制备方法，其中，形成所述源漏电极包括：
    在形成所述有源层的基板上形成源漏金属层，并对源漏金属层进行图案化以形成源漏电极和源漏电极之间的沟道区，然后将沟道区位置对应的所述部分厚度的光刻胶去除。
  5. 如权利要求1-4任一所述的阵列基板制备方法，还包括在形成有源层之前形成栅极和栅绝缘层。
  6. 如权利要求1-5任一所述的阵列基板制备方法，还包括形成源漏电极之后形成像素电极和钝化层。
  7. 如权利要求1-6任一所述的阵列基板制备方法，其中，所述有源层由ZnO、InZnO、ZnSnO、GaInZnO、或ZrInZnO形成。
  8. 如权利要求1-7任一所述的阵列基板制备方法，其中，所述有源层的 厚度为
    Figure PCTCN2014088589-appb-100001
  9. 如权利要求1-8任一所述的阵列基板制备方法，其中，形成所述源漏金属层的厚度为
    Figure PCTCN2014088589-appb-100002
  10. 如权利要求5所述的阵列基板制备方法，其中，所述栅极由Cr、Mo、Al、或Cu形成。
  11. 如权利要求6所述的阵列基板制备方法，其中，所述像素电极由厚度为
    Figure PCTCN2014088589-appb-100003
    的透明电极形成。
  12. 如权利要求6所述的阵列基板制备方法，其中，所述钝化层由一层SiOx形成，或者由SiOx层和SiNx层复合形成。
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US20160247828A1 (en) 2016-08-25

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