WO2016029557A1 - 阵列基板及其制造方法和显示面板 - Google Patents

阵列基板及其制造方法和显示面板 Download PDF

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WO2016029557A1
WO2016029557A1 PCT/CN2014/091121 CN2014091121W WO2016029557A1 WO 2016029557 A1 WO2016029557 A1 WO 2016029557A1 CN 2014091121 W CN2014091121 W CN 2014091121W WO 2016029557 A1 WO2016029557 A1 WO 2016029557A1
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Prior art keywords
pattern
layer
active
ohmic contact
film transistor
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PCT/CN2014/091121
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English (en)
French (fr)
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崔承镇
宋泳珍
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京东方科技集团股份有限公司
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Priority to US14/768,967 priority Critical patent/US9929184B2/en
Publication of WO2016029557A1 publication Critical patent/WO2016029557A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, and a display panel including the array substrate.
  • the array substrate includes a thin film transistor including an active layer 40, a channel region 41 formed in the active layer 40, an ohmic contact layer 51 disposed on the active layer 40, and an ohmic contact.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display panel including the array substrate.
  • the array substrate is fabricated by the manufacturing method, and there is no residue above the channel region, thereby improving the thin film transistor. Reliability and improved product yield.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, the array substrate including a thin film transistor.
  • the method of fabricating the array substrate includes: forming an intermediate pattern, the intermediate pattern including an active pattern and an ohmic contact pattern over the active pattern, the active pattern including a source active pattern region, a drain having a source pattern region and a channel active pattern region between the source active pattern region and the drain active pattern region, the ohmic contact pattern region including over the source active pattern region a source ohmic contact region, a drain ohmic contact region above the drain active pattern region, and a channel ohmic contact region over the channel active pattern region; forming a source including the thin film transistor a pattern of a drain, a source of the thin film transistor being above the source ohmic contact region, a drain of the thin film transistor being above the drain ohmic contact region; forming a transparent electrode material layer, the transparent electrode material a layer covering a substrate including a pattern of source and drain of the thin film transistor
  • patterning the transparent electrode material layer may include: forming a first photoresist layer over the transparent electrode material layer; performing photolithography on the first photoresist layer by using a first mask Forming a pattern corresponding to the pixel electrode on the first photoresist layer; etching the transparent electrode material layer according to a pattern of the first photoresist layer corresponding to the pixel electrode to obtain A pattern of the pixel electrode.
  • patterning the intermediate pattern may include: forming a second photoresist layer over the pattern including the pixel electrode; and photolithographically etching the second photoresist layer with the second mask to Forming a pattern corresponding to the active layer and the ohmic contact layer of the thin film transistor on the second photoresist layer; according to the pattern of the second photoresist layer corresponding to the active layer and the ohmic contact layer of the thin film transistor
  • the intermediate pattern is etched to form a pattern including an active layer of the thin film transistor and a pattern including the ohmic contact layer.
  • the patterning of the transparent electrode material layer and the patterning of the intermediate pattern may be performed, including: forming a third photoresist layer over the transparent electrode material layer; and the third photoresist layer Performing photolithography to form a pattern corresponding to the pixel electrode, the active layer of the thin film transistor, and the ohmic contact layer; according to the third photoresist layer corresponding to the pixel electrode, the thin film transistor
  • the pattern of the source layer and the ohmic contact layer etches the transparent electrode material layer and the intermediate pattern to obtain a pattern including an active layer, a pixel electrode, and an ohmic contact layer of the thin film transistor.
  • the step of forming an intermediate pattern may include: forming an active layer film and an ohmic contact layer film over the active layer film; patterning the active layer film and the ohmic contact layer film to form a The middle figure.
  • the step of forming an intermediate pattern and forming a pattern including the source and drain of the thin film transistor may be performed, including: forming a semiconductor layer; doping the semiconductor layer to form an active semiconductor layer and located at the a doped layer over the source semiconductor layer, the active semiconductor layer having the same composition as the semiconductor layer; a source/drain metal layer formed over the doped layer; and a fourth light formed over the source and drain metal layer a photoresist layer; photolithographically patterning the fourth photoresist layer with a halftone mask to form a pattern corresponding to a source and a drain of the thin film transistor and the intermediate pattern; The photoresist layer etches the source/drain metal layer, the doped layer, and the active semiconductor layer corresponding to a source and a drain of the thin film transistor and a pattern of the intermediate pattern to A pattern including a source and a drain of the thin film transistor and the intermediate pattern is obtained.
  • the thickness of the active semiconductor layer is to between.
  • the thickness of a portion of the material from which the channel active pattern region is removed is to between.
  • At least one embodiment of the present invention provides an array substrate produced by the manufacturing method provided by the above embodiment of the present invention.
  • the thickness of the channel region of the thin film transistor is to between.
  • At least one embodiment of the present invention provides a display panel including an array substrate, which is an array substrate provided by the above embodiments of the present invention.
  • 1 is a partial schematic view of an array substrate
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • Figure 3 is an intermediate structure forming the array substrate shown in Figure 2;
  • FIG. 8 are schematic diagrams showing intermediate structures at different stages when the array substrate is manufactured by using the manufacturing method provided by the embodiment of the present invention.
  • FIG. 9 is a schematic diagram of an array substrate according to an embodiment of the invention.
  • channel region 51 ohmic contact layer
  • C1 drain ohmic contact area
  • C2 channel ohmic contact area
  • D2 channel active pattern area
  • D3 source active pattern area
  • gate 70 gate insulating layer
  • the ohmic contact layer 51 and the ohmic contact layer 52 are obtained by etching a doped layer (i.e., an N+ layer).
  • 3 is an intermediate structure of an array substrate formed before depositing a pixel electrode, and as shown in FIG. 3, the intermediate structure has formed an active layer 40, a channel region 41, an ohmic contact layer 51, and an ohmic contact layer 52. Subsequently, a layer of a transparent electrode material is deposited on the intermediate structure in FIG. 3, and the pixel electrode 10 is obtained by etching a layer of the transparent electrode material.
  • the transparent electrode material is often not completely etched away, that is, a residue of a transparent electrode material or an organic substance (for example, a photoresist) is easily formed on the channel region 41. 10a, which results in reduced reliability of the thin film transistor and also reduces the yield of the product. Therefore, how to prevent the formation of residues above the channel region 41 has become a technical problem to be solved in the art.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, the array substrate including a thin film transistor. As shown in FIG. 4, the method for fabricating the array substrate can be as follows.
  • the intermediate pattern includes an active pattern D and an ohmic contact pattern C located above the active pattern D;
  • the active pattern D includes a source active pattern region D3, a drain active pattern region D1, and a source active pattern.
  • the ohmic contact pattern C includes a source ohmic contact region C3 over the source active pattern region D3, and is located in the drain active pattern region A drain ohmic contact region C1 above D1 and a channel ohmic contact region C2 above the channel active pattern region D2.
  • a pattern including the source 30 and the drain 20 of the thin film transistor is formed, the source 30 of the thin film transistor is located above the source ohmic contact region C3, and the drain 20 is located above the drain ohmic contact region C1.
  • a transparent electrode material layer E is formed which covers the substrate including the pattern of the source 30 and the drain 20 of the thin film transistor.
  • the transparent electrode material layer E is patterned to obtain a pattern including the pixel electrode 10.
  • the intermediate pattern is patterned to remove the channel ohmic contact region C2 and remove a portion of the material of the channel active pattern region D2 to form the active layer 40 of the thin film transistor (see FIGS. 7 to 9). ).
  • the source active pattern region D3, the channel active pattern region D2, and the drain active pattern region D1 are continuous.
  • the dotted line indicates only the above.
  • the approximate boundary of the active pattern region D3, the channel active pattern region D2, and the drain active pattern region D1, rather than the above-described active pattern region D3, channel active pattern region D2, and drain active pattern region D1 are strictly boundary.
  • the channel active pattern D2 is finally formed as a channel region 41 in the active layer 40 of the thin film transistor, and the drain active pattern region D1 finally forms a portion of the active layer 40 that is in contact with the drain 20, the source has The source pattern region D3 finally forms a portion of the active layer 40 that is in contact with the source electrode 30.
  • the drain ohmic contact region C1 is finally formed as an ohmic contact layer 51 in contact with the drain electrode 20, and the source ohmic contact region C3 is finally formed as an ohmic contact layer 52 in contact with the source electrode 30.
  • the ohmic contact pattern C for forming the ohmic contact layers 51, 52 is not etched before the transparent electrode material layer E is etched. Since a part of the transparent electrode material layer E is located above the channel ohmic contact region C2 of the ohmic contact pattern C, the transparent electrode material or the organic substance remains on the channel ohmic contact region C2 even after the etching of the transparent electrode material layer E is completed (for example, a photoresist), when the ohmic contact pattern C is etched, the transparent electrode material or organic material remaining on the ohmic contact pattern C can still be completely etched by etching away the channel ohmic contact region C2. It can be seen that after the ohmic contact layers 51 and 52 and the channel region 41 are formed by etching the ohmic contact pattern C, there is no residual of the transparent electrode material or the organic material on the channel region 41.
  • the ohmic contact pattern C can protect the active pattern D when the transparent electrode material layer E is etched.
  • the thin film transistor of the array substrate has a comparative High reliability and yield.
  • the manufacturing method further includes the following steps before the step of forming the intermediate pattern.
  • a pattern including the gate electrode 60 of the thin film transistor is formed; then, a gate insulating layer 70 is formed.
  • the intermediate pattern is formed on the gate insulating layer 70.
  • the ohmic contact pattern C herein may be a so-called "N+ layer” in the art.
  • the transparent electrode material layer may be an ITO (ie, indium tin oxide) layer, and the source 30 and the drain 20 may be formed using a metal such as Al or Mo.
  • the semiconductor layer may be made of amorphous silicon (i.e., a-Si), and the ohmic contact pattern C may be made of amorphous silicon (i.e., N+a-Si) doped with, for example, N+ impurities.
  • the step of etching the semiconductor layer, the transparent electrode material layer, and the doped layer is not particularly limited as long as a desired pattern can be formed.
  • the semiconductor layer, the transparent electrode material layer, and the doped layer may be etched using a conventional photolithography process to obtain a desired pattern.
  • patterning the transparent electrode material layer can be performed as follows.
  • Patterning the intermediate pattern can be performed, for example, as follows. Forming a second photoresist layer over the pattern including the pixel electrode 10; performing photolithography on the second photoresist layer by using a second mask to form a film corresponding to the film on the second photoresist layer a pattern of an active layer and an ohmic contact layer of the transistor; etching the intermediate pattern according to a pattern of the second photoresist layer corresponding to an active layer and an ohmic contact layer of the thin film transistor to form a package A pattern of an active layer of the thin film transistor and a pattern including the ohmic contact layer.
  • Two masks are used in the above method, and in at least one embodiment of the invention, the same effect can be achieved by using a mask (ie, obtaining a pixel electrode, a pattern of an active layer of a thin film transistor, and an ohmic contact layer).
  • patterning the transparent electrode material layer and patterning the intermediate pattern in synchronization i.e., performing the two-step patterning process in the same step
  • patterning the transparent electrode material layer and patterning the intermediate pattern in synchronization can be performed, for example, as follows.
  • a third photoresist layer F over the transparent electrode material layer E, as shown in FIG. 6; performing photolithography (exposure development) on the third photoresist layer F to form corresponding to the pixel electrode 10 and the thin film transistor a pattern of the source layer 40 and the ohmic contact layers 51, 52; a pattern pair corresponding to the pixel electrode 10, the active layer 40 of the thin film transistor, and the ohmic contact layers 51, 52 according to the third photoresist layer F
  • the transparent electrode material layer E and the intermediate pattern are etched to obtain a pattern including the active layer 40, the pixel electrode 10, and the ohmic contact layers 51, 52 of the thin film transistor.
  • the remaining portion of the third photoresist layer F may be peeled off to obtain a pattern.
  • the array substrate described in 9. Although the transparent electrode material remains on the source 30 in FIG. 9, the transparent electrode material does not have a gray scale signal and does not affect the display of the display panel.
  • the above method reduces one mask and reduces the one-step lithography process, thereby reducing the cost of manufacturing the array substrate.
  • the step of forming the intermediate pattern is also not particularly limited.
  • forming an intermediate graphic can be performed as follows.
  • An active layer film and an ohmic contact layer film over the active layer film are formed; the active layer film and the ohmic contact layer film are patterned to form the intermediate pattern.
  • forming the active layer film and the ohmic contact layer over the active layer film can be performed as follows.
  • Forming a semiconductor layer Forming a semiconductor layer; doping the semiconductor layer to form an active semiconductor layer and a doped layer over the active semiconductor layer, the active semiconductor layer having the same composition as the semiconductor layer.
  • the semiconductor layers may each be an amorphous silicon material, and the amorphous silicon material may be deposited on the substrate by evaporation or sputtering.
  • the so-called "patterning of the active semiconductor layer and the doped layer" herein may be a conventional photolithography process. That is, a photoresist is coated on the doped layer, and then the formed photoresist layer is photolithographically (ie, exposed, developed) by using a mask, so that the formed photoresist layer is formed on the photoresist layer corresponding to the intermediate pattern. The pattern is then etched using the exposed developed photoresist as a mask to form the intermediate pattern.
  • the step of forming the intermediate pattern and the pattern forming the source and the drain including the thin film transistor may be performed simultaneously, for example, as follows.
  • the source and drain metal layers, the doped layer, and the active semiconductor layer are etched to obtain a pattern including a source and a drain of the thin film transistor and the intermediate pattern.
  • the embodiment reduces the coating of the one-step photoresist and reduces the use of the one-step mask, simplifying the whole.
  • the steps of the production method save costs.
  • the method provided by this embodiment is also advantageous in that only one layer of photoresist (i.e., the fourth photoresist layer) is applied. Therefore, the photoresist is not introduced to the surface of the active pattern D after the channel ohmic contact region C2 of the ohmic contact pattern C is etched, thereby completely eliminating the residual organic matter on the channel region.
  • the thickness of each layer of material is not particularly limited.
  • the thickness of the active semiconductor layer may be set at to between.
  • the thickness of the doped layer can be set at to between.
  • the thickness of a portion of the material removed by the channel active pattern region is to Obtaining the channel region.
  • the thickness of the channel region 41 of the thin film transistor may be to between.
  • the thickness of the etch is Active graphics D as well
  • the ohmic contact pattern C is first, the portion of the ohmic contact pattern C corresponding to the channel region 41 (the channel ohmic contact region C2) is first completely etched, and then the portion of the active pattern D corresponding to the channel region 41 is That is, the channel active pattern region D2) is etched away Thereby obtaining a thickness of Channel region 41.
  • At least one embodiment of the present invention provides an array substrate, wherein the array substrate is fabricated by the manufacturing method provided by the above embodiment of the present invention. As described above, in the manufacturing method provided by at least one embodiment of the present invention, the channel ohmic contact region corresponding to the channel region in the ohmic contact pattern C is not applied before the transparent electrode material layer E is etched. C2 erosion.
  • the transparent electrode material layer E is located above the ohmic contact pattern C, even after etching the transparent electrode material layer E, In the ohmic contact pattern C, a transparent electrode material or an organic substance (for example, a photoresist) remains on the channel ohmic contact region C2 corresponding to the channel region, and then the channel can be ohmically contacted when etching the ohmic contact pattern C.
  • the transparent electrode material or the organic material remaining on the region C2 is completely etched. Therefore, when the ohmic contact layers 51, 52 and the channel region 41 are formed by etching the ohmic contact pattern C, there is no transparent electrode material on the channel region 41 or Residue of organic matter.
  • a thickness of a channel region of the thin film transistor is to between.
  • At least one embodiment of the present invention provides a display panel, the display panel including an array substrate, wherein the array substrate is the above array substrate provided by the present invention.
  • the display panel including the array substrate also has a high yield and has a good display effect.
  • the display panel further includes a pair of cassette substrates disposed on the array substrate.
  • the display panel can be used for electronic devices such as mobile phones and computers.

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Abstract

一种阵列基板及其制造方法和显示面板，所述阵列基板包括薄膜晶体管，所述制造方法包括：形成中间图形；形成包括所述薄膜晶体管的源极(30)和漏极(20)的图形，所述薄膜晶体管的源极(30)位于源极欧姆接触区(C3)上方，所述薄膜晶体管的漏极(20)位于漏极欧姆接触区(C1)上方；形成透明电极材料层(E)，所述透明电极材料层(E)覆盖包括所述薄膜晶体管的源极(30)和漏极(20)的图形的基板；对所述透明电极材料层(E)进行构图，以获得包括所述像素电极(10)的图形；对所述中间图形进行构图，以去除所述沟道欧姆接触区(C2)，并去除所述沟道有源图形区(D2)的部分材料，以形成所述薄膜晶体管的有源层(40)。

Description

阵列基板及其制造方法和显示面板 技术领域
本发明的实施例涉及一种阵列基板及其制造方法和包括所述阵列基板的显示面板。
背景技术
图1和图2中所示的是一种阵列基板的局部示意图。如图中所示，阵列基板包括薄膜晶体管，所述薄膜晶体管包括有源层40、形成在有源层40中的沟道区41、设置在有源层40上的欧姆接触层51和欧姆接触层52、设置在欧姆接触层51上的漏极20和设置在欧姆接触层52上的源极30；漏极20电连接至像素电极10。
发明内容
本发明至少一实施例提供一种阵列基板及其制造方法和一种包括所述阵列基板的显示面板，利用所述制造方法制造阵列基板，沟道区的上方没有残留物，提高了薄膜晶体管的可靠性，并且提高了产品的良率。
本发明至少一实施例提供一种阵列基板的制造方法，所述阵列基板包括薄膜晶体管。所述阵列基板的制造方法包括：形成中间图形，所述中间图形包括有源图形和位于所述有源图形上方的欧姆接触图形，所述有源图形包括源极有源图形区、漏极有源图形区和位于所述源极有源图形区和所述漏极有源图形区之间的沟道有源图形区，所述欧姆接触图形区包括位于所述源极有源图形区上方的源极欧姆接触区、位于所述漏极有源图形区上方的漏极欧姆接触区和位于所述沟道有源图形区上方的沟道欧姆接触区；形成包括所述薄膜晶体管的源极和漏极的图形，所述薄膜晶体管的源极位于所述源极欧姆接触区上方，所述薄膜晶体管的漏极位于所述漏极欧姆接触区上方；形成透明电极材料层，所述透明电极材料层覆盖包括所述薄膜晶体管的源极和漏极的图形的基板；对所述透明电极材料层进行构图，以获得包括所述像素电极的图形；对所述中间图形进行构图，以去除所述沟道欧姆接触区，并去除所述 沟道有源图形区的部分材料，以形成所述薄膜晶体管的有源层。
例如，对所述透明电极材料层进行构图可以包括：在所述透明电极材料层上方形成第一光刻胶层；利用第一掩膜板对所述第一光刻胶层进行光刻，以在所述第一光刻胶层上形成对应于所述像素电极的图形；根据所述第一光刻胶层对应于所述像素电极的图形对所述透明电极材料层进行刻蚀，以获得所述像素电极的图形。
例如，对所述中间图形进行构图可以包括：在包括所述像素电极的图形上方形成第二光刻胶层；利用第二掩膜板对所述第二光刻胶层进行光刻，以在第二光刻胶层上形成对应于所述薄膜晶体管的有源层和欧姆接触层的图形；根据所述第二光刻胶层对应于所述薄膜晶体管的有源层和欧姆接触层的图形对所述中间图形进行刻蚀，以形成包括所述薄膜晶体管的有源层的图形和包括所述欧姆接触层的图形。
例如，对所述透明电极材料层的构图以及对所述中间图形的构图同步进行，可以包括：在所述透明电极材料层上方形成第三光刻胶层；对所述第三光刻胶层进行光刻，以形成对应于所述像素电极、所述薄膜晶体管的有源层和欧姆接触层的图形；根据所述第三光刻胶层对应于所述像素电极、所述薄膜晶体管的有源层和所述欧姆接触层的图形对所述透明电极材料层和所述中间图形进行刻蚀，以获得包括所述薄膜晶体管的有源层、像素电极和欧姆接触层的图形。
例如，形成中间图形的步骤可以包括：形成有源层薄膜和位于所述有源层薄膜上方的欧姆接触层薄膜；对所述有源层薄膜和所述欧姆接触层薄膜进行构图，以形成所述中间图形。
例如，形成中间图形的步骤和形成包括所述薄膜晶体管的源极和漏极的图形同步进行，可以包括：形成半导体层；对半导体层进行掺杂，以形成有源半导体层和位于所述有源半导体层上方的掺杂层，所述有源半导体层的成分与所述半导体层相同；在所述掺杂层上方形成源漏金属层；在所述源漏极金属层上方形成第四光刻胶层；利用半色调掩膜板对所述第四光刻胶层进行光刻，以形成对应于所述薄膜晶体管的源极和漏极以及所述中间图形的图形；根据所述第四光刻胶层对应于所述薄膜晶体管的源极和漏极以及所述中间图形的图形对所述源漏金属层、所述掺杂层和所述有源半导体层进行刻蚀，以 获得包括所述薄膜晶体管的源极和漏极以及所述中间图形的图形。
例如，所述有源半导体层的厚度在
Figure PCTCN2014091121-appb-000001
至
Figure PCTCN2014091121-appb-000002
之间。
例如，对所述中间图形进行构图的步骤中，去除所述沟道欧姆接触区后，去除所述沟道有源图形区的部分材料的厚度在
Figure PCTCN2014091121-appb-000003
至
Figure PCTCN2014091121-appb-000004
之间。
本发明至少一实施例提供一种阵列基板，所述阵列基板由本发明上述实施例提供的制造方法制得。
例如，所述薄膜晶体管的沟道区厚度在
Figure PCTCN2014091121-appb-000005
至
Figure PCTCN2014091121-appb-000006
之间。
本发明至少一实施例提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板为本发明上述实施例所提供的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是一种阵列基板的局部示意图；
图2是沿图1中的A-A线剖切得到的剖视图；
图3是形成图2中所示的阵列基板的中间结构；
图4至图8展示了利用本发明实施例所提供的制造方法制造所述阵列基板时，不同阶段的中间结构的示意图；
图9是本发明一实施例所提供的阵列基板的示意图。
附图标记
10：像素电极        20：漏极
30：源极            40：有源层
41：沟道区          51：欧姆接触层
52：欧姆接触层      10a：残留物
C：欧姆接触图形     D：有源图形
E：透明电极材料层   F：第三光刻胶层
C1：漏极欧姆接触区  C2：沟道欧姆接触区
C3：源极欧姆接触区  D1漏极有源图形区
D2：沟道有源图形区  D3：源极有源图形区
60：栅极            70：栅绝缘层
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图2所示，通过刻蚀掺杂层(即，N+层)获得欧姆接触层51和欧姆接触层52。图3是在沉积形成像素电极之前形成的阵列基板的中间结构，如图3所示，所述中间结构已经形成了有源层40、沟道区41、欧姆接触层51和欧姆接触层52。随后在图3中的中间结构上沉积一层透明电极材料层，通过刻蚀透明电极材料层获得像素电极10。在刻蚀透明电极材料层形成像素电极10的过程中，透明电极材料往往不能完全被蚀除，即，在沟道区41上容易形成透明电极材料或有机物(例如，光刻胶)的残留物10a，这导致薄膜晶体管可靠性降低，并且还降低了产品的良率。因此，如何防止沟道区41上方形成残留物成为本领域亟待解决的技术问题。
本发明至少一实施例提供一种阵列基板的制造方法，所述阵列基板包括薄膜晶体管，如图4所示，所述阵列基板的制造方法可如下所述。
形成中间图形。所述中间图形包括有源图形D和位于该有源图形D上方的欧姆接触图形C；有源图形D包括源极有源图形区D3、漏极有源图形区D1和位于源极有源图形区D3和漏极有源图形区D1之间的沟道有源图形区D2；欧姆接触图形C包括位于源极有源图形区D3上方的源极欧姆接触区C3、位于漏极有源图形区D1上方的漏极欧姆接触区C1以及位于沟道有源图形区D2上方的沟道欧姆接触区C2。
形成包括所述薄膜晶体管的源极30和漏极20的图形，所述薄膜晶体管的源极30位于源极欧姆接触区C3上方，漏极20位于漏极欧姆接触区C1上方。
形成透明电极材料层E，该透明电极材料层E覆盖包括所述薄膜晶体管的源极30和漏极20的图形的基板。
对透明电极材料层E进行构图，以获得包括像素电极10的图形。
对所述中间图形进行构图，以去除所述沟道欧姆接触区C2，并去除沟道有源图形区D2的部分材料，以形成所述薄膜晶体管的有源层40(参见图7至图9)。
容易理解的是，在有源图形D中，源极有源图形区D3、沟道有源图形区D2和漏极有源图形区D1是连续的，在图4中，虚线表示的仅仅是上述有源图形区D3、沟道有源图形区D2和漏极有源图形区D1的大致边界，而非上述有源图形区D3、沟道有源图形区D2和漏极有源图形区D1严格边界。沟道有源图形D2最终形成为所述薄膜晶体管的有源层40中的沟道区41，漏极有源图形区D1最终形成有源层40上与漏极20接触的部分，源极有源图形区D3最终形成有源层40上与源极30接触的部分。
同理，在欧姆接触图形C中，漏极欧姆接触区C1、沟道欧姆接触区C2和源极欧姆接触区C3是连续的，虚线表示的仅仅是漏极欧姆接触区C1、沟道欧姆接触区C2和源极欧姆接触区C3之间的大致边界。在欧姆接触图形C中，漏极欧姆接触区C1最终形成为与漏极20接触的欧姆接触层51，源极欧姆接触区C3最终形成为与源极30接触的欧姆接触层52。
在本发明至少一实施例所提供的制造方法中，在对透明电极材料层E进行刻蚀之前，并未对用于形成欧姆接触层51、52的欧姆接触图形C进行刻蚀。由于透明电极材料层E的一部分位于欧姆接触图形C的沟道欧姆接触区C2上方，因此，即便对透明电极材料层E刻蚀完毕后沟道欧姆接触区C2上残留有透明电极材料或有机物(例如，光刻胶)，那么在刻蚀欧姆接触图形C时，仍然能够通过将沟道欧姆接触区C2刻蚀掉而将欧姆接触图形C上残留的透明电极材料或有机物完全刻蚀。由此可知，在对欧姆接触图形C刻蚀完毕形成了欧姆接触层51、52以及沟道区41后，沟道区41上并没有透明电极材料或有机物的残留。
在刻蚀透明电极材料层E时，欧姆接触图形C可以对有源图形D进行保护。
由此可知，利用本发明至少一实施例所提供的制造方法制得的阵列基板中，薄膜晶体管的沟道区41上方没有透明电极材料或有机物的残留，因此所述阵列基板的薄膜晶体管具有较高的可靠性和良率。
容易理解的是，在形成中间图形之前，阵列基板的衬底上已经形成有栅极60和栅绝缘层70。例如，所述制造方法在形成中间图形的步骤之前还包括如下步骤。
形成包括所述薄膜晶体管的栅极60的图形；然后，形成栅绝缘层70。所述中间图形形成在栅绝缘层70上。
本领域技术人员应当理解的是，此处的欧姆接触图形C可以为本领域中所谓的“N+层”。例如，透明电极材料层可以为ITO(即，氧化铟锡)层，可以利用Al、Mo等金属形成源极30和漏极20。例如，半导体层可以由非晶硅(即，a-Si)制成，而欧姆接触图形C则可由掺杂如N+杂质的非晶硅(即，N+a-Si)制成。
对所述半导体层、所述透明电极材料层和所述掺杂层进行刻蚀的步骤并没有特殊的规定，只要能够形成所需的图形即可。例如，可以利用传统的光刻工艺对所述半导体层、所述透明电极材料层和所述掺杂层进行刻蚀已获得所需的图形。
本发明至少一实施例中，对所述透明电极材料层进行构图可以如下进行。
在透明电极材料层E上方形成第一光刻胶层；利用第一掩膜板对所述第一光刻胶层进行光刻(即，曝光显影)，以在所述第一光刻胶层上形成对应于所述像素电极的图形；根据所述第一光刻胶胶层对应于所述像素电极的图形对透明电极材料层E进行刻蚀，以获得像素电极10的图形。
对所述中间图形进行构图例如可以如下进行。在包括像素电极10的图形上方形成第二光刻胶层；利用第二掩膜板对所述第二光刻胶层进行光刻，以在第二光刻胶层上形成对应于所述薄膜晶体管的有源层和欧姆接触层的图形；根据所述第二光刻胶层对应于所述薄膜晶体管的有源层和欧姆接触层的图形对所述中间图形进行刻蚀，以形成包括所述薄膜晶体管的有源层的图形和包括所述欧姆接触层的图形。
在上述方法中使用了两个掩膜板(第一掩膜板和第二掩膜板)，在本发明至少一实施例中，使用一个掩膜板也可以达到相同的效果(即，获得包括像素电极、薄膜晶体管的有源层和欧姆接触层的图形)。
例如，对所述透明电极材料层进行构图以及对所述中间图形进行构图同步进行(即，在同一步骤中完成上述两步构图工艺)，例如可以如下进行。
在透明电极材料层E上方形成第三光刻胶层F，如图6所示；对第三光刻胶层F进行光刻(曝光显影)，以形成对应于像素电极10、薄膜晶体管的有源层40和欧姆接触层51、52的图形；根据第三光刻胶层F对应于所述像素电极10、所述薄膜晶体管的有源层40和所述欧姆接触层51、52的图形对所述透明电极材料层E和所述中间图形进行刻蚀，以获得包括所述薄膜晶体管的有源层40、像素电极10和欧姆接触层51、52的图形。
在形成了包括所述薄膜晶体管的有源层40、像素电极10和欧姆接触层40的图形(参见图8)后，可以对第三光刻胶层F中剩余的部分进行剥离，以获得图9中所述的阵列基板。虽然在图9中，源极30上方残留有透明电极材料，但是，该透明电极材料并不接入灰阶信号，不会对显示面板的显示造成影响。
上述方法减少了一个掩膜板，并且减少了一步光刻工艺，因此，可以降低制造阵列基板的成本。
在本发明至少一实施例中，对形成所述中间图形的步骤也没有特殊的限定。例如，形成中间图形可以如下进行。
形成有源层薄膜和位于所述有源层薄膜上方的欧姆接触层薄膜；对所述有源层薄膜和所述欧姆接触层薄膜进行构图，以形成所述中间图形。
例如，形成有源层薄膜和位于所述有源层薄膜上方的欧姆接触层可以如下进行。
形成半导体层；对半导体层进行掺杂，以形成有源半导体层和位于所述有源半导体层上方的掺杂层，所述有源半导体层的成分与所述半导体层相同。
在上述实施例中，半导体层均可以为非晶硅材料，可以通过蒸镀或溅射等方式将非晶硅材料沉积在基板上。此处所谓的“对所述有源半导体层和所述掺杂层进行构图”可以为传统的光刻工艺。即，在掺杂层上方涂敷光刻胶，然后利用掩膜板对形成的光刻胶层进行光刻(即，曝光、显影)，使得形成的光刻胶层上形成对应于中间图形的图形，随后利用曝光显影后的光刻胶作为掩膜对掺杂层和有源半导体层进行刻蚀，以形成所述中间图形。
为了减少工艺步骤、降低工艺成本，例如，形成中间图形的步骤和形成包括所述薄膜晶体管的源极和漏极的图形可以同步进行，例如，可以如下进行。
形成半导体层；对半导体层进行掺杂，以形成有源半导体层和位于所述有源半导体层上方的掺杂层，所述有源半导体层的成分与所述半导体层相同；在所述掺杂层上方形成源漏金属层；在所述源漏极金属层上方形成第四光刻胶层；利用半色调掩膜板对所述第四光刻胶层进行光刻(即，曝光显影)，以形成对应于所述薄膜晶体管的源极和漏极以及所述中间图形的图形；根据所述第四光刻胶层对应于所述薄膜晶体管的源极和漏极以及所述中间图形的图形对所述源漏金属层、所述掺杂层和所述有源半导体层进行刻蚀，以获得包括所述薄膜晶体管的源极和漏极以及所述中间图形的图形。
与前述分别形成中间图形和形成包括所述薄膜晶体管的源极和漏极的图形相比，本实施例减少了一步光刻胶的涂敷，也减少了一步掩膜板的使用，简化了整个制作方法的步骤，节约了成本。除了上述优点之外，本实施例所提供的方法的优点还在于，仅涂敷了一层光刻胶(即，第四光刻胶层)。因此，蚀除了欧姆接触图形C的沟道欧姆接触区C2之后不会向有源图形D的表面上引入光刻胶，从而完全杜绝了在沟道区上残留有机物。
在本发明至少一实施例中，对各层材料的厚度并没有特殊的限制，例如，所述有源半导体层的厚度可以设置在
Figure PCTCN2014091121-appb-000007
至
Figure PCTCN2014091121-appb-000008
之间。掺杂层的厚度可以设置在
Figure PCTCN2014091121-appb-000009
至
Figure PCTCN2014091121-appb-000010
之间。对所述中间图形进行构图的步骤中，去除所述沟道欧姆接触区后，所述沟道有源图形区去除的部分材料的厚度为
Figure PCTCN2014091121-appb-000011
至
Figure PCTCN2014091121-appb-000012
以获得所述沟道区。
利用本发明至少一实施例所提供的制造方法制得的阵列基板中，薄膜晶体管的沟道区41的厚度可以在
Figure PCTCN2014091121-appb-000013
至
Figure PCTCN2014091121-appb-000014
之间。在刻蚀厚度为
Figure PCTCN2014091121-appb-000015
的有源图形D以及
Figure PCTCN2014091121-appb-000016
的欧姆接触图形C时，首先将欧姆接触图形C中对应于沟道区41的部分(沟道欧姆接触区C2)完全蚀除，然后将有源图形D上对应于沟道区41的部分(即，沟道有源图形区D2)蚀除
Figure PCTCN2014091121-appb-000017
从而可以得到厚度为
Figure PCTCN2014091121-appb-000018
的沟道区41。
本发明至少一实施例提供一种阵列基板，其中，所述阵列基板由本发明上述实施例所提供的制造方法制得。如上文中所述，在本发明至少一实施例所提供的制造方法中，在对透明电极材料层E进行刻蚀之前，并未对欧姆接触图形C中对应于沟道区的沟道欧姆接触区C2蚀除。由于透明电极材料层E位于欧姆接触图形C上方，因此，即便对透明电极材料层E刻蚀完毕后， 欧姆接触图形C中对应于沟道区的沟道欧姆接触区C2上残留有透明电极材料或有机物(例如，光刻胶)，那么，在刻蚀欧姆接触图形C时仍然能够将沟道欧姆接触区C2上残留的透明电极材料或有机物完全刻蚀，因此，在对欧姆接触图形C刻蚀完毕形成了欧姆接触层51、52以及沟道区41时，沟道区41上没有透明电极材料或有机物的残留。
在本发明至少一实施例中所提供的阵列基板中，所述薄膜晶体管的沟道区厚度在
Figure PCTCN2014091121-appb-000019
至
Figure PCTCN2014091121-appb-000020
之间。
在本发明至少一实施例提供一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
由于所述阵列基板的薄膜晶体管具有较高的可靠性和良率，因此，包括所述阵列基板的显示面板也具有较高的良率，并具有较好的显示效果。
容易理解的是，所述显示面板还包括与所述阵列基板对盒设置的对盒基板。所述显示面板可以用于手机、电脑等电子设备。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年8月25日递交的中国专利申请第201410421632.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种阵列基板的制造方法，所述阵列基板包括薄膜晶体管，所述制造方法包括：
    形成中间图形，所述中间图形包括有源图形和位于所述有源图形上方的欧姆接触图形，所述有源图形包括源极有源图形区、漏极有源图形区和位于所述源极有源图形区和所述漏极有源图形区之间的沟道有源图形区，所述欧姆接触图形区包括位于所述源极有源图形区上方的源极欧姆接触区、位于所述漏极有源图形区上方的漏极欧姆接触区和位于所述沟道有源图形区上方的沟道欧姆接触区；
    形成包括所述薄膜晶体管的源极和漏极的图形，所述薄膜晶体管的源极和漏极位于所述掺杂层上方；
    形成透明电极材料层，所述透明电极材料层覆盖包括所述薄膜晶体管的源极和漏极的图形的基板；
    对所述透明电极材料层进行构图，以形成包括像素电极的图形；
    对所述中间图形进行构图，以去除所述沟道欧姆接触区，并去除所述沟道有源图形区的部分材料，以形成所述薄膜晶体管的有源层。
  2. 根据权利要求1所述的阵列基板的制造方法，其中，对所述透明电极材料层进行构图包括：
    在所述透明电极材料层上方形成第一光刻胶层；
    利用第一掩膜板对所述第一光刻胶层进行光刻，以在所述第一光刻胶层上形成对应于所述像素电极的图形；
    根据所述第一光刻胶层对应于所述像素电极的图形对所述透明电极材料层进行刻蚀，以获得所述像素电极的图形。
  3. 根据权利要求1所述的阵列基板的制造方法，其中，对所述中间图形进行构图包括：
    在包括所述像素电极的图形上方形成第二光刻胶层；
    利用第二掩膜板对所述第二光刻胶层进行光刻，以在第二光刻胶层上形成对应于所述薄膜晶体管的有源层和欧姆接触层的图形；
    根据所述第二光刻胶层对应于所述薄膜晶体管的有源层和欧姆接触层的 图形对所述中间图形进行刻蚀，以形成包括所述薄膜晶体管的有源层的图形和包括所述欧姆接触层的图形。
  4. 根据权利要求1所述的阵列基板的制造方法，其中，对所述透明电极材料层的构图以及对所述中间图形的构图同步进行。
  5. 根据权利要求4所述的阵列基板的制造方法，其中，
    在所述透明电极材料层上方形成第三光刻胶层；
    对所述第三光刻胶层进行光刻，以形成对应于所述像素电极、所述薄膜晶体管的有源层和欧姆接触层的图形；
    根据所述第三光刻胶层对应于所述像素电极、所述薄膜晶体管的有源层和所述欧姆接触层的图形对所述透明电极材料层和所述中间图形进行刻蚀，以形成包括所述薄膜晶体管的有源层、像素电极和欧姆接触层的图形。
  6. 根据权利要求1所述的制造方法，其中，形成中间图形包括：
    形成有源层薄膜和位于所述有源层薄膜上方的欧姆接触层薄膜；
    对所述有源层薄膜和所述欧姆接触层薄膜进行构图，以形成所述中间图形。
  7. 根据权利要求1所述的制造方法，其中，形成中间图形的步骤和形成包括所述薄膜晶体管的源极和漏极的图形同步进行。
  8. 根据权利要求7所述的制造方法，其中，
    形成半导体层；
    对半导体层进行掺杂，以形成有源半导体层和位于所述有源半导体层上方的掺杂层，所述有源半导体层的成分与所述半导体层相同；
    在所述掺杂层上方形成源漏金属层；
    在所述源漏极金属层上方形成第四光刻胶层；
    利用半色调掩膜板对所述第四光刻胶层进行光刻，以形成对应于所述薄膜晶体管的源极和漏极以及所述中间图形的图形；
    根据所述第四光刻胶层对应于所述薄膜晶体管的源极和漏极以及所述中间图形的图形对所述源漏金属层、所述掺杂层和所述有源半导体层进行刻蚀，以形成包括所述薄膜晶体管的源极和漏极以及所述中间图形的图形。
  9. 根据权利要求8所述的制造方法，其中，所述有源半导体层的厚度在
    Figure PCTCN2014091121-appb-100001
    至
    Figure PCTCN2014091121-appb-100002
    之间。
  10. 根据权利要求9所述的制造方法，其中，对所述中间图形进行构图中，去除所述沟道欧姆接触区后，所述沟道有源图形区去除的部分材料的厚度在
    Figure PCTCN2014091121-appb-100003
    至
    Figure PCTCN2014091121-appb-100004
    之间。
  11. 一种阵列基板，所述阵列基板由权利要求1至10中任意一项所述的制造方法制得。
  12. 根据权利要求11所述的阵列基板，其中，所述薄膜晶体管的沟道区厚度在
    Figure PCTCN2014091121-appb-100005
    至
    Figure PCTCN2014091121-appb-100006
    之间。
  13. 一种显示面板，所述显示面板包括如权利要求11或12所述的阵列基板。
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