WO2016065780A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2016065780A1
WO2016065780A1 PCT/CN2015/073333 CN2015073333W WO2016065780A1 WO 2016065780 A1 WO2016065780 A1 WO 2016065780A1 CN 2015073333 W CN2015073333 W CN 2015073333W WO 2016065780 A1 WO2016065780 A1 WO 2016065780A1
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Prior art keywords
substrate
trench
film layer
pattern
layer pattern
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PCT/CN2015/073333
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English (en)
French (fr)
Inventor
张颖
丁欣
陈甫
刘建辉
董康旭
刘祖宏
吴代吾
侯智
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US14/653,400 priority Critical patent/US20160284737A1/en
Publication of WO2016065780A1 publication Critical patent/WO2016065780A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a method for fabricating the same, and a display device.
  • FIG. 1 is a schematic structural diagram of a thin film transistor array substrate including a base substrate 101 and a gate electrode 102, a gate insulating layer 103, and an active layer formed on the base substrate 101. 104. Source/drain electrodes 105, a passivation layer 106, and a pixel electrode 107.
  • each film layer is stacked on the surface of the flat substrate 101, and the edge of the pattern of the gate electrode 102 causes a step difference at the subsequent film layer, which easily causes the subsequent film layer to break at the position. This causes leakage between the gate and the source/drain electrodes, affecting important thin film transistor performance parameters such as off-state current (Ioff).
  • Ioff off-state current
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can improve the flatness of the overall structure of the display substrate, thereby improving the performance of the display substrate.
  • An embodiment of the first aspect of the present disclosure provides a display substrate including a substrate substrate and a film layer pattern disposed on the substrate and in direct contact with the substrate substrate, wherein the substrate substrate surface is disposed There is a trench, and the film layer pattern is disposed in the trench.
  • the film layer pattern fills the trench.
  • the display substrate is a thin film transistor array substrate
  • the film layer pattern is a gate pattern or an active layer pattern.
  • the film layer pattern is a gate pattern
  • the display substrate specifically includes:
  • the base substrate is a glass substrate.
  • An embodiment of the second aspect of the present disclosure further provides a method of manufacturing a display substrate, including:
  • a film layer pattern filling the trench is formed in the trench.
  • the step of forming a trench on a surface of the base substrate comprises:
  • the photoresist of the photoresist retention region is removed.
  • the step of forming a film layer pattern filling the trench in the trench comprises:
  • the film layer outside the trench is etched away by an etching process to form a film layer pattern located in the trench and filling the trench.
  • the thickness of the entire film layer is at least 1.2 times the depth of the trench.
  • the display substrate is a thin film transistor array substrate
  • the film layer pattern is a gate pattern or an active layer pattern.
  • An embodiment of the third aspect of the present disclosure also provides a display device including the above display substrate.
  • FIG. 1 is a schematic structural view of a thin film transistor array substrate in the related art
  • FIG. 2 is a schematic structural view of a thin film transistor array substrate according to an embodiment of the present disclosure
  • 3-1 to 3-11 are schematic views of a method of fabricating the thin film transistor array substrate of FIG. 2.
  • An embodiment of the first aspect of the present disclosure provides a display substrate including a substrate substrate and a film layer pattern disposed on the substrate and in direct contact with the substrate substrate, wherein the substrate substrate surface is disposed There is a trench, and the film layer pattern is disposed in the trench.
  • the film layer pattern is a non-integral film layer structure.
  • a trench is disposed on a surface of the substrate, and a film pattern of a non-layer film structure directly contacting the substrate is disposed in the trench to reduce a subsequently formed film layer in the film layer.
  • the step difference generated at the pattern improves the overall flatness of the structure of the display substrate and improves the performance of the display substrate.
  • the film layer pattern fills the trench to eliminate a step formed by the subsequently formed film layer at the film layer pattern, further improving the overall flatness of the display substrate and improving the performance of the display substrate.
  • the display substrate may be a thin film transistor array substrate.
  • the film layer pattern may be a gate pattern or an active layer pattern.
  • the film layer pattern may be a gate pattern
  • the film layer pattern may be It is an active layer graphic.
  • the base substrate is a glass substrate.
  • substrate substrates are also possible.
  • FIG. 2 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present disclosure.
  • the thin film transistor array substrate includes: a substrate substrate 201, and a gate electrode 202 and a gate insulating layer disposed on the substrate substrate 201.
  • the surface of the base substrate 201 is provided with a groove 2011, and the pattern of the gate 202 is disposed in the groove 2011, and the groove 2011 is filled.
  • the gate electrode 202, the gate insulating layer 203, the active layer 204, and the source/drain electrodes 205 form a thin film transistor which is a thin film transistor of a bottom gate structure.
  • the film layer difference caused by the edge of the gate 202 can be eliminated, the overall flatness of the structure of the display substrate is improved, and the performance of the display substrate is improved.
  • the thin film transistor array substrate of the embodiment of the present disclosure has a significantly improved flatness of the overall structure as compared with the thin film transistor array substrate of the related art.
  • the embodiment of the present disclosure further provides a thin film transistor array substrate including: a substrate substrate, and an active layer, a source/drain electrode, a gate insulating layer, and a gate formed on the substrate a passivation layer and a pixel electrode, wherein the surface of the base substrate is provided with a groove, and a pattern of the active layer is disposed in the groove and fills the groove.
  • the active layer, the source/drain electrodes, the gate insulating layer, and the gate form a thin film transistor, which is a thin film transistor of a top gate structure.
  • the film layer difference caused by the edge of the active layer can be eliminated, the overall flatness of the structure of the display substrate is improved, and the performance of the display substrate is improved.
  • An embodiment of another aspect of the present disclosure also provides a display device comprising the display substrate described in any of the above embodiments.
  • An embodiment of still another aspect of the present disclosure also provides a method of fabricating a display substrate, the method comprising the steps of:
  • Step S1 forming a trench on the surface of the base substrate, the size of the trench being the same as the size of the subsequently formed film layer pattern;
  • Step S2 forming a film layer pattern filling the trench in the trench.
  • the film layer pattern non-integral film layer structure according to the present disclosure.
  • a trench is formed on the surface of the base substrate, and a film layer pattern of the flattened trench is formed in the trench, so that the subsequently formed film layer does not have a step difference at the film layer pattern, thereby improving The overall flatness of the structure of the substrate is displayed, and the performance of the display substrate is improved.
  • the step of forming a trench on a surface of the base substrate comprises:
  • Step S11 applying a photoresist on a surface of the base substrate
  • Step S12 exposing and developing the photoresist to form a photoresist retention region and a photoresist removal region, wherein the photoresist removal region corresponds to the film layer pattern region;
  • Step S13 etching a substrate corresponding to the completely removed region of the photoresist by an etching process to form the trench;
  • Step S14 removing the photoresist of the photoresist remaining region.
  • the step of forming a film layer pattern in the trench comprises:
  • Step S21 forming a full film layer on the substrate substrate on which the trench is formed, wherein a thickness of the film layer formed on the trench is higher than a depth of the trench;
  • the reason why the thickness of the film layer formed over the trench is higher than the depth of the trench is to achieve the purpose of better smoothing the film layer at the groove position, so that the surface of the formed film pattern is
  • the surface of the base substrate is on a flat surface.
  • Step S22 etching the film layer outside the trench by an etching process to form a film layer pattern located in the trench and filling the trench.
  • the thickness of the entire film layer is at least 1.2 times the depth of the trench.
  • the display substrate may be a thin film transistor array substrate or a color film substrate.
  • the film layer pattern may be a gate pattern or an active layer pattern.
  • the film layer pattern may be a gate pattern
  • the film layer pattern may be It is an active layer graphic.
  • the base substrate is a glass substrate.
  • substrate substrates are also possible.
  • a method of manufacturing a display substrate will be described in detail by taking a display substrate as a thin film transistor array substrate as an example.
  • 3-1 to 3-11 show schematic views of a method of fabricating the thin film transistor array substrate of Fig. 2, which includes steps S31-S37.
  • Step S31 The trench 2011 is etched on the glass substrate 201 in accordance with the size of the gate pattern.
  • Step S31 may specifically include the following steps:
  • a photoresist 301 is coated on the surface of the glass substrate 201.
  • the photoresist 301 is exposed and developed to form a photoresist retention region 3011 and a photoresist removal region 3012, wherein the photoresist removal region 3012 corresponds to a pattern of subsequently formed gates. region.
  • the glass substrate 201 corresponding to the photoresist completely removed region 3012 is etched by an etching process to form a trench 2011, wherein the size of the trench 2011 and the pattern of the gate to be subsequently formed are formed.
  • the glass substrate 201 of the region 3012 can be completely removed by a dry etching or a wet etching process to form the trenches 2011.
  • the photoresist of the photoresist retention region 3011 is removed. Specifically, the photoresist of the photoresist retention region 3011 can be removed by wet stripping or dry stripping.
  • Step S32 A pattern of the gate 202 filling the trench 2011 is formed in the trench 2011.
  • Step S32 may specifically include the following steps:
  • a gate metal film layer 302 is formed on the glass substrate 201 on which the trenches 2011 are formed, wherein the thickness of the gate metal film layer 302 located in the trenches 2011 is higher than the trenches The depth of 2011.
  • the gate metal film layer 302 may be formed using a sputtering process, and the gate metal may be a metal such as Mo (alloy) or Al (aluminum).
  • a gate metal film layer other than the trenches 2011 is etched away by an etching process to form a pattern of the gates 202 located in the trenches 2011 and filling the trenches 2011.
  • the gate metal film layer outside the trench 2011 may be etched away by using a dry etching or a wet etching process which is biased toward each peer etching, and the etching amount should be controlled to be slightly larger than the trench The thickness of the gate metal outside the trench 2011 does not cause excessive etching of the gate metal within the trench 2011.
  • Step S33 Referring to FIGS. 3-7, a gate insulating layer 203 is formed.
  • the gate junction layer 203 may be formed by PECVD (plasma enhanced chemical vapor deposition), and the gate insulating layer 203 may be composed of SiO 2 (silicon dioxide) and Si 3 N 4 (silicon nitride).
  • Step S34 Referring to FIGS. 3-8, the active layer 204 is formed.
  • the active layer 204 may include a semiconductor and a doped semiconductor.
  • Step S35 Referring to FIGS. 3-9, the source/drain electrodes 205 are formed.
  • the source/drain electrodes 205 may be formed using a sputtering process, and the source/drain electrodes 205 may be composed of a metal such as Mo (alloy) or Al (aluminum).
  • Step S36 Referring to FIGS. 3-10, a passivation layer 206 is formed, and a via hole 2061 is formed on the passivation layer 206.
  • the passivation layer 206 may be made of a material such as Si 3 N 4 (silicon nitride), and may be formed by PECVD (plasma enhanced chemical vapor deposition).
  • the via hole 2061 may be formed of a photoresist mask by PHOTO (lithography), formed by dry etching or wet etching.
  • Step S37 Referring to FIGS. 3-11, a pixel electrode 207 is formed, and the pixel electrode 207 is overlapped with the source or the drain through the via 2061.
  • the pixel electrode 207 may be made of a material such as ITO (Indium Tin Oxide).

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Abstract

一种显示基板及其制作方法、显示装置，该显示面板包括衬底基板（201）以及设置于所述衬底基板上且与所述衬底基板直接接触的膜层图形，所述衬底基板表面设置有沟槽（2011），所述膜层图形设置于所述沟槽内。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2014年10月29日在中国提交的中国专利申请号No.201410597037.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
在液晶显示面板生产过程中，需要形成包括栅极、源极、漏极、有源层等膜层结构的薄膜晶体管阵列基板。参考图1，图1为相关技术中的薄膜晶体管阵列基板的结构示意图，该薄膜晶体管阵列基板包括衬底基板101以及形成在衬底基板101上的栅极102、栅绝缘层103、有源层104、源/漏电极105、钝化层106和像素电极107。
现有的薄膜晶体管的制作工艺中，各膜层在平坦的衬底基板101表面堆叠，栅极102图形边缘处会使后续膜层在该处产生段差，易使后续膜层在该位置断裂，从而造成栅极与源/漏电极间漏电，影响关态电流(Ioff)等重要的薄膜晶体管性能参数。
发明内容
有鉴于此，本公开的实施例提供了一种显示基板及其制作方法、显示装置，能够提升显示基板整体结构的平坦度，从而提高显示基板的性能。
本公开第一方面的实施例提供了一种显示基板，包括衬底基板以及设置于所述衬底基板上且与所述衬底基板直接接触的膜层图形，其中所述衬底基板表面设置有沟槽，所述膜层图形设置于所述沟槽内。
可选地，所述膜层图形填平所述沟槽。
可选地，所述显示基板为薄膜晶体管阵列基板，所述膜层图形为栅极图形或有源层图形。
可选地，所述膜层图形为栅极图形，所述显示基板具体包括：
所述衬底基板，以及依次设置于所述衬底基板上的栅极、栅绝缘层、有 源层、源/漏电极、钝化层和像素电极，其中所述衬底基板表面设置有沟槽，所述栅极图形设置于所述沟槽内。
可选地，所述衬底基板为玻璃基板。
本公开第二方面的实施例还提供了一种制作显示基板的方法，包括：
在衬底基板的表面形成沟槽；以及
在所述沟槽内形成填平所述沟槽的膜层图形。
可选地，所述在所述衬底基板的表面形成沟槽的步骤包括：
在所述衬底基板的表面涂敷光刻胶；
对所述光刻胶进行曝光和显影，形成光刻胶保留区域和光刻胶去除区域，所述光刻胶去除区域对应所述膜层图形区域；
采用刻蚀工艺刻蚀对应于所述光刻胶完全去除区域的衬底基板，形成所述沟槽，其中所述沟槽的尺寸与后续需要形成的膜层图形的尺寸相同；以及
去除所述光刻胶保留区域的光刻胶。
可选地，所述在所述沟槽内形成填平所述沟槽的膜层图形的步骤包括：
在形成有所述沟槽的衬底基板上形成整层膜层，其中形成于所述沟槽之上的膜层的厚度高于所述沟槽的深度；以及
采用刻蚀工艺刻蚀掉所述沟槽之外的膜层，形成位于所述沟槽内且填平所述沟槽的膜层图形。
可选地，所述整层膜层的厚度至少是所述沟槽的深度的1.2倍。
可选地，所述显示基板为薄膜晶体管阵列基板，所述膜层图形为栅极图形或有源层图形。
本公开第三方面的实施例还提供一种显示装置，包括上述显示基板。
本公开的上述技术方案的有益效果如下：
在衬底基板表面设置沟槽，将与衬底基板直接接触的非整层膜层结构的膜层图形设置于沟槽内，以减少后续形成的膜层在该膜层图形处产生的段差，提升了显示基板的结构整体平坦度，提高了显示基板的性能。
附图说明
图1为相关技术中的薄膜晶体管阵列基板的结构示意图；
图2为本公开实施例的薄膜晶体管阵列基板的结构示意图；以及
图3-1至3-11为图2中的薄膜晶体管阵列基板的制作方法的示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开第一方面的实施例提供了一种显示基板，包括衬底基板以及设置于所述衬底基板上且与所述衬底基板直接接触的膜层图形，其中所述衬底基板表面设置有沟槽，所述膜层图形设置于所述沟槽内。
根据本公开的一个实施例，所述膜层图形非整层膜层结构。
本公开实施例中，在衬底基板表面设置沟槽，将与衬底基板直接接触的非整层膜层结构的膜层图形设置于沟槽内，以减少后续形成的膜层在该膜层图形处产生的段差，提升了显示基板的结构整体平坦度，提高了显示基板的性能。
可选地，所述膜层图形填平所述沟槽，以消除后续形成的膜层在该膜层图形处产生的段差，进一步提升了显示基板的结构整体平坦度，提高了显示基板的性能。
根据本公开的一个实施例，该显示基板可以为薄膜晶体管阵列基板。当显示基板为薄膜晶体管阵列基板时，所述膜层图形可以为栅极图形或有源层图形。具体的，当薄膜晶体管阵列基板中的薄膜晶体管为底栅结构时，所述膜层图形可以为栅极图形，当薄膜晶体管阵列基板中的薄膜晶体管为顶栅结构时，所述膜层图形可以为有源层图形。
可选地，所述衬底基板为玻璃基板。当然，也可以为其他类型的衬底基板。
参考图2，图2为本公开实施例的薄膜晶体管阵列基板的结构示意图，所述薄膜晶体管阵列基板包括：衬底基板201，以及设置于所述衬底基板201上的栅极202、栅绝缘层203、有源层204、源/漏电极205、钝化层206和像素电极207。其中，所述衬底基板201表面设置有沟槽2011，所述栅极202的图形设置于所述沟槽2011内，且填平所述沟槽2011。
其中，栅极202、栅绝缘层203、有源层204和源/漏电极205形成薄膜晶体管，该薄膜晶体管为底栅结构的薄膜晶体管。
本公开实施例中，可以消除因栅极202的边缘造成的膜层段差，提升了显示基板的结构整体平坦度，提高了显示基板的性能。
从图2中可以看出，本公开实施例的薄膜晶体管阵列基板与相关技术中的薄膜晶体管阵列基板相比，整体结构的平坦度明显提升。
本公开实施例还提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：衬底基板，以及形成于所述衬底基板上的有源层、源/漏电极、栅绝缘层、栅极、钝化层和像素电极，其中所述衬底基板表面设置有沟槽，所述有源层的图形设置于所述沟槽内，且填平所述沟槽。
其中，有源层、源/漏电极、栅绝缘层和栅极形成薄膜晶体管，该薄膜晶体管为顶栅结构的薄膜晶体管。
本公开实施例中，可以消除因有源层的边缘造成的膜层段差，提升了显示基板的结构整体平坦度，提高了显示基板的性能。
本公开另一方面的实施例还提供了一种显示装置，包括上述任一实施例中所述的显示基板。
本公开再一方面的实施例还提供了一种制作显示基板的方法，该方法包括以下步骤：
步骤S1：在衬底基板的表面形成沟槽，所述沟槽的尺寸与后续需要形成的膜层图形的尺寸相同；以及
步骤S2：在所述沟槽内形成填平所述沟槽的膜层图形。
根据本公开的所述膜层图形非整层膜层结构。
本公开实施例中，在衬底基板表面形成沟槽，并在沟槽内形成填平沟槽的膜层图形，使得在后续形成的膜层在该膜层图形处不会产生段差，提升了显示基板的结构整体平坦度，提高了显示基板的性能。
可选地，所述在所述衬底基板的表面形成沟槽的步骤包括：
步骤S11：在所述衬底基板的表面涂敷光刻胶；
步骤S12：对所述光刻胶进行曝光和显影，形成光刻胶保留区域和光刻胶去除区域，其中所述光刻胶去除区域对应所述膜层图形区域；
步骤S13：采用刻蚀工艺刻蚀对应于所述光刻胶完全去除区域的衬底基板，形成所述沟槽；以及
步骤S14：去除所述光刻胶保留区域的光刻胶。
可选地，所述在所述沟槽内形成膜层图形的步骤包括：
步骤S21：在形成有所述沟槽的衬底基板上形成整层膜层，其中形成于所述沟槽之上的膜层的厚度高于所述沟槽的深度；
形成于所述沟槽之上的膜层的厚度高于所述沟槽的深度的原因是为了达到更好地抹平沟槽位置处的膜层的目的，使得形成的膜层图形的表面与衬底基板的表面处于一个平整的表面。
步骤S22：采用刻蚀工艺刻蚀掉所述沟槽之外的膜层，形成位于所述沟槽内且填平所述沟槽的膜层图形。
可选地，所述整层膜层的厚度至少是所述沟槽的深度的1.2倍。
该显示基板可以为薄膜晶体管阵列基板，也可以为彩膜基板。当显示基板为薄膜晶体管阵列基板时，所述膜层图形可以为栅极图形或有源层图形。具体的，当薄膜晶体管阵列基板中的薄膜晶体管为底栅结构时，所述膜层图形可以为栅极图形，当薄膜晶体管阵列基板中的薄膜晶体管为顶栅结构时，所述膜层图形可以为有源层图形。
可选地，所述衬底基板为玻璃基板。当然，也可以为其他类型的衬底基板。
下面以显示基板为薄膜晶体管阵列基板为例，对显示基板的制作方法进行详细说明。
图3-1至3-11显示了制作图2中的薄膜晶体管阵列基板的方法的示意图，所述制作方法包括步骤S31-S37。
步骤S31：按照栅极图形的尺寸在玻璃基板201上刻蚀出沟槽2011。
步骤S31可以具体包括以下步骤：
参考图3-1，在玻璃基板201表面涂覆光刻胶301。
参考图3-2，对所述光刻胶301进行曝光和显影，形成光刻胶保留区域3011和光刻胶去除区域3012，其中所述光刻胶去除区域3012对应后续形成的栅极的图形区域。
参考图3-3，采用刻蚀工艺刻蚀对应于所述光刻胶完全去除区域3012的玻璃基板201，形成沟槽2011，其中所述沟槽2011的尺寸与后续需要形成的栅极的图形的尺寸相同。具体的，可采用干法刻蚀或湿法刻蚀工艺刻蚀光刻胶完全去除区域3012的玻璃基板201，形成沟槽2011。
参考图3-4，去除所述光刻胶保留区域3011的光刻胶。具体的，可采用湿法剥离或干法去胶去除光刻胶保留区域3011的光刻胶。
步骤S32：在沟槽2011中形成填平沟槽2011的栅极202的图形。
步骤S32可以具体包括以下步骤：
参考图3-5，在形成有所述沟槽2011的玻璃基板201上形成栅金属膜层302，其中位于所述沟槽2011内的所述栅金属膜层302的厚度高于所述沟槽2011的深度。具体的，可以使用Sputter(溅射工艺)形成栅金属膜层302，栅金属可以为Mo(镆)，Al(铝)等金属。
参考图3-6，采用刻蚀工艺刻蚀掉所述沟槽2011之外的栅金属膜层，形成位于所述沟槽2011内且填平所述沟槽2011的栅极202的图形。具体的，可以使用偏向于各项同行刻蚀的干法刻蚀或湿法刻蚀工艺刻蚀掉所述沟槽2011之外的栅金属膜层，刻蚀量应控制在略大于所述沟槽2011之外的栅金属的厚度，同时对所述沟槽2011之内的栅金属不会造成过多刻蚀。
步骤S33：参考图3-7，形成栅绝缘层203。
具体的，可采用PECVD(等离子体增强化学气相淀积)形成栅结缘层203，栅绝缘层203可选择SiO2(二氧化硅)与Si3N4(氮化硅)构成。
步骤S34：参考图3-8，形成有源层204。
具体的，有源层204可包含半导体与掺杂半导体。
步骤S35：参考图3-9，形成源/漏电极205。
具体的，源/漏电极205可采用Sputter(溅射工艺)形成，源/漏电极205可由Mo(镆)，Al(铝)等金属构成。
步骤S36：参考图3-10，形成钝化层206，并在所述钝化层206上形成过孔2061。
具体的，钝化层206可由Si3N4(氮化硅)等材料构成，可采用PECVD(等离子体增强化学气相淀积)形成。过孔2061可由PHOTO(光刻)形成光刻胶掩膜，经干法刻蚀或湿法刻蚀形成。
步骤S37：参考图3-11，形成像素电极207，像素电极207通过过孔2061与源极或漏极搭接。
具体的，像素电极207可由ITO(氧化铟锡)等材料构成。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (11)

  1. 一种显示基板，包括衬底基板以及设置于所述衬底基板上且与所述衬底基板直接接触的膜层图形，其中所述衬底基板表面设置有沟槽，所述膜层图形设置于所述沟槽内。
  2. 根据权利要求1所述的显示基板，其中所述膜层图形填平所述沟槽。
  3. 根据权利要求1或2所述的显示基板，其中所述显示基板为薄膜晶体管阵列基板，所述膜层图形为栅极图形或有源层图形。
  4. 根据权利要求1-3任一项所述的显示基板，其中所述膜层图形为栅极图形，所述显示基板具体包括：
    所述衬底基板，以及依次设置于所述衬底基板上的栅极、栅绝缘层、有源层、源/漏电极、钝化层和像素电极，其中所述衬底基板表面设置有沟槽，所述栅极图形设置于所述沟槽内。
  5. 根据权利要求1-4任一项所述的显示基板，其中所述衬底基板为玻璃基板。
  6. 一种制作显示基板的方法，包括：
    在衬底基板的表面形成沟槽；以及
    在所述沟槽内形成填平所述沟槽的膜层图形。
  7. 根据权利要求6所述的方法，其中所述在所述衬底基板的表面形成沟槽的步骤包括：
    在所述衬底基板的表面涂敷光刻胶；
    对所述光刻胶进行曝光和显影，形成光刻胶保留区域和光刻胶去除区域，所述光刻胶去除区域对应所述膜层图形区域；
    采用刻蚀工艺刻蚀对应于所述光刻胶完全去除区域的衬底基板，形成所述沟槽，所述沟槽的尺寸与后续需要形成的膜层图形的尺寸相同；以及
    去除所述光刻胶保留区域的光刻胶。
  8. 根据权利要求6或7所述的方法，其中所述在所述沟槽内形成填平所述沟槽的膜层图形的步骤包括：
    在形成有所述沟槽的衬底基板上形成一整层膜层，其中形成于所述沟槽之上的膜层的厚度高于所述沟槽的深度；以及
    采用刻蚀工艺刻蚀掉所述沟槽之外的膜层，形成位于所述沟槽内且填平所述沟槽的膜层图形。
  9. 根据权利要求8所述的方法，其中所述整层膜层的厚度至少是所述沟槽的深度的1.2倍。
  10. 根据权利要求6-9任一项所述的方法，其中所述显示基板为薄膜晶体管阵列基板，所述膜层图形为栅极图形或有源层图形。
  11. 一种显示装置，包括如权利要求1-5任一项所述的显示基板。
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