WO2018028304A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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WO2018028304A1
WO2018028304A1 PCT/CN2017/088645 CN2017088645W WO2018028304A1 WO 2018028304 A1 WO2018028304 A1 WO 2018028304A1 CN 2017088645 W CN2017088645 W CN 2017088645W WO 2018028304 A1 WO2018028304 A1 WO 2018028304A1
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Prior art keywords
pattern
ohmic contact
substrate
forming
insulating layer
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PCT/CN2017/088645
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English (en)
French (fr)
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段献学
宫奎
李贺飞
李纪龙
安晖
董必良
王铖铖
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/750,477 priority Critical patent/US20190019814A1/en
Publication of WO2018028304A1 publication Critical patent/WO2018028304A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display substrate, a method for fabricating the same, and a display panel.
  • TFT Thin Film Transistor
  • the display area thereof includes a plurality of pixel units arranged in an array.
  • a TFT switch for controlling the pixel unit is provided in each pixel unit.
  • Amorphous silicon thin film transistors are widely used due to their better performance, mature process and low cost.
  • the active layer in the amorphous silicon thin film transistor includes an amorphous silicon active layer and an n + amorphous silicon ohmic contact layer. Forming the active layer typically involves two etching processes. The first etching process is used to form the silicon island pattern of the active layer, and the second etching process is used to etch the gap between the n + amorphous silicon ohmic contact layers.
  • Embodiments of the present invention provide a display substrate, a method of fabricating the same, and a display panel that alleviate or solve one or more problems in the art.
  • a method of fabricating a display substrate comprising forming a TFT on a substrate, the TFT including a gate, a gate insulating layer, an active layer, an ohmic contact layer, and Source drain,
  • the method further includes forming a first pattern in the non-TFT region, wherein the first pattern covers the non-TFT region Gate insulation layer.
  • the method further includes forming a second pattern located in a channel region of the active layer using the same insulating material while forming the first pattern in the non-TFT region.
  • the second pattern is partially etched such that the second pattern thickness portion remains to form a protective insulating layer pattern.
  • the protective insulating layer pattern has a thickness of 5 to 15 nm.
  • forming the ohmic contact layer, the protective insulating layer pattern, and the source drain include:
  • the first pattern is etched away or etched to a thickness less than the protective insulating layer pattern.
  • the method further includes:
  • the source and drain electrodes are formed on a substrate on which the ohmic contact transition pattern is formed.
  • the method further includes etching the first pattern and the second pattern to the same thickness.
  • both the first pattern and the second pattern are etched away.
  • the active layer is formed of amorphous silicon
  • the ohmic contact layer is formed of n + amorphous silicon.
  • the insulating material includes at least one of SiO 2 , Si x N y , and SiO x N y .
  • dry etching is performed on the ohmic contact transition pattern, the first pattern, and the second The pattern is etched.
  • a display substrate comprising a TFT disposed on a substrate, the TFT including a gate, a gate insulating layer, an active layer, an ohmic contact layer, and a source and drain on the substrate And including a protective insulating layer pattern disposed on a side of the active layer away from the substrate and located in the channel region.
  • the protective insulating layer pattern has a thickness of 5 to 15 nm.
  • the active layer is formed of amorphous silicon
  • the ohmic contact layer is formed of n + amorphous silicon.
  • the material of the protective insulating layer pattern includes at least one of SiO 2 , Si x N y , and SiO x N y .
  • the display substrate is an array substrate.
  • a display panel including the above display substrate is provided.
  • 1a is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 1b is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIGS. 9 and 10 are schematic diagrams showing a process of preparing a display substrate according to an embodiment of the present invention.
  • FIG. 11 is a schematic flowchart diagram of preparing a display substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic flowchart diagram of preparing a display substrate according to an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of an array display substrate according to an embodiment of the present invention.
  • the thickness of the portion of the gate insulating layer located in the non-TFT region is often lowered, causing damage to the gate insulating layer.
  • the gate insulating layer is usually thinned by 80 nm.
  • the embodiment of the present invention provides a method for preparing a display substrate. As shown in FIG. 1a, FIG. 1b and FIG. 2, the method includes forming a TFT 02 on a substrate 01, and the TFT 02 includes a gate electrode 11 sequentially formed on the substrate 01.
  • a gate insulating layer 12, an amorphous silicon active layer 13, an n + amorphous silicon ohmic contact layer 15, and a source 16 and a drain 17 are provided.
  • the method before forming the amorphous silicon active layer 13, before forming the n + amorphous silicon ohmic contact layer 15, the method further includes forming a protective insulating layer 14, the protective insulating layer 14 including the non-TFT The first pattern 141 of the region 30, wherein the first pattern 141 covers the gate insulating layer 12 in the non-TFT region 30.
  • the leakage current mainly includes: a first leakage current between the source and the drain, and a leakage current between the gate and the source and a leakage current between the gate and the drain.
  • the second leakage current When the gate insulating layer on the side of the amorphous silicon active layer has poor coverage or the gate insulating layer is thin, the parasitic capacitance formed between the gate and the source and between the gate and the drain is large, resulting in a second leakage current. Large, which in turn causes a large leakage current of the TFT.
  • the gate insulating layer 12 on the side of the amorphous silicon active layer 13 is well covered, and the thickness of the gate insulating layer 12 is maintained.
  • the parasitic capacitance formed by the gate 11 and the source 16 and the gate 11 and the drain 17 is small, resulting in a small second leakage current, which in turn causes a small leakage current of the TFT.
  • the method further includes: forming the second pattern located in the channel region of the active layer 13 by using the same insulating material while forming the first pattern 141 located in the non-TFT region 30 142.
  • the channel region herein refers to a region in the TFT region between the source region and the drain region.
  • the protective insulating layer 14 is formed of, for example, any suitable material as long as the material does not affect the channel region.
  • the first pattern 141 of the protective insulating layer 14 is either retained or removed, which is not limited herein. In an embodiment, the first pattern 141 retains only a portion of the thickness. In another embodiment, the entire thickness of the first pattern 141 is preserved.
  • the second pattern 142 in the protective insulating layer 14 is retained or retained. Or remove, not limited here. In an embodiment, the second pattern 142 retains only a portion of the thickness. In another embodiment, the entire thickness of the second pattern 142 is preserved.
  • the first pattern 141 and the second pattern 142 when both the first pattern 141 and the second pattern 142 are removed, the first pattern 141 and the second pattern 142 may be simultaneously removed.
  • the first pattern 141 in the process of fabricating the display substrate, if the first pattern 141 is to be removed, it is not limited in which step the first pattern 141 is removed, as long as the subsequent process steps of forming the gate insulating layer 12 are performed. In this case, damage to the gate insulating layer 12 can be avoided.
  • the materials of the active layer and the ohmic contact layer are not limited, although the amorphous silicon active layer 13 and the n + amorphous silicon ohmic contact layer 15 are exemplified in the following embodiments.
  • Embodiments of the present invention provide a method of fabricating a display substrate by forming a first pattern 141 including the non-TFT region 30 before forming the n + amorphous silicon ohmic contact layer 15 after forming the amorphous silicon active layer 13 and A protective insulating layer 14 of the second pattern 142 located in the channel region.
  • the protective insulating layer 14 completes the gate insulating layer 12, avoiding damage to the gate insulating layer 12, thereby ensuring the performance of the display substrate.
  • the material of the protective insulating layer 14 is an insulating material, the channel region of the amorphous silicon active layer 13 (i.e., the portion corresponding to the gap between the source 16 and the drain 17 in the amorphous silicon active layer 13 is avoided).
  • the pollution ensures the performance of TFT 02.
  • the second pattern 142 is partially etched so that the second pattern 142 of the remaining thickness forms the protective insulating layer pattern 143. .
  • the materials of the first pattern 141 and the second pattern 142 are the same and the thickness is the same, and the n + amorphous silicon film is directly formed over the first pattern 141 and the second pattern 142. Therefore, while the second pattern 142 is being etched, the first pattern 141 is also necessarily etched. Based on this, embodiments of the present invention do not define whether the first pattern 141 is completely removed (Fig. 1a) or a portion of the thickness is retained (Fig. 1b).
  • the first pattern 141 is removed, and the second pattern 142 of a partial thickness is left to make the remaining thickness
  • the second pattern 142 forms a protective insulating layer pattern 143.
  • n + amorphous is formed in the etching.
  • the n + amorphous silicon film above the first pattern 141 or the thickness of the n + amorphous silicon film above the first pattern 141 is required to be smaller than the thickness of the n + amorphous silicon film above the second pattern 142. .
  • the protective insulating layer pattern 143 is formed over the channel region of the amorphous silicon active layer 13, the external conductive particles are prevented from contaminating the channel, thereby reducing the leakage current of the TFT 02.
  • the second pattern 142 is partially etched to prevent conductive particles accumulated on the surface of the second pattern 142 from penetrating into the channel.
  • the protective insulating layer pattern 143 has a thickness of 5 to 15 nm.
  • the thickness of the protective insulating layer pattern 143 by setting the thickness of the protective insulating layer pattern 143 to 5 to 15 nm, on the one hand, it is sufficient to prevent external conductive particles from contaminating the channel, and on the other hand, since the thickness of 5 to 15 nm is negligible, The influence on the overall thickness of the display substrate is avoided.
  • forming the display substrate includes the following steps:
  • the gate electrode 11 and the gate insulating layer 12 are sequentially formed on the substrate 01.
  • a metal thin film having a thickness of 100 nm to 700 nm is prepared on the substrate 01 by a magnetron sputtering method.
  • a metal thin film having a thickness of about 300 nm is prepared.
  • the material of the metal thin film is usually a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above materials.
  • the gate electrode 11 is formed on the TFT region of the display substrate (i.e., the region between the two non-TFT regions 30 in FIG. 3) by a patterning process such as exposure, development, etching, and lift-off using a mask.
  • a gate line is formed while the gate electrode 11 is being formed.
  • an insulating film having a thickness of 100 nm to 600 nm is deposited on the display substrate on which the gate electrode 11 is formed by plasma enhanced chemical vapor deposition (PECVD).
  • the material of the insulating film is usually silicon nitride, silicon oxide, silicon oxynitride or the like.
  • a gate insulating layer 12 made of silicon nitride having a thickness of about 400 nm is prepared.
  • the substrate 01 is first cleaned.
  • an active layer 13 of, for example, amorphous silicon is formed.
  • an amorphous silicon film having a thickness of 100 nm to 600 nm is deposited on the substrate 01 on which the gate insulating layer 12 is formed by PECVD.
  • an amorphous silicon film having a thickness of about 200 nm is prepared.
  • the amorphous silicon active layer 13 located above the gate electrode 11 is formed on the TFT region of the display substrate by a patterning process such as exposure, development, etching, and lift-off using a mask.
  • the protective insulating layer 14 includes a first pattern 141 in the non-TFT region 30 and a channel region in the amorphous silicon active layer 13.
  • the second pattern 142 is formed.
  • an insulating film having a thickness of 40 nm to 60 nm is deposited on the substrate 01 on which the amorphous silicon active layer 13 is formed by PECVD. Then, the first pattern 141 located in the non-TFT region 30 and the second pattern 142 located in the channel region are formed by a patterning process such as exposure, development, etching, and lift-off using a mask. For example, a protective insulating layer 14 made of silicon dioxide (SiO 2 ) having a thickness of about 50 nm is prepared. In other embodiments, the protective insulating layer 14 is silicon nitride (Si x N y ) or silicon oxynitride (SiO x N y ).
  • the dry etching process can very well control the sidewall profile of the formed amorphous silicon active layer 13, so that the performance of the finally formed active layer is better. Therefore, in the embodiment of the present invention, the insulating film is etched, for example, by a dry etching process.
  • etching gas for example, a fluorine-containing or chlorine-containing gas such as carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), sulfur hexafluoride (SF 6 ), or difluoromethylene chloride (CCl 2 F 2 ). Or a mixture of these gases and oxygen (O 2 ).
  • an ohmic contact transition pattern of, for example, n + amorphous silicon is formed in the TFT region, the shape of the ohmic contact transition pattern and the shape of the amorphous silicon active layer 13 the same.
  • an n + amorphous silicon film 151 having a thickness of 40 nm to 70 nm is deposited on the substrate 01 on which the protective insulating layer 14 is formed by PECVD.
  • the n + amorphous silicon transition pattern 152 as shown in FIG. 5 is formed by a patterning process such as exposure, development, etching, and lift-off using a mask.
  • an n + amorphous silicon transition pattern 152 having a thickness of about 50 nm is prepared.
  • the mask used in the preparation of the amorphous silicon active layer 13 is used in this step S13.
  • n + amorphous silicon film 151 is etched, for example, by a dry etching process.
  • n + amorphous silicon transition pattern 152 forms an n + amorphous silicon ohmic contact layer 15
  • the second partially preserved thickness pattern 142 forms a protective insulating layer pattern 143 .
  • a metal thin film 161 having a thickness of 100 nm to 700 nm is deposited on the substrate 01 on which the n + amorphous silicon transition pattern 152 is formed by magnetron sputtering, for example, a metal thin film 161 having a thickness of about 250 nm is prepared. .
  • a photoresist 18 having a thickness of 1.5 ⁇ m is then coated on the metal film 161.
  • the material of the metal thin film is usually a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above materials.
  • the patterning process such as exposure, development, etching, and peeling is performed by a mask to form the source 16 and the drain 17 as shown in FIG. 7 on the TFT region of the display substrate.
  • the metal thin film 161 is etched by wet etching.
  • the display substrate is an array substrate, for example, a data line is formed while forming the source 16 and the drain 17.
  • the n + amorphous silicon transition pattern 152, the first pattern 141, and the second pattern 142 are etched.
  • the etched n + amorphous silicon transition pattern 152 forms an n + amorphous silicon ohmic contact layer 15
  • the second portion 142 of which the thickness portion remains forms a protective insulating layer pattern 143 .
  • the photoresist remaining portion 181 above the source 16 and the drain 17 is removed to form a display substrate as shown in FIG. 1a.
  • n + amorphous silicon transition pattern 152, the first pattern 141, and the second pattern 142 are etched, for example, by a dry etching process.
  • etching gas capable of simultaneously etching the n + amorphous silicon and the first pattern 141 and the second pattern 142 material, and appropriately setting the n + amorphous silicon transition pattern 152 and the first pattern 141 and the second pattern
  • the thickness of 142 allows the n + amorphous silicon over the second pattern 142 to be etched away, the first pattern 141 is also completely etched away, and a portion of the thickness of the second pattern 142 is retained to form the protective insulating layer pattern 143.
  • the materials of the first pattern 141 and the second pattern 142 of the embodiment of the present invention include, for example, SiO 2 , Si x . At least one of N y and SiO x N y . That is, the material of the protective insulating layer 14 includes at least one of SiO 2 , Si x N y , and SiO x N y .
  • the n + amorphous silicon transition pattern 152, the first pattern 141 and the second pattern 142 are engraved by dry etching, for example, in a mixed gas atmosphere of SF 6 and O 2 . eclipse.
  • the etching rate of silicon is larger than that of SiO 2 . Therefore, the n + amorphous silicon located above the second pattern 142 is quickly etched away until the first pattern 141 of the SiO 2 material is completely etched away, and the etching process is stopped. At this time, only a part of the thickness of SiO 2 in the second pattern 142 is etched away, and the remaining portion of the thickness of SiO 2 is left, thereby forming the protective insulating layer pattern 143.
  • the mixed gas atmosphere of chlorine (Cl 2 ) and O 2 or CF 4 and O 2 also has an effect of mixing with SF 6 and O 2 , and will not be described herein.
  • Si x N y and SiO x N y also have the same effects as SiO 2 .
  • the thickness of the n + amorphous silicon is set to be the same as the thickness of the first pattern 141 or slightly larger than the thickness of the first pattern 141 such that when the first pattern 141 is etched away, n + amorphous silicon Has been etched away.
  • the first pattern 141 and the second pattern 142 have the same thickness.
  • the n + amorphous silicon transition pattern 152, the first pattern 141 and the first method are dry etched in a mixed gas atmosphere of SF 6 and O 2 , or Cl 2 and O 2 , or CF 4 and O 2 .
  • the second pattern 142 is etched such that the process of forming the protective insulating layer pattern 143 is easily controlled.
  • forming the display substrate includes the following steps:
  • the gate electrode 11 and the gate insulating layer 12 are sequentially formed on the substrate 01.
  • an active layer 13 of, for example, amorphous silicon is formed.
  • the protective insulating layer 14 includes a first pattern 141 located in the non-TFT region 30 and a second pattern 142 located in the channel region.
  • n + amorphous silicon ohmic contact layer 15 is formed in the TFT region.
  • a metal thin film 161 is first deposited on the substrate 01 on which the n + amorphous silicon ohmic contact layer 15 is formed, and a photoresist 18 is coated on the metal thin film 161. Then, a patterning process such as exposure, development, etching, and lift-off is performed using a mask to form a source 16 and a drain 17 as shown in FIG. 10 on the TFT region of the display substrate.
  • the first pattern 141 and the second pattern 142 are etched.
  • the photoresist retention portion 181 above the source 16 and the drain 17 is then removed.
  • both the first pattern 141 and the second pattern 142 are etched away.
  • the amorphous silicon active layer 13 under the first pattern 141 is also appropriately etched to avoid amorphous silicon.
  • the embodiment of the present invention further provides a display substrate, as shown in FIG. 1a and FIG. 1b, comprising a TFT 02 disposed on a substrate 01, the TFT 02 including a gate electrode 11 and a gate insulating layer sequentially disposed on the substrate 01. 12.
  • the display substrate further includes a protective insulating layer pattern 143 disposed on a side of the amorphous silicon active layer 13 away from the substrate 01 and located in the channel region.
  • the material of the protective insulating layer 14 is not limited as long as it does not affect the channel region.
  • Embodiments of the present invention provide a display substrate by forming a first pattern 141 located in the non-TFT region 30 and located in the channel before forming the n + amorphous silicon ohmic contact layer 15 after forming the amorphous silicon active layer 13.
  • the protective insulating layer 14 of the second pattern 142 of the region For example, in the process of forming the n + amorphous silicon ohmic contact layer 15, the first pattern 141 is completely removed, and the second pattern 142 of a partial thickness is left, thereby forming the protective insulating layer pattern 143.
  • the gate insulating layer 12 is ensured to be intact, and damage to the gate insulating layer 12 is avoided, thereby ensuring the performance of the display substrate.
  • the protective insulating layer pattern 143 is formed over the channel region to prevent external conductive particles from contaminating the channel, thereby reducing the leakage current of the TFT 02.
  • the protective insulating layer pattern has a thickness of 5 to 15 nm.
  • the thickness of the protective insulating layer pattern 143 by setting the thickness of the protective insulating layer pattern 143 to 5 to 15 nm, on the one hand, it is sufficient to prevent external conductive particles from contaminating the channel, and on the other hand, since the thickness of 5 to 15 nm is negligible, Avoid shadowing the overall thickness of the display substrate ring.
  • the material of the protective insulating layer pattern includes, for example, SiO 2 , Si x N y , SiO x N y . At least one of them.
  • the display substrate is an array substrate.
  • the liquid crystal capacitance and the storage capacitance caused by the damage of the gate insulating layer 12 are prevented from deviating from the simulation result, and the image flicker is caused, and the parameters such as the coupling voltage, the corresponding time, and the charging rate are deviated.
  • the array substrate further includes a pixel electrode 19 electrically connected to the drain of the TFT 02.
  • the array substrate further includes, for example, a common electrode.
  • the pixel electrode and the common electrode are spaced apart in the same layer and are strip electrodes; for advanced super-dimensional field conversion type (Advanced- In the case of a super Dimensional Switching (ADS) array substrate, the pixel electrode and the common electrode are disposed in different layers, wherein the upper electrode is a strip electrode and the lower electrode is a plate electrode.
  • ADS super Dimensional Switching
  • the embodiment of the invention further provides a display panel comprising the above display substrate.
  • an embodiment of the present invention further provides a display device including the display panel.
  • the display device is specifically, for example, a product or a component having any display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • An embodiment of the present invention provides a display substrate, a method for fabricating the same, and a display panel. After forming an n + amorphous silicon ohmic contact layer after forming an amorphous silicon active layer, forming a first pattern including the non-TFT region and A protective insulating layer of the second pattern located in the channel region. In the process of forming the n + amorphous silicon ohmic contact layer, the gate insulating layer is completed without damaging the gate insulating layer, thereby ensuring the performance of the display substrate.
  • the material of the protective insulating layer is an insulating material, contamination of the channel region of the amorphous silicon active layer (ie, a portion corresponding to the gap between the source and the drain in the amorphous silicon active layer) is avoided, and the TFT is ensured. performance.

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Abstract

一种显示基板及其制备方法、显示面板。该显示基板的制备方法包括在衬底（01）上形成TFT（02），TFT包括依次形成在衬底上的栅极（11）、栅绝缘层（12）、有源层（13）、欧姆接触层（15）、以及源漏极（16、17），其中在形成有源层之后，并且在形成欧姆接触层之前，还包括形成位于非TFT区域（30）的第一图案（141），其中第一图案在非TFT区域覆盖栅绝缘层。

Description

显示基板及其制备方法、显示面板
相关专利申请
本申请主张于2016年8月12日提交的中国专利申请No.201610666482.3的优先权，其全部内容通过引用结合于此。
技术领域
本发明涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示面板。
背景技术
薄膜晶体管(Thin Film Transistor，简称TFT)作为开关控制单元，在显示领域有着广泛的应用。以TFT阵列基板为例，其显示区包括阵列排布的多个像素单元。每个像素单元中都设置有用于控制该像素单元的TFT开关。
非晶硅薄膜晶体管由于性能较好，工艺成熟且成本较低，目前被广泛应用。非晶硅薄膜晶体管中的有源层包括非晶硅有源层和n+非晶硅欧姆接触层。形成该有源层通常涉及两次刻蚀工艺。第一次刻蚀工艺用于形成有源层的硅岛图形，并且第二次刻蚀工艺用于刻蚀出各n+非晶硅欧姆接触层之间的间隙。
发明内容
本发明的实施例提供一种显示基板及其制备方法、显示面板，其可减轻或解决本领域中存在的一个或多个问题。
第一方面，提供一种显示基板的制备方法，包括在衬底上形成TFT，所述TFT包括依次形成在所述衬底上的栅极、栅绝缘层、有源层、欧姆接触层、以及源漏极，
其中在形成所述有源层之后，并且在形成所述欧姆接触层之前，所述方法还包括形成位于非TFT区域的第一图案，其中所述第一图案在所述非TFT区域覆盖所述栅绝缘层。
例如，该方法还包括：在形成位于所述非TFT区域的所述第一图案同时，利用同一绝缘材料形成位于所述有源层的沟道区域的第二图案。
例如，在形成所述欧姆接触层的同时，对所述第二图案进行部分刻蚀，使所述第二图案厚度部分保留以形成保护绝缘层图案。
例如，所述保护绝缘层图案的厚度为5～15nm。
例如，形成所述欧姆接触层、所述保护绝缘层图案以及所源漏极包括：
在形成有所述有源层的衬底上，形成所述第一图案和第二图案；
在形成有所述第一图案和第二图案的衬底上，形成欧姆接触过渡图案，其中所述欧姆接触过渡图案的形状与所述有源层的形状相同；以及
在形成有所述欧姆接触过渡图案的衬底上，形成所源漏极，并对所述欧姆接触过渡图案、所述第一图案和所述第二图案刻蚀，以形成所述欧姆接触层和所述保护绝缘层图案。
例如，所述第一图案被刻蚀掉，或者被刻蚀至比所述保护绝缘层图案小的厚度。
例如，在形成所述第一图案和第二图案之后，所述方法还包括：
在形成有所述第一图案和第二图案的衬底上，形成欧姆接触过渡图案，其中所述欧姆接触过渡图案位于TFT区域的源极区和漏极区；以及
在形成有所述欧姆接触过渡图案的衬底上，形成所述源漏极。
例如，在形成所述源漏极之后，所述方法还包括：将所述第一图案和第二图案刻蚀至相同的厚度。
例如，所述第一图案和第二图案都被刻蚀掉。
例如，所述有源层由非晶硅形成，并且所述欧姆接触层由n+非晶硅形成。
例如，所述绝缘材料包括SiO2、SixNy、SiOxNy中的至少一种。
例如，在SF6与O2，Cl2与O2，或CF4与O2的混合气体环境下，采用干法刻蚀对所述欧姆接触过渡图案、所述第一图案和所述第二图案进行刻蚀。
第二方面，提供一种显示基板，包括设置在衬底上的TFT，所述TFT包括依次位于所述衬底上的栅极、栅绝缘层、有源层、欧姆接触层、以及源漏极；并且包括设置在所述有源层远离所述衬底一侧、且位于沟道区域的保护绝缘层图案。
例如，所述保护绝缘层图案的厚度为5～15nm。
例如，所述有源层由非晶硅形成，并且所述欧姆接触层由n+非晶 硅形成。
例如，所述保护绝缘层图案的材料包括SiO2、SixNy、SiOxNy中的至少一种。
例如，所述显示基板为阵列基板。
第三方面，提供一种显示面板，包括上述的显示基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为本发明实施例提供的一种显示基板的结构示意图；
图1b为本发明实施例提供的一种显示基板的结构示意图；
图2为本发明实施例提供的一种显示基板的结构示意图；
图3、4、5、6、7、8为本发明实施例提供的一种制备显示基板的过程示意图；
图9和10为本发明实施例提供的一种制备显示基板的过程示意图；
图11为本发明实施例提供的一种制备显示基板的流程示意图；
图12为本发明实施例提供的一种制备显示基板的流程示意图；以及
图13为本发明实施例提供的一种阵列显示基板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
附图标记：01-衬底；02-TFT；11-栅极；12-栅绝缘层；13-非晶硅有源层；14-保护绝缘层；141-第一图案；142-第二图案；143-保护绝缘层图案；15-n+非晶硅欧姆接触层；151-n+非晶硅薄膜；152-n+非晶硅过渡图案；16-源极；17-漏极；18-光刻胶；181-光刻胶保留部分；19-像素电极；30-非TFT区域。
在形成n+非晶硅欧姆接触层的过程中，由于栅绝缘层上方没有遮挡，往往会使栅绝缘层的位于非TFT区域的部分厚度降低，造成栅绝缘层的损伤。举例来说，当第二次刻蚀有源层的刻蚀量为100nm时，通常会造成栅绝缘层减薄80nm。本发明实施例目的之一是减轻或解决在形成欧姆接触层的过程中栅绝缘层损伤以及由此引发的问题。
本发明实施例提供一种显示基板的制备方法，如图1a、图1b和图2所示，包括在衬底01上形成TFT 02，TFT 02包括依次形成在衬底01上的栅极11、栅绝缘层12、非晶硅有源层13、n+非晶硅欧姆接触层15、以及源极16和漏极17。
如图3所示，在形成非晶硅有源层13之后，形成n+非晶硅欧姆接触层15之前，所述方法还包括形成保护绝缘层14，所述保护绝缘层14包括位于非TFT区域30的第一图案141，其中第一图案141在非TFT区域30覆盖栅绝缘层12。
对于具有上述图示结构的TFT，漏电流主要包括：源极和漏极之间的第一漏电流，以及栅极与源极之间的漏电流和栅极与漏极之间的漏电流组成的第二漏电流。当非晶硅有源层侧面的栅绝缘层覆盖性不佳或栅绝缘层较薄时，栅极与源极以及栅极与漏极之间形成的寄生电容较大，导致第二漏电流较大，进而导致TFT的漏电流较大。根据本发明实施例，由于在非TFT区域30上形成覆盖栅绝缘层12的第一图案141，非晶硅有源层13侧面的栅绝缘层12覆盖性良好，并且栅绝缘层12厚度被保持，栅极11与源极16以及栅极11与漏极17形成的寄生电容较小，导致第二漏电流较小，进而导致TFT的漏电流较小。
在本发明实施例中，该方法还包括：在形成位于所述非TFT区域30的所述第一图案141同时，利用同一绝缘材料形成位于所述有源层13的沟道区域的第二图案142。此处的沟道区域是指TFT区域中位于源极区域和漏极区域之间的区域。
在本发明实施例中，保护绝缘层14例如由任何合适材料形成，只要该材料不对沟道区域产生影响即可。
在本发明实施例中，保护绝缘层14的第一图案141或者保留，或者去除，在此不做限定。在一实施例中，第一图案141仅仅保留部分厚度。在另一实施例中，第一图案141全部厚度被保留。
在本发明实施例中，保护绝缘层14中的第二图案142或者保留， 或者去除，在此不做限定。在一实施例中，第二图案142仅仅保留部分厚度。在另一实施例中，第二图案142全部厚度被保留。
在本发明实施例中，当第一图案141和第二图案142均被去除时，可同时将第一图案141和第二图案142去除。
在本发明实施例中，在制作上述显示基板的工艺过程中，若需将第一图案141去除，并不限定在哪个步骤中去除第一图案141，只要在形成栅绝缘层12的后续工艺步骤中，能避免对栅绝缘层12的损伤即可。
在本发明实施例中，对有源层和欧姆接触层的材料不做限定，尽管在下述实施例中以非晶硅有源层13和n+非晶硅欧姆接触层15为例进行描述。
应指出，本发明实施例及所有附图只为清楚描述与本方案发明点相关的结构，对于其他的与发明点无关的结构并未体现或只体现部分。
本发明实施例提供一种显示基板的制备方法，通过在形成非晶硅有源层13之后，形成n+非晶硅欧姆接触层15之前，形成包括位于非TFT区域30的第一图案141以及位于沟道区域的第二图案142的保护绝缘层14。在形成n+非晶硅欧姆接触层15的过程中，该保护绝缘层14使栅绝缘层12完整，避免对栅绝缘层12的损伤，从而保证所述显示基板的性能。由于保护绝缘层14的材料为绝缘材料，避免对非晶硅有源层13的沟道区域(即，非晶硅有源层13中与源极16和漏极17之间的间隙对应的部分)的污染，保证TFT 02的性能。
例如，如图1a和图1b所示，在形成n+非晶硅欧姆接触层15的同时，对第二图案142进行部分刻蚀，使剩余厚度的第二图案142，形成保护绝缘层图案143。
此处，第一图案141和第二图案142的材料相同并且厚度相同，而且n+非晶硅薄膜直接形成在第一图案141和第二图案142上方。因此，在对第二图案142进行刻蚀的同时，势必对第一图案141也进行刻蚀。基于此，本发明实施例并不对第一图案141是否被完全去除(图1a)或有部分厚度被保留(图1b)进行限定。
示例的，如图4-8所示，在形成n+非晶硅欧姆接触层15的同时，将第一图案141去除，并将部分厚度的所述第二图案142保留，使剩余厚度的第二图案142形成保护绝缘层图案143。
需要说明的是，由于第一图案141和第二图案142的材料相同且厚度相同，为了使第一图案141完全去除，而保留部分厚度的第二图案142，则在刻蚀形成n+非晶硅欧姆接触层15之前，需使第一图案141上方无n+非晶硅薄膜或第一图案141上方的n+非晶硅薄膜厚度小于第二图案142上方的n+非晶硅薄膜的厚度。在此基础上，还应保证n+非晶硅以及第一图案141和第二图案142的材料能在相同刻蚀环境下被刻蚀。
本发明实施例中，通过在非晶硅有源层13的沟道区域上方形成保护绝缘层图案143，避免外界的导电粒子污染沟道，从而减小TFT 02的漏电流。对第二图案142进行部分刻蚀，避免第二图案142表面聚集的导电粒子渗入沟道中。
例如，所述保护绝缘层图案143的厚度为5～15nm。
本发明实施例中，通过将保护绝缘层图案143的厚度设定为5～15nm，一方面足以避免外界的导电粒子污染沟道，另一方面，由于5～15nm的厚度是可忽略的，因此避免对所述显示基板整体厚度的影响。
下面提供一具体实施例以对上述显示基板的制备方法进行具体说明。如图11所示，形成所述显示基板例如包括如下步骤：
S10、如图3所示，在衬底01上依次形成栅极11和栅绝缘层12。
具体的，使用磁控溅射方法，在衬底01上制备一层厚度为100nm至700nm的金属薄膜。例如制备300nm左右厚度的金属薄膜。该金属薄膜的材料通常为钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，或者上述几种材料的组合。然后，用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在显示基板的TFT区域(即图3中的两个非TFT区域30之间的区域)上形成栅极11。
当然，若所述显示基板为阵列基板，例如还在形成栅极11的同时形成栅线。
进一步的，利用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)在形成有栅极11的显示基板上沉积厚度为100nm至600nm的绝缘薄膜。绝缘薄膜的材料通常是氮化硅、氧化硅、氮氧化硅等。例如制备400nm左右厚度的氮化硅材质的栅绝缘层12。
需要说明的是，在形成金属薄膜之前，例如先对衬底01进行清洗。
S11、如图3所示，在S10的基础上，形成例如非晶硅的有源层13。
具体的，利用PECVD在形成有栅绝缘层12的衬底01上沉积厚度为100nm至600nm的非晶硅薄膜。例如制备200nm左右厚度的非晶硅薄膜。用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在显示基板的TFT区域上形成位于栅极11上方的非晶硅有源层13。
S12、如图3所示，在S11的基础上，形成保护绝缘层14，所述保护绝缘层14包括位于非TFT区域30的第一图案141以及位于非晶硅有源层13的沟道区域的第二图案142。
具体的，利用PECVD在形成有非晶硅有源层13的衬底01上沉积厚度为40nm至60nm的绝缘薄膜。然后，用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，形成位于非TFT区域30的第一图案141以及位于沟道区域的第二图案142。例如制备50nm左右厚度的二氧化硅(SiO2)材质的保护绝缘层14。在其它实施例中，保护绝缘层14是氮化硅(SixNy)或者氮氧化硅(SiOxNy)。
考虑到干法刻蚀工艺能够非常好的控制形成的非晶硅有源层13的侧壁剖面，使最终形成的有源层的性能更好。因此，本发明实施例例如采用干法刻蚀工艺，对所述绝缘薄膜进行刻蚀。
干法刻蚀例如选用等离子刻蚀、反应离子刻蚀(Reactive Ion Etching，简称RIE)、电感耦合等离子体(Inductively Coupled Plasma，ICP)刻蚀等方法。刻蚀气体例如选择含氟、氯的气体，如四氟化碳(CF4)、三氟甲烷(CHF3)、六氟化硫(SF6)、二氟二氯甲烷(CCl2F2)等或者这些气体与氧气(O2)的混合气体。
S13、如图4和5所示，在S12的基础上，在TFT区域形成例如n+非晶硅的欧姆接触过渡图案，所述欧姆接触过渡图案的形状与非晶硅有源层13的形状相同。
具体的，如图4所示，利用PECVD在形成有保护绝缘层14的衬底01上沉积厚度为40nm至70nm的n+非晶硅薄膜151。用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，形成如图5所示的所述n+非晶硅过渡图案152。例如制备50nm左右厚度的n+非晶硅过渡图案152。
由于n+非晶硅过渡图案152的形状与非晶硅有源层13的形状相 同，因此，该步骤S13中，使用制备非晶硅有源层13时所采用的掩模板。
此外，例如采用干法刻蚀工艺，对n+非晶硅薄膜151进行刻蚀。
S14、如图6-8所示，在S13的基础上，形成源极16和漏极17，并对n+非晶硅过渡图案152、第一图案141和第二图案142刻蚀，经刻蚀的n+非晶硅过渡图案152形成n+非晶硅欧姆接触层15，厚度部分保留的第二图案142形成保护绝缘层图案143。
具体的，如图6所示，利用磁控溅射在形成有n+非晶硅过渡图案152的衬底01上沉积厚度为100nm至700nm的金属薄膜161，例如制备250nm左右厚度的金属薄膜161。之后在金属薄膜161上涂覆1.5μm厚度的光刻胶18。该金属薄膜的材料通常为钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，或者上述几种材料的组合。然后，用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在显示基板的TFT区域上形成如图7所示的源极16和漏极17。例如，采用湿法刻蚀对金属薄膜161进行刻蚀。
当然，若所述显示基板为阵列基板，例如还在形成源极16和漏极17的同时形成数据线。
进一步的，如图8所示，对n+非晶硅过渡图案152、第一图案141和第二图案142进行刻蚀。经刻蚀后的n+非晶硅过渡图案152形成n+非晶硅欧姆接触层15，并且厚度部分保留的第二图案142形成保护绝缘层图案143。之后，将源极16和漏极17上方的光刻胶保留部分181去除，形成如图1a所示的显示基板。
例如采用干法刻蚀工艺，对n+非晶硅过渡图案152、第一图案141和第二图案142进行刻蚀。
需要说明的是，在刻蚀n+非晶硅过渡图案152、第一图案141和第二图案142之前，第二图案142被n+非晶硅过渡图案152遮挡，而第一图案141上方无任何遮挡，如图7所示。因此，只需选择能同时刻蚀n+非晶硅以及第一图案141和第二图案142材料的刻蚀气体，且合理设置n+非晶硅过渡图案152以及第一图案141和第二图案142厚度，便可使第二图案142上方的n+非晶硅被刻蚀掉，第一图案141也被完全刻蚀掉，而第二图案142的部分厚度被保留以形成保护绝缘层图案143。
考虑到SiO2、SixNy、SiOxNy是很好的绝缘材料，而且成本较低，因此，本发明实施例第一图案141和第二图案142的材料例如包括SiO2、SixNy、SiOxNy中的至少一种。即，保护绝缘层14的材料包括SiO2、SixNy、SiOxNy中的至少一种。
在此基础上，在上述步骤S14中，例如在SF6与O2的混合气体环境下，采用干法刻蚀对n+非晶硅过渡图案152、第一图案141和第二图案142进行刻蚀。
以SiO2为例，在SF6与O2的混合气体环境下，硅的刻蚀速率大于SiO2。因此，位于第二图案142上方的n+非晶硅很快被刻蚀掉，直到SiO2材料的第一图案141被全部刻蚀掉以后，刻蚀工艺停止。此时，第二图案142中只有部分厚度的SiO2被刻蚀掉，其余部分厚度的SiO2则被保留下来，从而形成保护绝缘层图案143。
当然，氯气(Cl2)与O2、或CF4与O2的混合气体环境也具有与SF6与O2混合气体环境的效果，在此不再赘述。在这些混合气体环境下，SixNy、SiOxNy也具有与SiO2相同的效果。
基于此，例如将n+非晶硅的厚度设置为与第一图案141的厚度相同，或略大于第一图案141的厚度，使得当第一图案141被刻蚀掉时，n+非晶硅已经被刻蚀掉。第一图案141和第二图案142的厚度相同。
本发明实施例通过在SF6与O2，或Cl2与O2，或CF4与O2的混合气体环境下，采用干法刻蚀对n+非晶硅过渡图案152、第一图案141和第二图案142进行刻蚀这样，使得形成保护绝缘层图案143的工艺容易控制。
下面提供另一具体实施例对上述显示基板的制备方法进行具体说明。如图12所示，形成所述显示基板例如包括如下步骤：
S20、如图3所示，在衬底01上依次形成栅极11和栅绝缘层12。
S21、如图3所示，在S20的基础上，形成例如非晶硅的有源层13。
S22、如图3所示，在S21的基础上，形成保护绝缘层14，所述保护绝缘层14包括位于非TFT区域30的第一图案141以及位于沟道区域的第二图案142。
S23、如图9所示，在S22的基础上，在TFT区域形成n+非晶硅欧姆接触层15。
S24、如图9-10所示，在S23的基础上，形成源极16和漏极17， 并对第一图案141和第二图案142刻蚀，形成如图2所示的显示基板。
此处，如图9所示，例如先在形成有n+非晶硅欧姆接触层15的衬底01上沉积金属薄膜161，并在金属薄膜161上涂覆光刻胶18。然后，用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在显示基板的TFT区域上形成如图10所示的源极16和漏极17。
进一步的，如图2所示，对第一图案141和第二图案142进行刻蚀。之后将源极16和漏极17上方的光刻胶保留部分181去除。
此处，由于第一图案141和第二图案142的厚度相同，因此第一图案141和第二图案142都会被刻蚀掉。
在此基础上，如图2所示，当第一图案141被刻蚀去除后，例如还对第一图案141下方的非晶硅有源层13进行适当的过刻，以避免非晶硅有源层13表面聚集的导电粒子渗入沟道中。
本发明实施例还提供一种显示基板，如图1a和图1b所示，包括设置在衬底01上的TFT 02，所述TFT 02包括依次位于衬底01上的栅极11、栅绝缘层12、非晶硅有源层13、n+非晶硅欧姆接触层15、以及源极16和漏极17。所述显示基板还包括设置在非晶硅有源层13远离衬底01一侧、且位于沟道区域的保护绝缘层图案143。
需要说明的是，不对保护绝缘层14的材料进行限定，只要不对沟道区域产生影响即可。
本发明实施例提供一种显示基板，通过在形成非晶硅有源层13之后，形成n+非晶硅欧姆接触层15之前，形成包括位于非TFT区域30的第一图案141以及位于沟道区域的第二图案142的保护绝缘层14。例如在形成n+非晶硅欧姆接触层15的过程中，使第一图案141完全去除，使部分厚度的第二图案142保留，从而形成保护绝缘层图案143。一方面，在此过程中，保证栅绝缘层12完整，而避免对栅绝缘层12的损伤，从而保证所述显示基板的性能。另一方面，在沟道区域上方形成保护绝缘层图案143，避免外界的导电粒子污染沟道，从而减小TFT 02的漏电流。
例如，所述保护绝缘层图案的厚度为5～15nm。
本发明实施例中，通过将保护绝缘层图案143的厚度设定为5～15nm，一方面足以避免外界的导电粒子污染沟道，另一方面，由于5～15nm的厚度是可忽略的，因此避免对所述显示基板整体厚度的影 响。
考虑到SiO2、SixNy、SiOxNy是很好的绝缘材料，而且成本较低，因此，所述保护绝缘层图案的材料例如包括SiO2、SixNy、SiOxNy中的至少一种。
例如所述显示基板为阵列基板。
这样，避免栅绝缘层12的损伤而造成的液晶电容以及存储电容偏离模拟结果，而导致的图像闪烁，以及耦合电压、相应时间、充电率等参数偏离的问题。
如图13所示，阵列基板还包括与TFT 02的漏极电连接的像素电极19。
进一步的，阵列基板例如还包括公共电极。
对于共平面切换型(In-Plane Switch，简称IPS)阵列基板而言，所述像素电极和所述公共电极同层间隔设置，且均为条状电极；对于高级超维场转换型(Advanced-super Dimensional Switching，简称ADS)阵列基板而言，所述像素电极和所述公共电极不同层设置，其中在上的电极为条状电极，在下的电极为板状电极。
本发明实施例还提供一种显示面板，包括上述的显示基板。
此外，本发明实施例还提供一种显示装置，包括所述显示面板。
显示装置具体例如为液晶显示器、液晶电视、数码相框、手机、平板电脑等具有任何显示功能的产品或者部件。
本发明实施例提供一种显示基板及其制备方法、显示面板，通过在形成非晶硅有源层之后，形成n+非晶硅欧姆接触层之前，形成包括位于非TFT区域的第一图案以及位于沟道区域的第二图案的保护绝缘层。在形成n+非晶硅欧姆接触层的过程中，使栅绝缘层完整，而避免对栅绝缘层的损伤，从而保证所述显示基板的性能。由于保护绝缘层的材料为绝缘材料，避免对非晶硅有源层的沟道区域(即，非晶硅有源层中与源漏极之间的间隙对应的部分)的污染，保证TFT的性能。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种显示基板的制备方法，包括在衬底上形成TFT，所述TFT包括依次形成在所述衬底上的栅极、栅绝缘层、有源层、欧姆接触层、以及源漏极，
    其中在形成所述有源层之后，并且在形成所述欧姆接触层之前，所述方法还包括形成位于非TFT区域的第一图案，其中所述第一图案在所述非TFT区域覆盖所述栅绝缘层。
  2. 根据权利要求1所述的方法，还包括：在形成位于所述非TFT区域的所述第一图案同时，利用同一绝缘材料形成位于所述有源层的沟道区域的第二图案。
  3. 根据权利要求2所述的方法，其中在形成所述欧姆接触层的同时，对所述第二图案进行部分刻蚀，使所述第二图案厚度部分保留以形成保护绝缘层图案。
  4. 根据权利要求3所述的方法，其中所述保护绝缘层图案的厚度为5～15nm。
  5. 根据权利要求3所述的方法，其中形成所述欧姆接触层、所述保护绝缘层图案以及所源漏极包括：
    在形成有所述有源层的衬底上，形成所述第一图案和第二图案；
    在形成有所述第一图案和第二图案的衬底上，形成欧姆接触过渡图案，其中所述欧姆接触过渡图案的形状与所述有源层的形状相同；以及
    在形成有所述欧姆接触过渡图案的衬底上，形成所源漏极，并对所述欧姆接触过渡图案、所述第一图案和所述第二图案刻蚀，以形成所述欧姆接触层和所述保护绝缘层图案。
  6. 根据权利要求5所述的方法，其中所述第一图案被刻蚀掉，或者被刻蚀至比所述保护绝缘层图案小的厚度。
  7. 根据权利要求2所述的方法，其中在形成所述第一图案和第二图案之后，所述方法还包括：
    在形成有所述第一图案和第二图案的衬底上，形成欧姆接触过渡图案，其中所述欧姆接触过渡图案位于TFT区域的源极区和漏极区；以及
    在形成有所述欧姆接触过渡图案的衬底上，形成所述源漏极。
  8. 根据权利要求7所述的方法，其中在形成所述源漏极之后，所述方法还包括：将所述第一图案和第二图案刻蚀至相同的厚度。
  9. 根据权利要求8所述的方法，其中所述第一图案和第二图案都被刻蚀掉。
  10. 根据权利要求2-9中任意一项所述的方法，其中所述有源层由非晶硅形成，并且所述欧姆接触层由n+非晶硅形成。
  11. 根据权利要求10所述的方法，其中所述绝缘材料包括SiO2、SixNy、SiOxNy中的至少一种。
  12. 根据权利要求11所述的方法，其中在SF6与O2，Cl2与O2，或CF4与O2的混合气体环境下，采用干法刻蚀对所述欧姆接触过渡图案、所述第一图案和所述第二图案进行刻蚀。
  13. 一种显示基板，包括设置在衬底上的TFT，所述TFT包括依次位于所述衬底上的栅极、栅绝缘层、有源层、欧姆接触层、以及源漏极；并且包括设置在所述有源层远离所述衬底一侧、且位于沟道区域的保护绝缘层图案。
  14. 根据权利要求13所述的显示基板，其中所述保护绝缘层图案的厚度为5～15nm。
  15. 根据权利要求13或14所述的显示基板，其中所述有源层由非晶硅形成，并且所述欧姆接触层由n+非晶硅形成。
  16. 根据权利要求15所述的显示基板，其中所述保护绝缘层图案的材料包括SiO2、SixNy、SiOxNy中的至少一种。
  17. 根据权利要求13-16中任意一项所述的显示基板，其中所述显示基板为阵列基板。
  18. 一种显示面板，包括权利要求13-17中任意一项所述的显示基板。
PCT/CN2017/088645 2016-08-12 2017-06-16 显示基板及其制备方法、显示面板 WO2018028304A1 (zh)

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