WO2019109712A1 - 阵列基板及制作方法、显示面板、显示装置 - Google Patents

阵列基板及制作方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2019109712A1
WO2019109712A1 PCT/CN2018/107092 CN2018107092W WO2019109712A1 WO 2019109712 A1 WO2019109712 A1 WO 2019109712A1 CN 2018107092 W CN2018107092 W CN 2018107092W WO 2019109712 A1 WO2019109712 A1 WO 2019109712A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film layer
ohmic contact
photoresist
source
Prior art date
Application number
PCT/CN2018/107092
Other languages
English (en)
French (fr)
Inventor
韩笑
白金超
丁向前
郭会斌
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/332,882 priority Critical patent/US11049889B2/en
Publication of WO2019109712A1 publication Critical patent/WO2019109712A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a manufacturing method thereof, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • a gate electrode Forming a gate electrode, a gate insulating layer, an active layer film layer, an ohmic contact layer film layer, and a copper metal film layer on the base substrate;
  • the contact layer film layer and the active layer film layer remove patterns corresponding to the source drain and the conductive channel region;
  • the ohmic contact layer film layer and the active layer film layer are etched in the conductive channel region with the source drain as an occlusion to form an ohmic contact layer and an active layer.
  • the etching the copper metal film layer, the ohmic contact layer film layer, and the active layer film layer by using the first photoresist pattern comprises:
  • the ohmic contact layer film layer and the active layer film layer with the first photoresist pattern as an occlusion Performing a first dry etch on the ohmic contact layer film layer and the active layer film layer with the first photoresist pattern as an occlusion, the ohmic contact layer film layer and the active layer
  • the film layer removes a pattern corresponding to the source drain and the conductive channel region;
  • Thinning the first photoresist pattern removing a pattern at the conductive channel region in the first photoresist pattern
  • etching the ohmic contact layer film layer and the active layer film layer in the conductive channel region specifically including:
  • the forming a pixel electrode in contact with the source and drain portions on the source and drain electrodes of the first photoresist layer specifically:
  • the second photoresist layer on the pixel electrode is stripped.
  • the method further includes:
  • a passivation layer is formed on the pixel electrode.
  • the method further includes:
  • a common electrode is formed on the passivation layer.
  • the method further includes:
  • a common electrode is formed on the base substrate.
  • An embodiment of the present disclosure further provides an array substrate fabricated by the above method, including:
  • the gate insulating layer is located on the base substrate and covers the gate;
  • An active layer the active layer being located on the gate insulating layer
  • An ohmic contact layer located on the active layer
  • the source drain is located on the ohmic contact layer, and the material is copper metal;
  • a pixel electrode located on the source drain and in contact with the source drain portion.
  • the method further includes: a passivation layer on the pixel electrode.
  • the method further includes: a common electrode on the passivation layer.
  • the method further includes: a common electrode; the common electrode is disposed in the same layer as the gate.
  • the embodiment of the present disclosure further provides a display panel including the array substrate provided by any embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device including the display panel provided by any embodiment of the present disclosure.
  • FIG. 1 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • 3( a ) to 3 ( i ) are schematic structural diagrams after completion of each step in a process for preparing an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the active layer and the source and drain electrodes in the array substrate of the TFT-LCD are usually fabricated by using the same mask.
  • the manufacturing steps include: (1) sequentially forming a gate electrode and a gate insulating layer on the substrate. , an active layer film layer, an ohmic contact layer film layer, and a source/drain film layer; (2) applying a photoresist (PR glue) on the source/drain film layer, and using a halftone mask (Half-tone Mask) Exposing the photoresist and then developing; (3) sequentially performing a first wet etching (ie, 1SD Wet Etch) on the source/drain film layer according to the developed photoresist, and the ohmic contact layer The film layer and the active layer film layer are subjected to a first dry etching (ie, 1SD Dry Etch); (4) the photoresist is thinned to remove the photoresist at the conductive channel region, and the source and drain film layers are subjected to Two we
  • the source/drain film layer is usually an aluminum (Al) metal film layer. Copper (Cu) has a lower resistivity than Al. In order to increase the pixel aperture ratio, copper is selected as a source/drain film layer in the related art. If the photoresist on the source drain is wet-peeled in the above step (5), the copper ions diffuse into the conductive channel region of the TFT with the stripping solution due to the easy diffusion of the copper ions, thereby causing the conductive of the TFT. Channel area contamination.
  • the photoresist on the source and drain electrodes is selected to be dry-peeled, but the dry stripping increases the time, reduces the productivity, and the Cu metal surface is easily caused during the dry stripping process. Oxidation forms CuO. Further, since the difference in resistivity between Cu and CuO is large, contact between the drain and the pixel electrode is liable to occur.
  • the embodiment of the present disclosure provides an array substrate and a manufacturing method thereof, a display panel, and a display device.
  • a method for fabricating an array substrate according to an embodiment of the present disclosure includes the following steps:
  • the order of peeling off the first photoresist layer is changed, and in the step S106, the ohmic contact layer film layer and the active layer film layer are performed in the conductive channel region.
  • step S104 Before etching (ie, performing conductive channel etching of the TFT) to form the ohmic contact layer and the active layer, performing step S104 to wet-peel the first photoresist layer on the source and drain electrodes, thus performing wet
  • the conductive channel region is formed after the stripping, so that copper ions contaminate the conductive channel region of the TFT during wet stripping.
  • the productivity can be improved relative to the first photoresist layer on the drain of the source by dry stripping, and the oxidation of the Cu metal surface where the source and drain electrodes are overlapped with the pixel electrode can be avoided.
  • the step S103 uses a first photoresist pattern to etch the copper metal film layer, the ohmic contact layer film layer and the active layer film layer, which may be specifically include:
  • the second photoresist pattern is used as a occlusion, and the copper metal film layer is subjected to a second wet etching, and a pattern corresponding to the conductive channel region is removed in the copper metal film layer to form a source and a drain.
  • the etching of the ohmic contact layer film layer and the active layer film layer in the conductive channel region in step S106 may specifically include:
  • a second dry etching is performed on the ohmic contact layer film layer and the active layer film layer, and patterns other than the conductive channel regions are removed in the ohmic contact layer film layer and the active layer film layer.
  • the step S105 is performed on the source and drain electrodes of the first photoresist layer to form the pixel electrode in contact with the source and drain portions, and may specifically include:
  • the transparent electrode layer is formed on the source and drain electrodes of the first photoresist layer; for example, the transparent electrode layer may be an indium tin oxide (ITO) film layer, which is not limited herein;
  • ITO indium tin oxide
  • the second photoresist layer on the pixel electrode is stripped.
  • the method may further include:
  • a passivation layer is formed on the pixel electrode, and the passivation layer can protect the covered TFT device and the pixel electrode.
  • an embodiment of the present disclosure further provides an array substrate.
  • the array substrate is fabricated by using the method for fabricating an array substrate according to an embodiment of the present disclosure.
  • a gate insulating layer 13 is located on the substrate substrate 11 and covers the gate electrode 12;
  • the active layer 14 is disposed on the gate insulating layer 13;
  • An ohmic contact layer 15, an ohmic contact layer 15 is disposed on the active layer 14;
  • the source and drain electrodes 16 and the source and drain electrodes 16 are located on the ohmic contact layer 15 and are made of copper metal;
  • the pixel electrode 17 is located on the source and drain electrodes 16 and is in partial contact with the source and drain electrodes 16.
  • the display panel including the above array substrate may be, for example, a twisted nematic (TN) mode LCD display panel.
  • TN twisted nematic
  • the above array substrate provided by the embodiment of the present disclosure may further include: a passivation layer 18 on the pixel electrode 17.
  • the above array substrate provided by the embodiment of the present disclosure may further include: a common electrode 19 on the passivation layer 18 .
  • the display panel including the above array substrate may be, for example, an Advanced Super Dimension Switch (ADS) mode LCD display panel.
  • ADS Advanced Super Dimension Switch
  • the above array substrate provided by the embodiment of the present disclosure may further include: a common electrode 19; the common electrode 19 is disposed in the same layer as the gate electrode 12.
  • the display panel including the above array substrate may be, for example, an Advanced Super Dimension Switch (ADS) mode LCD display panel.
  • ADS Advanced Super Dimension Switch
  • Step 1 refer to FIG. 3 (a), sequentially forming a gate electrode 12, a gate insulating layer 13, an active layer film layer 141, an ohmic contact layer film layer 151 and a copper metal film layer 161 on the base substrate 11;
  • Step 2 referring to FIG. 3 (b), forming a first photoresist layer on the copper metal film layer 161, and patterning the first photoresist layer to form a first photoresist pattern 162;
  • Step 3 referring to FIG. 3(c), the first photoresist pattern 162 is used as a shield, and the copper metal film layer 161 is first wet etched, and the copper metal film layer 161 is removed corresponding to the source and drain electrodes and conductive. a pattern outside the channel region;
  • Step 4 referring to FIG. 3(d), the first photoresist pattern 162 is used as an occlusion, and the ohmic contact layer film layer 151 and the active layer film layer 141 are firstly etched in the ohmic contact layer. 151 and the active layer film layer 141 remove patterns corresponding to the source drain and the conductive channel region;
  • Step 5 referring to FIG. 3(e), thinning the first photoresist pattern 162, removing the pattern at the conductive channel region in the first photoresist pattern 162;
  • Step 6 using the thinned first photoresist pattern 162 as a mask, performing a second wet etching on the copper metal film layer 161, removing a pattern corresponding to the conductive channel region in the copper metal film layer 161, Forming the source and drain electrodes 16, a schematic structural view thereof is shown in FIG. 3(f);
  • Step 7 Referring to FIG. 3(g), the first photoresist layer 162 on the source and drain electrodes 16 is wet-peeled;
  • Step 8 refer to FIG. 3 (h), forming a pixel electrode 17 in contact with the source and drain electrodes 16 on the source and drain electrodes 16 of the first photoresist layer 162;
  • Step IX Referring to FIG. 3(i), the source drain 16 is used as a mask, and the ohmic contact layer film layer 151 and the active layer film layer 141 are subjected to a second dry etching (ie, 2SD Dry Etch) to Forming an ohmic contact layer 15 and an active layer 14;
  • a second dry etching ie, 2SD Dry Etch
  • Step 6 Referring to FIG. 2, a passivation layer 18 is formed on the pixel electrode 17.
  • a method of fabricating an array substrate according to Embodiment 2 of the present disclosure further includes: forming a common electrode on the passivation layer.
  • an embodiment of the present disclosure further provides a display panel including the array substrate provided by any embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device, including the display panel provided by any embodiment of the present disclosure.
  • the display device can be: a display panel of any product having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the order of peeling off the first photoresist layer is changed, and the ohmic contact layer film layer and the active layer film layer are etched in the conductive channel region (ie, Performing wet stripping on the first photoresist layer on the source and drain electrodes before performing the conductive channel etching of the TFT to form the ohmic contact layer and the active layer, thus forming a conductive trench after performing wet stripping In the track region, it is possible to prevent copper ions from contaminating the conductive channel region of the TFT during wet stripping. Moreover, the productivity can be improved relative to the first photoresist layer on the drain of the source by dry stripping, and the oxidation of the Cu metal surface where the source and drain electrodes are overlapped with the pixel electrode can be avoided.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

本公开提供了一种阵列基板及制作方法、显示面板、显示装置，变更了对第一光刻胶层进行剥离的顺序，在对欧姆接触层膜层和有源层膜层在导电沟道区域进行刻蚀（即进行TFT的导电沟道刻蚀），以形成欧姆接触层和有源层之前，执行对源漏极上的第一光刻胶层进行湿法剥离的步骤，这样，在进行湿法剥离之后形成导电沟道区域，可以避免在湿法剥离时铜离子污染TFT的导电沟道区域。并且，相对于采用干法剥离源漏极上的第一光刻胶层，可以提高产能，避免源漏极与像素电极搭接处的Cu金属表面氧化。

Description

阵列基板及制作方法、显示面板、显示装置
相关申请的交叉引用
本申请要求在2017年12月6日提交中国专利局、申请号为201711277247.8、发明名称为“一种阵列基板及制作方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板及制作方法、显示面板、显示装置。
背景技术
在平板显示装置中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有体积小、功耗低、制造成本相对较低和无辐射等特点，在当前的平板显示器市场占据了主导地位。
发明内容
本公开实施例提供的一种阵列基板的制作方法，包括：
在衬底基板上依次形成栅极、栅极绝缘层、有源层膜层、欧姆接触层膜层和铜金属膜层；
在所述铜金属膜层上形成第一光刻胶层，并对所述第一光刻胶进行构图，形成所述第一光刻胶图案；
采用所述第一光刻胶图案，对所述铜金属膜层、欧姆接触层膜层和有源层膜层进行刻蚀，以在所述铜金属膜层形成源漏极，在所述欧姆接触层膜层和有源层膜层去除对应于所述源漏极和导电沟道区域之外的图案；
对所述第一光刻胶层进行湿法剥离；
在剥离所述第一光刻胶层的源漏极上形成与所述源漏极部分接触的像素 电极；
以所述源漏极作为遮挡，在所述导电沟道区域对所述欧姆接触层膜层和所述有源层膜层进行刻蚀，以形成欧姆接触层和有源层。
可选地，所述采用所述第一光刻胶图案，对所述铜金属膜层、欧姆接触层膜层和有源层膜层进行刻蚀，具体包括：
以所述第一光刻胶图案作为遮挡，对所述铜金属膜层进行第一道湿法刻蚀，在所述铜金属膜层去除对应于所述源漏极和导电沟道区域之外的图案；
以所述第一光刻胶图案作为遮挡，对所述欧姆接触层膜层和所述有源层膜层进行第一道干法刻蚀，在所述欧姆接触层膜层和所述有源层膜层去除对应于所述源漏极和导电沟道区域之外的图案；
减薄所述第一光刻胶图案，在所述第一光刻胶图案去除所述导电沟道区域处的图案；
以减薄后的第一光刻胶图案作为遮挡，对所述铜金属膜层进行第二道湿法刻蚀，在所述铜金属膜层去除对应于所述导电沟道区域的图案，以形成所述源漏极。
可选地，在所述导电沟道区域对所述欧姆接触层膜层和所述有源层膜层进行刻蚀，具体包括：
对所述欧姆接触层膜层和所述有源层膜层进行第二道干法刻蚀，在所述欧姆接触层膜层和所述有源层膜层去除对应于导电沟道区域之外的图案。
可选地，所述在剥离所述第一光刻胶层的源漏极上形成与所述源漏极部分接触的像素电极，具体包括：
在剥离所述第一光刻胶层的源漏极上形成透明电极层；
在所述透明电极层上形成第二光刻胶层，并对所述第二光刻胶层进行构图，形成第二光刻胶图案；
采用第二光刻胶图案，对所述透明电极层进行刻蚀，以形成所述像素电极；
剥离所述像素电极上的第二光刻胶层。
可选地，在形成所述欧姆接触层和有源层之后，该方法还包括：
在所述像素电极上形成钝化层。
可选地，该方法还包括：
在所述钝化层上形成公共电极。
可选地，在形成所述栅极之前，该方法还包括：
在所述衬底基板上形成公共电极。
本公开实施例还提供了一种采用上述方法制作的阵列基板，其中，包括：
衬底基板；
栅极，所述栅极位于所述衬底基板上；
栅极绝缘层，所述栅极绝缘层位于所述衬底基板上且覆盖所述栅极；
有源层，所述有源层位于所述栅极绝缘层上；
欧姆接触层，所述欧姆接触层位于所述有源层上；
源漏极，所述源漏极位于所述欧姆接触层上，且材质为铜金属；
像素电极，所述像素电极位于所述源漏极上且与所述源漏极部分接触。
可选地，还包括：位于所述像素电极上的钝化层。
可选地，还包括：位于所述钝化层上的公共电极。
可选地，还包括：公共电极；所述公共电极与所述栅极同层设置。
本公开实施例还提供了一种显示面板，包括本公开任意实施例提供的阵列基板。
本公开实施例还提供了一种显示装置，包括本公开任意实施例提供的显示面板。
附图说明
图1为本公开实施例提供的阵列基板的制作方法的流程示意图；
图2为本公开实施例提供的阵列基板的结构示意图；
图3(a)～图3(i)为本公开实施例提供的阵列基板的制备工艺流程中各步骤完成后的结构示意图；
图4为本公开实施例提供的阵列基板的另一种结构示意图；
图5为本公开实施例提供的阵列基板的另一种结构示意图。
具体实施方式
目前，通常采用同一掩膜版(mask)制作TFT-LCD的阵列基板中的有源层和源漏极，其制作步骤包括：(1)在衬底基板上依次形成栅极、栅极绝缘层、有源层膜层、欧姆接触层膜层和源漏极膜层；(2)在源漏极膜层上涂光刻胶(PR胶)，并采用半色调掩膜版(Half-tone Mask)对该光刻胶进行曝光、然后进行显影；(3)根据显影后的光刻胶，依次对源漏极膜层进行第一道湿法刻蚀(即1SD Wet Etch)，对欧姆接触层膜层和有源层膜层进行第一道干法刻蚀(即1SD Dry Etch)；(4)减薄光刻胶去除导电沟道区域处的光刻胶，对源漏极膜层进行第二道湿法刻蚀(即2SD Wet Etch)，对欧姆接触层膜层和有源层膜层进行第二道干法刻蚀(即2SD Dry Etch)，以形成有源层、欧姆接触层和源漏极；(5)剥离源漏极上的光刻胶；(6)在剥离光刻胶的源漏极上依次形成钝化层和像素电极；其中，像素电极通过钝化层上的过孔与漏极电连接。
上述工艺步骤制作的阵列基板中，源漏极膜层通常为铝(Al)金属膜层。而铜(Cu)相比Al具有更低的电阻率，为了提高像素开口率，在相关技术中选择使用铜作为源漏极膜层。若在上述步骤(5)中采用湿法剥离源漏极上的光刻胶，由于铜离子的易扩散性，铜离子会随着剥离液扩散进TFT的导电沟道区域，从而造成TFT的导电沟道区域污染。为了防止铜离子污染TFT的导电沟道区域，源漏极上的光刻胶选择采用干法剥离，但干法剥离会增加占时，降低产能，且干法剥离的过程中容易导致Cu金属表面氧化形成CuO。并且，由于Cu与CuO的电阻率差异较大，容易导致漏极与像素电极的接触不良。
为了同时避免铜离子污染TFT的导电沟道，以及避免源漏极与像素电极的搭接处Cu金属表面氧化，本公开实施例提供了一种阵列基板及其制作方法、显示面板、显示装置。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本公开附图中各层的厚度和形状不反映真实比例，目的只是示意说明本公开内容。
参见图1，本公开实施例提供的一种阵列基板的制作方法，具体包括如下步骤：
S101、在衬底基板上依次形成栅极、栅极绝缘层、有源层膜层、欧姆接触层膜层和铜金属膜层；
S102、在铜金属膜层上形成第一光刻胶层，并对第一光刻胶进行构图，形成第一光刻胶图案；
S103、采用第一光刻胶图案，对铜金属膜层、欧姆接触层膜层和有源层膜层进行刻蚀，以在铜金属膜层形成源漏极，在欧姆接触层膜层和有源层膜层去除对应于源漏极和导电沟道区域之外的图案；
S104、对第一光刻胶层进行湿法剥离；
S105、在剥离第一光刻胶层的源漏极上形成与源漏极部分接触的像素电极；
S106、以源漏极作为遮挡，在导电沟道区域对欧姆接触层膜层和有源层膜层进行刻蚀，以形成欧姆接触层和有源层。
具体地，在本发明实施例提供的上述制作方法中，变更了对第一光刻胶层进行剥离的顺序，在步骤S106对欧姆接触层膜层和有源层膜层在导电沟道区域进行刻蚀(即进行TFT的导电沟道刻蚀)，以形成欧姆接触层和有源层之前，执行步骤S104对源漏极上的第一光刻胶层进行湿法剥离，这样，在进行湿法剥离之后形成导电沟道区域，可以避免在湿法剥离时铜离子污染TFT的导电沟道区域。并且，相对于采用干法剥离源漏极上的第一光刻胶层，可以提高产能，避免源漏极与像素电极搭接处的Cu金属表面氧化。
可选地，在本发明实施例提供的上述制作方法中，上述步骤S103采用第一光刻胶图案，对铜金属膜层、欧姆接触层膜层和有源层膜层进行刻蚀，可以具体包括：
以第一光刻胶图案作为遮挡，对铜金属膜层进行第一道湿法刻蚀，在铜金属膜层去除对应于源漏极和导电沟道区域之外的图案；
以第一光刻胶图案作为遮挡，对欧姆接触层膜层和有源层膜层进行第一道干法刻蚀，在欧姆接触层膜层和有源层膜层去除对应于源漏极和导电沟道区域之外的图案；
减薄第一光刻胶图案，在第一光刻胶图案去除导电沟道区域处的图案；
以减薄后的第一光刻胶图案作为遮挡，对铜金属膜层进行第二道湿法刻蚀，在铜金属膜层去除对应于导电沟道区域的图案，以形成源漏极。
可选地，在本发明实施例提供的上述制作方法中，步骤S106在导电沟道区域对欧姆接触层膜层和有源层膜层进行刻蚀，可以具体包括：
对欧姆接触层膜层和有源层膜层进行第二道干法刻蚀，在欧姆接触层膜层和有源层膜层去除对应于导电沟道区域之外的图案。
可选地，在本发明实施例提供的上述制作方法中，步骤S105在剥离第一光刻胶层的源漏极上形成与源漏极部分接触的像素电极，可以具体包括：
在剥离第一光刻胶层的源漏极上形成透明电极层；具体地，透明电极层例如可以为氧化铟锡(ITO)膜层，在此不做限定；
在透明电极层上形成第二光刻胶层，并对第二光刻胶层进行构图，形成第二光刻胶图案；
采用第二光刻胶图案，对透明电极层进行刻蚀，以形成像素电极；
剥离像素电极上的第二光刻胶层。
可选地，在本发明实施例提供的上述制作方法中，为了能够对阵列基板上的器件进行保护，在形成欧姆接触层和有源层之后，该方法还可以包括：
在像素电极上形成钝化层，钝化层可以对覆盖的TFT器件和像素电极起到保护作用。
基于同一发明构思，本公开实施例还提供了一种阵列基板，参见图2，其采用本公开实施例提供的阵列基板的制作方法制作而成，该阵列基板包括：
衬底基板11；
栅极12，栅极12位于衬底基板11上；
栅极绝缘层13，栅极绝缘层13位于衬底基板11上且覆盖栅极12；
有源层14，有源层14位于栅极绝缘层13上；
欧姆接触层15，欧姆接触层15位于有源层14上；
源漏极16，源漏极16位于欧姆接触层15上，且材质为铜金属；
像素电极17，像素电极17位于源漏极16上且与源漏极16部分接触。
具体地，包含上述阵列基板的显示面板例如可以为扭曲向列(Twisted Nematic，TN)模式的LCD显示面板。
可选地，如图2所示，本公开实施例提供的上述阵列基板还可以包括：位于像素电极17上的钝化层18。
可选地，如图4所示，本公开实施例提供的上述阵列基板还可以包括：位于钝化层18上的公共电极19。
具体地，包含上述阵列基板的显示面板例如可以为高级超维场转换技术(Advanced Super Dimension Switch，ADS)模式的LCD显示面板。
可选地，如图5所示，本公开实施例提供的上述阵列基板还可以包括：公共电极19；公共电极19与栅极12同层设置。
具体地，包含上述阵列基板的显示面板例如可以为高级超维场转换技术(Advanced Super Dimension Switch，ADS)模式的LCD显示面板。
下面以图2所示的阵列基板为例，结合附图3(a)～3(i)来具体说明本公开实施例提供的阵列基板的制备工艺流程。
步骤一、参见图3(a)，在衬底基板11上依次形成栅极12、栅极绝缘层13、有源层膜层141、欧姆接触层膜层151和铜金属膜层161；
步骤二、参见图3(b)，在铜金属膜层161上形成第一光刻胶层，并对第一光刻胶层进行构图，形成第一光刻胶图案162；
步骤三、参见图3(c)，以第一光刻胶图案162作为遮挡，对铜金属膜层161进行第一道湿法刻蚀，在铜金属膜层161去除对应于源漏极和导电沟道区域之外的图案；
步骤四、参见图3(d)，以第一光刻胶图案162作为遮挡，对欧姆接触层膜层151和有源层膜层141进行第一道干法刻蚀，在欧姆接触层膜层151和有源层膜层141去除对应于源漏极和导电沟道区域之外的图案；
步骤五、参见图3(e)，减薄第一光刻胶图案162，在第一光刻胶图案162去除导电沟道区域处的图案；
步骤六、以减薄后的第一光刻胶图案162作为遮挡，对铜金属膜层161进行第二道湿法刻蚀，在铜金属膜层161去除对应于导电沟道区域的图案，以形成源漏极16，其结构示意图如图3(f)所示；
步骤七、参见图3(g)，对源漏极16上的第一光刻胶层162进行湿法剥离；
步骤八、参见图3(h)，在剥离第一光刻胶层162的源漏极16上形成与源漏极16部分接触的像素电极17；
步骤九、参见图3(i)，以源漏极16为掩膜版，对欧姆接触层膜层151和有源层膜层141进行第二道干法刻蚀(即2SD Dry Etch)，以形成欧姆接触层15和有源层14；
步骤六、参见图2，在像素电极17上形成钝化层18。
本公开实施例二提供的阵列基板的制作方法，该方法还包括：在钝化层上形成公共电极。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括本公开任意实施例提供的阵列基板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开任意实施例提供的显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品的显示面板。
综上，本公开实施例提供的技术方案中，变更了对第一光刻胶层进行剥 离的顺序，在对欧姆接触层膜层和有源层膜层在导电沟道区域进行刻蚀(即进行TFT的导电沟道刻蚀)，以形成欧姆接触层和有源层之前，执行对源漏极上的第一光刻胶层进行湿法剥离，这样，在进行湿法剥离之后形成导电沟道区域，可以避免在湿法剥离时铜离子污染TFT的导电沟道区域。并且，相对于采用干法剥离源漏极上的第一光刻胶层，可以提高产能，避免源漏极与像素电极搭接处的Cu金属表面氧化。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (13)

  1. 一种阵列基板的制作方法，其中，包括：
    在衬底基板上依次形成栅极、栅极绝缘层、有源层膜层、欧姆接触层膜层和铜金属膜层；
    在所述铜金属膜层上形成第一光刻胶层，并对所述第一光刻胶进行构图，形成所述第一光刻胶图案；
    采用所述第一光刻胶图案，对所述铜金属膜层、欧姆接触层膜层和有源层膜层进行刻蚀，以在所述铜金属膜层形成源漏极，在所述欧姆接触层膜层和有源层膜层去除对应于所述源漏极和导电沟道区域之外的图案；
    对所述第一光刻胶层进行湿法剥离；
    在剥离所述第一光刻胶层的源漏极上形成与所述源漏极部分接触的像素电极；
    以所述源漏极作为遮挡，在所述导电沟道区域对所述欧姆接触层膜层和所述有源层膜层进行刻蚀，以形成欧姆接触层和有源层。
  2. 根据权利要求1所述的方法，其中，所述采用所述第一光刻胶图案，对所述铜金属膜层、欧姆接触层膜层和有源层膜层进行刻蚀，具体包括：
    以所述第一光刻胶图案作为遮挡，对所述铜金属膜层进行第一道湿法刻蚀，在所述铜金属膜层去除对应于所述源漏极和导电沟道区域之外的图案；
    以所述第一光刻胶图案作为遮挡，对所述欧姆接触层膜层和所述有源层膜层进行第一道干法刻蚀，在所述欧姆接触层膜层和所述有源层膜层去除对应于所述源漏极和导电沟道区域之外的图案；
    减薄所述第一光刻胶图案，在所述第一光刻胶图案去除所述导电沟道区域处的图案；
    以减薄后的第一光刻胶图案作为遮挡，对所述铜金属膜层进行第二道湿法刻蚀，在所述铜金属膜层去除对应于所述导电沟道区域的图案，以形成所述源漏极。
  3. 根据权利要求2所述的方法，其中，在所述导电沟道区域对所述欧姆接触层膜层和所述有源层膜层进行刻蚀，具体包括：
    对所述欧姆接触层膜层和所述有源层膜层进行第二道干法刻蚀，在所述欧姆接触层膜层和所述有源层膜层去除对应于导电沟道区域之外的图案。
  4. 根据权利要求1所述的方法，其中，所述在剥离所述第一光刻胶层的源漏极上形成与所述源漏极部分接触的像素电极，具体包括：
    在剥离所述第一光刻胶层的源漏极上形成透明电极层；
    在所述透明电极层上形成第二光刻胶层，并对所述第二光刻胶层进行构图，形成第二光刻胶图案；
    采用第二光刻胶图案，对所述透明电极层进行刻蚀，以形成所述像素电极；
    剥离所述像素电极上的第二光刻胶层。
  5. 根据权利要求1所述的方法，其中，在所述形成欧姆接触层和有源层之后，该方法还包括：
    在所述像素电极上形成钝化层。
  6. 根据权利要求5所述的方法，其中，该方法还包括：
    在所述钝化层上形成公共电极。
  7. 根据权利要求1-5任一项所述的方法，其中，在形成所述栅极之前，该方法还包括：
    在所述衬底基板上形成公共电极。
  8. 一种采用如权利要求1-7任一项所述的方法制作的阵列基板，其中，包括：
    衬底基板；
    栅极，所述栅极位于所述衬底基板上；
    栅极绝缘层，所述栅极绝缘层位于所述衬底基板上且覆盖所述栅极；
    有源层，所述有源层位于所述栅极绝缘层上；
    欧姆接触层，所述欧姆接触层位于所述有源层上；
    源漏极，所述源漏极位于所述欧姆接触层上，且材质为铜金属；
    像素电极，所述像素电极位于所述源漏极上且与所述源漏极部分接触。
  9. 根据权利要求8所述的阵列基板，其中，还包括：位于所述像素电极上的钝化层。
  10. 根据权利要求9所述的阵列基板，其中，还包括：位于所述钝化层上的公共电极。
  11. 根据权利要求9所述的阵列基板，其中，还包括：公共电极；所述公共电极与所述栅极同层设置。
  12. 一种显示面板，其中，包括如权利要求8-11任一项所述的阵列基板。
  13. 一种显示装置，其中，包括如权利要求12所述的显示面板。
PCT/CN2018/107092 2017-12-06 2018-09-21 阵列基板及制作方法、显示面板、显示装置 WO2019109712A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/332,882 US11049889B2 (en) 2017-12-06 2018-09-21 Method for preparing array substrate by stripping first photo-resist layer through wet etching before forming ohm contact layer and active layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711277247.8A CN108010924A (zh) 2017-12-06 2017-12-06 一种阵列基板及制作方法、显示面板
CN201711277247.8 2017-12-06

Publications (1)

Publication Number Publication Date
WO2019109712A1 true WO2019109712A1 (zh) 2019-06-13

Family

ID=62056980

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/107092 WO2019109712A1 (zh) 2017-12-06 2018-09-21 阵列基板及制作方法、显示面板、显示装置

Country Status (3)

Country Link
US (1) US11049889B2 (zh)
CN (1) CN108010924A (zh)
WO (1) WO2019109712A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108010924A (zh) * 2017-12-06 2018-05-08 京东方科技集团股份有限公司 一种阵列基板及制作方法、显示面板
KR102086411B1 (ko) * 2018-06-04 2020-03-09 주식회사 코엠에스 반도체 기판용 보호필름 박리 여부 감시 장치 및 방법
CN110957214A (zh) * 2018-09-26 2020-04-03 株洲中车时代电气股份有限公司 一种沟槽及其蚀刻方法
CN109616416A (zh) * 2018-12-17 2019-04-12 惠科股份有限公司 主动开关及其制作方法、显示装置
CN110854068B (zh) * 2019-10-28 2022-06-07 Tcl华星光电技术有限公司 Tft阵列基板的制备方法及tft阵列基板
CN112309970B (zh) * 2020-10-30 2022-11-08 成都中电熊猫显示科技有限公司 阵列基板的制作方法以及阵列基板
CN113594185A (zh) * 2021-07-29 2021-11-02 北海惠科光电技术有限公司 阵列基板的制作方法及阵列基板
CN114695529A (zh) * 2022-03-16 2022-07-01 Tcl华星光电技术有限公司 Tft基板及其制作方法、液晶显示面板和oled显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188242A (zh) * 2006-11-20 2008-05-28 三星电子株式会社 薄膜晶体管基板及其制造方法
US20100155733A1 (en) * 2008-12-18 2010-06-24 Lg Display Co., Ltd. Array substrate for display device and method for fabricating the same
CN102237305A (zh) * 2010-05-06 2011-11-09 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN104091784A (zh) * 2014-07-11 2014-10-08 合肥鑫晟光电科技有限公司 一种阵列基板制备方法
CN104766859A (zh) * 2015-04-28 2015-07-08 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN108010924A (zh) * 2017-12-06 2018-05-08 京东方科技集团股份有限公司 一种阵列基板及制作方法、显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100872494B1 (ko) * 2002-12-31 2008-12-05 엘지디스플레이 주식회사 액정 표시 장치용 어레이 기판의 제조 방법
KR100598737B1 (ko) 2003-05-06 2006-07-10 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
CN101273106B (zh) * 2005-09-29 2012-09-26 陶氏康宁东丽株式会社 导热有机硅弹性体、导热有机硅弹性体组合物和导热介质
KR101529557B1 (ko) * 2011-06-09 2015-06-19 엘지디스플레이 주식회사 프린지 필드형 액정표시장치의 제조방법
KR101964826B1 (ko) * 2011-06-15 2019-04-03 삼성디스플레이 주식회사 금속 패턴의 형성 방법 및 이를 포함하는 표시 기판의 제조 방법
CN102944959B (zh) * 2012-11-20 2014-12-24 京东方科技集团股份有限公司 阵列基板、其制作方法、其测试方法及显示装置
CN104241139B (zh) * 2014-08-28 2017-11-10 京东方科技集团股份有限公司 制作薄膜晶体管的方法及薄膜晶体管
CN105304643A (zh) * 2015-09-28 2016-02-03 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188242A (zh) * 2006-11-20 2008-05-28 三星电子株式会社 薄膜晶体管基板及其制造方法
US20100155733A1 (en) * 2008-12-18 2010-06-24 Lg Display Co., Ltd. Array substrate for display device and method for fabricating the same
CN102237305A (zh) * 2010-05-06 2011-11-09 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
CN104091784A (zh) * 2014-07-11 2014-10-08 合肥鑫晟光电科技有限公司 一种阵列基板制备方法
CN104766859A (zh) * 2015-04-28 2015-07-08 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN108010924A (zh) * 2017-12-06 2018-05-08 京东方科技集团股份有限公司 一种阵列基板及制作方法、显示面板

Also Published As

Publication number Publication date
US11049889B2 (en) 2021-06-29
US20210028200A1 (en) 2021-01-28
CN108010924A (zh) 2018-05-08

Similar Documents

Publication Publication Date Title
WO2019109712A1 (zh) 阵列基板及制作方法、显示面板、显示装置
WO2017054384A1 (zh) 一种阵列基板及其制作方法、显示面板
WO2015067148A1 (zh) 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置
CN107611139B (zh) 薄膜晶体管阵列基板及制作方法
US20180292696A1 (en) Array substrate, manufacturing method thereof, display panel and display device
US9153606B2 (en) Method of manufacturing an array substrate
US9276014B2 (en) Array substrate and method of fabricating the same, and liquid crystal display device
WO2015149482A1 (zh) 阵列基板及其制作方法、显示装置
WO2017024640A1 (zh) 阵列基板及其制造方法
US8586453B2 (en) Methods for fabricating thin film pattern and array substrate
CN109494257B (zh) 一种薄膜晶体管及其制造方法、阵列基板、显示装置
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
US20140206139A1 (en) Methods for fabricating a thin film transistor and an array substrate
US11043515B2 (en) Display substrate, manufacturing method thereof, and display device
US9653578B2 (en) Thin film transistor, its manufacturing method and display device
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
US9494837B2 (en) Manufacturing method of TFT array substrate, TFT array substrate and display device
CN107735853B (zh) 薄膜晶体管制造方法及阵列基板
US10497724B2 (en) Manufacturing method of a thin film transistor and manufacturing method of an array substrate
WO2018040795A1 (zh) 一种阵列基板及其制备方法、显示面板及其制备方法
US20180210296A1 (en) Array substrate, manufacturing method thereof and display device
US10714512B2 (en) Thin film transistor, method for fabricating the same, and display device
CN109119428B (zh) Tft基板的制作方法
WO2015096393A1 (zh) 阵列基板及其制造方法、显示装置
JP2003031780A (ja) 薄膜トランジスタパネルの製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18885432

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18885432

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 02/10/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18885432

Country of ref document: EP

Kind code of ref document: A1